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foss-eda-tools/third_party/shuttle/sky130/mpw-006/slot-006/a1a182e24291f09ec215a8b36622f806b5074fa5^!/.
commit
a1a182e24291f09ec215a8b36622f806b5074fa5
[log]
author
dineshannayya <dinesh.annayya@gmail.com>
Fri Mar 18 14:39:35 2022 +0530
committer
dineshannayya <dinesh.annayya@gmail.com>
Fri Mar 18 14:39:35 2022 +0530
tree
2f2937a3b37cfae6d81bd3fef763c63ba1ac0d72
parent
4b67d58e56dfe4fa19fc89c6dde30310fbbdaa7d [diff]
caravel address range fix + test bench update for MPW5

diff --git a/Makefile b/Makefile
index b50ea0e..67a92ac 100644
--- a/Makefile
+++ b/Makefile

@@ -13,95 +13,135 @@
 # limitations under the License.
 #
 # SPDX-License-Identifier: Apache-2.0
+MAKEFLAGS+=--warn-undefined-variables
 
 CARAVEL_ROOT?=$(PWD)/caravel
 PRECHECK_ROOT?=${HOME}/mpw_precheck
-SIM ?= RTL
-DUMP ?= OFF
+MCW_ROOT?=$(PWD)/mgmt_core_wrapper
+SIM?=RTL
+DUMP?=OFF
+
+export SKYWATER_COMMIT=c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+export OPEN_PDKS_COMMIT=7519dfb04400f224f140749cda44ee7de6f5e095
+export PDK_MAGIC_COMMIT=7d601628e4e05fd17fcb80c3552dacb64e9f6e7b
+export OPENLANE_TAG=2022.02.23_02.50.41
 
 # Install lite version of caravel, (1): caravel-lite, (0): caravel
 CARAVEL_LITE?=1
 
-ifeq ($(CARAVEL_LITE),1) 
+MPW_TAG ?= mpw-5c
+
+ifeq ($(CARAVEL_LITE),1)
 	CARAVEL_NAME := caravel-lite
-	CARAVEL_REPO := https://github.com/efabless/caravel-lite 
-	CARAVEL_TAG := 'mpw-5a'
+	CARAVEL_REPO := https://github.com/efabless/caravel-lite
+	CARAVEL_TAG := $(MPW_TAG)
 else
 	CARAVEL_NAME := caravel
-	CARAVEL_REPO := https://github.com/efabless/caravel 
-	CARAVEL_TAG := 'mpw-5a'
+	CARAVEL_REPO := https://github.com/efabless/caravel
+	CARAVEL_TAG := $(MPW_TAG)
 endif
 
-# Install caravel as submodule, (1): submodule, (0): clone
-SUBMODULE?=1
-
-#RISCV COMPLIANCE test Environment
-COREMARK_DIR   = verilog/dv/riscv_regress/dependencies/coremark
-RISCV_COMP_DIR = verilog/dv/riscv_regress/dependencies/riscv-compliance
-RISCV_TEST_DIR = verilog/dv/riscv_regress/dependencies/riscv-tests
-
-COREMARK_REPO   =  https://github.com/eembc/coremark
-RISCV_COMP_REPO =  https://github.com/riscv/riscv-compliance
-RISCV_TEST_REPO =  https://github.com/riscv/riscv-tests
-
-COREMARK_BRANCH   =  7f420b6bdbff436810ef75381059944e2b0d79e8
-RISCV_COMP_BRANCH =  d51259b2a949be3af02e776c39e135402675ac9b
-RISCV_TEST_BRANCH =  e30978a71921159aec38eeefd848fca4ed39a826
-
 # Include Caravel Makefile Targets
 .PHONY: % : check-caravel
-%: 
+%:
 	export CARAVEL_ROOT=$(CARAVEL_ROOT) && $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
 
-# Verify Target for running simulations
-.PHONY: verify
-verify:
-	cd ./verilog/dv/ && \
-	export SIM=${SIM} DUMP=${DUMP} && \
-		$(MAKE) -j$(THREADS)
+.PHONY: install
+install:
+	if [ -d "$(CARAVEL_ROOT)" ]; then\
+		echo "Deleting exisiting $(CARAVEL_ROOT)" && \
+		rm -rf $(CARAVEL_ROOT) && sleep 2;\
+	fi
+	echo "Installing $(CARAVEL_NAME).."
+	git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT) --depth=1
 
 # Install DV setup
 .PHONY: simenv
 simenv:
 	docker pull riscduino/dv_setup:latest
 
-PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
-DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
-TARGET_PATH=$(shell pwd)
-PDK_PATH=${PDK_ROOT}/sky130A
-VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} && make"
-$(DV_PATTERNS): verify-% : ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo
-	docker run -v ${TARGET_PATH}:${TARGET_PATH} \
-                -e TARGET_PATH=${TARGET_PATH}  \
-                -u $(id -u $$USER):$(id -g $$USER) riscduino/dv_setup:mpw5 \
-                sh -c $(VERIFY_COMMAND)
-				
-# Openlane Makefile Targets
-BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
-.PHONY: $(BLOCKS)
-$(BLOCKS): %:
+.PHONY: setup
+setup: install check-env install_mcw pdk openlane
+
+# Openlane
+blocks=$(shell cd openlane && find * -maxdepth 0 -type d)
+.PHONY: $(blocks)
+$(blocks): % :
 	export CARAVEL_ROOT=$(CARAVEL_ROOT) && cd openlane && $(MAKE) $*
 
-# Install caravel
-.PHONY: install
-install:
-ifeq ($(SUBMODULE),1)
-	@echo "Installing $(CARAVEL_NAME) as a submodule.."
-# Convert CARAVEL_ROOT to relative path because .gitmodules doesn't accept '/'
-	$(eval CARAVEL_PATH := $(shell realpath --relative-to=$(shell pwd) $(CARAVEL_ROOT)))
-	@if [ ! -d $(CARAVEL_ROOT) ]; then git submodule add --name $(CARAVEL_NAME) $(CARAVEL_REPO) $(CARAVEL_PATH); fi
-	@git submodule update --init
-	@cd $(CARAVEL_ROOT); git checkout $(CARAVEL_BRANCH)
-	$(MAKE) simlink
-else
-	@echo "Installing $(CARAVEL_NAME).."
-	@git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT)
-endif
+dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+dv-targets-rtl=$(dv_patterns:%=verify-%-rtl)
+dv-targets-gl=$(dv_patterns:%=verify-%-gl)
+dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf)
+
+TARGET_PATH=$(shell pwd)
+verify_command="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} && make"
+dv_base_dependencies=
+docker_run_verify=\
+	docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
+		-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+		-e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+		-e CARAVEL_ROOT=${CARAVEL_ROOT} \
+		-e TOOLS=/opt/riscv64i \
+		-e DESIGNS=$(TARGET_PATH) \
+		-e CORE_VERILOG_PATH=$(CARAVEL_ROOT)/mgmt_core_wrapper/verilog \
+		-e GCC_PREFIX=riscv64-unknown-elf \
+		-e MCW_ROOT=$(MCW_ROOT) \
+		-u $$(id -u $$USER):$$(id -g $$USER) riscduino/dv_setup:latest \
+		sh -c $(verify_command)
+
+.PHONY: harden
+harden: $(blocks)
+
+.PHONY: verify-all-rtl
+verify-all-rtl: $(dv-targets-rtl)
+
+.PHONY: verify-all-gl
+verify-all-gl: $(dv-targets-gl)
+
+.PHONY: verify-all-gl-sdf
+verify-all-gl-sdf: $(dv-targets-gl-sdf)
+
+$(dv-targets-rtl): SIM=RTL
+$(dv-targets-rtl): verify-%-rtl: $(dv_base_dependencies)
+	$(docker_run_verify)
+
+$(dv-targets-gl): SIM=GL
+$(dv-targets-gl): verify-%-gl: $(dv_base_dependencies)
+	$(docker_run_verify)
+
+$(dv-targets-gl-sdf): SIM=GL_SDF
+$(dv-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies)
+	$(docker_run_verify)
+
+clean-targets=$(blocks:%=clean-%)
+.PHONY: $(clean-targets)
+$(clean-targets): clean-% :
+	rm -f ./verilog/gl/$*.v
+	rm -f ./spef/$*.spef
+	rm -f ./sdc/$*.sdc
+	rm -f ./sdf/$*.sdf
+	rm -f ./gds/$*.gds
+	rm -f ./mag/$*.mag
+	rm -f ./lef/$*.lef
+	rm -f ./maglef/*.maglef
+
+make_what=setup $(blocks) $(dv-targets-rtl) $(dv-targets-gl) $(dv-targets-gl-sdf) $(clean-targets)
+.PHONY: what
+what:
+	# $(make_what)
+
+# Install Openlane
+.PHONY: openlane
+openlane:
+	cd openlane && $(MAKE) openlane
+
+#### Not sure if the targets following are of any use
 
 # Create symbolic links to caravel's main files
 .PHONY: simlink
 simlink: check-caravel
-### Symbolic links relative path to $CARAVEL_ROOT 
+### Symbolic links relative path to $CARAVEL_ROOT
 	$(eval MAKEFILE_PATH := $(shell realpath --relative-to=openlane $(CARAVEL_ROOT)/openlane/Makefile))
 	$(eval PIN_CFG_PATH  := $(shell realpath --relative-to=openlane/user_project_wrapper $(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/pin_order.cfg))
 	mkdir -p openlane
@@ -118,29 +158,26 @@
 
 # Uninstall Caravel
 .PHONY: uninstall
-uninstall: 
+uninstall:
 	rm -rf $(CARAVEL_ROOT)
 
-# Install Openlane
-.PHONY: openlane
-openlane: 
-	cd openlane && $(MAKE) openlane
 
 # Install Pre-check
 # Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
 .PHONY: precheck
 precheck:
-	@git clone --depth=1 --branch mpw-5 https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
-	@docker pull efabless/mpw_precheck:mpw5
+	@git clone --depth=1 --branch mpw-5a https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT)
+	@docker pull efabless/mpw_precheck:latest
 
 .PHONY: run-precheck
-run-precheck: check-precheck check-pdk check-caravel
+run-precheck: check-pdk check-precheck
 	$(eval INPUT_DIRECTORY := $(shell pwd))
 	cd $(PRECHECK_ROOT) && \
-	docker run -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) \
-	-u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --pdk_root $(PDK_ROOT) --input_directory $(INPUT_DIRECTORY)"
+	docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) \
+	-u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_root $(PDK_ROOT)"
 
-# Clean 
+
+
 .PHONY: clean
 clean:
 	cd ./verilog/dv/ && \
@@ -164,27 +201,6 @@
 		exit 1; \
 	fi
 
-check-coremark_repo:
-	@if [ ! -d "$(COREMARK_DIR)" ]; then \
-		echo "Installing Core Mark Repo.."; \
-		git clone $(COREMARK_REPO) $(COREMARK_DIR); \
-		cd $(COREMARK_DIR); git checkout $(COREMARK_BRANCH); \
-	fi
-
-check-riscv_comp_repo:
-	@if [ ! -d "$(RISCV_COMP_DIR)" ]; then \
-		echo "Installing Risc V Complance Repo.."; \
-		git clone $(RISCV_COMP_REPO) $(RISCV_COMP_DIR); \
-		cd $(RISCV_COMP_DIR); git checkout $(RISCV_COMP_BRANCH); \
-	fi
-
-check-riscv_test_repo:
-	@if [ ! -d "$(RISCV_TEST_DIR)" ]; then \
-		echo "Installing RiscV Test Repo.."; \
-		git clone $(RISCV_TEST_REPO) $(RISCV_TEST_DIR); \
-		cd $(RISCV_TEST_DIR); git checkout $(RISCV_TEST_BRANCH); \
-	fi
-
 zip:
 	gzip -f def/*
 	gzip -f lef/*
@@ -205,5 +221,8 @@
 
 .PHONY: help
 help:
-	cd $(CARAVEL_ROOT) && $(MAKE) help 
+	cd $(CARAVEL_ROOT) && $(MAKE) help
 	@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
+
+
+

diff --git a/openlane/Makefile b/openlane/Makefile
index ecdee61..89c9e7f 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile

@@ -31,24 +31,24 @@
 	@exit 1
 
 $(BLOCKS) : % : ./%/config.tcl FORCE
-ifeq ($(OPENLANE_ROOT),)
-	@echo "Please export OPENLANE_ROOT"
-	@exit 1
-endif
-ifeq ($(PDK_ROOT),)
-	@echo "Please export PDK_ROOT"
-	@exit 1
-endif
+#ifeq ($(OPENLANE_ROOT),)
+#	@echo "Please export OPENLANE_ROOT"
+#	@exit 1
+#endif
+#ifeq ($(PDK_ROOT),)
+#	@echo "Please export PDK_ROOT"
+#	@exit 1
+#endif
 	@echo "###############################################"
 	@sleep 1
 
 	@if [ -f ./$*/interactive.tcl ]; then\
-		docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+		docker run -it  \
 		-v $(PWD)/..:/project \
 		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
 		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
 	else\
-		docker run -it -v $(OPENLANE_ROOT):/openLANE_flow \
+		docker run -it  \
 		-v $(PWD)/..:/project \
 		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
 		$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index 954a8a9..eec7126 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl

@@ -120,7 +120,7 @@
 	                met4  125  1750  675   2490, \
 	                met4  125  2645  675   3385, \
 	                met4  125  900   675   1640, \
-	                met4  850  110  1400    850, \
+	                met4  800  110  1350    850, \
 	                met4  850  2645 1400   3385, \
 	                met4  1575 2645 2125   3385 \
 	              "

diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index 8c4c88a..9b2fa9f 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg

@@ -6,10 +6,10 @@
 u_tcm_1KB_mem1          125             2645           N 
 u_riscv_top	        850	        955	       N
 u_icache_1KB_mem0       125             900            N
-u_icache_1KB_mem1       850             110            N
+u_icache_1KB_mem1       800             110            N
 
 u_dcache_1KB_mem0       850             2645           N
 u_dcache_1KB_mem1       1575            2645           N
 
 u_intercon              1850            710            N
-u_wb_host               1750            150            N
+u_wb_host               1750            175            N

diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv
index f0549cd..4e40692 100644
--- a/signoff/pinmux/final_summary_report.csv
+++ b/signoff/pinmux/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h8m38s0ms,0h5m38s0ms,44129.29292929293,0.2475,22064.646464646466,26.19,891.48,5461,0,0,0,0,0,0,0,-1,0,-1,-1,445725,56513,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,349875542.0,0.0,58.45,43.05,33.36,20.01,-1,3480,8519,562,5601,0,0,0,4063,123,107,40,77,933,109,14,285,1086,1034,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h11m36s0ms,0h7m40s0ms,49478.78787878788,0.2475,24739.39393939394,29.44,961.59,6123,0,0,0,0,0,0,0,-1,0,-1,-1,465138,60979,-9.79,-17.09,-1,0.0,0.0,-11322.82,-19533.62,-1,0.0,0.0,369999398.0,0.0,59.87,48.06,30.66,22.85,-1,4043,9507,808,6272,0,0,0,4590,151,83,49,96,1013,154,18,283,1206,1171,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4

diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index 54ca8c7..12bab39 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h30m55s0ms,0h4m38s0ms,-2.0,-1,-1,-1,541.58,12,0,0,0,0,0,0,0,0,0,-1,-1,1395490,6872,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.93,9.0,0.93,0.38,0.0,226,2315,226,2315,0,0,0,12,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,130,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h33m17s0ms,0h4m32s0ms,-2.0,-1,-1,-1,558.4,12,0,0,0,0,0,0,0,0,0,-1,-1,1380862,6682,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.95,8.98,0.73,0.3,0.0,224,2251,224,2251,0,0,0,12,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,130,0.55,0.3,sky130_fd_sc_hd,4,0

diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv
index 0bbe179..53e67f7 100644
--- a/signoff/wb_host/final_summary_report.csv
+++ b/signoff/wb_host/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h5m9s0ms,0h3m24s0ms,61297.47899159664,0.14875,30648.73949579832,37.15,777.15,4559,0,0,0,0,0,0,0,12,0,0,-1,209244,37027,0.0,-0.21,0.0,0.0,0.0,0.0,-17.73,0.0,0.0,0.0,158619913.0,0.0,46.06,48.87,4.05,12.29,-1,3513,6206,1009,3558,0,0,0,3833,380,52,75,186,650,146,23,466,1022,997,11,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4
+0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h5m56s0ms,0h4m0s0ms,61700.84033613445,0.14875,30850.420168067227,37.22,765.37,4589,0,0,0,0,0,0,0,11,0,0,-1,205225,36945,0.0,-0.19,0.0,0.0,0.0,0.0,-23.16,0.0,0.0,0.0,155719018.0,0.0,46.7,45.31,3.63,15.99,-1,3577,6294,1049,3622,0,0,0,3856,373,52,77,183,651,146,23,461,1023,1001,12,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4

diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv
index 5385acd..9172666 100644
--- a/signoff/wb_interconnect/final_summary_report.csv
+++ b/signoff/wb_interconnect/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h40m59s0ms,0h35m23s0ms,37937.5,0.5760000000000001,18968.75,16.98,1388.21,10926,0,0,0,0,0,0,0,-1,0,-1,-1,1075525,94792,-1.53,-3.34,-1,-2.98,-3.4,-106.67,-233.97,-1,-293.74,-303.87,834639052.0,0.0,25.33,47.4,4.97,27.65,-1,3846,12928,637,9716,0,0,0,5341,269,12,304,131,626,98,13,1402,1753,1688,16,1306,7532,0,8838,74.6268656716418,13.4,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,10,4
+0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h40m7s0ms,0h32m41s0ms,37826.38888888888,0.5760000000000001,18913.19444444444,16.95,1428.07,10894,0,0,0,0,0,0,0,-1,0,-1,-1,1010027,91907,-1.53,-3.35,-1,-3.07,-3.34,-106.67,-240.35,-1,-319.27,-324.23,794830726.0,0.0,23.63,45.8,2.76,26.56,-1,3846,12864,637,9652,0,0,0,5341,269,12,304,131,626,98,13,1402,1753,1688,16,1306,7532,0,8838,74.96251874062969,13.34,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,10,4

diff --git a/signoff/yifive/final_summary_report.csv b/signoff/yifive/final_summary_report.csv
index c0b31b8..6933a2d 100644
--- a/signoff/yifive/final_summary_report.csv
+++ b/signoff/yifive/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h8m10s,-1,54876.90223886543,1.2551,27438.451119432713,30.94,1597.95,34438,0,0,0,0,0,0,0,40,0,-1,-1,2726452,382921,-15.47,-41.5,-1,-1.15,-1,-34139.48,-18385.69,-1,-8.8,-1,2033771950.0,21.88,40.38,55.32,5.28,9.71,-1,28675,48362,1777,21057,0,0,0,34227,0,0,0,0,0,0,0,4,8315,8734,55,1116,17360,0,18476,90.9090909090909,11,10,AREA 0,4,50,1,153.6,153.18,0.32,0.0,sky130_fd_sc_hd,4,4
+0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h23m13s,-1,54857.780256553255,1.2551,27428.890128276627,30.93,1595.83,34426,0,0,0,0,0,0,0,28,0,-1,-1,2725161,380767,-15.47,-48.03,-1,-1.08,-1,-34141.95,-19449.1,-1,-6.74,-1,2044017615.0,31.0,39.79,55.63,5.64,9.67,-1,28618,48305,1777,21057,0,0,0,34170,0,0,0,0,0,0,0,4,8283,8734,54,1116,17360,0,18476,90.9090909090909,11,10,AREA 0,4,50,1,153.6,153.18,0.32,0.0,sky130_fd_sc_hd,4,4

diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index c8c838c..8df6ef7 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile

@@ -14,100 +14,225 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-## PDK 
-PDK_PATH = $(PDK_ROOT)/sky130A
 
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+ 
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
 
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_BEHAVIOURAL_MODELS = ../model
-UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
-UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
-UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
-UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
-UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
+# ---- Include Partitioned Makefiles ----
 
-## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
-## RISCV GCC 
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-GCC64_PREFIX?=riscv64-unknown-elf
+CONFIG = caravel_user_project
 
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
+########################################################
+#include $(MCW_ROOT)/verilog/dv/make/env.makefile
+########################################################
+#######################################################################
+## Global Environment Variables for local repo  
+#######################################################################
+
+export PDK_PATH =      $(PDK_ROOT)/sky130A
+export VIP_PATH =      $(CORE_VERILOG_PATH)/dv/vip
+export FIRMWARE_PATH = $(CORE_VERILOG_PATH)/dv/firmware
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+export CARAVEL_VERILOG_PATH ?=  $(CARAVEL_ROOT)/verilog
+export CORE_VERILOG_PATH    ?=  $(CARAVEL_ROOT)/mgmt_core_wrapper/verilog
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+
+export CARAVEL_PATH = $(CARAVEL_VERILOG_PATH)
+export VERILOG_PATH = $(CORE_VERILOG_PATH)
+
+#######################################################################
+## Compiler Information 
+#######################################################################
+
+export TOOLS     ?=  /opt/riscv64i 
+export GCC_PATH  ?=  $(TOOLS)/bin
+export GCC_PREFIX?=  riscv32-unknown-linux-gnu
+
+
+############## USER SPECIFIC DEFINE ##################
+
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+
+######################################################
+
+
+
+
+
+########################################################
+#include $(MCW_ROOT)/verilog/dv/make/var.makefile
+########################################################
+
+CPU=vexriscv
+CPUFAMILY=riscv
+CPUFLAGS=-march=rv32i      -mabi=ilp32 -D__vexriscv__
+CPUENDIANNESS=little
+CLANG=0
+
+
+######################################################
+# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+######################################################
+
+ifeq ($(CPU),picorv32)
+	LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds
+	SOURCE_FILES=$(FIRMWARE_PATH)/start.s 
+	VERILOG_FILES=
+endif
+
+ifeq ($(CPU),ibex)
+	LINKER_SCRIPT=$(FIRMWARE_PATH)/link_ibex.ld
+	SOURCE_FILES=$(FIRMWARE_PATH)/crt0_ibex.S $(FIRMWARE_PATH)/simple_system_common.c
+# 	VERILOG_FILES=../ibex/*
+	VERILOG_FILES=
+endif
+
+ifeq ($(CPU),vexriscv)
+# 	LINKER_SCRIPT=$(FIRMWARE_PATH)/sections_vexriscv.lds
+# 	SOURCE_FILES=$(FIRMWARE_PATH)/start_caravel_vexriscv.s
+	LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds
+	SOURCE_FILES=$(FIRMWARE_PATH)/crt0_vex.S $(FIRMWARE_PATH)/isr.c
+	VERILOG_FILES=
+endif
+
+
+
+#####################################################
+#include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+######################################################
+
+export IVERILOG_DUMPER = fst
+
+# RTL/GL/GL_SDF
 SIM?=RTL
 DUMP?=OFF
 
+
 .SUFFIXES:
 
-PATTERN = risc_boot
 
-all:  ${PATTERN:=.vcd}
+all:  ${BLOCKS:=.vcd} ${BLOCKS:=.lst}
 
-hex:  ${PATTERN:=.hex}
+hex:  ${BLOCKS:=.hex}
 
-vvp:  ${PATTERN:=.vvp}
+#.SUFFIXES:
 
-%.vvp: %_tb.v %.hex
-	${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  user_uart.c -o user_uart.o
-	${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
-	${GCC64_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -o user_uart.elf -N
-	${GCC64_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex
-	${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump
-	rm crt.o user_uart.o
-ifeq ($(SIM),RTL)
-   ifeq ($(DUMP),OFF)
-	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH)  \
-	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-	-I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
-	$< -o $@ 
-   else
-	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH)  \
-	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-	-I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
-	$< -o $@ 
-   endif
-else  
-	iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
-	$< -o $@ 
-endif
+##############################################################################
+# Comiple firmeware
+##############################################################################
+%.elf: %.c $(LINKER_SCRIPT) $(SOURCE_FILES)
+	${GCC_PATH}/${GCC_PREFIX}-gcc -g \
+	-I$(FIRMWARE_PATH) \
+	-I$(VERILOG_PATH)/dv/generated \
+	-I$(VERILOG_PATH)/dv/ \
+	-I$(VERILOG_PATH)/common \
+	  $(CPUFLAGS) \
+	-Wl,-Bstatic,-T,$(LINKER_SCRIPT),--strip-debug \
+	-ffreestanding -nostdlib -o $@ $(SOURCE_FILES) $<
 
-%.vcd: %.vvp
-	vvp $<
-
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s
-	${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
+%.lst: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objdump -d -S $< > $@
 
 %.hex: %.elf
-	${GCC64_PREFIX}-objcopy -O verilog $< $@ 
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
 	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
+	sed -ie 's/@10/@00/g' $@
 
 %.bin: %.elf
 	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+	
+	
+##############################################################################
+# Runing the simulations
+##############################################################################
+
+%.vvp: %_tb.v %.hex
+	${GCC_PATH}/${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  user_uart.c -o user_uart.o
+	${GCC_PATH}/${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
+	${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -o user_uart.elf -N
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex
+	${GCC_PATH}/${GCC_PREFIX}-objdump -D user_uart.elf > user_uart.dump
+	rm crt.o user_uart.o
+
+## RTL
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
+    else  
+	iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
+   endif
+endif 
+
+## GL
+ifeq ($(SIM),GL)
+    ifeq ($(CONFIG),caravel_user_project)
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
+    else
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \
+		-f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $<
+    endif
+endif 
+
+## GL+SDF
+ifeq ($(SIM),GL_SDF)
+    ifeq ($(CONFIG),caravel_user_project)
+		cvc64  +interp \
+		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+		-f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
+		-f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $<
+	else
+		cvc64  +interp \
+		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+		-f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \
+		-f $CARAVEL_PATH/gl/__user_project_wrapper.v $<
+    endif
+endif
+
+%.vcd: %.vvp
+	vvp  $<
+
+# twinwave: RTL-%.vcd GL-%.vcd
+#     twinwave RTL-$@ * + GL-$@ *
+
+check-env:
+ifndef PDK_ROOT
+	$(error PDK_ROOT is undefined, please export it before running make)
+endif
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
+	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
+endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
+# check for efabless style installation
+ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
+SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
+endif
+
 
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+	\rm  -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe
 
 .PHONY: clean hex all
+
+
+
+
+
+

diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index d3af045..bc41e1b 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c

@@ -16,8 +16,8 @@
  */
 
 // This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
+#include <defs.h>
+#include <stub.c>
 #include "../c_func/inc/user_reg_map.h"
 
 // User Project Slaves (0x3000_0000)
@@ -36,7 +36,6 @@
 
 #define GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP   0x1C00
 
-#define SC_SIM_OUTPORT (0xf0000000)
 
 /*
          RiscV Hello World test.
@@ -64,38 +63,36 @@
 	Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
 	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
 	| 001    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 1     | 0       |
-
-	Input: 0000_0001_0000_1111 (0x1800) = GPIO_MODE_USER_STD_BIDIRECTIONAL
-	| DM     | VTRIP | SLOW  | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
-	| 110    | 0     | 0     | 0      | 0      | 0     | 0       | 0       | 0     | 0     | 0       |
 	*/
 
 	/* Set up the housekeeping SPI to be connected internally so	*/
 	/* that external pin changes don't affect it.			*/
 
-	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+    reg_spi_enable = 1;
+    reg_wb_enable = 1;
+	// reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
                                         // connect to housekeeping SPI
 
 	// Connect the housekeeping SPI to the SPI master
 	// so that the CSB line is not left floating.  This allows
 	// all of the GPIO pins to be used for user functions.
-        reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
-        reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
 
+    reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+    reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
 
      /* Apply configuration */
     reg_mprj_xfer = 1;

diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index 766e403..e879f99 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v

@@ -71,13 +71,6 @@
 
 `timescale 1 ns / 1 ps
 
-`define FULL_CHIP_SIM
-
-`include "s25fl256s.sv"
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-`include "mt48lc8m8a2.v"
 `include "uart_agent.v"
 
 module risc_boot_tb;
@@ -133,15 +126,35 @@
         begin
            $dumpfile("simx.vcd");
            $dumpvars(1,risc_boot_tb);
-           $dumpvars(1,risc_boot_tb.u_spi_flash_256mb);
+           //$dumpvars(1,risc_boot_tb.u_spi_flash_256mb);
            //$dumpvars(2,risc_boot_tb.uut);
-           $dumpvars(4,risc_boot_tb.uut.mprj);
-           $dumpvars(0,risc_boot_tb.tb_uart);
+           $dumpvars(1,risc_boot_tb.uut.mprj);
+           $dumpvars(0,risc_boot_tb.uut.mprj.u_wb_host);
+           $dumpvars(1,risc_boot_tb.uut.mprj.u_riscv_top);
+           //$dumpvars(0,risc_boot_tb.tb_uart);
            //$dumpvars(0,risc_boot_tb.u_user_spiflash);
 	   $display("Waveform Dump started");
         end
         `endif
 
+	initial begin
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (80) begin
+			repeat (2000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+		$display("%c[1;31m",27);
+		$display ("##########################################################");
+		`ifdef GL
+			$display ("Monitor: Timeout, Test Risc Boot (GL) Failed");
+		`else
+			$display ("Monitor: Timeout, Test Risc Boot (RTL) Failed");
+		`endif
+		$display ("##########################################################");
+		$display("%c[0m",27);
+		$finish;
+	end
 
         initial
         begin
@@ -156,40 +169,37 @@
         
            #200; // Wait for reset removal
 
-           fork
-	   begin
-          
-	      // Wait for Managment core to boot up 
-	      wait(checkbits == 16'h AB60);
-	      $display("Monitor: Test User Risc Boot Started");
-       
-	      // Wait for user risc core to boot up 
-              repeat (30000) @(posedge clock);  
-              tb_uart.uart_init;
-              tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
-                                             uart_stick_parity, uart_timeout, uart_divisor);
-              
-              for (i=0; i<40; i=i+1)
-              	uart_write_data[i] = $random;
-              
-              
-              
-              fork
-                 begin
-                    for (i=0; i<40; i=i+1)
-                    begin
-                      $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
-                       tb_uart.write_char (uart_write_data[i]);
-                    end
-                 end
-              
-                 begin
-                    for (j=0; j<40; j=j+1)
-                    begin
-                      tb_uart.read_char_chk(uart_write_data[j]);
-                    end
-                 end
-                 join
+		// Wait for Managment core to boot up 
+		wait(checkbits == 16'h AB60);
+		$display("Monitor: Test User Risc Boot Started");
+
+		// Wait for user risc core to boot up 
+		repeat (50000) @(posedge clock);  
+		tb_uart.uart_init;
+		tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, 
+					     uart_stick_parity, uart_timeout, uart_divisor);
+
+		for (i=0; i<40; i=i+1)
+		uart_write_data[i] = $random;
+
+
+
+		fork
+		 begin
+		    for (i=0; i<40; i=i+1)
+		    begin
+		      $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
+		       tb_uart.write_char (uart_write_data[i]);
+		    end
+		 end
+
+		 begin
+		    for (j=0; j<40; j=j+1)
+		    begin
+		      tb_uart.read_char_chk(uart_write_data[j]);
+		    end
+		 end
+		 join
               
                  #100
                  tb_uart.report_status(uart_rx_nu, uart_tx_nu);
@@ -204,28 +214,19 @@
                  if(uart_rx_nu != 40) test_fail = 1;
                  if(tb_uart.err_cnt != 0) test_fail = 1;
         
-	      end
-	      begin
-                   // Loop for TimeOut
-                   repeat (60000) @(posedge clock);
-                		// $display("+1000 cycles");
-                   test_fail = 1;
-              end
-              join_any
-              disable fork; //disable pending fork activity
 
               $display("###################################################");
               if(test_fail == 0) begin
                  `ifdef GL
-                     $display("Monitor: Standalone User UART Test (GL) Passed");
+                     $display("Monitor: Standalone User Risc Boot Test (GL) Passed");
                  `else
-                     $display("Monitor: Standalone User UART Test (RTL) Passed");
+                     $display("Monitor: Standalone User Risc Boot Test (RTL) Passed");
                  `endif
               end else begin
                   `ifdef GL
-                      $display("Monitor: Standalone User UART Test (GL) Failed");
+                      $display("Monitor: Standalone User Risc Boot Test (GL) Failed");
                   `else
-                      $display("Monitor: Standalone User UART Test (RTL) Failed");
+                      $display("Monitor: Standalone User Risc Boot Test (RTL) Failed");
                   `endif
                end
               $display("###################################################");
@@ -358,34 +359,7 @@
 initial begin
 end
 `endif    
-
-
-/**
-//-----------------------------------------------------------------------------
-// RISC IMEM amd DMEM Monitoring TASK
-//-----------------------------------------------------------------------------
-logic [`SCR1_DMEM_AWIDTH-1:0]           core2imem_addr_o_r;           // DMEM address
-logic [`SCR1_DMEM_AWIDTH-1:0]           core2dmem_addr_o_r;           // DMEM address
-logic                                   core2dmem_cmd_o_r;
-
-`define RISC_CORE  test_tb.uut.mprj.u_core.u_riscv_top.i_core_top
-
-always@(posedge `RISC_CORE.clk) begin
-    if(`RISC_CORE.imem2core_req_ack_i && `RISC_CORE.core2imem_req_o)
-          core2imem_addr_o_r <= `RISC_CORE.core2imem_addr_o;
-
-    if(`RISC_CORE.dmem2core_req_ack_i && `RISC_CORE.core2dmem_req_o) begin
-          core2dmem_addr_o_r <= `RISC_CORE.core2dmem_addr_o;
-          core2dmem_cmd_o_r  <= `RISC_CORE.core2dmem_cmd_o;
-    end
-
-    if(`RISC_CORE.imem2core_resp_i !=0)
-          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x Resonse: %x", core2imem_addr_o_r,`RISC_CORE.imem2core_rdata_i,`RISC_CORE.imem2core_resp_i);
-    if((`RISC_CORE.dmem2core_resp_i !=0) && core2dmem_cmd_o_r)
-          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.core2dmem_wdata_o,`RISC_CORE.dmem2core_resp_i);
-    if((`RISC_CORE.dmem2core_resp_i !=0) && !core2dmem_cmd_o_r)
-          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.dmem2core_rdata_i,`RISC_CORE.dmem2core_resp_i);
-end
-*/
 endmodule
+// SSFLASH has 1ps/1ps time scale
+`include "s25fl256s.sv"
 `default_nettype wire

diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index 44caa21..518084f 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v

@@ -73,7 +73,6 @@
 
 `timescale 1 ns / 1 ns
 
-`include "s25fl256s.sv"
 `include "uprj_netlists.v"
 `include "mt48lc8m8a2.v"
 `include "is62wvs1288.v"
@@ -536,4 +535,5 @@
 `endif
 **/
 endmodule
+`include "s25fl256s.sv"
 `default_nettype wire

diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v
index 5b5f7a4..3b4d47a 100644
--- a/verilog/dv/user_qspi/user_qspi_tb.v
+++ b/verilog/dv/user_qspi/user_qspi_tb.v

@@ -79,7 +79,6 @@
 
 `timescale 1 ns / 1 ns
 
-`include "s25fl256s.sv"
 `include "uprj_netlists.v"
 `include "mt48lc8m8a2.v"
 `include "is62wvs1288.v"
@@ -1398,4 +1397,5 @@
 `endif
 **/
 endmodule
+`include "s25fl256s.sv"
 `default_nettype wire

diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index 2961b83..698216c 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v

@@ -74,7 +74,6 @@
 
 `timescale 1 ns / 1 ns
 
-`include "s25fl256s.sv"
 `include "uprj_netlists.v"
 `include "mt48lc8m8a2.v"
 `include "user_reg_map.v"
@@ -397,4 +396,5 @@
 `endif
 **/
 endmodule
+`include "s25fl256s.sv"
 `default_nettype wire

diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index df5f4d6..21a848c 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v

@@ -74,9 +74,7 @@
 
 `timescale 1 ns / 1 ns
 
-`include "s25fl256s.sv"
 `include "uprj_netlists.v"
-`include "mt48lc8m8a2.v"
 `include "uart_agent.v"
 `include "user_reg_map.v"
 
@@ -453,4 +451,5 @@
 `endif
 **/
 endmodule
+`include "s25fl256s.sv"
 `default_nettype wire

diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index c135403..887f270 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile

@@ -14,84 +14,188 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-## PDK 
-PDK_PATH = $(PDK_ROOT)/sky130A
 
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+ 
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
 
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
-UPRJ_BEHAVIOURAL_MODELS = ../
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
-UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
-UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
-UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
-UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
-## RISCV GCC 
-GCC_PATH?=/ef/apps/bin
-GCC_PREFIX?=riscv32-unknown-elf
-GCC64_PREFIX?=riscv64-unknown-elf
+# ---- Include Partitioned Makefiles ----
 
-## Simulation mode: RTL/GL
-SIM_DEFINES = -DFUNCTIONAL -DSIM
+CONFIG = caravel_user_project
+
+########################################################
+#include $(MCW_ROOT)/verilog/dv/make/env.makefile
+########################################################
+#######################################################################
+## Global Environment Variables for local repo  
+#######################################################################
+
+export PDK_PATH =      $(PDK_ROOT)/sky130A
+export VIP_PATH =      $(CORE_VERILOG_PATH)/dv/vip
+export FIRMWARE_PATH = $(CORE_VERILOG_PATH)/dv/firmware
+
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+export CARAVEL_VERILOG_PATH ?=  $(CARAVEL_ROOT)/verilog
+export CORE_VERILOG_PATH    ?=  $(CARAVEL_ROOT)/mgmt_core_wrapper/verilog
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+
+export CARAVEL_PATH = $(CARAVEL_VERILOG_PATH)
+export VERILOG_PATH = $(CORE_VERILOG_PATH)
+
+#######################################################################
+## Compiler Information 
+#######################################################################
+
+export GCC_PATH?=      $(TOOLS)/bin
+export GCC_PREFIX?=    riscv32-unknown-linux-gnu
+
+
+
+
+
+
+
+
+########################################################
+#include $(MCW_ROOT)/verilog/dv/make/var.makefile
+########################################################
+
+CPU=vexriscv
+CPUFAMILY=riscv
+CPUFLAGS=-march=rv32i      -mabi=ilp32 -D__vexriscv__
+CPUENDIANNESS=little
+CLANG=0
+
+
+######################################################
+# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+######################################################
+
+ifeq ($(CPU),picorv32)
+	LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds
+	SOURCE_FILES=$(FIRMWARE_PATH)/start.s 
+	VERILOG_FILES=
+endif
+
+ifeq ($(CPU),ibex)
+	LINKER_SCRIPT=$(FIRMWARE_PATH)/link_ibex.ld
+	SOURCE_FILES=$(FIRMWARE_PATH)/crt0_ibex.S $(FIRMWARE_PATH)/simple_system_common.c
+# 	VERILOG_FILES=../ibex/*
+	VERILOG_FILES=
+endif
+
+ifeq ($(CPU),vexriscv)
+# 	LINKER_SCRIPT=$(FIRMWARE_PATH)/sections_vexriscv.lds
+# 	SOURCE_FILES=$(FIRMWARE_PATH)/start_caravel_vexriscv.s
+	LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds
+	SOURCE_FILES=$(FIRMWARE_PATH)/crt0_vex.S $(FIRMWARE_PATH)/isr.c
+	VERILOG_FILES=
+endif
+
+
+
+#####################################################
+#include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+######################################################
+
+export IVERILOG_DUMPER = fst
+
+# RTL/GL/GL_SDF
 SIM?=RTL
 DUMP?=OFF
 
+
 .SUFFIXES:
 
-PATTERN = wb_port
 
-all:  ${PATTERN:=.vcd}
+all:  ${BLOCKS:=.vcd} ${BLOCKS:=.lst}
 
-hex:  ${PATTERN:=.hex}
+hex:  ${BLOCKS:=.hex}
 
-vvp:  ${PATTERN:=.vvp}
+#.SUFFIXES:
+
+##############################################################################
+# Comiple firmeware
+##############################################################################
+%.elf: %.c $(LINKER_SCRIPT) $(SOURCE_FILES)
+	${GCC_PATH}/${GCC_PREFIX}-gcc -g \
+	-I$(FIRMWARE_PATH) \
+	-I$(VERILOG_PATH)/dv/generated \
+	-I$(VERILOG_PATH)/dv/ \
+	-I$(VERILOG_PATH)/common \
+	  $(CPUFLAGS) \
+	-Wl,-Bstatic,-T,$(LINKER_SCRIPT),--strip-debug \
+	-ffreestanding -nostdlib -o $@ $(SOURCE_FILES) $<
+
+%.lst: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objdump -d -S $< > $@
+
+%.hex: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ 
+	# to fix flash base address
+	sed -ie 's/@10/@00/g' $@
+
+%.bin: %.elf
+	${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+	
+	
+##############################################################################
+# Runing the simulations
+##############################################################################
 
 %.vvp: %_tb.v %.hex
+
+## RTL
 ifeq ($(SIM),RTL)
    ifeq ($(DUMP),OFF)
-	iverilog -g2005-sv $(SIM_DEFINES) -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-	-I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
-	$< -o $@ 
+	iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
     else  
-	iverilog -g2005-sv -DWFDUMP $(SIM_DEFINES) -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-	-I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
-	$< -o $@ 
+	iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
    endif
-else  
-	iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_GL_PATH)  -I$(UPRJ_RTL_PATH)  -I $(UPRJ_VERILOG_PATH) \
-	$< -o $@ 
+endif 
+
+## GL
+ifeq ($(SIM),GL)
+    ifeq ($(CONFIG),caravel_user_project)
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
+    else
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \
+		-f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $<
+    endif
+endif 
+
+## GL+SDF
+ifeq ($(SIM),GL_SDF)
+    ifeq ($(CONFIG),caravel_user_project)
+		cvc64  +interp \
+		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+		-f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
+		-f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $<
+	else
+		cvc64  +interp \
+		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+		-f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \
+		-f $CARAVEL_PATH/gl/__user_project_wrapper.v $<
+    endif
 endif
 
 %.vcd: %.vvp
-	vvp $<
+	vvp  $<
 
-%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s 
-	${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $<
-
-%.hex: %.elf
-	${GCC64_PREFIX}-objcopy -O verilog $< $@ 
-	# to fix flash base address
-	sed -i 's/@10000000/@00000000/g' $@
-
-%.bin: %.elf
-	${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+# twinwave: RTL-%.vcd GL-%.vcd
+#     twinwave RTL-$@ * + GL-$@ *
 
 check-env:
 ifndef PDK_ROOT
@@ -100,17 +204,24 @@
 ifeq (,$(wildcard $(PDK_ROOT)/sky130A))
 	$(error $(PDK_ROOT)/sky130A not found, please install pdk before running make)
 endif
-#ifeq (,$(wildcard $(GCC64_PREFIX)-gcc ))
-#	$(error $(GCC64_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
-#endif
+ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc ))
+	$(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make)
+endif
 # check for efabless style installation
 ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
 SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE
 endif
 
+
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+	\rm  -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe
 
 .PHONY: clean hex all
+
+
+
+
+
+

diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index f776eb4..4250a62 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c

@@ -16,8 +16,8 @@
  */
 
 // This include is relative to $CARAVEL_PATH (see Makefile)
-#include "verilog/dv/caravel/defs.h"
-#include "verilog/dv/caravel/stub.c"
+#include <defs.h>
+#include <stub.c>
 #include "../c_func/inc/user_reg_map.h"
 
 // User Project Slaves (0x3000_0000)
@@ -57,7 +57,9 @@
 	/* Set up the housekeeping SPI to be connected internally so	*/
 	/* that external pin changes don't affect it.			*/
 
-	reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
+    reg_spi_enable = 1;
+    reg_wb_enable = 1;
+	// reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
                                         // connect to housekeeping SPI
 
 	// Connect the housekeeping SPI to the SPI master

diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index 5f7e8a7..fdbbf92 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v

@@ -17,12 +17,6 @@
 
 `timescale 1 ns / 1 ps
 
-`define FULL_CHIP_SIM
-
-`include "uprj_netlists.v"
-`include "caravel_netlists.v"
-`include "spiflash.v"
-
 module wb_port_tb;
 	reg clock;
 	reg RSTB;
@@ -64,7 +58,7 @@
 
 		// Repeat cycles of 1000 clock edges as needed to complete testbench
 		repeat (30) begin
-			repeat (1000) @(posedge clock);
+			repeat (2000) @(posedge clock);
 			// $display("+1000 cycles");
 		end
 		$display("%c[1;31m",27);

diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
new file mode 100644
index 0000000..cbeda71
--- /dev/null
+++ b/verilog/includes/includes.rtl.caravel_user_project

@@ -0,0 +1,107 @@
+# Caravel user project includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/includes
++incdir+$(USER_PROJECT_VERILOG)/dv/model
++incdir+$(USER_PROJECT_VERILOG)/dv/agents
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_if.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_regs.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_clkgen.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_ctrl.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_rx.sv
+-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_tx.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_core.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_cfg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_rxfsm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_txfsm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo_th.sv  
+-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv  
+-v $(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v  
+-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_buf.v  
+-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_bit_ctrl.v
+-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_byte_ctrl.v
+-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_top.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_core.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc16.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc5.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_sie.sv
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_fs_phy.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_transceiver.v
+-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/top/usb1_host.sv
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_top.sv  
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_ctl.sv  
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_if.sv
+-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_cfg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv  
+-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v
+-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v
+-v $(USER_PROJECT_VERILOG)/rtl/lib/ser_inf_32b.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/ser_shift.sv
+-v $(USER_PROJECT_VERILOG)/rtl/digital_core/src/glbl_cfg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_host.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/async_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_wbb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo2.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_slave_port.sv
+-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_interconnect.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_hdu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_tdu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_ipic.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_csr.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_exu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_ialu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_idu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_ifu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_lsu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_mprf.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_mul.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_div.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/primitives/ycr1_reset_cells.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/primitives/ycr1_cg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_clk_ctrl.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_tapc_shift_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_tapc.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_tapc_synchronizer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_core_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_dm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_dmi.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_scu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_imem_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_dmem_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_dp_memory.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_tcm_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_timer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_dmem_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_imem_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_intf.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_top_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_icache_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_dcache_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/icache_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/dcache_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/lib/ycr1_async_wbb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/lib/ycr1_arb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo.sv
+-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv 
+-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv 
+-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart_msg_handler.v 
+-v $(USER_PROJECT_VERILOG)/rtl/lib/async_reg_bus.sv
+-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
+-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv
+-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv

diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index 94217f7..2fb66d0 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv

@@ -150,9 +150,9 @@
 // Timer Register                          
 // -------------------------------------------------------
 logic [2:0]    cfg_timer_update        ; // CPU write to timer register
-logic [18:0]   cfg_timer0              ; // Timer-0 register
-logic [18:0]   cfg_timer1              ; // Timer-1 register
-logic [18:0]   cfg_timer2              ; // Timer-2 register
+logic [31:0]   cfg_timer0              ; // Timer-0 register
+logic [31:0]   cfg_timer1              ; // Timer-1 register
+logic [31:0]   cfg_timer2              ; // Timer-2 register
 logic [2:0]    timer_intr              ;
 
 //---------------------------------------------------

diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index c0aab56..a5738c8 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv

@@ -255,7 +255,7 @@
 wb_arb u_arb(
 	.clk      (wbm_clk_i), 
 	.rstn     (wbm_rst_n), 
-	.req      ({1'b0,wbm_uart_stb_i,(wbm_stb_i & wbm_cyc_i)}), 
+	.req      ({2'b0,wbm_uart_stb_i,(wbm_stb_i & wbm_cyc_i)}), 
 	.gnt      (grnt)
         );