Uart increased to 2 and sspi cs# to 4
diff --git a/openlane/Makefile b/openlane/Makefile index 89c9e7f..e2e91a5 100644 --- a/openlane/Makefile +++ b/openlane/Makefile
@@ -31,14 +31,6 @@ @exit 1 $(BLOCKS) : % : ./%/config.tcl FORCE -#ifeq ($(OPENLANE_ROOT),) -# @echo "Please export OPENLANE_ROOT" -# @exit 1 -#endif -#ifeq ($(PDK_ROOT),) -# @echo "Please export PDK_ROOT" -# @exit 1 -#endif @echo "###############################################" @sleep 1 @@ -58,17 +50,6 @@ cp $*/runs/$*/PDK_SOURCES ../signoff/$*/ cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/ -.PHONY: openlane -openlane: -ifeq ($(OPENLANE_ROOT),) - @echo "Please export OPENLANE_ROOT" - @exit 1 -endif - git clone https://github.com/efabless/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \ - cd $(OPENLANE_ROOT) && \ - export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \ - make openlane - FORCE: clean:
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg index 4c64993..2ff62e6 100644 --- a/openlane/pinmux/pin_order.cfg +++ b/openlane/pinmux/pin_order.cfg
@@ -8,11 +8,26 @@ cpu_intf_rst_n qspim_rst_n sspim_rst_n -uart_rst_n +uart_rst_n\[1\] +uart_rst_n\[0\] i2cm_rst_n usb_rst_n -cfg_riscv_debug_sel\[1\] -cfg_riscv_debug_sel\[0\] +cfg_riscv_ctrl\[15\] +cfg_riscv_ctrl\[14\] +cfg_riscv_ctrl\[13\] +cfg_riscv_ctrl\[12\] +cfg_riscv_ctrl\[11\] +cfg_riscv_ctrl\[10\] +cfg_riscv_ctrl\[9\] +cfg_riscv_ctrl\[8\] +cfg_riscv_ctrl\[7\] +cfg_riscv_ctrl\[6\] +cfg_riscv_ctrl\[5\] +cfg_riscv_ctrl\[4\] +cfg_riscv_ctrl\[3\] +cfg_riscv_ctrl\[2\] +cfg_riscv_ctrl\[1\] +cfg_riscv_ctrl\[0\] user_irq\[0\] user_irq\[1\] user_irq\[2\] @@ -21,8 +36,10 @@ usb_oen usb_dp_i usb_dn_i -uart_txd -uart_rxd +uart_txd\[1\] +uart_rxd\[1\] +uart_txd\[0\] +uart_rxd\[0\] i2cm_clk_o i2cm_clk_i i2cm_clk_oen @@ -30,7 +47,10 @@ i2cm_data_o i2cm_data_i spim_sck -spim_ss +spim_ssn\[3\] +spim_ssn\[2\] +spim_ssn\[1\] +spim_ssn\[0\] spim_miso spim_mosi pulse1m_mclk
diff --git a/openlane/uart_i2cm_usb_spi_top/base.sdc b/openlane/uart_i2cm_usb_spi_top/base.sdc index 36725cd..735b5fb 100644 --- a/openlane/uart_i2cm_usb_spi_top/base.sdc +++ b/openlane/uart_i2cm_usb_spi_top/base.sdc
@@ -7,7 +7,8 @@ # Timing Constraints ############################################################################### create_clock -name app_clk -period 10.0000 [get_ports {app_clk}] -create_clock -name line_clk -period 100.0000 [get_pins {u_uart_core.u_lineclk_buf.u_mux/X}] +create_clock -name uart0_baud_clk -period 100.0000 [get_pins {u_uart0_core.u_lineclk_buf.u_mux/X}] +create_clock -name uart1_baud_clk -period 100.0000 [get_pins {u_uart1_core.u_lineclk_buf.u_mux/X}] create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}] set_clock_transition 0.1500 [all_clocks] @@ -19,7 +20,8 @@ set_clock_groups -name async_clock -asynchronous \ -group [get_clocks {app_clk}]\ -group [get_clocks {usb_clk}]\ - -group [get_clocks {line_clk}] -comment {Async Clock group} + -group [get_clocks {uart0_baud_clk}]\ + -group [get_clocks {uart1_baud_clk}] -comment {Async Clock group} ### ClkSkew Adjust set_case_analysis 0 [get_ports {cfg_cska_uart[0]}]
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl index 48ac117..2627452 100644 --- a/openlane/uart_i2cm_usb_spi_top/config.tcl +++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -90,7 +90,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) "absolute" -set ::env(DIE_AREA) [list 0.0 0.0 500.0 700.0] +set ::env(DIE_AREA) [list 0.0 0.0 510.0 725.0]
diff --git a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg b/openlane/uart_i2cm_usb_spi_top/pin_order.cfg index 3fc5625..aba1684 100644 --- a/openlane/uart_i2cm_usb_spi_top/pin_order.cfg +++ b/openlane/uart_i2cm_usb_spi_top/pin_order.cfg
@@ -12,6 +12,7 @@ reg_cs 0100 0 2 reg_wr +reg_addr\[8\] reg_addr\[7\] reg_addr\[6\] reg_addr\[5\] @@ -94,7 +95,8 @@ #S usb_clk -uart_rstn +uart_rstn\[1] +uart_rstn\[0] i2c_rstn usb_rstn @@ -106,8 +108,10 @@ sda_pad_i sda_pad_o sda_padoen_o -uart_rxd -uart_txd +uart_rxd\[0\] +uart_txd\[0\] +uart_rxd\[1\] +uart_txd\[1\] usb_in_dp usb_in_dn usb_out_dp @@ -121,7 +125,10 @@ sspim_sck sspim_si sspim_so -sspim_ssn +sspim_ssn\[3\] +sspim_ssn\[2\] +sspim_ssn\[1\] +sspim_ssn\[0\]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index eec7126..c1e47ab 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -16,7 +16,6 @@ # Base Configurations. Don't Touch # section begin -set ::env(PDK) "sky130A" set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" # YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS @@ -115,6 +114,7 @@ # set ::env(VDD_PIN) "vccd1" set ::env(GND_PIN) "vssd1" +set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0" set ::env(GLB_RT_OBS) " met5 0 0 2920 3520, \ met4 125 1750 675 2490, \ @@ -125,7 +125,6 @@ met4 1575 2645 2125 3385 \ " -set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0" #set ::env(FP_PDN_MACRO_HOOKS) " \ # u_intercon vccd1 vssd1 \
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index 097c11b..2b03cd9 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -70,7 +70,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 320 1800" +set ::env(DIE_AREA) "0 0 300 1725" # If you're going to use multiple power domains, then keep this disabled. @@ -82,7 +82,7 @@ set ::env(PL_TIME_DRIVEN) 1 set ::env(PL_TARGET_DENSITY) "0.20" -set ::env(CELL_PAD) "10" +set ::env(CELL_PAD) "8" # helps in anteena fix set ::env(USE_ARC_ANTENNA_CHECK) "0"
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index f4bd653..cca8e25 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -621,6 +621,7 @@ s1_wbd_stb_o 0800 0 2 s1_wbd_we_o +s1_wbd_adr_o\[8\] s1_wbd_adr_o\[7\] s1_wbd_adr_o\[6\] s1_wbd_adr_o\[5\]
diff --git a/openlane/yifive/pin_order.cfg b/openlane/yifive/pin_order.cfg index 0fbd01f..c2fb874 100644 --- a/openlane/yifive/pin_order.cfg +++ b/openlane/yifive/pin_order.cfg
@@ -20,7 +20,10 @@ irq_lines\[3\] irq_lines\[2\] irq_lines\[1\] -irq_lines\[0\] +irq_lines\[0\] +cfg_cache_ctrl\[2\] +cfg_cache_ctrl\[1\] +cfg_cache_ctrl\[0\] cfg_cska_riscv\[3\] cfg_cska_riscv\[2\]
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv index 4e40692..c89b8c1 100644 --- a/signoff/pinmux/final_summary_report.csv +++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h11m36s0ms,0h7m40s0ms,49478.78787878788,0.2475,24739.39393939394,29.44,961.59,6123,0,0,0,0,0,0,0,-1,0,-1,-1,465138,60979,-9.79,-17.09,-1,0.0,0.0,-11322.82,-19533.62,-1,0.0,0.0,369999398.0,0.0,59.87,48.06,30.66,22.85,-1,4043,9507,808,6272,0,0,0,4590,151,83,49,96,1013,154,18,283,1206,1171,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4 +0,/project/openlane/pinmux,pinmux,pinmux,flow completed,0h17m45s0ms,0h12m53s0ms,49486.86868686869,0.2475,24743.434343434346,29.48,917.81,6124,0,0,0,0,0,0,0,-1,0,-1,-1,483164,61636,-9.79,-17.46,-1,0.0,0.0,-11345.75,-19773.69,-1,0.0,0.0,383662660.0,0.0,61.73,48.44,33.8,24.46,-1,4054,9557,810,6313,0,0,0,4601,152,83,49,97,1014,154,18,287,1210,1172,11,314,3259,0,3573,100.0,10.0,10,AREA 0,4,50,1,100,100,0.3,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION new file mode 100644 index 0000000..80c7664 --- /dev/null +++ b/signoff/qspim_top/OPENLANE_VERSION
@@ -0,0 +1 @@ +openlane N/A
diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES new file mode 100644 index 0000000..22e7dc1 --- /dev/null +++ b/signoff/qspim_top/PDK_SOURCES
@@ -0,0 +1,3 @@ +openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f +skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb +open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
diff --git a/signoff/qspim_top/final_summary_report.csv b/signoff/qspim_top/final_summary_report.csv new file mode 100644 index 0000000..3b910a0 --- /dev/null +++ b/signoff/qspim_top/final_summary_report.csv
@@ -0,0 +1,2 @@ +,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY +0,/project/openlane/qspim_top,qspim_top,qspim_top,flow completed,0h19m49s0ms,0h14m3s0ms,65696.9696969697,0.2475,32848.48484848485,37.92,1031.26,8130,0,0,0,0,0,0,0,-1,0,-1,-1,419590,71747,-0.55,-5.04,-1,0.0,0.0,-21.45,-1943.78,-1,0.0,0.0,256460720.0,0.0,50.47,49.05,23.05,22.36,-1,7374,11038,803,4466,0,0,0,8348,263,96,195,114,1420,214,34,1460,1553,1517,17,388,3234,0,3622,100.0,10.0,10,AREA 0,4,50,1,100,100,0.42,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv b/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv index d98fd15..ca6c2a3 100644 --- a/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv +++ b/signoff/uart_i2cm_usb_spi_top/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/uart_i2cm_usb_spi_top,uart_i2c_usb_spi_top,uart_i2cm_usb_spi_top,flow completed,0h18m2s0ms,0h13m15s0ms,69285.71428571429,0.35,34642.857142857145,39.21,1430.34,12125,0,0,0,0,0,0,0,-1,0,-1,-1,594439,103896,0.0,0.0,0.0,0.0,-0.02,0.0,0.0,0.0,0.0,-0.02,369917177.0,0.0,51.11,51.47,19.26,22.98,-1,8702,13067,1552,5853,0,0,0,9824,392,189,256,272,2200,354,88,807,2409,2348,18,498,4643,0,5141,99.8003992015968,10.02,10,AREA 0,4,50,1,100,100,0.45,0.3,sky130_fd_sc_hd,4,4 +0,/project/openlane/uart_i2cm_usb_spi_top,uart_i2c_usb_spi_top,uart_i2cm_usb_spi_top,flow completed,0h30m23s0ms,0h22m25s0ms,78025.69303583504,0.36975,39012.84651791752,44.35,1490.59,14425,0,0,0,0,0,0,0,-1,0,-1,-1,702950,122604,0.0,-0.0,0.0,0.0,0.0,0.0,-0.0,0.0,0.0,0.0,442593619.0,0.0,56.86,57.94,21.95,25.41,-1,10340,15543,1940,7056,0,0,0,11580,425,250,279,358,2406,481,113,1133,2832,2749,18,516,4940,0,5456,100.0,10.0,10,AREA 0,4,50,1,100,100,0.45,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index 12bab39..02c41ae 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h33m17s0ms,0h4m32s0ms,-2.0,-1,-1,-1,558.4,12,0,0,0,0,0,0,0,0,0,-1,-1,1380862,6682,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.95,8.98,0.73,0.3,0.0,224,2251,224,2251,0,0,0,12,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,130,0.55,0.3,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h31m15s0ms,0h4m59s0ms,-2.0,-1,-1,-1,544.62,12,0,0,0,0,0,0,0,0,0,-1,-1,1400075,6719,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.97,8.98,0.79,0.41,0.0,228,2283,228,2283,0,0,0,12,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,130,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv index 53e67f7..4d5ce7a 100644 --- a/signoff/wb_host/final_summary_report.csv +++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h5m56s0ms,0h4m0s0ms,61700.84033613445,0.14875,30850.420168067227,37.22,765.37,4589,0,0,0,0,0,0,0,11,0,0,-1,205225,36945,0.0,-0.19,0.0,0.0,0.0,0.0,-23.16,0.0,0.0,0.0,155719018.0,0.0,46.7,45.31,3.63,15.99,-1,3577,6294,1049,3622,0,0,0,3856,373,52,77,183,651,146,23,461,1023,1001,12,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4 +0,/project/openlane/wb_host,wb_host,wb_host,flow completed,0h5m18s0ms,0h3m32s0ms,61700.84033613445,0.14875,30850.420168067227,37.22,773.48,4589,0,0,0,0,0,0,0,11,0,0,-1,205225,36945,0.0,-0.19,0.0,0.0,0.0,0.0,-23.16,0.0,0.0,0.0,155719018.0,0.0,46.7,45.31,3.63,15.99,-1,3577,6294,1049,3622,0,0,0,3856,373,52,77,183,651,146,23,461,1023,1001,12,296,1950,0,2246,100.0,10.0,10,AREA 0,4,50,1,100,100,0.38,0.3,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv index 9172666..4dc0381 100644 --- a/signoff/wb_interconnect/final_summary_report.csv +++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h40m7s0ms,0h32m41s0ms,37826.38888888888,0.5760000000000001,18913.19444444444,16.95,1428.07,10894,0,0,0,0,0,0,0,-1,0,-1,-1,1010027,91907,-1.53,-3.35,-1,-3.07,-3.34,-106.67,-240.35,-1,-319.27,-324.23,794830726.0,0.0,23.63,45.8,2.76,26.56,-1,3846,12864,637,9652,0,0,0,5341,269,12,304,131,626,98,13,1402,1753,1688,16,1306,7532,0,8838,74.96251874062969,13.34,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,10,4 +0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow completed,0h27m17s0ms,0h19m55s0ms,42171.98067632851,0.5175,21085.990338164254,18.97,1292.36,10912,0,0,0,0,0,0,0,-1,0,-1,-1,957798,90676,-1.37,-3.26,-1,-2.8,-2.95,-101.7,-207.95,-1,-256.77,-245.67,793379352.0,0.0,22.26,51.14,2.73,26.86,-1,3853,12872,637,9653,0,0,0,5356,272,12,304,131,628,98,13,1407,1758,1694,17,1252,6908,0,8160,77.22007722007723,12.95,10,AREA 0,2,50,1,153.6,153.18,0.2,0,sky130_fd_sc_hd,8,4
diff --git a/signoff/yifive/final_summary_report.csv b/signoff/yifive/final_summary_report.csv index 6933a2d..9ce9289 100644 --- a/signoff/yifive/final_summary_report.csv +++ b/signoff/yifive/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h23m13s,-1,54857.780256553255,1.2551,27428.890128276627,30.93,1595.83,34426,0,0,0,0,0,0,0,28,0,-1,-1,2725161,380767,-15.47,-48.03,-1,-1.08,-1,-34141.95,-19449.1,-1,-6.74,-1,2044017615.0,31.0,39.79,55.63,5.64,9.67,-1,28618,48305,1777,21057,0,0,0,34170,0,0,0,0,0,0,0,4,8283,8734,54,1116,17360,0,18476,90.9090909090909,11,10,AREA 0,4,50,1,153.6,153.18,0.32,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h23m37s,-1,54940.642179905975,1.2551,27470.321089952988,30.97,1607.58,34478,0,0,0,0,0,0,0,33,0,-1,-1,2753267,389772,-15.47,-48.52,-1,-1.05,-1,-34117.75,-19828.04,-1,-6.64,-1,2065115550.0,17.89,40.67,58.45,4.63,5.31,-1,28633,48324,1779,21063,0,0,0,34183,0,0,0,0,0,0,0,4,8286,8734,54,1116,17360,0,18476,90.9090909090909,11,10,AREA 0,4,50,1,153.6,153.18,0.32,0.0,sky130_fd_sc_hd,4,4
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index 6deeae1..f84307f 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -19,10 +19,10 @@ create_clock -name cpu_clk -period 20.0000 [get_pins {mprj/u_wb_host/cpu_clk}] create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_wb_host/rtc_clk}] create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_wb_host/usb_clk}] -create_clock -name uarts_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart_core.u_lineclk_buf.u_mux/X}] +create_clock -name uarts0_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.u_mux/X}] +create_clock -name uarts1_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.u_mux/X}] create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.u_mux/X}] -create_generated_clock -name spi_clk -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 2 -comment {Spi Clock} [get_ports mprj_io[24]] ## Case analysis @@ -76,7 +76,8 @@ -group [get_clocks {cpu_ref_clk}]\ -group [get_clocks {rtc_clk}]\ -group [get_clocks {usb_clk}]\ - -group [get_clocks {uarts_clk}]\ + -group [get_clocks {uarts0_clk}]\ + -group [get_clocks {uarts1_clk}]\ -group [get_clocks {uartm_clk}]\ -comment {Async Clock group} @@ -131,24 +132,6 @@ set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io0}] set_output_delay $output_delay_value -clock [get_clocks {clock}] -add_delay [get_ports {flash_io1}] -################################################################################ -## User SPI constraints -## Reducing the Tight SPI spec -## As spi cs# asserted atleast 2 cycle before transaction, we are not constrainting it -## In Spi Interace Data lanuch by negedge and capture at Posedge, So effective Interface hold and setup should not be -## any issue. Any timing issue, we need to reduce the SPI interface clock -################################################################################## -# -#set user_spi_out [list mprj_io[29] mprj_io[30] mprj_io[31] mprj_io[32]] -#set user_spi_in [list mprj_io[29] mprj_io[30] mprj_io[31] mprj_io[32]] -# -#set_input_delay -clock spi_clk -clock_fall -min 0 -add_delay $user_spi_in -#set_input_delay -clock spi_clk -clock_fall -max 10 -add_delay $user_spi_in -# -#set_output_delay -clock spi_clk -clock_fall -min -0 -add_delay $user_spi_out -#set_output_delay -clock spi_clk -clock_fall -max 10 -add_delay $user_spi_out - - set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design] ## Set system monitoring mux select to zero so that the clock/user_clk monitoring is disabled
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 384be25..ca64f10 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = wb_port risc_boot user_risc_boot user_uart user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master +PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/agents/uart_agent.v b/verilog/dv/agents/uart_agent.v index 72121e9..9d647c8 100644 --- a/verilog/dv/agents/uart_agent.v +++ b/verilog/dv/agents/uart_agent.v
@@ -14,6 +14,10 @@ // limitations under the License. // SPDX-License-Identifier: Apache-2.0 // SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +// + +`timescale 1ns/1ps + module uart_agent ( mclk, txd,
diff --git a/verilog/dv/model/is62wvs1288.v b/verilog/dv/model/is62wvs1288.v index c938977..37bf718 100644 --- a/verilog/dv/model/is62wvs1288.v +++ b/verilog/dv/model/is62wvs1288.v
@@ -43,7 +43,8 @@ // module is62wvs1288 #( - parameter mem_file_name = "firmware.hex" + //parameter mem_file_name = "firmware.hex" + parameter mem_file_name = "none" )( input csb, input clk,
diff --git a/verilog/dv/model/spiram.v b/verilog/dv/model/spiram.v new file mode 100644 index 0000000..cd33c11 --- /dev/null +++ b/verilog/dv/model/spiram.v
@@ -0,0 +1,329 @@ +`default_nettype none +/* + * SPDX-FileCopyrightText: 2022 <Dinesh Annayya> + * + * Riscdunio + * + * Copyright (C) 2022 Dinesh Annayya <dinesha.opencore.org> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * SPDX-License-Identifier: ISC + */ + +`timescale 1 ns / 1 ps + +// +// Simple SPI Ram simulation model for 128Kx8 LOW VOLTAGE, FAST SERIAL SRAM +// (IS62/65WVS1288GALL) +// +// This model samples io input signals 1ns before the SPI clock edge and +// updates output signals 1ns after the SPI clock edge. +// +// Supported commands: +// 0x03, 0x02, 0x3B , 0x38, 0xFF, 0x05 , 0x01 +// Instruction Hex Description +// READ 0x03 Read data from memory array beginning at selected address +// WRITE 0x02 Write data to memory array beginning at selected address +// ESDI 0x3B Enter SDI mode +// ESQI 0x38 Enter SQI mode +// RSTDQI 0xFF Reset SDI/SQI mode +// RDMR 0x05 Read Mode Register +// WRMR 0x01 Write Mode Register +// + +module spiram #( + parameter mem_file_name = "firmware.hex" +)( + input csb, + input clk, + inout io0, // MOSI + inout io1, // MISO + inout io2, + inout io3 +); + localparam verbose = 0; + localparam integer latency = 8; + + reg [7:0] buffer; + reg [3:0] reset_count = 0; + reg [3:0] reset_monitor = 0; + integer bitcount = 0; + integer bytecount = 0; + integer dummycount = 0; + + reg [7:0] spi_cmd; + reg [23:0] spi_addr; + + reg [7:0] spi_in; + reg [7:0] spi_out; + reg spi_io_vld; + + + localparam [1:0] sspi = 1; + localparam [1:0] dspi = 2; + localparam [1:0] qspi = 3; + + localparam [3:0] mode_sspi_rd = 1; + localparam [3:0] mode_sspi_wr = 2; + localparam [3:0] mode_dspi_rd = 3; + localparam [3:0] mode_dspi_wr = 4; + localparam [3:0] mode_qspi_rd = 5; + localparam [3:0] mode_qspi_wr = 6; + + reg [3:0] spi_phase = mode_sspi_rd; + reg [3:0] spi_data_phase = 0; + reg [3:0] spi_mode = sspi; + + reg io0_oe = 0; + reg io1_oe = 0; + reg io2_oe = 0; + reg io3_oe = 0; + + reg io0_dout = 0; + reg io1_dout = 0; + reg io2_dout = 0; + reg io3_dout = 0; + + assign #1 io0 = io0_oe ? io0_dout : 1'bz; + assign #1 io1 = io1_oe ? io1_dout : 1'bz; + assign #1 io2 = io2_oe ? io2_dout : 1'bz; + assign #1 io3 = io3_oe ? io3_dout : 1'bz; + + wire io0_delayed; + wire io1_delayed; + wire io2_delayed; + wire io3_delayed; + + assign #1 io0_delayed = io0; + assign #1 io1_delayed = io1; + assign #1 io2_delayed = io2; + assign #1 io3_delayed = io3; + + // 128KB RAM + reg [7:0] memory [0:128*1024-1]; + + initial begin + if (!(mem_file_name == "none")) + $readmemh(mem_file_name,memory); + end + + task spi_action; + begin + spi_in = buffer; + + if (bytecount == 1) begin + spi_cmd = buffer; + + if (spi_cmd == 8'h 3b) begin + spi_mode = dspi; + end + + if (spi_cmd == 8'h 38) begin + spi_mode = qspi; + end + + if (spi_cmd == 8'h ff) begin + spi_mode = sspi; + end + + // spi read + if (spi_cmd == 8'h 03 && spi_mode == sspi) + spi_phase = mode_sspi_rd; + + // spi write + if (spi_cmd == 8'h 02 && spi_mode == sspi) + spi_phase = mode_sspi_wr; + + // dual spi read + if (spi_cmd == 8'h 03 && spi_mode == dspi) + spi_phase = mode_dspi_rd; + + // dual spi write + if (spi_cmd == 8'h 02 && spi_mode == dspi) + spi_phase = mode_dspi_wr; + + // quad spi read + if (spi_cmd == 8'h 03 && spi_mode == qspi) + spi_phase = mode_qspi_rd; + + // quad spi write + if (spi_cmd == 8'h 02 && spi_mode == qspi) + spi_phase = mode_qspi_wr; + end + + if (spi_cmd == 'h 03 || (spi_cmd == 'h 02)) begin + if (bytecount == 2) + spi_addr[23:16] = buffer; + + if (bytecount == 3) + spi_addr[15:8] = buffer; + + if (bytecount == 4) begin + spi_addr[7:0] = buffer; + spi_data_phase = spi_phase; + end + + // Dummy by selection at end of address phase for read + // mode only + if (bytecount == 4 && spi_mode == sspi && spi_cmd ==8'h03 ) + dummycount = 8; + if (bytecount == 4 && spi_mode == dspi && spi_cmd ==8'h03) + dummycount = 4; + if (bytecount == 4 && spi_mode == qspi && spi_cmd ==8'h03) + dummycount = 2; + + if (bytecount >= 4 && spi_cmd ==8'h03) begin // Data Read Phase + buffer = memory[spi_addr]; + //$display("%m: Read Memory Address: %x Data: %x",spi_addr,buffer); + spi_addr = spi_addr + 1; + end + if (bytecount > 4 && spi_cmd ==8'h02) begin // Data Write Phase + memory[spi_addr] = buffer; + //$display("%m: Write Memory Address: %x Data: %x",spi_addr,buffer); + spi_addr = spi_addr + 1; + end + end + + spi_out = buffer; + spi_io_vld = 1; + + if (verbose) begin + if (bytecount == 1) + $write("<SPI-START>"); + $write("<SPI:%02x:%02x>", spi_in, spi_out); + end + + end + endtask + + + always @(csb) begin + if (csb) begin + if (verbose) begin + $display(""); + $fflush; + end + buffer = 0; + bitcount = 0; + bytecount = 0; + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + spi_data_phase = 0; + + end + end + + + always @(csb, clk) begin + spi_io_vld = 0; + if (!csb && !clk) begin + if (dummycount > 0) begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end else + case (spi_data_phase) + mode_sspi_rd: begin + io0_oe = 0; + io1_oe = 1; + io2_oe = 0; + io3_oe = 0; + io1_dout = buffer[7]; + end + mode_sspi_wr: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + mode_dspi_wr: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + mode_dspi_rd: begin + io0_oe = 1; + io1_oe = 1; + io2_oe = 0; + io3_oe = 0; + io0_dout = buffer[6]; + io1_dout = buffer[7]; + end + mode_qspi_wr: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + mode_qspi_rd: begin + io0_oe = 1; + io1_oe = 1; + io2_oe = 1; + io3_oe = 1; + io0_dout = buffer[4]; + io1_dout = buffer[5]; + io2_dout = buffer[6]; + io3_dout = buffer[7]; + end + default: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + endcase + end + end + + always @(posedge clk) begin + if (!csb) begin + if (dummycount > 0) begin + dummycount = dummycount - 1; + end else + case (spi_mode) + sspi: begin + buffer = {buffer, io0}; + bitcount = bitcount + 1; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + dspi: begin + buffer = {buffer, io1, io0}; + bitcount = bitcount + 2; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + qspi: begin + buffer = {buffer, io3, io2, io1, io0}; + bitcount = bitcount + 4; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + endcase + end + end +endmodule
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile index 8df6ef7..4422d7d 100644 --- a/verilog/dv/risc_boot/Makefile +++ b/verilog/dv/risc_boot/Makefile
@@ -21,6 +21,7 @@ # ---- Include Partitioned Makefiles ---- +DESIGNS?=../../.. CONFIG = caravel_user_project ######################################################## @@ -51,7 +52,7 @@ export TOOLS ?= /opt/riscv64i export GCC_PATH ?= $(TOOLS)/bin -export GCC_PREFIX?= riscv32-unknown-linux-gnu +export GCC_PREFIX?= riscv64-unknown-linux-gnu ############## USER SPECIFIC DEFINE ################## @@ -126,7 +127,7 @@ # Comiple firmeware ############################################################################## %.elf: %.c $(LINKER_SCRIPT) $(SOURCE_FILES) - ${GCC_PATH}/${GCC_PREFIX}-gcc -g \ + ${GCC_PREFIX}-gcc -g \ -I$(FIRMWARE_PATH) \ -I$(VERILOG_PATH)/dv/generated \ -I$(VERILOG_PATH)/dv/ \ @@ -136,15 +137,15 @@ -ffreestanding -nostdlib -o $@ $(SOURCE_FILES) $< %.lst: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objdump -d -S $< > $@ + ${GCC_PREFIX}-objdump -d -S $< > $@ %.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ + ${GCC_PREFIX}-objcopy -O verilog $< $@ # to fix flash base address sed -ie 's/@10/@00/g' $@ %.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + ${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ ############################################################################## @@ -152,11 +153,11 @@ ############################################################################## %.vvp: %_tb.v %.hex - ${GCC_PATH}/${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o - ${GCC_PATH}/${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o - ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -o user_uart.elf -N - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex - ${GCC_PATH}/${GCC_PREFIX}-objdump -D user_uart.elf > user_uart.dump + ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o + ${GCC_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o + ${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -o user_uart.elf -N + ${GCC_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex + ${GCC_PREFIX}-objdump -D user_uart.elf > user_uart.dump rm crt.o user_uart.o ## RTL @@ -215,8 +216,8 @@ ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) endif -ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) - $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) +ifeq (,$(wildcard $(GCC_PREFIX)-gcc )) + $(error $(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) endif # check for efabless style installation ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c index bc41e1b..7de5444 100644 --- a/verilog/dv/risc_boot/risc_boot.c +++ b/verilog/dv/risc_boot/risc_boot.c
@@ -98,7 +98,7 @@ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); - reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64] + reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] // Flag start of the test reg_mprj_datal = 0xAB600000;
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile index 0461ba3..6883700 100644 --- a/verilog/dv/riscv_regress/Makefile +++ b/verilog/dv/riscv_regress/Makefile
@@ -167,6 +167,10 @@ export RISCV_RAM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -R .text.init -R .text -R .rodata -R .rodata.str1.4 -O verilog export RISCV_READELF ?= $(CROSS_PREFIX)readelf -s + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + ifneq (,$(findstring e,$(ARCH_lowercase))) # Tests can be compiled for RVE only if gcc version 8.0.0 or higher GCCVERSIONGT7 := $(shell expr `$(RISCV_GCC) -dumpfullversion | cut -f1 -d'.'` \> 7)
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile index ec6f963..0746413 100644 --- a/verilog/dv/uart_master/Makefile +++ b/verilog/dv/uart_master/Makefile
@@ -14,88 +14,191 @@ # # SPDX-License-Identifier: Apache-2.0 -## PDK -PDK_PATH = $(PDK_ROOT)/sky130A -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel + +PWDD := $(shell pwd) +BLOCKS := $(shell basename $(PWDD)) -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -GCC64_PREFIX?=riscv64-unknown-elf +# ---- Include Partitioned Makefiles ---- -## Simulation mode: RTL/GL -SIM_DEFINES = -DFUNCTIONAL -DSIM +DESIGNS?=../../.. +CONFIG = caravel_user_project + +######################################################## +#include $(MCW_ROOT)/verilog/dv/make/env.makefile +######################################################## +####################################################################### +## Global Environment Variables for local repo +####################################################################### + +export PDK_PATH = $(PDK_ROOT)/sky130A +export VIP_PATH = $(CORE_VERILOG_PATH)/dv/vip +export FIRMWARE_PATH = $(CORE_VERILOG_PATH)/dv/firmware + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +export CARAVEL_VERILOG_PATH ?= $(CARAVEL_ROOT)/verilog +export CORE_VERILOG_PATH ?= $(CARAVEL_ROOT)/mgmt_core_wrapper/verilog +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog + +export CARAVEL_PATH = $(CARAVEL_VERILOG_PATH) +export VERILOG_PATH = $(CORE_VERILOG_PATH) + +####################################################################### +## Compiler Information +####################################################################### + +export GCC_PATH?= $(TOOLS)/bin +export GCC_PREFIX?= riscv64-unknown-linux-gnu + + +############## USER SPECIFIC DEFINE ################## + +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware + +###################################################### + + + + + +######################################################## +#include $(MCW_ROOT)/verilog/dv/make/var.makefile +######################################################## + +CPU=vexriscv +CPUFAMILY=riscv +CPUFLAGS=-march=rv32i -mabi=ilp32 -D__vexriscv__ +CPUENDIANNESS=little +CLANG=0 + + +###################################################### +# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile +###################################################### + +ifeq ($(CPU),picorv32) + LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds + SOURCE_FILES=$(FIRMWARE_PATH)/start.s + VERILOG_FILES= +endif + +ifeq ($(CPU),ibex) + LINKER_SCRIPT=$(FIRMWARE_PATH)/link_ibex.ld + SOURCE_FILES=$(FIRMWARE_PATH)/crt0_ibex.S $(FIRMWARE_PATH)/simple_system_common.c +# VERILOG_FILES=../ibex/* + VERILOG_FILES= +endif + +ifeq ($(CPU),vexriscv) +# LINKER_SCRIPT=$(FIRMWARE_PATH)/sections_vexriscv.lds +# SOURCE_FILES=$(FIRMWARE_PATH)/start_caravel_vexriscv.s + LINKER_SCRIPT=$(FIRMWARE_PATH)/sections.lds + SOURCE_FILES=$(FIRMWARE_PATH)/crt0_vex.S $(FIRMWARE_PATH)/isr.c + VERILOG_FILES= +endif + + + +##################################################### +#include $(MCW_ROOT)/verilog/dv/make/sim.makefile +###################################################### + +export IVERILOG_DUMPER = fst + +# RTL/GL/GL_SDF SIM?=RTL DUMP?=OFF + .SUFFIXES: -PATTERN = uart_master -all: ${PATTERN:=.vcd} +all: ${BLOCKS:=.vcd} ${BLOCKS:=.lst} -hex: ${PATTERN:=.hex} +hex: ${BLOCKS:=.hex} -vvp: ${PATTERN:=.vvp} +#.SUFFIXES: + +############################################################################## +# Comiple firmeware +############################################################################## +%.elf: %.c $(LINKER_SCRIPT) $(SOURCE_FILES) + ${GCC_PREFIX}-gcc -g \ + -I$(FIRMWARE_PATH) \ + -I$(VERILOG_PATH)/dv/generated \ + -I$(VERILOG_PATH)/dv/ \ + -I$(VERILOG_PATH)/common \ + $(CPUFLAGS) \ + -Wl,-Bstatic,-T,$(LINKER_SCRIPT),--strip-debug \ + -ffreestanding -nostdlib -o $@ $(SOURCE_FILES) $< + +%.lst: %.elf + ${GCC_PREFIX}-objdump -d -S $< > $@ + +%.hex: %.elf + ${GCC_PREFIX}-objcopy -O verilog $< $@ + # to fix flash base address + sed -ie 's/@10/@00/g' $@ + +%.bin: %.elf + ${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + + +############################################################################## +# Runing the simulations +############################################################################## %.vvp: %_tb.v %.hex ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv $(SIM_DEFINES) -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ - $< -o $@ + iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< else - iverilog -g2005-sv -DWFDUMP $(SIM_DEFINES) -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ - $< -o $@ + iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< endif -else - iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_GL_PATH) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - $< -o $@ +endif + +## GL +ifeq ($(SIM),GL) + ifeq ($(CONFIG),caravel_user_project) + iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + -f$(VERILOG_PATH)/includes/includes.gl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< + else + iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \ + -f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $< + endif +endif + +## GL+SDF +ifeq ($(SIM),GL_SDF) + ifeq ($(CONFIG),caravel_user_project) + cvc64 +interp \ + +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \ + +change_port_type +dump2fst +fst+parallel2=on +nointeractive +notimingchecks +mipdopt \ + -f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \ + -f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $< + else + cvc64 +interp \ + +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \ + +change_port_type +dump2fst +fst+parallel2=on +nointeractive +notimingchecks +mipdopt \ + -f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \ + -f $CARAVEL_PATH/gl/__user_project_wrapper.v $< + endif endif %.vcd: %.vvp - vvp $< + vvp $< -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s check-env - ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: %.elf - ${GCC64_PREFIX}-objcopy -O verilog $< $@ - # to fix flash base address - sed -i 's/@10000000/@00000000/g' $@ - -%.bin: %.elf - ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ +# twinwave: RTL-%.vcd GL-%.vcd +# twinwave RTL-$@ * + GL-$@ * check-env: ifndef PDK_ROOT @@ -104,17 +207,18 @@ ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) endif -#ifeq (,$(wildcard $(GCC64_PREFIX)-gcc )) -# $(error $(GCC64_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) -#endif +ifeq (,$(wildcard $(GCC_PREFIX)-gcc )) + $(error $(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) +endif # check for efabless style installation ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE endif + # ---- Clean ---- clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + \rm -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe .PHONY: clean hex all
diff --git a/verilog/dv/uart_master/uart_master.c b/verilog/dv/uart_master/uart_master.c index 1f5912a..46d6e97 100644 --- a/verilog/dv/uart_master/uart_master.c +++ b/verilog/dv/uart_master/uart_master.c
@@ -16,8 +16,9 @@ */ // This include is relative to $CARAVEL_PATH (see Makefile) -#include "verilog/dv/caravel/defs.h" -#include "verilog/dv/caravel/stub.c" +#include <defs.h> +#include <stub.c> +#include "../c_func/inc/user_reg_map.h" // User Project Slaves (0x3000_0000) @@ -61,37 +62,40 @@ /* Set up the housekeeping SPI to be connected internally so */ /* that external pin changes don't affect it. */ - reg_spimaster_config = 0xa002; // Enable, prescaler = 2, + reg_spi_enable = 1; + reg_wb_enable = 1; + // reg_spimaster_config = 0xa002; // Enable, prescaler = 2, // connect to housekeeping SPI // Connect the housekeeping SPI to the SPI master // so that the CSB line is not left floating. This allows // all of the GPIO pins to be used for user functions. - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_la0_oenb = reg_la0_iena = 0x0000000; /* Apply configuration */ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); - reg_mprj_datal = 0xAB600000; - reg_la0_oenb = reg_la0_iena = 0x0000000; + reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] + + // Flag start of the test + reg_mprj_datal = 0xAB600000; //----------------------------------------------------- // Start of User Functionality and take over the GPIO Pins
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v index 1442c8c..2b021ee 100644 --- a/verilog/dv/uart_master/uart_master_tb.v +++ b/verilog/dv/uart_master/uart_master_tb.v
@@ -16,14 +16,7 @@ `default_nettype none `timescale 1 ns / 1 ps - -`define FULL_CHIP_SIM - -`include "uprj_netlists.v" -`include "caravel_netlists.v" -`include "spiflash.v" `include "uart_agent.v" -`include "user_reg_map.v" module uart_master_tb; reg clock; @@ -116,13 +109,16 @@ uart_timeout = 600;// wait time limit uart_fifo_enable = 0; // fifo mode disable tb_master_uart.debug_mode = 0; // disable debug display + + #200; // Wait for reset removal + + wait(checkbits == 16'h AB60); + $display("Monitor: UART Master Test Started"); + + repeat (50000) @(posedge clock); tb_master_uart.uart_init; tb_master_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); - wait(checkbits == 16'h AB60); - $display("Monitor: UART Master Test Started"); - - repeat (4000) @(posedge clock); //$write ("\n(%t)Response:\n",$time); flag = 0; while(flag == 0) @@ -279,4 +275,7 @@ `include "uart_master_tasks.sv" endmodule + +// SSFLASH has 1ps/1ps time scale +`include "s25fl256s.sv" `default_nettype wire
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile index e9e1108..37feef0 100644 --- a/verilog/dv/user_basic/Makefile +++ b/verilog/dv/user_basic/Makefile
@@ -14,40 +14,28 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### -## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware -GCC64_PREFIX?=riscv64-unknown-elf +DESIGNS?=../../.. -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog + ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + + .SUFFIXES: PATTERN = user_basic @@ -62,40 +50,22 @@ ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s - ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - -%.bin: %.elf - ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ # ---- Clean ----
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index 9ee701c..4aa572c 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -74,9 +74,7 @@ `timescale 1 ns/10 ps -`include "uprj_netlists.v" -`include "user_reg_map.v" - +`include "DFFRAM/DFFRAM.v" module user_basic_tb; parameter CLK1_PERIOD = 10; @@ -242,8 +240,8 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h1603_2022); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0003_9000); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h0604_2022); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_2000); end
diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile index 5788ed8..e7d9b13 100644 --- a/verilog/dv/user_i2cm/Makefile +++ b/verilog/dv/user_i2cm/Makefile
@@ -14,40 +14,31 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + + .SUFFIXES: PATTERN = user_i2cm @@ -59,49 +50,25 @@ vvp: ${PATTERN:=.vvp} %.vvp: %_tb.v - ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o - ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt_tcm.S -o crt_tcm.o - ${GCC64_PREFIX}-gcc -o user_uart.elf -T $(YIFIVE_FIRMWARE_PATH)/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 - ${GCC64_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex - ${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump - rm crt_tcm.o user_uart.o ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s - ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - -%.bin: %.elf - ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ # ---- Clean ----
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v index c9bcd8b..8bfde16 100644 --- a/verilog/dv/user_i2cm/user_i2cm_tb.v +++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -65,9 +65,8 @@ `timescale 1 ns / 1 ns -`include "uprj_netlists.v" +`include "DFFRAM/DFFRAM.v" `include "i2c_slave_model.v" -`include "user_reg_map.v" module tb_top; @@ -147,7 +146,7 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h01); // Enable I2C Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h200); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h4000); // Remove i2m reset wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h010);
diff --git a/verilog/dv/user_pwm/Makefile b/verilog/dv/user_pwm/Makefile index 220c33c..96815e2 100644 --- a/verilog/dv/user_pwm/Makefile +++ b/verilog/dv/user_pwm/Makefile
@@ -14,37 +14,31 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/usb1_host/src/includes +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/opt/pdk/sky130A ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + .SUFFIXES: @@ -58,36 +52,23 @@ %.vvp: %_tb.v ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \ - -I $(UPRJ_INCLUDE_PATH3) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \ - -I $(UPRJ_INCLUDE_PATH3) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - # ---- Clean ----
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v index 575d604..817a8c6 100644 --- a/verilog/dv/user_pwm/user_pwm_tb.v +++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -64,14 +64,12 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns / 1 ps `define TB_GLBL user_pwm_tb -`include "uprj_netlists.v" -`include "user_reg_map.v" - +`include "DFFRAM/DFFRAM.v" module user_pwm_tb; reg clock;
diff --git a/verilog/dv/user_qspi/Makefile b/verilog/dv/user_qspi/Makefile index 2192cb7..1932afc 100644 --- a/verilog/dv/user_qspi/Makefile +++ b/verilog/dv/user_qspi/Makefile
@@ -14,39 +14,31 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + .SUFFIXES: @@ -60,36 +52,23 @@ %.vvp: %_tb.v ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - # ---- Clean ----
diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v index 3b4d47a..e8ba4ee 100644 --- a/verilog/dv/user_qspi/user_qspi_tb.v +++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -77,13 +77,10 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns/1 ps -`include "uprj_netlists.v" -`include "mt48lc8m8a2.v" +`include "DFFRAM/DFFRAM.v" `include "is62wvs1288.v" -`include "user_reg_map.v" - module user_qspi_tb; reg clock;
diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile index 1057c10..4a0c488 100644 --- a/verilog/dv/user_risc_boot/Makefile +++ b/verilog/dv/user_risc_boot/Makefile
@@ -14,39 +14,31 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + .SUFFIXES: @@ -67,41 +59,23 @@ rm crt.o user_risc_boot.o ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp - vvp $< + vvp $< +risc_core_id=$(RISC_CORE) -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s - ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - -%.bin: %.elf - ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ # ---- Clean ----
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v index 698216c..0538cb1 100644 --- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v +++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -74,11 +74,6 @@ `timescale 1 ns / 1 ns -`include "uprj_netlists.v" -`include "mt48lc8m8a2.v" -`include "user_reg_map.v" - -`define ADDR_SPACE_PINMUX 32'h3002_0000 module user_risc_boot_tb; reg clock; reg wb_rst_i; @@ -165,23 +160,13 @@ // 0x3000002C = 0x66778899; test_fail = 0; - wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data); - if(read_data != 32'h11223344) test_fail = 1; + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788); + wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899); - wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data); - if(read_data != 32'h22334455) test_fail = 1; - - wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data); - if(read_data != 32'h33445566) test_fail = 1; - - wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data); - if(read_data!= 32'h44556677) test_fail = 1; - - wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data); - if(read_data!= 32'h55667788) test_fail = 1; - - wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data) ; - if(read_data != 32'h66778899) test_fail = 1; $display("###################################################"); @@ -348,6 +333,40 @@ end endtask +task wb_user_core_read_check; +input [31:0] address; +output [31:0] data; +input [31:0] cmp_data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + test_fail = 1; + end else begin + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + end + repeat (2) @(posedge clock); +end +endtask + `ifdef GL wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
diff --git a/verilog/dv/user_sspi/Makefile b/verilog/dv/user_sspi/Makefile index 2a8d7f1..9d8bd45 100644 --- a/verilog/dv/user_sspi/Makefile +++ b/verilog/dv/user_sspi/Makefile
@@ -14,39 +14,31 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/opt/pdk/sky130A ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + .SUFFIXES: @@ -60,36 +52,23 @@ %.vvp: %_tb.v ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - # ---- Clean ----
diff --git a/verilog/dv/user_sspi/flash0.hex b/verilog/dv/user_sspi/flash0.hex new file mode 100755 index 0000000..5f4ad8c --- /dev/null +++ b/verilog/dv/user_sspi/flash0.hex
@@ -0,0 +1,26 @@ +@00000000 +00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f +10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f +20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f +30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f +40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f +50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f +60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f +70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f +80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f +90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f +a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af +b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf +c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf +d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df +e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef +f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff + +@00000100 +00 11 22 33 44 55 66 77 88 99 AA BB CC DD EE FF + +@00000200 +11 11 11 11 22 22 22 22 33 33 33 33 44 44 44 44 +55 55 55 55 66 66 66 66 77 77 77 77 88 88 88 88 +99 99 99 99 AA AA AA AA BB BB BB BB CC CC CC CC +DD DD DD DD EE EE EE EE FF FF FF FF 00 00 00 00
diff --git a/verilog/dv/user_sspi/flash1.hex b/verilog/dv/user_sspi/flash1.hex index e3c4b1b..476541e 100755 --- a/verilog/dv/user_sspi/flash1.hex +++ b/verilog/dv/user_sspi/flash1.hex
@@ -1,5 +1,4 @@ @00000000 -00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f @@ -17,10 +16,10 @@ f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff @00000100 -00 11 22 33 44 55 66 77 88 99 AA BB CC DD EE FF +11 22 33 44 55 66 77 88 99 AA BB CC DD EE FF 00 @00000200 -11 11 11 11 22 22 22 22 33 33 33 33 44 44 44 44 -55 55 55 55 66 66 66 66 77 77 77 77 88 88 88 88 -99 99 99 99 AA AA AA AA AA BB BB BB BB CC CC CC -DD DD DD DD EE EE EE EE FF FF FF FF 00 00 00 00 +22 22 22 22 33 33 33 33 44 44 44 44 55 55 55 55 +66 66 66 66 77 77 77 77 88 88 88 88 99 99 99 99 +AA AA AA AA BB BB BB BB CC CC CC CC DD DD DD DD +EE EE EE EE FF FF FF FF 00 00 00 00 11 11 11 11
diff --git a/verilog/dv/user_sspi/flash2.hex b/verilog/dv/user_sspi/flash2.hex new file mode 100755 index 0000000..477d682 --- /dev/null +++ b/verilog/dv/user_sspi/flash2.hex
@@ -0,0 +1,24 @@ +@00000000 +20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f +30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f +40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f +50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f +60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f +70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f +80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f +90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f +a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af +b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf +c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf +d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df +e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef +f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff + +@00000100 +22 33 44 55 66 77 88 99 AA BB CC DD EE FF 00 11 + +@00000200 +33 33 33 33 44 44 44 44 55 55 55 55 66 66 66 66 +77 77 77 77 88 88 88 88 99 99 99 99 AA AA AA AA +BB BB BB BB CC CC CC CC DD DD DD DD EE EE EE EE +FF FF FF FF 00 00 00 00 11 11 11 11 22 22 22 22
diff --git a/verilog/dv/user_sspi/flash3.hex b/verilog/dv/user_sspi/flash3.hex new file mode 100755 index 0000000..200525e --- /dev/null +++ b/verilog/dv/user_sspi/flash3.hex
@@ -0,0 +1,23 @@ +@00000000 +30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f +40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f +50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f +60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f +70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f +80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f +90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f +a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af +b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf +c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf +d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df +e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef +f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff + +@00000100 +33 44 55 66 77 88 99 AA BB CC DD EE FF 00 11 22 + +@00000200 +44 44 44 44 55 55 55 55 66 66 66 66 77 77 77 77 +88 88 88 88 99 99 99 99 AA AA AA AA BB BB BB BB +CC CC CC CC DD DD DD DD EE EE EE EE FF FF FF FF +00 00 00 00 11 11 11 11 22 22 22 22 11 11 11 11
diff --git a/verilog/dv/user_sspi/sspi_task.v b/verilog/dv/user_sspi/sspi_task.v index 1ce38eb..b084a0c 100755 --- a/verilog/dv/user_sspi/sspi_task.v +++ b/verilog/dv/user_sspi/sspi_task.v
@@ -63,7 +63,7 @@ sspi_write_dword({cmd,address[23:0]},BIG_ENDIAN,8'h0); sspi_write_byte(32'h00,BIG_ENDIAN,8'h0); // 8 Bit Dummy Cycle sspi_read_dword(LITTLE_ENDIAN,read_data,8'h1); - if(read_data != exp_data) begin + if(read_data !== exp_data) begin -> sspi_error_detected; $display("%m : ERROR : Address: %x Exp : %x Rxd : %x",address,exp_data,read_data); end else begin
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v index 512e40d..e3d52f9 100644 --- a/verilog/dv/user_sspi/user_sspi_tb.v +++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -64,14 +64,13 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns/1 ps +`include "DFFRAM/DFFRAM.v" +`include "is62wvs1288.v" `define TB_GLBL user_sspi_tb -`include "uprj_netlists.v" -`include "is62wvs1288.v" -`include "user_reg_map.v" @@ -141,7 +140,7 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); // Enable SPI Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h3C00); repeat (2) @(posedge clock); #1; @@ -156,7 +155,7 @@ repeat (200) @(posedge clock); wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 $display("############################################"); - $display(" Testing IS62/65WVS1288GALL SSRAM Read/Write Access "); + $display(" Testing IS62/65WVS1288GALL SSRAM[0] Read/Write Access "); $display("############################################"); // SSPI Indirect RAM READ ACCESS- // Byte Read Option @@ -208,7 +207,182 @@ sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC); sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00); + $display("############################################"); + $display(" Testing IS62/65WVS1288GALL SSRAM[1] Read/Write Access "); + $display("############################################"); + // SSPI Indirect RAM READ ACCESS- + // Byte Read Option + // <Instr:0x3> <Addr:24Bit Address> <Read Data Out> + spi_chip_no = 2'b01; // Select the Chip Select to zero + sspi_dw_read_check(8'h03,24'h0000,32'h13121110); + sspi_dw_read_check(8'h03,24'h0004,32'h17161514); + sspi_dw_read_check(8'h03,24'h0008,32'h1B1A1918); + sspi_dw_read_check(8'h03,24'h000C,32'h1F1E1D1C); + + sspi_dw_read_check(8'h03,24'h0010,32'h23222120); + sspi_dw_read_check(8'h03,24'h0014,32'h27262524); + sspi_dw_read_check(8'h03,24'h0018,32'h2B2A2928); + sspi_dw_read_check(8'h03,24'h001C,32'h2F2E2D2C); + + sspi_dw_read_check(8'h03,24'h0020,32'h33323130); + sspi_dw_read_check(8'h03,24'h0024,32'h37363534); + sspi_dw_read_check(8'h03,24'h0028,32'h3B3A3938); + sspi_dw_read_check(8'h03,24'h002C,32'h3F3E3D3C); + sspi_dw_read_check(8'h03,24'h0030,32'h43424140); + sspi_dw_read_check(8'h03,24'h0034,32'h47464544); + sspi_dw_read_check(8'h03,24'h0038,32'h4B4A4948); + sspi_dw_read_check(8'h03,24'h003C,32'h4F4E4D4C); + + sspi_dw_read_check(8'h03,24'h00a0,32'hb3b2b1b0); + sspi_dw_read_check(8'h03,24'h00a4,32'hb7b6b5b4); + sspi_dw_read_check(8'h03,24'h00a8,32'hbbbab9b8); + sspi_dw_read_check(8'h03,24'h00aC,32'hbfbebdbc); + + sspi_dw_read_check(8'h03,24'h0200,32'h22222222); + sspi_dw_read_check(8'h03,24'h0204,32'h33333333); + sspi_dw_read_check(8'h03,24'h0208,32'h44444444); + sspi_dw_read_check(8'h03,24'h020C,32'h55555555); + + // SPI Write + sspi_dw_write(8'h02,24'h0000,32'h00112233); + sspi_dw_write(8'h02,24'h0004,32'h44556677); + sspi_dw_write(8'h02,24'h0008,32'h8899AABB); + sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF); + + sspi_dw_write(8'h02,24'h0200,32'h11223344); + sspi_dw_write(8'h02,24'h0204,32'h55667788); + sspi_dw_write(8'h02,24'h0208,32'h99AABBCC); + sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00); + + // SPI Read Check + sspi_dw_read_check(8'h03,24'h0000,32'h00112233); + sspi_dw_read_check(8'h03,24'h0004,32'h44556677); + sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB); + sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF); + + sspi_dw_read_check(8'h03,24'h0200,32'h11223344); + sspi_dw_read_check(8'h03,24'h0204,32'h55667788); + sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC); + sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00); + + $display("############################################"); + $display(" Testing IS62/65WVS1288GALL SSRAM[2] Read/Write Access "); + $display("############################################"); + // SSPI Indirect RAM READ ACCESS- + // Byte Read Option + // <Instr:0x3> <Addr:24Bit Address> <Read Data Out> + spi_chip_no = 2'b10; // Select the Chip Select to zero + sspi_dw_read_check(8'h03,24'h0000,32'h23222120); + sspi_dw_read_check(8'h03,24'h0004,32'h27262524); + sspi_dw_read_check(8'h03,24'h0008,32'h2b2a2928); + sspi_dw_read_check(8'h03,24'h000C,32'h2f2e2d2c); + + sspi_dw_read_check(8'h03,24'h0010,32'h33323130); + sspi_dw_read_check(8'h03,24'h0014,32'h37363534); + sspi_dw_read_check(8'h03,24'h0018,32'h3B3A3938); + sspi_dw_read_check(8'h03,24'h001C,32'h3F3E3D3C); + + sspi_dw_read_check(8'h03,24'h0020,32'h43424140); + sspi_dw_read_check(8'h03,24'h0024,32'h47464544); + sspi_dw_read_check(8'h03,24'h0028,32'h4B4A4948); + sspi_dw_read_check(8'h03,24'h002C,32'h4F4E4D4C); + + sspi_dw_read_check(8'h03,24'h0030,32'h53525150); + sspi_dw_read_check(8'h03,24'h0034,32'h57565554); + sspi_dw_read_check(8'h03,24'h0038,32'h5B5A5958); + sspi_dw_read_check(8'h03,24'h003C,32'h5F5E5D5C); + + sspi_dw_read_check(8'h03,24'h0040,32'h63626160); + sspi_dw_read_check(8'h03,24'h0044,32'h67666564); + sspi_dw_read_check(8'h03,24'h0048,32'h6B6A6968); + sspi_dw_read_check(8'h03,24'h004C,32'h6F6E6D6C); + + sspi_dw_read_check(8'h03,24'h00a0,32'hc3c2c1c0); + sspi_dw_read_check(8'h03,24'h00a4,32'hc7c6c5c4); + sspi_dw_read_check(8'h03,24'h00a8,32'hcbcac9c8); + sspi_dw_read_check(8'h03,24'h00aC,32'hcfcecdcc); + + sspi_dw_read_check(8'h03,24'h0200,32'h33333333); + sspi_dw_read_check(8'h03,24'h0204,32'h44444444); + sspi_dw_read_check(8'h03,24'h0208,32'h55555555); + sspi_dw_read_check(8'h03,24'h020C,32'h66666666); + + // SPI Write + sspi_dw_write(8'h02,24'h0000,32'h00112233); + sspi_dw_write(8'h02,24'h0004,32'h44556677); + sspi_dw_write(8'h02,24'h0008,32'h8899AABB); + sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF); + + sspi_dw_write(8'h02,24'h0200,32'h11223344); + sspi_dw_write(8'h02,24'h0204,32'h55667788); + sspi_dw_write(8'h02,24'h0208,32'h99AABBCC); + sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00); + + // SPI Read Check + sspi_dw_read_check(8'h03,24'h0000,32'h00112233); + sspi_dw_read_check(8'h03,24'h0004,32'h44556677); + sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB); + sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF); + + sspi_dw_read_check(8'h03,24'h0200,32'h11223344); + sspi_dw_read_check(8'h03,24'h0204,32'h55667788); + sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC); + sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00); + + $display("############################################"); + $display(" Testing IS62/65WVS1288GALL SSRAM[3] Read/Write Access "); + $display("############################################"); + // SSPI Indirect RAM READ ACCESS- + // Byte Read Option + // <Instr:0x3> <Addr:24Bit Address> <Read Data Out> + spi_chip_no = 2'b11; // Select the Chip Select to zero + sspi_dw_read_check(8'h03,24'h0000,32'h33323130); + sspi_dw_read_check(8'h03,24'h0004,32'h37363534); + sspi_dw_read_check(8'h03,24'h0008,32'h3b3a3938); + sspi_dw_read_check(8'h03,24'h000C,32'h3f3e3d3c); + + sspi_dw_read_check(8'h03,24'h0010,32'h43424140); + sspi_dw_read_check(8'h03,24'h0014,32'h47464544); + sspi_dw_read_check(8'h03,24'h0018,32'h4B4A4948); + sspi_dw_read_check(8'h03,24'h001C,32'h4F4E4D4C); + + sspi_dw_read_check(8'h03,24'h0020,32'h53525150); + sspi_dw_read_check(8'h03,24'h0024,32'h57565554); + sspi_dw_read_check(8'h03,24'h0028,32'h5B5A5958); + sspi_dw_read_check(8'h03,24'h002C,32'h5F5E5D5C); + + sspi_dw_read_check(8'h03,24'h00a0,32'hd3d2d1d0); + sspi_dw_read_check(8'h03,24'h00a4,32'hd7d6d5d4); + sspi_dw_read_check(8'h03,24'h00a8,32'hdbdad9d8); + sspi_dw_read_check(8'h03,24'h00aC,32'hdfdedddc); + + sspi_dw_read_check(8'h03,24'h0200,32'h44444444); + sspi_dw_read_check(8'h03,24'h0204,32'h55555555); + sspi_dw_read_check(8'h03,24'h0208,32'h66666666); + sspi_dw_read_check(8'h03,24'h020C,32'h77777777); + + // SPI Write + sspi_dw_write(8'h02,24'h0000,32'h00112233); + sspi_dw_write(8'h02,24'h0004,32'h44556677); + sspi_dw_write(8'h02,24'h0008,32'h8899AABB); + sspi_dw_write(8'h02,24'h000C,32'hCCDDEEFF); + + sspi_dw_write(8'h02,24'h0200,32'h11223344); + sspi_dw_write(8'h02,24'h0204,32'h55667788); + sspi_dw_write(8'h02,24'h0208,32'h99AABBCC); + sspi_dw_write(8'h02,24'h020C,32'hDDEEFF00); + + // SPI Read Check + sspi_dw_read_check(8'h03,24'h0000,32'h00112233); + sspi_dw_read_check(8'h03,24'h0004,32'h44556677); + sspi_dw_read_check(8'h03,24'h0008,32'h8899AABB); + sspi_dw_read_check(8'h03,24'h000C,32'hCCDDEEFF); + + sspi_dw_read_check(8'h03,24'h0200,32'h11223344); + sspi_dw_read_check(8'h03,24'h0204,32'h55667788); + sspi_dw_read_check(8'h03,24'h0208,32'h99AABBCC); + sspi_dw_read_check(8'h03,24'h020C,32'hDDEEFF00); repeat (100) @(posedge clock); // $display("+1000 cycles"); @@ -285,7 +459,6 @@ // ---------------------------------------------------- wire flash_io1; wire flash_clk = io_out[16]; - wire spiram_csb = io_out[13]; tri #1 flash_io0 = io_out[15]; assign io_in[14] = flash_io1; @@ -293,18 +466,57 @@ tri #1 flash_io3 = 1'b1; - is62wvs1288 #(.mem_file_name("flash1.hex")) - u_sfram ( + wire spiram_csb0 = io_out[13]; + is62wvs1288 #(.mem_file_name("flash0.hex")) + u_sfram_0 ( // Data Inputs/Outputs .io0 (flash_io0), .io1 (flash_io1), // Controls .clk (flash_clk), - .csb (spiram_csb), + .csb (spiram_csb0), .io2 (flash_io2), .io3 (flash_io3) ); + wire spiram_csb1 = io_out[12]; + is62wvs1288 #(.mem_file_name("flash1.hex")) + u_sfram_1 ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb1), + .io2 (flash_io2), + .io3 (flash_io3) + ); + + wire spiram_csb2 = io_out[9]; +is62wvs1288 #(.mem_file_name("flash2.hex")) + u_sfram_2 ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb2), + .io2 (flash_io2), + .io3 (flash_io3) + ); + + wire spiram_csb3 = io_out[8]; +is62wvs1288 #(.mem_file_name("flash3.hex")) + u_sfram_3 ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb3), + .io2 (flash_io2), + .io3 (flash_io3) + ); //---------------------------------------------------- // Task
diff --git a/verilog/dv/user_timer/Makefile b/verilog/dv/user_timer/Makefile index cda351b..6520c31 100644 --- a/verilog/dv/user_timer/Makefile +++ b/verilog/dv/user_timer/Makefile
@@ -14,37 +14,31 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/usb1_host/src/includes +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/opt/pdk/sky130A ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + .SUFFIXES: @@ -58,36 +52,23 @@ %.vvp: %_tb.v ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \ - -I $(UPRJ_INCLUDE_PATH3) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \ - -I $(UPRJ_INCLUDE_PATH3) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - # ---- Clean ----
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v index f2d7f11..dab309a 100644 --- a/verilog/dv/user_timer/user_timer_tb.v +++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -64,12 +64,10 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns / 1 ps `define TB_GLBL user_timer_tb -`include "uprj_netlists.v" -`include "user_reg_map.v" module user_timer_tb;
diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile index 387f35d..97726ee 100644 --- a/verilog/dv/user_uart/Makefile +++ b/verilog/dv/user_uart/Makefile
@@ -14,39 +14,31 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + .SUFFIXES: @@ -54,7 +46,6 @@ all: ${PATTERN:=.vcd} -hex: ${PATTERN:=.hex} vvp: ${PATTERN:=.vvp} @@ -67,41 +58,23 @@ rm crt.o user_uart.o ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp - vvp $< + vvp $< +risc_core_id=$(RISC_CORE) -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s - ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - -%.bin: %.elf - ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ # ---- Clean ----
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index 21a848c..14f0c7f 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -72,11 +72,10 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns/1 ps -`include "uprj_netlists.v" +`include "DFFRAM/DFFRAM.v" `include "uart_agent.v" -`include "user_reg_map.v" module user_uart_tb; @@ -184,7 +183,7 @@ repeat (100) @(posedge clock); // wait for Processor Get Ready tb_uart.uart_init; - wb_user_core_write(`ADDR_SPACE_UART+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1}); + wb_user_core_write(`ADDR_SPACE_UART0+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1}); tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor);
diff --git a/verilog/dv/user_uart1/.user_uart.c.un~ b/verilog/dv/user_uart1/.user_uart.c.un~ new file mode 100644 index 0000000..5835313 --- /dev/null +++ b/verilog/dv/user_uart1/.user_uart.c.un~ Binary files differ
diff --git a/verilog/dv/user_uart1/Makefile b/verilog/dv/user_uart1/Makefile new file mode 100644 index 0000000..046c8df --- /dev/null +++ b/verilog/dv/user_uart1/Makefile
@@ -0,0 +1,84 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC64_PREFIX?=riscv64-unknown-elf + + +## Simulation mode: RTL/GL +SIM?=RTL +DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + + +.SUFFIXES: + +PATTERN = user_uart1 + +all: ${PATTERN:=.vcd} + + +vvp: ${PATTERN:=.vvp} + +%.vvp: %_tb.v + ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_uart.c -o user_uart.o + ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o + ${GCC64_PREFIX}-gcc -o user_uart.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_uart.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N + ${GCC64_PREFIX}-objcopy -O verilog user_uart.elf user_uart.hex + ${GCC64_PREFIX}-objdump -D user_uart.elf > user_uart.dump + rm crt.o user_uart.o +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + $< -o $@ + endif +else + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + $< -o $@ +endif + +%.vcd: %.vvp + vvp $< +risc_core_id=$(RISC_CORE) + + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump + +.PHONY: clean hex all
diff --git a/verilog/dv/user_uart1/run_iverilog b/verilog/dv/user_uart1/run_iverilog new file mode 100755 index 0000000..e461fd1 --- /dev/null +++ b/verilog/dv/user_uart1/run_iverilog
@@ -0,0 +1,42 @@ +# ////////////////////////////////////////////////////////////////////////////// +# // SPDX-FileCopyrightText: 2021, Dinesh Annayya +# // +# // Licensed under the Apache License, Version 2.0 (the "License"); +# // you may not use this file except in compliance with the License. +# // You may obtain a copy of the License at +# // +# // http://www.apache.org/licenses/LICENSE-2.0 +# // +# // Unless required by applicable law or agreed to in writing, software +# // distributed under the License is distributed on an "AS IS" BASIS, +# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# // See the License for the specific language governing permissions and +# // limitations under the License. +# // SPDX-License-Identifier: Apache-2.0 +# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +# // ////////////////////////////////////////////////////////////////////////// +riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_uart.c -o user_uart.o + +riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o + +riscv64-unknown-elf-gcc -o user_uart.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 + +riscv64-unknown-elf-objcopy -O verilog user_uart.elf user_uart.hex + +riscv64-unknown-elf-objdump -D user_uart.elf > user_uart.dump + +rm crt_tcm.o user_uart.o + +#iverilog with waveform dump +iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I ../../../verilog/rtl/i2cm/src/includes -I ../../../verilog/rtl/usb1_host/src/includes -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp + + +#iverilog -g2005-sv -I $PDK_PATH -DFUNCTIONAL -DSIM -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp + +# GLS +#iverilog -g2005-sv -D GL -D FUNCTIONAL -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/gl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp +# + +vvp user_uart_tb.vvp | tee test.log + +\rm -rf user_uart_tb.vvp
diff --git a/verilog/dv/user_uart1/user_uart.c b/verilog/dv/user_uart1/user_uart.c new file mode 100644 index 0000000..ac8c50f --- /dev/null +++ b/verilog/dv/user_uart1/user_uart.c
@@ -0,0 +1,43 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021, Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +// ////////////////////////////////////////////////////////////////////////// +#define SC_SIM_OUTPORT (0xf0000000) +#define uint32_t long + + +#define reg_mprj_uart_reg0 (*(volatile uint32_t*)0x10010100) +#define reg_mprj_uart_reg1 (*(volatile uint32_t*)0x10010104) +#define reg_mprj_uart_reg2 (*(volatile uint32_t*)0x10010108) +#define reg_mprj_uart_reg3 (*(volatile uint32_t*)0x1001010C) +#define reg_mprj_uart_reg4 (*(volatile uint32_t*)0x10010110) +#define reg_mprj_uart_reg5 (*(volatile uint32_t*)0x10010114) +#define reg_mprj_uart_reg6 (*(volatile uint32_t*)0x10010118) +#define reg_mprj_uart_reg7 (*(volatile uint32_t*)0x1001011C) +#define reg_mprj_uart_reg8 (*(volatile uint32_t*)0x10010120) + +int main() +{ + + while(1) { + // Check UART RX fifo has data, if available loop back the data + if(reg_mprj_uart_reg8 != 0) { + reg_mprj_uart_reg5 = reg_mprj_uart_reg6; + } + } + + return 0; +}
diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v new file mode 100644 index 0000000..4946c9f --- /dev/null +++ b/verilog/dv/user_uart1/user_uart1_tb.v
@@ -0,0 +1,469 @@ +//////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +////////////////////////////////////////////////////////////////////// +//// //// +//// Standalone User validation Test bench //// +//// //// +//// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// +//// http://www.opencores.org/cores/yifive/ //// +//// //// +//// Description //// +//// This is a standalone test bench to validate the //// +//// Digital core. //// +//// 1. User Risc core is booted using compiled code of //// +//// user_risc_boot.c //// +//// 2. User Risc core uses Serial Flash and SDRAM to boot //// +//// 3. After successful boot, Risc core will check the UART //// +//// RX Data, If it's available then it loop back the same //// +//// data in uart tx //// +//// 4. Test bench send random 40 character towards User uart //// +//// and expect same data to return back //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 16th Feb 2021, Dinesh A //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`default_nettype wire + +`timescale 1 ns/1 ps + +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "uart_agent.v" + + +module user_uart1_tb; + +reg clock ; +reg wb_rst_i ; +reg power1, power2; +reg power3, power4; + +reg wbd_ext_cyc_i; // strobe/request +reg wbd_ext_stb_i; // strobe/request +reg [31:0] wbd_ext_adr_i; // address +reg wbd_ext_we_i; // write +reg [31:0] wbd_ext_dat_i; // data output +reg [3:0] wbd_ext_sel_i; // byte enable + +wire [31:0] wbd_ext_dat_o; // data input +wire wbd_ext_ack_o; // acknowlegement +wire wbd_ext_err_o; // error + +// User I/O +wire [37:0] io_oeb ; +wire [37:0] io_out ; +wire [37:0] io_in ; + +wire [37:0] mprj_io ; +wire [7:0] mprj_io_0 ; +reg test_fail ; +reg [31:0] read_data ; +//---------------------------------- +// Uart Configuration +// --------------------------------- +reg [1:0] uart_data_bit ; +reg uart_stop_bits ; // 0: 1 stop bit; 1: 2 stop bit; +reg uart_stick_parity ; // 1: force even parity +reg uart_parity_en ; // parity enable +reg uart_even_odd_parity ; // 0: odd parity; 1: even parity + +reg [7:0] uart_data ; +reg [15:0] uart_divisor ; // divided by n * 16 +reg [15:0] uart_timeout ;// wait time limit + +reg [15:0] uart_rx_nu ; +reg [15:0] uart_tx_nu ; +reg [7:0] uart_write_data [0:39]; +reg uart_fifo_enable ; // fifo mode disable + + integer d_risc_id; + +integer i,j; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + end + + `ifdef WFDUMP + initial begin + $dumpfile("simx.vcd"); + $dumpvars(0, user_uart1_tb); + end + `endif + + initial begin + wb_rst_i <= 1'b1; + #100; + wb_rst_i <= 1'b0; // Release reset + end +initial +begin + uart_data_bit = 2'b11; + uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; + uart_stick_parity = 0; // 1: force even parity + uart_parity_en = 0; // parity enable + uart_even_odd_parity = 1; // 0: odd parity; 1: even parity + uart_divisor = 15;// divided by n * 16 + uart_timeout = 500;// wait time limit + uart_fifo_enable = 0; // fifo mode disable + + $value$plusargs("risc_core_id=%d", d_risc_id); + + #200; // Wait for reset removal + repeat (10) @(posedge clock); + $display("Monitor: Standalone User Uart Test Started"); + + // Remove Wb Reset + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + // Enable UART Multi Functional Ports + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h200); + + repeat (2) @(posedge clock); + #1; + // Remove all the reset + if(d_risc_id == 0) begin + $display("STATUS: Working with Risc core 0"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h143); + end else if(d_risc_id == 1) begin + $display("STATUS: Working with Risc core 1"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h243); + end else if(d_risc_id == 2) begin + $display("STATUS: Working with Risc core 2"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h443); + end else if(d_risc_id == 3) begin + $display("STATUS: Working with Risc core 2"); + wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h84F); + end + + repeat (100) @(posedge clock); // wait for Processor Get Ready + + tb_uart.uart_init; + wb_user_core_write(`ADDR_SPACE_UART1+8'h0,{3'h0,2'b00,1'b1,1'b1,1'b1}); + tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, + uart_stick_parity, uart_timeout, uart_divisor); + + repeat (30000) @(posedge clock); // wait for Processor Get Ready + + + for (i=0; i<40; i=i+1) + uart_write_data[i] = $random; + + + + fork + begin + for (i=0; i<40; i=i+1) + begin + $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]); + tb_uart.write_char (uart_write_data[i]); + end + end + + begin + for (j=0; j<40; j=j+1) + begin + tb_uart.read_char_chk(uart_write_data[j]); + end + end + join + + #100 + tb_uart.report_status(uart_rx_nu, uart_tx_nu); + + test_fail = 0; + + // Check + // if all the 40 byte transmitted + // if all the 40 byte received + // if no error + if(uart_tx_nu != 40) test_fail = 1; + if(uart_rx_nu != 40) test_fail = 1; + if(tb_uart.err_cnt != 0) test_fail = 1; + + $display("###################################################"); + if(test_fail == 0) begin + `ifdef GL + $display("Monitor: Standalone User UART Test (GL) Passed"); + `else + $display("Monitor: Standalone User UART Test (RTL) Passed"); + `endif + end else begin + `ifdef GL + $display("Monitor: Standalone User UART Test (GL) Failed"); + `else + $display("Monitor: Standalone User UART Test (RTL) Failed"); + `endif + end + $display("###################################################"); + #100 + $finish; +end + + +wire USER_VDD1V8 = 1'b1; +wire VSS = 1'b0; + + +user_project_wrapper u_top( +`ifdef USE_POWER_PINS + .vccd1(USER_VDD1V8), // User area 1 1.8V supply + .vssd1(VSS), // User area 1 digital ground +`endif + .wb_clk_i (clock), // System clock + .user_clock2 (1'b1), // Real-time clock + .wb_rst_i (wb_rst_i), // Regular Reset signal + + .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request + .wbs_stb_i (wbd_ext_stb_i), // strobe/request + .wbs_adr_i (wbd_ext_adr_i), // address + .wbs_we_i (wbd_ext_we_i), // write + .wbs_dat_i (wbd_ext_dat_i), // data output + .wbs_sel_i (wbd_ext_sel_i), // byte enable + + .wbs_dat_o (wbd_ext_dat_o), // data input + .wbs_ack_o (wbd_ext_ack_o), // acknowlegement + + + // Logic Analyzer Signals + .la_data_in ('1) , + .la_data_out (), + .la_oenb ('0), + + + // IOs + .io_in (io_in) , + .io_out (io_out) , + .io_oeb (io_oeb) , + + .user_irq () + +); + +`ifndef GL // Drive Power for Hold Fix Buf + // All standard cell need power hook-up for functionality work + initial begin + end +`endif + + +//------------------------------------------------------ +// Integrate the Serial flash with qurd support to +// user core using the gpio pads +// ---------------------------------------------------- + + wire flash_clk = io_out[24]; + wire flash_csb = io_out[25]; + // Creating Pad Delay + wire #1 io_oeb_29 = io_oeb[29]; + wire #1 io_oeb_30 = io_oeb[30]; + wire #1 io_oeb_31 = io_oeb[31]; + wire #1 io_oeb_32 = io_oeb[32]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; + + assign io_in[29] = flash_io0; + assign io_in[30] = flash_io1; + assign io_in[31] = flash_io2; + assign io_in[32] = flash_io3; + + + // Quard flash + s25fl256s #(.mem_file_name("user_uart.hex"), + .otp_file_name("none"), + .TimingModel("S25FL512SAGMFI010_F_30pF")) + u_spi_flash_256mb + ( + // Data Inputs/Outputs + .SI (flash_io0), + .SO (flash_io1), + // Controls + .SCK (flash_clk), + .CSNeg (flash_csb), + .WPNeg (flash_io2), + .HOLDNeg (flash_io3), + .RSTNeg (!wb_rst_i) + + ); + + +//--------------------------- +// UART Agent integration +// -------------------------- +wire uart_txd,uart_rxd; + +assign uart_txd = io_out[5]; +assign io_in[3] = uart_rxd ; + +uart_agent tb_uart( + .mclk (clock ), + .txd (uart_rxd ), + .rxd (uart_txd ) + ); + + +task wb_user_core_write; +input [31:0] address; +input [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h1; // write + wbd_ext_dat_i =data; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read; +input [31:0] address; +output [31:0] data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); + repeat (2) @(posedge clock); +end +endtask + +`ifdef GL + +wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; + +wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i; +wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o; +wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i; +wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i; +wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i; +wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o; +wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i; + +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; +wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; + +`endif + +/** +`ifdef GL +//----------------------------------------------------------------------------- +// RISC IMEM amd DMEM Monitoring TASK +//----------------------------------------------------------------------------- + +`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top + +always@(posedge `RISC_CORE.wb_clk) begin + if(`RISC_CORE.wbd_imem_ack_i) + $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i); + if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o); + if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i); +end + +`endif +**/ +endmodule +`include "s25fl256s.sv" +`default_nettype wire
diff --git a/verilog/dv/user_uart_master/Makefile b/verilog/dv/user_uart_master/Makefile index b52caef..340954d 100644 --- a/verilog/dv/user_uart_master/Makefile +++ b/verilog/dv/user_uart_master/Makefile
@@ -43,6 +43,10 @@ SIM?=RTL DUMP?=OFF +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + + .SUFFIXES: PATTERN = user_uart_master
diff --git a/verilog/dv/user_usb/Makefile b/verilog/dv/user_usb/Makefile index f72ca56..a25bc69 100644 --- a/verilog/dv/user_usb/Makefile +++ b/verilog/dv/user_usb/Makefile
@@ -14,40 +14,31 @@ # # SPDX-License-Identifier: Apache-2.0 -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel +# ---- Include Partitioned Makefiles ---- -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_BEHAVIOURAL_BFM = ../bfm -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware GCC64_PREFIX?=riscv64-unknown-elf -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/opt/pdk/sky130A ## Simulation mode: RTL/GL SIM?=RTL DUMP?=OFF +RISC_CORE?=0 + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + .SUFFIXES: @@ -61,36 +52,23 @@ %.vvp: %_tb.v ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) -I $(UPRJ_BEHAVIOURAL_BFM) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) -I $(UPRJ_BEHAVIOURAL_BFM) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ $< -o $@ endif %.vcd: %.vvp vvp $< -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - # ---- Clean ----
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v index 96f1446..f1e498d 100644 --- a/verilog/dv/user_usb/user_usb_tb.v +++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -38,13 +38,11 @@ `default_nettype wire -`timescale 1 ns / 1 ns +`timescale 1 ns / 1 ps `define TB_GLBL user_usb_tb `define USB_BFM u_usb_agent -`include "user_reg_map.v" -`include "uprj_netlists.v" `include "usb_agents.v" `include "test_control.v" `include "usb1d_defines.v"
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile index 887f270..633a369 100644 --- a/verilog/dv/wb_port/Makefile +++ b/verilog/dv/wb_port/Makefile
@@ -21,6 +21,7 @@ # ---- Include Partitioned Makefiles ---- +DESIGNS?=../../.. CONFIG = caravel_user_project ######################################################## @@ -50,7 +51,7 @@ ####################################################################### export GCC_PATH?= $(TOOLS)/bin -export GCC_PREFIX?= riscv32-unknown-linux-gnu +export GCC_PREFIX?= riscv64-unknown-linux-gnu @@ -121,7 +122,7 @@ # Comiple firmeware ############################################################################## %.elf: %.c $(LINKER_SCRIPT) $(SOURCE_FILES) - ${GCC_PATH}/${GCC_PREFIX}-gcc -g \ + ${GCC_PREFIX}-gcc -g \ -I$(FIRMWARE_PATH) \ -I$(VERILOG_PATH)/dv/generated \ -I$(VERILOG_PATH)/dv/ \ @@ -131,15 +132,15 @@ -ffreestanding -nostdlib -o $@ $(SOURCE_FILES) $< %.lst: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objdump -d -S $< > $@ + ${GCC_PREFIX}-objdump -d -S $< > $@ %.hex: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ + ${GCC_PREFIX}-objcopy -O verilog $< $@ # to fix flash base address sed -ie 's/@10/@00/g' $@ %.bin: %.elf - ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + ${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ ############################################################################## @@ -204,8 +205,8 @@ ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) endif -ifeq (,$(wildcard $(GCC_PATH)/$(GCC_PREFIX)-gcc )) - $(error $(GCC_PATH)/$(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) +ifeq (,$(wildcard $(GCC_PREFIX)-gcc )) + $(error $(GCC_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) endif # check for efabless style installation ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog))
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c index 4250a62..f148932 100644 --- a/verilog/dv/wb_port/wb_port.c +++ b/verilog/dv/wb_port/wb_port.c
@@ -87,7 +87,7 @@ reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); - reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64] + reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] reg_la0_data = 0x000; reg_la0_data = 0x001; // Remove Soft Reset
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project index cbeda71..882391f 100644 --- a/verilog/includes/includes.rtl.caravel_user_project +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -1,9 +1,12 @@ # Caravel user project includes ++incdir+$(USER_PROJECT_VERILOG)/rtl/ +incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes +incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes +incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/includes ++incdir+$(USER_PROJECT_VERILOG)/dv/bfm +incdir+$(USER_PROJECT_VERILOG)/dv/model +incdir+$(USER_PROJECT_VERILOG)/dv/agents +$(USER_PROJECT_VERILOG)/rtl/user_reg_map.v -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_reg.sv -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv
diff --git a/verilog/rtl/DFFRAM/DFFRAM.v b/verilog/rtl/DFFRAM/DFFRAM.v index 939fe2c..c90ae93 100644 --- a/verilog/rtl/DFFRAM/DFFRAM.v +++ b/verilog/rtl/DFFRAM/DFFRAM.v
@@ -16,6 +16,8 @@ `default_nettype none + + module DFFRAM ( `ifdef USE_POWER_PINS input VPWR, @@ -29,8 +31,9 @@ input [7:0] A ); +parameter MEM_WORDS= 256; -reg [31:0] mem [0:`MEM_WORDS-1]; +reg [31:0] mem [0:MEM_WORDS-1]; always @(posedge CLK) begin if (EN == 1'b1) begin
diff --git a/verilog/rtl/lib/async_fifo.sv b/verilog/rtl/lib/async_fifo.sv index fd59cfa..cedffdb 100755 --- a/verilog/rtl/lib/async_fifo.sv +++ b/verilog/rtl/lib/async_fifo.sv
@@ -58,7 +58,7 @@ //------------------------------------------- // async FIFO //----------------------------------------------- -//`timescale 1ns/1ps +`timescale 1ns/1ps module async_fifo (wr_clk, wr_reset_n,
diff --git a/verilog/rtl/lib/async_fifo_th.sv b/verilog/rtl/lib/async_fifo_th.sv index 05860f8..5162802 100755 --- a/verilog/rtl/lib/async_fifo_th.sv +++ b/verilog/rtl/lib/async_fifo_th.sv
@@ -70,6 +70,7 @@ // rd_total_aval --> Indicate total no of transfer available //----------------------------------------------- +`timescale 1ns/1ps module async_fifo_th ( wr_clk, wr_reset_n,
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index aed3a9d..c07e16e 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -34,6 +34,9 @@ //// Revision : //// //// 0.1 - 16th Feb 2021, Dinesh A //// //// initial version //// +//// 0.2 - 6 April 2021, Dinesh A //// +//// 1. SSPI CS# increased from 1 to 4 //// +// 2. UART I/F increase from 1 to 2 //// ////////////////////////////////////////////////////////////////////// module pinmux ( @@ -55,11 +58,11 @@ output logic cpu_intf_rst_n , output logic qspim_rst_n , output logic sspim_rst_n , - output logic uart_rst_n , + output logic [1:0] uart_rst_n , output logic i2cm_rst_n , output logic usb_rst_n , - output logic [1:0] cfg_riscv_debug_sel, + output logic [15:0] cfg_riscv_ctrl, // Reg Bus Interface Signal input logic reg_cs, @@ -106,8 +109,8 @@ output logic usb_dn_i, // UART I/F - input logic uart_txd, - output logic uart_rxd, + input logic [1:0] uart_txd, + output logic [1:0] uart_rxd, // I2CM I/F input logic i2cm_clk_o, @@ -119,7 +122,7 @@ // SPI MASTER input logic spim_sck, - input logic spim_ss, + input logic [3:0] spim_ssn, input logic spim_miso, output logic spim_mosi, @@ -365,7 +368,7 @@ .i2cm_rst_n (i2cm_rst_n ), .usb_rst_n (usb_rst_n ), - .cfg_riscv_debug_sel (cfg_riscv_debug_sel ), + .cfg_riscv_ctrl (cfg_riscv_ctrl ), // Reg read/write Interface Inputs @@ -542,9 +545,9 @@ assign cfg_pwm_enb = cfg_multi_func_sel[5:0]; wire [1:0] cfg_int_enb = cfg_multi_func_sel[7:6]; -wire cfg_uart_enb = cfg_multi_func_sel[8]; -wire cfg_i2cm_enb = cfg_multi_func_sel[9]; -wire cfg_spim_enb = cfg_multi_func_sel[10]; +wire [1:0] cfg_uart_enb = cfg_multi_func_sel[9:8]; +wire [3:0] cfg_spim_enb = cfg_multi_func_sel[13:10]; +wire cfg_i2cm_enb = cfg_multi_func_sel[14]; wire [7:0] cfg_port_a_dir_sel = cfg_gpio_dir_sel[7:0]; wire [7:0] cfg_port_b_dir_sel = cfg_gpio_dir_sel[15:8]; @@ -567,23 +570,24 @@ //Pin-1 PC6/RESET* digital_io[0] port_c_in[6] = digital_io_in[0]; - //Pin-2 PD0/RXD digital_io[1] + //Pin-2 PD0/RXD[0] digital_io[1] port_d_in[0] = digital_io_in[1]; - if(cfg_uart_enb) uart_rxd = digital_io_in[1]; + if(cfg_uart_enb[0]) uart_rxd[0] = digital_io_in[1]; - //Pin-3 PD1/TXD digital_io[2] + //Pin-3 PD1/TXD[0] digital_io[2] port_d_in[1] = digital_io_in[2]; - //Pin-4 PD2/INT0 digital_io[3] + //Pin-4 PD2/RXD[1]/INT0 digital_io[3] port_d_in[2] = digital_io_in[3]; - if(cfg_int_enb[0]) ext_intr_in[0] = digital_io_in[3]; + if(cfg_uart_enb[1]) uart_rxd[1] = digital_io_in[3]; + else if(cfg_int_enb[0]) ext_intr_in[0] = digital_io_in[3]; //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] port_d_in[3] = digital_io_in[4]; if(cfg_int_enb[1]) ext_intr_in[1] = digital_io_in[4]; - //Pin-6 PD4 digital_io[5] + //Pin-6 PD4/TXD[1] digital_io[5] port_d_in[4] = digital_io_in[5]; //Pin-9 PB6/XTAL1/TOSC1 digital_io[6] @@ -612,7 +616,7 @@ //Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] port_b_in[3] = digital_io_in[14]; - if(cfg_spim_enb) spim_mosi = digital_io_in[14]; + if(cfg_spim_enb[0]) spim_mosi = digital_io_in[14]; //Pin-18 PB4/MISO digital_io[15] port_b_in[4] = digital_io_in[15]; @@ -658,23 +662,24 @@ //Pin-1 PC6/RESET* digital_io[0] if(cfg_port_c_dir_sel[6]) digital_io_out[0] = port_c_out[6]; - //Pin-2 PD0/RXD digital_io[1] + //Pin-2 PD0/RXD[0] digital_io[1] if(cfg_port_d_dir_sel[0]) digital_io_out[1] = port_d_out[0]; - //Pin-3 PD1/TXD digital_io[2] - if (cfg_uart_enb) digital_io_out[2] = uart_txd; + //Pin-3 PD1/TXD[0] digital_io[2] + if (cfg_uart_enb[0]) digital_io_out[2] = uart_txd[0]; else if(cfg_port_d_dir_sel[1]) digital_io_out[2] = port_d_out[1]; - //Pin-4 PD2/INT0 digital_io[3] + //Pin-4 PD2/RXD[1]/INT0 digital_io[3] if(cfg_port_d_dir_sel[2]) digital_io_out[3] = port_d_out[2]; //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] if(cfg_pwm_enb[0]) digital_io_out[4] = pwm_wfm[0]; else if(cfg_port_d_dir_sel[3]) digital_io_out[4] = port_d_out[3]; - //Pin-6 PD4 digital_io[5] - if(cfg_port_d_dir_sel[4]) digital_io_out[5] = port_d_out[4]; + //Pin-6 PD4/TXD[1] digital_io[5] + if (cfg_uart_enb[1]) digital_io_out[5] = uart_txd[1]; + else if(cfg_port_d_dir_sel[4]) digital_io_out[5] = port_d_out[4]; //Pin-9 PB6/XTAL1/TOSC1 digital_io[6] if(cfg_port_b_dir_sel[6]) digital_io_out[6] = port_b_out[6]; @@ -683,12 +688,14 @@ // Pin-10 PB7/XTAL2/TOSC2 digital_io[7] if(cfg_port_b_dir_sel[7]) digital_io_out[7] = port_b_out[7]; - //Pin-11 PD5/OC0B(PWM1)/T1 digital_io[8] + //Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8] if(cfg_pwm_enb[1]) digital_io_out[8] = pwm_wfm[1]; + else if(cfg_spim_enb[3]) digital_io_out[8] = spim_ssn[3]; else if(cfg_port_d_dir_sel[5]) digital_io_out[8] = port_d_out[5]; - //Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] + //Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] if(cfg_pwm_enb[2]) digital_io_out[9] = pwm_wfm[2]; + else if(cfg_spim_enb[2]) digital_io_out[9] = spim_ssn[2]; else if(cfg_port_d_dir_sel[6]) digital_io_out[9] = port_d_out[6]; @@ -698,13 +705,14 @@ //Pin-14 PB0/CLKO/ICP1 digital_io[11] if(cfg_port_b_dir_sel[0]) digital_io_out[11] = port_b_out[0]; - //Pin-15 PB1/OC1A(PWM3) digital_io[12] + //Pin-15 PB1/SS[1]/OC1A(PWM3) digital_io[12] if(cfg_pwm_enb[3]) digital_io_out[12] = pwm_wfm[3]; + else if(cfg_spim_enb[1]) digital_io_out[12] = spim_ssn[1]; else if(cfg_port_b_dir_sel[1]) digital_io_out[12] = port_b_out[1]; - //Pin-16 PB2/SS/OC1B(PWM4) digital_io[13] + //Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13] if(cfg_pwm_enb[4]) digital_io_out[13] = pwm_wfm[4]; - else if(cfg_spim_enb) digital_io_out[13] = spim_ss; + else if(cfg_spim_enb[0]) digital_io_out[13] = spim_ssn[0]; else if(cfg_port_b_dir_sel[2]) digital_io_out[13] = port_b_out[2]; //Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] @@ -712,11 +720,11 @@ else if(cfg_port_b_dir_sel[3]) digital_io_out[14] = port_b_out[3]; //Pin-18 PB4/MISO digital_io[15] - if(cfg_spim_enb) digital_io_out[15] = spim_miso; + if(cfg_spim_enb[0]) digital_io_out[15] = spim_miso; else if(cfg_port_b_dir_sel[4]) digital_io_out[15] = port_b_out[4]; //Pin-19 PB5/SCK digital_io[16] - if(cfg_spim_enb) digital_io_out[16] = spim_sck; + if(cfg_spim_enb[0]) digital_io_out[16] = spim_sck; else if(cfg_port_b_dir_sel[5]) digital_io_out[16] = port_b_out[5]; //Pin-23 PC0/ADC0 digital_io[18]/analog_io[11] @@ -768,16 +776,17 @@ //Pin-1 PC6/RESET* digital_io[0] if(cfg_port_c_dir_sel[6]) digital_io_oen[0] = 1'b0; - //Pin-2 PD0/RXD digital_io[1] - if (cfg_uart_enb) digital_io_oen[1] = 1'b1; + //Pin-2 PD0/RXD[0] digital_io[1] + if (cfg_uart_enb[0]) digital_io_oen[1] = 1'b1; else if(cfg_port_d_dir_sel[0]) digital_io_oen[1] = 1'b0; - //Pin-3 PD1/TXD digital_io[2] - if (cfg_uart_enb) digital_io_oen[2] = 1'b0; + //Pin-3 PD1/TXD[0] digital_io[2] + if (cfg_uart_enb[0]) digital_io_oen[2] = 1'b0; else if(cfg_port_d_dir_sel[1]) digital_io_oen[2] = 1'b0; - //Pin-4 PD2/INT0 digital_io[3] - if(cfg_int_enb[0]) digital_io_oen[3] = 1'b1; + //Pin-4 PD2/RXD[1]/INT0 digital_io[3] + if (cfg_uart_enb[1]) digital_io_oen[3] = 1'b1; + else if(cfg_int_enb[0]) digital_io_oen[3] = 1'b1; else if(cfg_port_d_dir_sel[2]) digital_io_oen[3] = 1'b0; //Pin-5 PD3/INT1/OC2B(PWM0) digital_io[4] @@ -785,8 +794,9 @@ else if(cfg_int_enb[1]) digital_io_oen[4] = 1'b1; else if(cfg_port_d_dir_sel[3]) digital_io_oen[4] = 1'b0; - //Pin-6 PD4 digital_io[5] - if(cfg_port_d_dir_sel[4]) digital_io_oen[5] = 1'b0; + //Pin-6 PD4/TXD[1] digital_io[5] + if (cfg_uart_enb[1]) digital_io_oen[5] = 1'b0; + else if(cfg_port_d_dir_sel[4]) digital_io_oen[5] = 1'b0; //Pin-9 PB6/XTAL1/TOSC1 digital_io[6] if(cfg_port_b_dir_sel[6]) digital_io_oen[6] = 1'b0; @@ -794,12 +804,14 @@ // Pin-10 PB7/XTAL2/TOSC2 digital_io[7] if(cfg_port_b_dir_sel[7]) digital_io_oen[7] = 1'b0; - //Pin-11 PD5/OC0B(PWM1)/T1 digital_io[8] + //Pin-11 PD5/SS[3]/OC0B(PWM1)/T1 digital_io[8] if(cfg_pwm_enb[1]) digital_io_oen[8] = 1'b0; + else if(cfg_spim_enb[3]) digital_io_oen[8] = 1'b0; else if(cfg_port_d_dir_sel[5]) digital_io_oen[8] = 1'b0; - //Pin-12 PD6/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] + //Pin-12 PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2] if(cfg_pwm_enb[2]) digital_io_oen[9] = 1'b0; + else if(cfg_spim_enb[2]) digital_io_oen[9] = 1'b0; else if(cfg_port_d_dir_sel[6]) digital_io_oen[9] = 1'b0; //Pin-13 PD7/A1N1 digital_io[10]/analog_io[3] @@ -808,26 +820,27 @@ //Pin-14 PB0/CLKO/ICP1 digital_io[11] if(cfg_port_b_dir_sel[0]) digital_io_oen[11] = 1'b0; - //Pin-15 PB1/OC1A(PWM3) digital_io[12] + //Pin-15 PB1/SS[1]/OC1A(PWM3) digital_io[12] if(cfg_pwm_enb[3]) digital_io_oen[12] = 1'b0; + else if(cfg_spim_enb[1]) digital_io_oen[12] = 1'b0; else if(cfg_port_b_dir_sel[1]) digital_io_oen[12] = 1'b0; - //Pin-16 PB2/SS/OC1B(PWM4) digital_io[13] + //Pin-16 PB2/SS[0]/OC1B(PWM4) digital_io[13] if(cfg_pwm_enb[4]) digital_io_oen[13] = 1'b0; - else if(cfg_spim_enb) digital_io_oen[13] = 1'b0; + else if(cfg_spim_enb[0]) digital_io_oen[13] = 1'b0; else if(cfg_port_b_dir_sel[2]) digital_io_oen[13] = 1'b0; //Pin-17 PB3/MOSI/OC2A(PWM5) digital_io[14] - if(cfg_spim_enb) digital_io_oen[14] = 1'b1; + if(cfg_spim_enb[0]) digital_io_oen[14] = 1'b1; else if(cfg_pwm_enb[5]) digital_io_oen[14] = 1'b0; else if(cfg_port_b_dir_sel[3]) digital_io_oen[14] = 1'b0; - //Pin-18 PB4/MISO digital_io[15] - if(cfg_spim_enb) digital_io_oen[15] = 1'b0; + //Pin-18 PB4/MISO digital_io[15] + if(cfg_spim_enb[0]) digital_io_oen[15] = 1'b0; else if(cfg_port_b_dir_sel[4]) digital_io_oen[15] = 1'b0; //Pin-19 PB5/SCK digital_io[16] - if(cfg_spim_enb) digital_io_oen[16] = 1'b0; + if(cfg_spim_enb[0]) digital_io_oen[16] = 1'b0; else if(cfg_port_b_dir_sel[5]) digital_io_oen[16] = 1'b0; //Pin-23 PC0/ADC0 digital_io[18]/analog_io[11]
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv index ebe3b76..c6b33af 100644 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -47,7 +47,7 @@ output logic cpu_intf_rst_n , output logic qspim_rst_n , output logic sspim_rst_n , - output logic uart_rst_n , + output logic [1:0] uart_rst_n , output logic i2cm_rst_n , output logic usb_rst_n , @@ -72,7 +72,7 @@ input logic i2cm_intr, output logic [9:0] cfg_pulse_1us, - output logic [1:0] cfg_riscv_debug_sel, + output logic [15:0] cfg_riscv_ctrl, //--------------------------------------------------- // 6 PWM Configuration @@ -281,9 +281,10 @@ ctech_buf u_buf_cpu_intf_rst (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n)); ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n)); ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n)); -ctech_buf u_buf_uart_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n)); +ctech_buf u_buf_uart0_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n[0])); ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n)); ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[5]),.X(usb_rst_n)); +ctech_buf u_buf_uart1_rst (.A(cfg_glb_ctrl[6]),.X(uart_rst_n[1])); ctech_buf u_buf_cpu0_rst (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0])); ctech_buf u_buf_cpu1_rst (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1])); @@ -317,7 +318,7 @@ ); assign cfg_pulse_1us = reg_2[9:0]; -assign cfg_riscv_debug_sel = reg_2[31:30]; +assign cfg_riscv_ctrl = reg_2[31:16]; //----------------------------------------------------------------------- // reg-3 : Global Interrupt Mask @@ -715,7 +716,7 @@ //----------------------------------------- // Software Reg-2, Release date: <DAY><MONTH><YEAR> // ---------------------------------------- -gen_32b_reg #(32'h1603_2022) u_reg_23 ( +gen_32b_reg #(32'h0604_2022) u_reg_23 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -728,9 +729,9 @@ ); //----------------------------------------- -// Software Reg-3: Poject Revison 3.9 = 0003900 +// Software Reg-3: Poject Revison 4.1 = 0004200 // ---------------------------------------- -gen_32b_reg #(32'h0003_9000) u_reg_24 ( +gen_32b_reg #(32'h0004_2000) u_reg_24 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ),
diff --git a/verilog/rtl/qspim b/verilog/rtl/qspim index efa1519..201a604 160000 --- a/verilog/rtl/qspim +++ b/verilog/rtl/qspim
@@ -1 +1 @@ -Subproject commit efa151915f9d00cb329388845356c5b734601571 +Subproject commit 201a6047f18db8ec792d948a52327b070013ab53
diff --git a/verilog/rtl/sspim/src/sspim_top.sv b/verilog/rtl/sspim/src/sspim_top.sv index 8a632a0..2a28d2e 100755 --- a/verilog/rtl/sspim/src/sspim_top.sv +++ b/verilog/rtl/sspim/src/sspim_top.sv
@@ -44,6 +44,8 @@ //// i.e byte transfer [7:0],[15:8] ...[31:24] //// //// Note: As per SPI transfer still first bit sent //// //// out is big endian, i.e bit[7],[6] ..[0] //// +//// 0.3 - April 6, 2022, Dinesh A //// +//// Four chip select are driven out //// //// //// ////////////////////////////////////////////////////////////////////// //// //// @@ -98,7 +100,7 @@ output logic sck , // clock out output logic so , // serial data out input logic si , // serial data in - output logic ssn // cs_n + output logic [3:0] ssn // Chip Select ); @@ -123,9 +125,7 @@ logic [31:0] cfg_datain ; // data for transfer logic [31:0] cfg_dataout ; // data for received logic hware_op_done ; // operation done -logic [3:0] cs_n ; // cs_n -assign ssn = cs_n[0]; // Only 1 chip select supported in riscdunio sspim_if u_spi_if ( @@ -147,7 +147,7 @@ . sck (sck ), . so (so ), . si (si ), - . cs_n (cs_n ) + . cs_n (ssn ) );
diff --git a/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv index 028f1d7..d94013b 100644 --- a/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv +++ b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
@@ -35,7 +35,8 @@ //// - Dinesh Annayya, dinesha@opencores.org //// //// //// //// Revision : //// -//// //// +//// 0.2 - 7 April 2022, Dinesh-A //// +//// 2nd Uart Integrated //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -75,17 +76,17 @@ input logic wbd_clk_int, output logic wbd_clk_uart, - input logic uart_rstn , // async reset - input logic i2c_rstn , // async reset - input logic usb_rstn , // async reset - input logic spi_rstn , // async reset - input logic app_clk , - input logic usb_clk , // 48Mhz usb clock + input logic [1:0] uart_rstn , // async reset + input logic i2c_rstn , // async reset + input logic usb_rstn , // async reset + input logic spi_rstn , // async reset + input logic app_clk , + input logic usb_clk , // 48Mhz usb clock // Reg Bus Interface Signal input logic reg_cs, input logic reg_wr, - input logic [7:0] reg_addr, + input logic [8:0] reg_addr, input logic [31:0] reg_wdata, input logic [3:0] reg_be, @@ -106,8 +107,8 @@ output logic i2cm_intr_o , // UART I/F - input logic uart_rxd , - output logic uart_txd , + input logic [1:0] uart_rxd , + output logic [1:0] uart_txd , // USB 1.1 HOST I/F input logic usb_in_dp , @@ -123,7 +124,7 @@ output logic sspim_sck, // clock out output logic sspim_so, // serial data out input logic sspim_si, // serial data in - output logic sspim_ssn // cs_n + output logic [3:0] sspim_ssn // cs_n ); @@ -139,57 +140,84 @@ .clk_out (wbd_clk_uart ) ); -`define SEL_UART 2'b00 -`define SEL_I2C 2'b01 -`define SEL_USB 2'b10 -`define SEL_SPI 2'b11 +`define SEL_UART0 3'b000 +`define SEL_I2C 3'b001 +`define SEL_USB 3'b010 +`define SEL_SPI 3'b011 +`define SEL_UART1 3'b100 //---------------------------------------- // Register Response Path Mux // -------------------------------------- -logic [7:0] reg_uart_rdata; +logic [7:0] reg_uart0_rdata; +logic [7:0] reg_uart1_rdata; logic [7:0] reg_i2c_rdata; logic [31:0] reg_usb_rdata; logic [31:0] reg_spim_rdata; -logic reg_uart_ack; +logic reg_uart0_ack; +logic reg_uart1_ack; logic reg_i2c_ack; logic reg_usb_ack; logic reg_spim_ack; -assign reg_rdata = (reg_addr[7:6] == `SEL_UART) ? {24'h0,reg_uart_rdata} : - (reg_addr[7:6] == `SEL_I2C) ? {24'h0,reg_i2c_rdata} : - (reg_addr[7:6] == `SEL_USB) ? reg_usb_rdata : reg_spim_rdata; -assign reg_ack = (reg_addr[7:6] == `SEL_UART) ? reg_uart_ack : - (reg_addr[7:6] == `SEL_I2C) ? reg_i2c_ack : - (reg_addr[7:6] == `SEL_USB) ? reg_usb_ack : reg_spim_ack; +assign reg_rdata = (reg_addr[8:6] == `SEL_UART0) ? {24'h0,reg_uart0_rdata} : + (reg_addr[8:6] == `SEL_UART1) ? {24'h0,reg_uart1_rdata} : + (reg_addr[8:6] == `SEL_I2C) ? {24'h0,reg_i2c_rdata} : + (reg_addr[8:6] == `SEL_USB) ? reg_usb_rdata : reg_spim_rdata; +assign reg_ack = (reg_addr[8:6] == `SEL_UART0) ? reg_uart0_ack : + (reg_addr[8:6] == `SEL_UART1) ? reg_uart1_ack : + (reg_addr[8:6] == `SEL_I2C) ? reg_i2c_ack : + (reg_addr[8:6] == `SEL_USB) ? reg_usb_ack : reg_spim_ack; -wire reg_uart_cs = (reg_addr[7:6] == `SEL_UART) ? reg_cs : 1'b0; -wire reg_i2cm_cs = (reg_addr[7:6] == `SEL_I2C) ? reg_cs : 1'b0; -wire reg_usb_cs = (reg_addr[7:6] == `SEL_USB) ? reg_cs : 1'b0; -wire reg_spim_cs = (reg_addr[7:6] == `SEL_SPI) ? reg_cs : 1'b0; +wire reg_uart0_cs = (reg_addr[8:6] == `SEL_UART0) ? reg_cs : 1'b0; +wire reg_uart1_cs = (reg_addr[8:6] == `SEL_UART1) ? reg_cs : 1'b0; +wire reg_i2cm_cs = (reg_addr[8:6] == `SEL_I2C) ? reg_cs : 1'b0; +wire reg_usb_cs = (reg_addr[8:6] == `SEL_USB) ? reg_cs : 1'b0; +wire reg_spim_cs = (reg_addr[8:6] == `SEL_SPI) ? reg_cs : 1'b0; -uart_core u_uart_core ( +uart_core u_uart0_core ( - .arst_n (uart_rstn ), // async reset + .arst_n (uart_rstn[0] ), // async reset .app_clk (app_clk ), // Reg Bus Interface Signal - .reg_cs (reg_uart_cs ), + .reg_cs (reg_uart0_cs ), .reg_wr (reg_wr ), .reg_addr (reg_addr[5:2] ), .reg_wdata (reg_wdata[7:0] ), .reg_be (reg_be[0] ), // Outputs - .reg_rdata (reg_uart_rdata[7:0]), - .reg_ack (reg_uart_ack ), + .reg_rdata (reg_uart0_rdata[7:0]), + .reg_ack (reg_uart0_ack ), // Pad Control - .rxd (uart_rxd ), - .txd (uart_txd ) + .rxd (uart_rxd[0] ), + .txd (uart_txd[0] ) + ); + +uart_core u_uart1_core ( + + .arst_n (uart_rstn[1] ), // async reset + .app_clk (app_clk ), + + // Reg Bus Interface Signal + .reg_cs (reg_uart1_cs ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr[5:2] ), + .reg_wdata (reg_wdata[7:0] ), + .reg_be (reg_be[0] ), + + // Outputs + .reg_rdata (reg_uart1_rdata[7:0]), + .reg_ack (reg_uart1_ack ), + + // Pad Control + .rxd (uart_rxd[1] ), + .txd (uart_txd[1] ) ); i2cm_top u_i2cm (
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 3169451..10cc6c4 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -201,6 +201,9 @@ //// 3. Risc fuse_mhartid is removed and internal tied //// //// inside risc core //// //// 4. caravel wb addressing issue restrict to 0x300FFFFF//// +//// 4.2 April 6 2022, Dinesh A //// +//// 1. SSPI CS# increased from 1 to 4 //// +//// 2. uart port increase to two //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -416,7 +419,7 @@ // Global Register Wishbone Interface //--------------------------------------------------------------------- wire wbd_uart_stb_o ; // strobe/request -wire [7:0] wbd_uart_adr_o ; // address +wire [8:0] wbd_uart_adr_o ; // address wire wbd_uart_we_o ; // write wire [31:0] wbd_uart_dat_o ; // data output wire [3:0] wbd_uart_sel_o ; // byte enable @@ -433,7 +436,7 @@ wire [1:0] cpu_core_rst_n ; wire qspim_rst_n ; wire sspim_rst_n ; -wire uart_rst_n ; // uart reset +wire [1:0] uart_rst_n ; // uart reset wire i2c_rst_n ; // i2c reset wire usb_rst_n ; // i2c reset wire bist_rst_n ; // i2c reset @@ -515,8 +518,8 @@ wire usb_dn_i ; // UART I/F -wire uart_txd ; -wire uart_rxd ; +wire [1:0] uart_txd ; +wire [1:0] uart_rxd ; // I2CM I/F wire i2cm_clk_o ; @@ -560,7 +563,7 @@ wire sspim_sck ; // clock out wire sspim_so ; // serial data out wire sspim_si ; // serial data in -wire sspim_ssn ; // cs_n +wire [3:0] sspim_ssn ; // cs_n wire usb_intr_o ; @@ -576,6 +579,14 @@ wire [3:0] spi_csn ; +//-------------------------------------------------------------------------- +// Pinmux Risc core config +// ------------------------------------------------------------------------- +wire [15:0] cfg_riscv_ctrl; +wire [3:0] cfg_riscv_sram_lphase = cfg_riscv_ctrl[3:0]; +wire [2:0] cfg_riscv_cache_ctrl = cfg_riscv_ctrl[6:4]; +wire [1:0] cfg_riscv_debug_sel = cfg_riscv_ctrl[9:8]; + ///////////////////////////////////////////////////////// // Clock Skew Ctrl //////////////////////////////////////////////////////// @@ -668,6 +679,7 @@ .rst_n (wbd_int_rst_n ), .cpu_rst_n (cpu_core_rst_n[0] ), .riscv_debug (riscv_debug ), + .cfg_cache_ctrl (cfg_riscv_cache_ctrl ), // Clock .core_clk_mclk (cpu_clk ), @@ -1067,7 +1079,7 @@ // Reg Bus Interface Signal .reg_cs (wbd_uart_stb_o ), .reg_wr (wbd_uart_we_o ), - .reg_addr (wbd_uart_adr_o[7:0] ), + .reg_addr (wbd_uart_adr_o[8:0] ), .reg_wdata (wbd_uart_dat_o ), .reg_be (wbd_uart_sel_o ), @@ -1130,7 +1142,7 @@ .i2cm_rst_n (i2c_rst_n ), .usb_rst_n (usb_rst_n ), - .cfg_riscv_debug_sel ( ), + .cfg_riscv_ctrl (cfg_riscv_ctrl ), // Reg Bus Interface Signal .reg_cs (wbd_glbl_stb_o ), @@ -1185,7 +1197,7 @@ // SPI MASTER .spim_sck (sspim_sck ), - .spim_ss (sspim_ssn ), + .spim_ssn (sspim_ssn ), .spim_miso (sspim_so ), .spim_mosi (sspim_si ),
diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v index 1926c76..dfe3a99 100644 --- a/verilog/rtl/user_reg_map.v +++ b/verilog/rtl/user_reg_map.v
@@ -3,10 +3,11 @@ // So, using wb_host bank select we have changing MSB address [31:16] = 0x1000 // `define ADDR_SPACE_QSPI 32'h3000_0000 -`define ADDR_SPACE_UART 32'h3001_0000 +`define ADDR_SPACE_UART0 32'h3001_0000 `define ADDR_SPACE_I2CM 32'h3001_0040 `define ADDR_SPACE_USB 32'h3001_0080 `define ADDR_SPACE_SSPI 32'h3001_00C0 +`define ADDR_SPACE_UART1 32'h3001_0100 `define ADDR_SPACE_PINMUX 32'h3002_0000 `define ADDR_SPACE_WBHOST 32'h3008_0000
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index fd68e08..8ab9487 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -190,7 +190,7 @@ input logic s1_wbd_ack_i, // input logic s1_wbd_err_i, - unused output logic [31:0] s1_wbd_dat_o, - output logic [7:0] s1_wbd_adr_o, + output logic [8:0] s1_wbd_adr_o, // Uart output logic [3:0] s1_wbd_sel_o, output logic s1_wbd_we_o, output logic s1_wbd_cyc_o, @@ -299,6 +299,7 @@ // 0x1001_0080 to 0x1001_00BF - USB // 0x1001_00C0 to 0x1001_00FF - SSPIM // 0x1002_0000 to 0x1002_00FF - PINMUX +// 0x1001_0100 to 0x1001_013F - UART1 // 0x3080_0000 to 0x3080_00FF - WB HOST (This decoding happens at wb_host block) // --------------------------------------------------------------------------- // @@ -312,10 +313,11 @@ // RISC Data Memory Map // 0x0000_0000 to 0x0FFF_FFFF - QSPIM MEMORY // 0x1000_0000 to 0x1000_00FF - QSPIM REG -// 0x1001_0000 to 0x1001_003F - UART +// 0x1001_0000 to 0x1001_003F - UART0 // 0x1001_0040 to 0x1001_007F - I2 // 0x1001_0080 to 0x1001_00BF - USB // 0x1001_00C0 to 0x1001_00FF - SSPIM +// 0x1001_0100 to 0x1001_013F - UART1 // 0x1002_0000 to 0x1002_00FF - PINMUX //----------------------------- // @@ -660,7 +662,7 @@ assign s0_wbd_stb_o = s0_wb_wr.wbd_stb ; assign s1_wbd_dat_o = s1_wb_wr.wbd_dat ; - assign s1_wbd_adr_o = s1_wb_wr.wbd_adr[7:0] ; + assign s1_wbd_adr_o = s1_wb_wr.wbd_adr[8:0] ; assign s1_wbd_sel_o = s1_wb_wr.wbd_sel ; assign s1_wbd_we_o = s1_wb_wr.wbd_we ; assign s1_wbd_cyc_o = s1_wb_wr.wbd_cyc ;
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c index fe0b434..efc462a 160000 --- a/verilog/rtl/yifive/ycr1c +++ b/verilog/rtl/yifive/ycr1c
@@ -1 +1 @@ -Subproject commit fe0b434aae2822a90d062dc10682a9926c26e2c7 +Subproject commit efc462acd10fe6ba8f7aeed4eb0d6b05635115b3