commit | 952cc0ae9734038fadea0ca6348d62b47560ca49 | [log] [tgz] |
---|---|---|
author | dineshannayya <dinesh.annayya@gmail.com> | Wed Jul 28 14:53:32 2021 +0530 |
committer | dineshannayya <dinesh.annayya@gmail.com> | Wed Jul 28 14:53:32 2021 +0530 |
tree | b1eea2b0179c453c5acebc2a72164af01227ba38 | |
parent | e2d5787b1cd2c70627307283b54ee26fd6c1711c [diff] |
README updated with i2c info
diff --git a/README.md b/README.md index ad39806..62cfcb9 100644 --- a/README.md +++ b/README.md
@@ -50,6 +50,8 @@ * industry-grade and silicon-proven Open-Source RISC-V core from syntacore * industry-graded and silicon-proven 8-bit SDRAM controller * Quad SPI Master + * UART with 16Byte FIFO + * I2C Master * Wishbone compatible design * Written in System Verilog * Open-source tool set