diff --git a/README.md b/README.md
index ad39806..62cfcb9 100644
--- a/README.md
+++ b/README.md
@@ -50,6 +50,8 @@
     * industry-grade and silicon-proven Open-Source RISC-V core from syntacore 
     * industry-graded and silicon-proven 8-bit SDRAM controller
     * Quad SPI Master
+    * UART with 16Byte FIFO
+    * I2C Master
     * Wishbone compatible design
     * Written in System Verilog
     * Open-source tool set