clean up riscv core sim setup
diff --git a/verilog/rtl/sdram_ctrl/docs/sdram_controller_specs.pdf b/verilog/rtl/sdram_ctrl/docs/sdram_controller_specs.pdf deleted file mode 100755 index e54eaed..0000000 --- a/verilog/rtl/sdram_ctrl/docs/sdram_controller_specs.pdf +++ /dev/null Binary files differ
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v deleted file mode 100755 index a78ae9d..0000000 --- a/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v +++ /dev/null
@@ -1,590 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> -// -/********************************************************************* - - SDRAM Controller Bank Controller - - This file is part of the sdram controller project - https://github.com/dineshannayya/yifive_r0.git - http://www.opencores.org/cores/yifive/ - http://www.opencores.org/cores/sdr_ctrl/ - - Description: - This module takes requests from sdrc_req_gen, checks for page hit/miss and - issues precharge/activate commands and then passes the request to sdrc_xfr_ctl. - - To Do: - nothing - - Author(s): - - Dinesh Annayya, dinesha@opencores.org - Version : 1.0 - 8th Jan 2012 - - - - Copyright (C) 2000 Authors and OPENCORES.ORG - - This source file may be used and distributed without - restriction provided that this copyright statement is not - removed from the file and that any derivative work contains - the original copyright notice and the associated disclaimer. - - This source file is free software; you can redistribute it - and/or modify it under the terms of the GNU Lesser General - Public License as published by the Free Software Foundation; - either version 2.1 of the License, or (at your option) any -later version. - - This source is distributed in the hope that it will be - useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - PURPOSE. See the GNU Lesser General Public License for more - details. - - You should have received a copy of the GNU Lesser General - Public License along with this source; if not, download it - from http://www.opencores.org/lgpl.shtml - -*******************************************************************/ - - -`include "sdrc_define.v" - -module sdrc_bank_ctl (clk, - reset_n, - a2b_req_depth, // Number of requests we can buffer - - /* Req from req_gen */ - r2b_req, // request - r2b_req_id, // ID - r2b_start, // First chunk of burst - r2b_last, // Last chunk of burst - r2b_wrap, - r2b_ba, // bank address - r2b_raddr, // row address - r2b_caddr, // col address - r2b_len, // length - r2b_write, // write request - b2r_arb_ok, // OK to arbitrate for next xfr - b2r_ack, - - /* Transfer request to xfr_ctl */ - b2x_idle, // All banks are idle - b2x_req, // Request to xfr_ctl - b2x_start, // first chunk of transfer - b2x_last, // last chunk of transfer - b2x_wrap, - b2x_id, // Transfer ID - b2x_ba, // bank address - b2x_addr, // row/col address - b2x_len, // transfer length - b2x_cmd, // transfer command - x2b_ack, // command accepted - - /* Status to/from xfr_ctl */ - b2x_tras_ok, // TRAS OK for all banks - x2b_refresh, // We did a refresh - x2b_pre_ok, // OK to do a precharge (per bank) - x2b_act_ok, // OK to do an activate - x2b_rdok, // OK to do a read - x2b_wrok, // OK to do a write - - /* xfr msb address */ - xfr_bank_sel, - sdr_req_norm_dma_last, - - /* SDRAM Timing */ - tras_delay, // Active to precharge delay - trp_delay, // Precharge to active delay - trcd_delay); // Active to R/W delay - -parameter SDR_DW = 16; // SDR Data Width -parameter SDR_BW = 2; // SDR Byte Width - input clk, reset_n; - - input [1:0] a2b_req_depth; - - /* Req from bank_ctl */ - input r2b_req, r2b_start, r2b_last, - r2b_write, r2b_wrap; - input [`SDR_REQ_ID_W-1:0] r2b_req_id; - input [1:0] r2b_ba; - input [12:0] r2b_raddr; - input [12:0] r2b_caddr; - input [`REQ_BW-1:0] r2b_len; - output b2r_arb_ok, b2r_ack; - input sdr_req_norm_dma_last; - - /* Req to xfr_ctl */ - output b2x_idle, b2x_req, b2x_start, b2x_last, - b2x_tras_ok, b2x_wrap; - output [`SDR_REQ_ID_W-1:0] b2x_id; - output [1:0] b2x_ba; - output [12:0] b2x_addr; - output [`REQ_BW-1:0] b2x_len; - output [1:0] b2x_cmd; - input x2b_ack; - - /* Status from xfr_ctl */ - input [3:0] x2b_pre_ok; - input x2b_refresh, x2b_act_ok, x2b_rdok, - x2b_wrok; - - input [3:0] tras_delay, trp_delay, trcd_delay; - - input [1:0] xfr_bank_sel; - - /****************************************************************************/ - // Internal Nets - - wire [3:0] r2i_req, i2r_ack, i2x_req, - i2x_start, i2x_last, i2x_wrap, tras_ok; - wire [12:0] i2x_addr0, i2x_addr1, i2x_addr2, i2x_addr3; - wire [`REQ_BW-1:0] i2x_len0, i2x_len1, i2x_len2, i2x_len3; - wire [1:0] i2x_cmd0, i2x_cmd1, i2x_cmd2, i2x_cmd3; - wire [`SDR_REQ_ID_W-1:0] i2x_id0, i2x_id1, i2x_id2, i2x_id3; - - reg b2x_req; - wire b2x_idle, b2x_start, b2x_last, b2x_wrap; - wire [`SDR_REQ_ID_W-1:0] b2x_id; - wire [12:0] b2x_addr; - wire [`REQ_BW-1:0] b2x_len; - wire [1:0] b2x_cmd; - wire [3:0] x2i_ack; - reg [1:0] b2x_ba; - - reg [`SDR_REQ_ID_W-1:0] curr_id; - - wire [1:0] xfr_ba; - wire xfr_ba_last; - wire [3:0] xfr_ok; - - // This 8 bit register stores the bank addresses for upto 4 requests. - reg [7:0] rank_ba; - reg [3:0] rank_ba_last; - // This 3 bit counter counts the number of requests we have - // buffered so far, legal values are 0, 1, 2, 3, or 4. - reg [2:0] rank_cnt; - wire [3:0] rank_req, rank_wr_sel; - wire rank_fifo_wr, rank_fifo_rd; - wire rank_fifo_full, rank_fifo_mt; - - wire [12:0] bank0_row, bank1_row, bank2_row, bank3_row; - - assign b2x_tras_ok = &tras_ok; - - - // Distribute the request from req_gen - - assign r2i_req[0] = (r2b_ba == 2'b00) ? r2b_req & ~rank_fifo_full : 1'b0; - assign r2i_req[1] = (r2b_ba == 2'b01) ? r2b_req & ~rank_fifo_full : 1'b0; - assign r2i_req[2] = (r2b_ba == 2'b10) ? r2b_req & ~rank_fifo_full : 1'b0; - assign r2i_req[3] = (r2b_ba == 2'b11) ? r2b_req & ~rank_fifo_full : 1'b0; - - /****************** - Modified the Better FPGA Timing Purpose - assign b2r_ack = (r2b_ba == 2'b00) ? i2r_ack[0] : - (r2b_ba == 2'b01) ? i2r_ack[1] : - (r2b_ba == 2'b10) ? i2r_ack[2] : - (r2b_ba == 2'b11) ? i2r_ack[3] : 1'b0; - ********************/ - // Assumption: Only one Ack Will be asserted at a time. - assign b2r_ack =|i2r_ack; - - assign b2r_arb_ok = ~rank_fifo_full; - - // Put the requests from the 4 bank_fsms into a 4 deep shift - // register file. The earliest request is prioritized over the - // later requests. Also the number of requests we are allowed to - // buffer is limited by a 2 bit external input - - // Mux the req/cmd to xfr_ctl. Allow RD/WR commands from the request in - // rank0, allow only PR/ACT commands from the requests in other ranks - // If the rank_fifo is empty, send the request from the bank addressed by - // r2b_ba - - // In FPGA Mode, to improve the timing, also send the rank_ba - assign xfr_ba = (`TARGET_DESIGN == `FPGA) ? rank_ba[1:0]: - ((rank_fifo_mt) ? r2b_ba : rank_ba[1:0]); - assign xfr_ba_last = (`TARGET_DESIGN == `FPGA) ? rank_ba_last[0]: - ((rank_fifo_mt) ? sdr_req_norm_dma_last : rank_ba_last[0]); - - assign rank_req[0] = i2x_req[xfr_ba]; // each rank generates requests - - assign rank_req[1] = (rank_cnt < 3'h2) ? 1'b0 : - (rank_ba[3:2] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] : - (rank_ba[3:2] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] : - (rank_ba[3:2] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] : - i2x_req[3] & ~i2x_cmd3[1]; - - assign rank_req[2] = (rank_cnt < 3'h3) ? 1'b0 : - (rank_ba[5:4] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] : - (rank_ba[5:4] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] : - (rank_ba[5:4] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] : - i2x_req[3] & ~i2x_cmd3[1]; - - assign rank_req[3] = (rank_cnt < 3'h4) ? 1'b0 : - (rank_ba[7:6] == 2'b00) ? i2x_req[0] & ~i2x_cmd0[1] : - (rank_ba[7:6] == 2'b01) ? i2x_req[1] & ~i2x_cmd1[1] : - (rank_ba[7:6] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] : - i2x_req[3] & ~i2x_cmd3[1]; - - always @ (*) begin - b2x_req = 1'b0; - b2x_ba = xfr_ba; - - if(`TARGET_DESIGN == `ASIC) begin // Support Multiple Rank request only on ASIC - if (rank_req[0]) begin - b2x_req = 1'b1; - b2x_ba = xfr_ba; - end // if (rank_req[0]) - else if (rank_req[1]) begin - b2x_req = 1'b1; - b2x_ba = rank_ba[3:2]; - end // if (rank_req[1]) - else if (rank_req[2]) begin - b2x_req = 1'b1; - b2x_ba = rank_ba[5:4]; - end // if (rank_req[2]) - else if (rank_req[3]) begin - b2x_req = 1'b1; - b2x_ba = rank_ba[7:6]; - end // if (rank_req[3]) - end else begin // If FPGA - if (rank_req[0]) begin - b2x_req = 1'b1; - end - end - end // always @ (rank_req or rank_fifo_mt or r2b_ba or rank_ba) - - assign b2x_idle = rank_fifo_mt; - assign b2x_start = i2x_start[b2x_ba]; - assign b2x_last = i2x_last[b2x_ba]; - assign b2x_wrap = i2x_wrap[b2x_ba]; - - assign b2x_addr = (b2x_ba == 2'b11) ? i2x_addr3 : - (b2x_ba == 2'b10) ? i2x_addr2 : - (b2x_ba == 2'b01) ? i2x_addr1 : i2x_addr0; - - assign b2x_len = (b2x_ba == 2'b11) ? i2x_len3 : - (b2x_ba == 2'b10) ? i2x_len2 : - (b2x_ba == 2'b01) ? i2x_len1 : i2x_len0; - - assign b2x_cmd = (b2x_ba == 2'b11) ? i2x_cmd3 : - (b2x_ba == 2'b10) ? i2x_cmd2 : - (b2x_ba == 2'b01) ? i2x_cmd1 : i2x_cmd0; - - assign b2x_id = (b2x_ba == 2'b11) ? i2x_id3 : - (b2x_ba == 2'b10) ? i2x_id2 : - (b2x_ba == 2'b01) ? i2x_id1 : i2x_id0; - - assign x2i_ack[0] = (b2x_ba == 2'b00) ? x2b_ack : 1'b0; - assign x2i_ack[1] = (b2x_ba == 2'b01) ? x2b_ack : 1'b0; - assign x2i_ack[2] = (b2x_ba == 2'b10) ? x2b_ack : 1'b0; - assign x2i_ack[3] = (b2x_ba == 2'b11) ? x2b_ack : 1'b0; - - // Rank Fifo - // On a write write to selected rank and increment rank_cnt - // On a read shift rank_ba right 2 bits and decrement rank_cnt - - assign rank_fifo_wr = b2r_ack; - - assign rank_fifo_rd = b2x_req & b2x_cmd[1] & x2b_ack; - - assign rank_wr_sel[0] = (rank_cnt == 3'h0) ? rank_fifo_wr : - (rank_cnt == 3'h1) ? rank_fifo_wr & rank_fifo_rd : - 1'b0; - - assign rank_wr_sel[1] = (rank_cnt == 3'h1) ? rank_fifo_wr & ~rank_fifo_rd : - (rank_cnt == 3'h2) ? rank_fifo_wr & rank_fifo_rd : - 1'b0; - - assign rank_wr_sel[2] = (rank_cnt == 3'h2) ? rank_fifo_wr & ~rank_fifo_rd : - (rank_cnt == 3'h3) ? rank_fifo_wr & rank_fifo_rd : - 1'b0; - - assign rank_wr_sel[3] = (rank_cnt == 3'h3) ? rank_fifo_wr & ~rank_fifo_rd : - (rank_cnt == 3'h4) ? rank_fifo_wr & rank_fifo_rd : - 1'b0; - - assign rank_fifo_mt = (rank_cnt == 3'b0) ? 1'b1 : 1'b0; - - assign rank_fifo_full = (rank_cnt[2]) ? 1'b1 : - (rank_cnt[1:0] == a2b_req_depth) ? 1'b1 : 1'b0; - - // FIFO Check - - // synopsys translate_off - - always @ (posedge clk) begin - - if (~rank_fifo_wr & rank_fifo_rd && rank_cnt == 3'h0) begin - $display ("%t: %m: ERROR!!! Read from empty Fifo", $time); - $stop; - end // if (rank_fifo_rd && rank_cnt == 3'h0) - - if (rank_fifo_wr && ~rank_fifo_rd && rank_cnt == 3'h4) begin - $display ("%t: %m: ERROR!!! Write to full Fifo", $time); - $stop; - end // if (rank_fifo_wr && ~rank_fifo_rd && rank_cnt == 3'h4) - - end // always @ (posedge clk) - - // synopsys translate_on - - always @ (posedge clk) - if (~reset_n) begin - rank_cnt <= 3'b0; - rank_ba <= 8'b0; - rank_ba_last <= 4'b0; - - end // if (~reset_n) - else begin - - rank_cnt <= (rank_fifo_wr & ~rank_fifo_rd) ? rank_cnt + 3'b1 : - (~rank_fifo_wr & rank_fifo_rd) ? rank_cnt - 3'b1 : - rank_cnt; - - rank_ba[1:0] <= (rank_wr_sel[0]) ? r2b_ba : - (rank_fifo_rd) ? rank_ba[3:2] : rank_ba[1:0]; - - rank_ba[3:2] <= (rank_wr_sel[1]) ? r2b_ba : - (rank_fifo_rd) ? rank_ba[5:4] : rank_ba[3:2]; - - rank_ba[5:4] <= (rank_wr_sel[2]) ? r2b_ba : - (rank_fifo_rd) ? rank_ba[7:6] : rank_ba[5:4]; - - rank_ba[7:6] <= (rank_wr_sel[3]) ? r2b_ba : - (rank_fifo_rd) ? 2'b00 : rank_ba[7:6]; - - if(`TARGET_DESIGN == `ASIC) begin // This Logic is implemented for ASIC Only - // Note: Currenly top-level does not generate the - // sdr_req_norm_dma_last signal and can be tied zero at top-level - rank_ba_last[0] <= (rank_wr_sel[0]) ? sdr_req_norm_dma_last : - (rank_fifo_rd) ? rank_ba_last[1] : rank_ba_last[0]; - - rank_ba_last[1] <= (rank_wr_sel[1]) ? sdr_req_norm_dma_last : - (rank_fifo_rd) ? rank_ba_last[2] : rank_ba_last[1]; - - rank_ba_last[2] <= (rank_wr_sel[2]) ? sdr_req_norm_dma_last : - (rank_fifo_rd) ? rank_ba_last[3] : rank_ba_last[2]; - - rank_ba_last[3] <= (rank_wr_sel[3]) ? sdr_req_norm_dma_last : - (rank_fifo_rd) ? 1'b0 : rank_ba_last[3]; - end - - end // else: !if(~reset_n) - - assign xfr_ok[0] = (xfr_ba == 2'b00) ? 1'b1 : 1'b0; - assign xfr_ok[1] = (xfr_ba == 2'b01) ? 1'b1 : 1'b0; - assign xfr_ok[2] = (xfr_ba == 2'b10) ? 1'b1 : 1'b0; - assign xfr_ok[3] = (xfr_ba == 2'b11) ? 1'b1 : 1'b0; - - /****************************************************************************/ - // Instantiate Bank Ctl FSM 0 - - sdrc_bank_fsm bank0_fsm (.clk (clk), - .reset_n (reset_n), - - /* Req from req_gen */ - .r2b_req (r2i_req[0]), - .r2b_req_id (r2b_req_id), - .r2b_start (r2b_start), - .r2b_last (r2b_last), - .r2b_wrap (r2b_wrap), - .r2b_raddr (r2b_raddr), - .r2b_caddr (r2b_caddr), - .r2b_len (r2b_len), - .r2b_write (r2b_write), - .b2r_ack (i2r_ack[0]), - .sdr_dma_last(rank_ba_last[0]), - - /* Transfer request to xfr_ctl */ - .b2x_req (i2x_req[0]), - .b2x_start (i2x_start[0]), - .b2x_last (i2x_last[0]), - .b2x_wrap (i2x_wrap[0]), - .b2x_id (i2x_id0), - .b2x_addr (i2x_addr0), - .b2x_len (i2x_len0), - .b2x_cmd (i2x_cmd0), - .x2b_ack (x2i_ack[0]), - - /* Status to/from xfr_ctl */ - .tras_ok (tras_ok[0]), - .xfr_ok (xfr_ok[0]), - .x2b_refresh (x2b_refresh), - .x2b_pre_ok (x2b_pre_ok[0]), - .x2b_act_ok (x2b_act_ok), - .x2b_rdok (x2b_rdok), - .x2b_wrok (x2b_wrok), - - .bank_row(bank0_row), - - /* SDRAM Timing */ - .tras_delay (tras_delay), - .trp_delay (trp_delay), - .trcd_delay (trcd_delay)); - - /****************************************************************************/ - // Instantiate Bank Ctl FSM 1 - - sdrc_bank_fsm bank1_fsm (.clk (clk), - .reset_n (reset_n), - - /* Req from req_gen */ - .r2b_req (r2i_req[1]), - .r2b_req_id (r2b_req_id), - .r2b_start (r2b_start), - .r2b_last (r2b_last), - .r2b_wrap (r2b_wrap), - .r2b_raddr (r2b_raddr), - .r2b_caddr (r2b_caddr), - .r2b_len (r2b_len), - .r2b_write (r2b_write), - .b2r_ack (i2r_ack[1]), - .sdr_dma_last(rank_ba_last[1]), - - /* Transfer request to xfr_ctl */ - .b2x_req (i2x_req[1]), - .b2x_start (i2x_start[1]), - .b2x_last (i2x_last[1]), - .b2x_wrap (i2x_wrap[1]), - .b2x_id (i2x_id1), - .b2x_addr (i2x_addr1), - .b2x_len (i2x_len1), - .b2x_cmd (i2x_cmd1), - .x2b_ack (x2i_ack[1]), - - /* Status to/from xfr_ctl */ - .tras_ok (tras_ok[1]), - .xfr_ok (xfr_ok[1]), - .x2b_refresh (x2b_refresh), - .x2b_pre_ok (x2b_pre_ok[1]), - .x2b_act_ok (x2b_act_ok), - .x2b_rdok (x2b_rdok), - .x2b_wrok (x2b_wrok), - - .bank_row(bank1_row), - - /* SDRAM Timing */ - .tras_delay (tras_delay), - .trp_delay (trp_delay), - .trcd_delay (trcd_delay)); - - /****************************************************************************/ - // Instantiate Bank Ctl FSM 2 - - sdrc_bank_fsm bank2_fsm (.clk (clk), - .reset_n (reset_n), - - /* Req from req_gen */ - .r2b_req (r2i_req[2]), - .r2b_req_id (r2b_req_id), - .r2b_start (r2b_start), - .r2b_last (r2b_last), - .r2b_wrap (r2b_wrap), - .r2b_raddr (r2b_raddr), - .r2b_caddr (r2b_caddr), - .r2b_len (r2b_len), - .r2b_write (r2b_write), - .b2r_ack (i2r_ack[2]), - .sdr_dma_last(rank_ba_last[2]), - - /* Transfer request to xfr_ctl */ - .b2x_req (i2x_req[2]), - .b2x_start (i2x_start[2]), - .b2x_last (i2x_last[2]), - .b2x_wrap (i2x_wrap[2]), - .b2x_id (i2x_id2), - .b2x_addr (i2x_addr2), - .b2x_len (i2x_len2), - .b2x_cmd (i2x_cmd2), - .x2b_ack (x2i_ack[2]), - - /* Status to/from xfr_ctl */ - .tras_ok (tras_ok[2]), - .xfr_ok (xfr_ok[2]), - .x2b_refresh (x2b_refresh), - .x2b_pre_ok (x2b_pre_ok[2]), - .x2b_act_ok (x2b_act_ok), - .x2b_rdok (x2b_rdok), - .x2b_wrok (x2b_wrok), - - .bank_row(bank2_row), - - /* SDRAM Timing */ - .tras_delay (tras_delay), - .trp_delay (trp_delay), - .trcd_delay (trcd_delay)); - - /****************************************************************************/ - // Instantiate Bank Ctl FSM 3 - - sdrc_bank_fsm bank3_fsm (.clk (clk), - .reset_n (reset_n), - - /* Req from req_gen */ - .r2b_req (r2i_req[3]), - .r2b_req_id (r2b_req_id), - .r2b_start (r2b_start), - .r2b_last (r2b_last), - .r2b_wrap (r2b_wrap), - .r2b_raddr (r2b_raddr), - .r2b_caddr (r2b_caddr), - .r2b_len (r2b_len), - .r2b_write (r2b_write), - .b2r_ack (i2r_ack[3]), - .sdr_dma_last(rank_ba_last[3]), - - /* Transfer request to xfr_ctl */ - .b2x_req (i2x_req[3]), - .b2x_start (i2x_start[3]), - .b2x_last (i2x_last[3]), - .b2x_wrap (i2x_wrap[3]), - .b2x_id (i2x_id3), - .b2x_addr (i2x_addr3), - .b2x_len (i2x_len3), - .b2x_cmd (i2x_cmd3), - .x2b_ack (x2i_ack[3]), - - /* Status to/from xfr_ctl */ - .tras_ok (tras_ok[3]), - .xfr_ok (xfr_ok[3]), - .x2b_refresh (x2b_refresh), - .x2b_pre_ok (x2b_pre_ok[3]), - .x2b_act_ok (x2b_act_ok), - .x2b_rdok (x2b_rdok), - .x2b_wrok (x2b_wrok), - - .bank_row(bank3_row), - - /* SDRAM Timing */ - .tras_delay (tras_delay), - .trp_delay (trp_delay), - .trcd_delay (trcd_delay)); - - -/* address for current xfr, debug only */ -wire [12:0] cur_row = (xfr_bank_sel==3) ? bank3_row: - (xfr_bank_sel==2) ? bank2_row: - (xfr_bank_sel==1) ? bank1_row: bank0_row; - - - -endmodule // sdr_bank_ctl
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v deleted file mode 100755 index 2ce60d3..0000000 --- a/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v +++ /dev/null
@@ -1,395 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> -// -/********************************************************************* - - SDRAM Controller Bank Controller - - This file is part of the sdram controller project - https://github.com/dineshannayya/yifive_r0.git - http://www.opencores.org/cores/yifive/ - http://www.opencores.org/cores/sdr_ctrl/ - - Description: - This module takes requests from sdrc_req_gen, checks for page hit/miss and - issues precharge/activate commands and then passes the request to sdrc_xfr_ctl. - - To Do: - nothing - - Author(s): - - Dinesh Annayya, dinesha@opencores.org - Version : 1.0 - 8th Jan 2012 - Version : 1.1 - 27th Aug 2021 - Disabling the `TARGET_DESIGN with FPGA, Breaking timing path creating functional issue - Recommnended to use onlt in ASIC Mode. In FPGA mode, tRAS violation are noticed and design - has corner case between Active to Pre-charge - ERROR: tRAS violation during Precharge all bank - - - - Copyright (C) 2000 Authors and OPENCORES.ORG - - This source file may be used and distributed without - restriction provided that this copyright statement is not - removed from the file and that any derivative work contains - the original copyright notice and the associated disclaimer. - - This source file is free software; you can redistribute it - and/or modify it under the terms of the GNU Lesser General - Public License as published by the Free Software Foundation; - either version 2.1 of the License, or (at your option) any -later version. - - This source is distributed in the hope that it will be - useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - PURPOSE. See the GNU Lesser General Public License for more - details. - - You should have received a copy of the GNU Lesser General - Public License along with this source; if not, download it - from http://www.opencores.org/lgpl.shtml - -*******************************************************************/ - - -`include "sdrc_define.v" - -module sdrc_bank_fsm (clk, - reset_n, - - /* Req from req_gen */ - r2b_req, // request - r2b_req_id, // ID - r2b_start, // First chunk of burst - r2b_last, // Last chunk of burst - r2b_wrap, - r2b_raddr, // row address - r2b_caddr, // col address - r2b_len, // length - r2b_write, // write request - b2r_ack, - sdr_dma_last, - - /* Transfer request to xfr_ctl */ - b2x_req, // Request to xfr_ctl - b2x_start, // first chunk of transfer - b2x_last, // last chunk of transfer - b2x_wrap, - b2x_id, // Transfer ID - b2x_addr, // row/col address - b2x_len, // transfer length - b2x_cmd, // transfer command - x2b_ack, // command accepted - - /* Status to/from xfr_ctl */ - tras_ok, // TRAS OK for this bank - xfr_ok, - x2b_refresh, // We did a refresh - x2b_pre_ok, // OK to do a precharge (per bank) - x2b_act_ok, // OK to do an activate - x2b_rdok, // OK to do a read - x2b_wrok, // OK to do a write - - /* current xfr row address of the bank */ - bank_row, - - /* SDRAM Timing */ - tras_delay, // Active to precharge delay - trp_delay, // Precharge to active delay - trcd_delay); // Active to R/W delay - - -parameter SDR_DW = 16; // SDR Data Width -parameter SDR_BW = 2; // SDR Byte Width - - input clk, reset_n; - - /* Req from bank_ctl */ - input r2b_req, r2b_start, r2b_last, - r2b_write, r2b_wrap; - input [`SDR_REQ_ID_W-1:0] r2b_req_id; - input [12:0] r2b_raddr; - input [12:0] r2b_caddr; - input [`REQ_BW-1:0] r2b_len; - output b2r_ack; - input sdr_dma_last; - - /* Req to xfr_ctl */ - output b2x_req, b2x_start, b2x_last, - tras_ok, b2x_wrap; - output [`SDR_REQ_ID_W-1:0] b2x_id; - output [12:0] b2x_addr; - output [`REQ_BW-1:0] b2x_len; - output [1:0] b2x_cmd; - input x2b_ack; - - /* Status from xfr_ctl */ - input x2b_refresh, x2b_act_ok, x2b_rdok, - x2b_wrok, x2b_pre_ok, xfr_ok; - - input [3:0] tras_delay, trp_delay, trcd_delay; - - output [12:0] bank_row; - - /****************************************************************************/ - // Internal Nets - - `define BANK_IDLE 3'b000 - `define BANK_PRE 3'b001 - `define BANK_ACT 3'b010 - `define BANK_XFR 3'b011 - `define BANK_DMA_LAST_PRE 3'b100 - - reg [2:0] bank_st, next_bank_st; - wire b2x_start, b2x_last; - reg l_start, l_last; - reg b2x_req, b2r_ack; - wire [`SDR_REQ_ID_W-1:0] b2x_id; - reg [`SDR_REQ_ID_W-1:0] l_id; - reg [12:0] b2x_addr; - reg [`REQ_BW-1:0] l_len; - wire [`REQ_BW-1:0] b2x_len; - reg [1:0] b2x_cmd_t; - reg bank_valid; - reg [12:0] bank_row; - reg [3:0] tras_cntr, timer0; - reg l_wrap, l_write; - wire b2x_wrap; - reg [12:0] l_raddr; - reg [12:0] l_caddr; - reg l_sdr_dma_last; - reg bank_prech_page_closed; - - wire tras_ok_internal, tras_ok, activate_bank; - - wire page_hit, timer0_tc_t, ld_trp, ld_trcd; - - /*** Timing Break Logic Added for FPGA - Start ****/ - reg x2b_wrok_r, xfr_ok_r , x2b_rdok_r; - reg [1:0] b2x_cmd_r,timer0_tc_r,tras_ok_r,x2b_pre_ok_r,x2b_act_ok_r; - always @ (posedge clk) - if (~reset_n) begin - x2b_wrok_r <= 1'b0; - xfr_ok_r <= 1'b0; - x2b_rdok_r <= 1'b0; - b2x_cmd_r <= 2'b0; - timer0_tc_r <= 1'b0; - tras_ok_r <= 1'b0; - x2b_pre_ok_r <= 1'b0; - x2b_act_ok_r <= 1'b0; - end - else begin - x2b_wrok_r <= x2b_wrok; - xfr_ok_r <= xfr_ok; - x2b_rdok_r <= x2b_rdok; - b2x_cmd_r <= b2x_cmd_t; - timer0_tc_r <= (ld_trp | ld_trcd) ? 1'b0 : timer0_tc_t; - tras_ok_r <= tras_ok_internal; - x2b_pre_ok_r <= x2b_pre_ok; - x2b_act_ok_r <= x2b_act_ok; - end - - wire x2b_wrok_t = (`TARGET_DESIGN == `FPGA) ? x2b_wrok_r : x2b_wrok; - wire xfr_ok_t = (`TARGET_DESIGN == `FPGA) ? xfr_ok_r : xfr_ok; - wire x2b_rdok_t = (`TARGET_DESIGN == `FPGA) ? x2b_rdok_r : x2b_rdok; - wire [1:0] b2x_cmd = (`TARGET_DESIGN == `FPGA) ? b2x_cmd_r : b2x_cmd_t; - wire timer0_tc = (`TARGET_DESIGN == `FPGA) ? timer0_tc_r : timer0_tc_t; - assign tras_ok = (`TARGET_DESIGN == `FPGA) ? tras_ok_r : tras_ok_internal; - wire x2b_pre_ok_t = (`TARGET_DESIGN == `FPGA) ? x2b_pre_ok_r : x2b_pre_ok; - wire x2b_act_ok_t = (`TARGET_DESIGN == `FPGA) ? x2b_act_ok_r : x2b_act_ok; - - /*** Timing Break Logic Added for FPGA - End****/ - - - always @ (posedge clk) - if (~reset_n) begin - bank_valid <= 1'b0; - tras_cntr <= 4'b0; - timer0 <= 4'b0; - bank_st <= `BANK_IDLE; - end // if (~reset_n) - - else begin - - bank_valid <= (x2b_refresh || bank_prech_page_closed) ? 1'b0 : // force the bank status to be invalid - (activate_bank) ? 1'b1 : bank_valid; - - tras_cntr <= (activate_bank) ? tras_delay : - (~tras_ok_internal) ? tras_cntr - 4'b1 : 4'b0; - - timer0 <= (ld_trp) ? trp_delay : - (ld_trcd) ? trcd_delay : - (timer0 != 'h0) ? timer0 - 4'b1 : timer0; - - bank_st <= next_bank_st; - - end // else: !if(~reset_n) - - always @ (posedge clk) begin - - bank_row <= (bank_st == `BANK_ACT) ? b2x_addr : bank_row; - - if (~reset_n) begin - l_start <= 1'b0; - l_last <= 1'b0; - l_id <= 1'b0; - l_len <= 1'b0; - l_wrap <= 1'b0; - l_write <= 1'b0; - l_raddr <= 1'b0; - l_caddr <= 1'b0; - l_sdr_dma_last <= 1'b0; - end - else begin - if (b2r_ack) begin - l_start <= r2b_start; - l_last <= r2b_last; - l_id <= r2b_req_id; - l_len <= r2b_len; - l_wrap <= r2b_wrap; - l_write <= r2b_write; - l_raddr <= r2b_raddr; - l_caddr <= r2b_caddr; - l_sdr_dma_last <= sdr_dma_last; - end // if (b2r_ack) - end - - end // always @ (posedge clk) - - assign tras_ok_internal = ~|tras_cntr; - - assign activate_bank = (b2x_cmd == `OP_ACT) & x2b_ack; - - assign page_hit = (r2b_raddr == bank_row) ? bank_valid : 1'b0; // its a hit only if bank is valid - - assign timer0_tc_t = ~|timer0; - - assign ld_trp = (b2x_cmd == `OP_PRE) ? x2b_ack : 1'b0; - - assign ld_trcd = (b2x_cmd == `OP_ACT) ? x2b_ack : 1'b0; - - - - always @ (*) begin - - bank_prech_page_closed = 1'b0; - b2x_req = 1'b0; - b2x_cmd_t = 2'bx; - b2r_ack = 1'b0; - b2x_addr = 13'bx; - next_bank_st = bank_st; - - case (bank_st) - - `BANK_IDLE : begin - if(`TARGET_DESIGN == `FPGA) begin // To break the timing, b2x request are generated delayed - if (~r2b_req) begin - next_bank_st = `BANK_IDLE; - end // if (~r2b_req) - else if (page_hit) begin - b2r_ack = 1'b1; - b2x_cmd_t = (r2b_write) ? `OP_WR : `OP_RD; - next_bank_st = `BANK_XFR; - end // if (page_hit) - else begin // page_miss - b2r_ack = 1'b1; - b2x_cmd_t = `OP_PRE; - next_bank_st = `BANK_PRE; // bank was precharged on l_sdr_dma_last - end // else: !if(page_hit) - end else begin // ASIC - if (~r2b_req) begin - bank_prech_page_closed = 1'b0; - b2x_req = 1'b0; - b2x_cmd_t = 2'bx; - b2r_ack = 1'b0; - b2x_addr = 13'bx; - next_bank_st = `BANK_IDLE; - end // if (~r2b_req) - else if (page_hit) begin - b2x_req = (r2b_write) ? x2b_wrok_t & xfr_ok_t : - x2b_rdok_t & xfr_ok_t; - b2x_cmd_t = (r2b_write) ? `OP_WR : `OP_RD; - b2r_ack = 1'b1; - b2x_addr = r2b_caddr; - next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_XFR; // in case of hit, stay here till xfr sm acks - end // if (page_hit) - else begin // page_miss - b2x_req = tras_ok & x2b_pre_ok_t; - b2x_cmd_t = `OP_PRE; - b2r_ack = 1'b1; - b2x_addr = r2b_raddr & 13'hBFF; // Dont want to pre all banks! - next_bank_st = (l_sdr_dma_last) ? `BANK_PRE : (x2b_ack) ? `BANK_ACT : `BANK_PRE; // bank was precharged on l_sdr_dma_last - end // else: !if(page_hit) - end - end // case: `BANK_IDLE - - `BANK_PRE : begin - b2x_req = tras_ok & x2b_pre_ok_t; - b2x_cmd_t = `OP_PRE; - b2r_ack = 1'b0; - b2x_addr = l_raddr & 13'hBFF; // Dont want to pre all banks! - bank_prech_page_closed = 1'b0; - next_bank_st = (x2b_ack) ? `BANK_ACT : `BANK_PRE; - end // case: `BANK_PRE - - `BANK_ACT : begin - b2x_req = timer0_tc & x2b_act_ok_t; - b2x_cmd_t = `OP_ACT; - b2r_ack = 1'b0; - b2x_addr = l_raddr; - bank_prech_page_closed = 1'b0; - next_bank_st = (x2b_ack) ? `BANK_XFR : `BANK_ACT; - end // case: `BANK_ACT - - `BANK_XFR : begin - b2x_req = (l_write) ? timer0_tc & x2b_wrok_t & xfr_ok_t : - timer0_tc & x2b_rdok_t & xfr_ok_t; - b2x_cmd_t = (l_write) ? `OP_WR : `OP_RD; - b2r_ack = 1'b0; - b2x_addr = l_caddr; - bank_prech_page_closed = 1'b0; - next_bank_st = (x2b_refresh) ? `BANK_ACT : - (x2b_ack & l_sdr_dma_last) ? `BANK_DMA_LAST_PRE : - (x2b_ack) ? `BANK_IDLE : `BANK_XFR; - end // case: `BANK_XFR - - `BANK_DMA_LAST_PRE : begin - b2x_req = tras_ok & x2b_pre_ok_t; - b2x_cmd_t = `OP_PRE; - b2r_ack = 1'b0; - b2x_addr = l_raddr & 13'hBFF; // Dont want to pre all banks! - bank_prech_page_closed = 1'b1; - next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_DMA_LAST_PRE; - end // case: `BANK_DMA_LAST_PRE - - endcase // case(bank_st) - - end // always @ (bank_st or ...) - - assign b2x_start = (bank_st == `BANK_IDLE) ? r2b_start : l_start; - - assign b2x_last = (bank_st == `BANK_IDLE) ? r2b_last : l_last; - - assign b2x_id = (bank_st == `BANK_IDLE) ? r2b_req_id : l_id; - - assign b2x_len = (bank_st == `BANK_IDLE) ? r2b_len : l_len; - - assign b2x_wrap = (bank_st == `BANK_IDLE) ? r2b_wrap : l_wrap; - -endmodule // sdr_bank_fsm
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v deleted file mode 100755 index de96f95..0000000 --- a/verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v +++ /dev/null
@@ -1,247 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> -// -/********************************************************************* - - SDRAM Controller buswidth converter - - This file is part of the sdram controller project - https://github.com/dineshannayya/yifive_r0.git - http://www.opencores.org/cores/yifive/ - http://www.opencores.org/cores/sdr_ctrl/ - - Description: SDRAM Controller Buswidth converter - - This module does write/read data transalation between - application data to SDRAM bus width - - To Do: - nothing - - Author(s): - - Dinesh Annayya, dinesha@opencores.org - Version : 0.0 - 8th Jan 2012 - Initial structure - 0.2 - 2nd Feb 2012 - Improved the command pipe structure to accept up-to 4 command of different bank. - 0.3 - 6th Feb 2012 - Bug fix on read valid generation - - - - Copyright (C) 2000 Authors and OPENCORES.ORG - - This source file may be used and distributed without - restriction provided that this copyright statement is not - removed from the file and that any derivative work contains - the original copyright notice and the associated disclaimer. - - This source file is free software; you can redistribute it - and/or modify it under the terms of the GNU Lesser General - Public License as published by the Free Software Foundation; - either version 2.1 of the License, or (at your option) any -later version. - - This source is distributed in the hope that it will be - useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - PURPOSE. See the GNU Lesser General Public License for more - details. - - You should have received a copy of the GNU Lesser General - Public License along with this source; if not, download it - from http://www.opencores.org/lgpl.shtml - -*******************************************************************/ - -`include "sdrc_define.v" -module sdrc_bs_convert ( - clk , - reset_n , - sdr_width , - - /* Control Signal from xfr ctrl */ - x2a_rdstart , - x2a_wrstart , - x2a_rdlast , - x2a_wrlast , - x2a_rddt , - x2a_rdok , - a2x_wrdt , - a2x_wren_n , - x2a_wrnext , - - /* Control Signal from/to to application i/f */ - app_wr_data , - app_wr_en_n , - app_wr_next , - app_last_wr , - app_rd_data , - app_rd_valid , - app_last_rd - ); - - -parameter APP_AW = 30; // Application Address Width -parameter APP_DW = 32; // Application Data Width -parameter APP_BW = 4; // Application Byte Width - -parameter SDR_DW = 16; // SDR Data Width -parameter SDR_BW = 2; // SDR Byte Width - -input clk ; -input reset_n ; -input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit - -/* Control Signal from xfr ctrl Read Transaction*/ -input x2a_rdstart ; // read start indication -input x2a_rdlast ; // read last burst access -input [SDR_DW-1:0] x2a_rddt ; -input x2a_rdok ; - -/* Control Signal from xfr ctrl Write Transaction*/ -input x2a_wrstart ; // writ start indication -input x2a_wrlast ; // write last transfer -input x2a_wrnext ; -output [SDR_DW-1:0] a2x_wrdt ; -output [SDR_BW-1:0] a2x_wren_n ; - -// Application Write Transaction -input [APP_DW-1:0] app_wr_data ; -input [APP_BW-1:0] app_wr_en_n ; -output app_wr_next ; -output app_last_wr ; // Indicate last Write Transfer for a given burst size - -// Application Read Transaction -output [APP_DW-1:0] app_rd_data ; -output app_rd_valid ; -output app_last_rd ; // Indicate last Read Transfer for a given burst size - -//---------------------------------------------- -// Local Decleration -// ---------------------------------------- - -reg [APP_DW-1:0] app_rd_data ; -reg app_rd_valid ; -reg [SDR_DW-1:0] a2x_wrdt ; -reg [SDR_BW-1:0] a2x_wren_n ; -reg app_wr_next ; - -reg [23:0] saved_rd_data ; -reg [1:0] rd_xfr_count ; -reg [1:0] wr_xfr_count ; - - -assign app_last_wr = x2a_wrlast; -assign app_last_rd = x2a_rdlast; - -always @(*) begin - if(sdr_width == 2'b00) // 32 Bit SDR Mode - begin - a2x_wrdt = app_wr_data; - a2x_wren_n = app_wr_en_n; - app_wr_next = x2a_wrnext; - app_rd_data = x2a_rddt; - app_rd_valid = x2a_rdok; - end - else if(sdr_width == 2'b01) // 16 Bit SDR Mode - begin - // Changed the address and length to match the 16 bit SDR Mode - app_wr_next = (x2a_wrnext & wr_xfr_count[0]); - app_rd_valid = (x2a_rdok & rd_xfr_count[0]); - if(wr_xfr_count[0] == 1'b1) - begin - a2x_wren_n = app_wr_en_n[3:2]; - a2x_wrdt = app_wr_data[31:16]; - end - else - begin - a2x_wren_n = app_wr_en_n[1:0]; - a2x_wrdt = app_wr_data[15:0]; - end - - app_rd_data = {x2a_rddt,saved_rd_data[15:0]}; - end else // 8 Bit SDR Mode - begin - // Changed the address and length to match the 16 bit SDR Mode - app_wr_next = (x2a_wrnext & (wr_xfr_count[1:0]== 2'b11)); - app_rd_valid = (x2a_rdok & (rd_xfr_count[1:0]== 2'b11)); - if(wr_xfr_count[1:0] == 2'b11) - begin - a2x_wren_n = app_wr_en_n[3]; - a2x_wrdt = app_wr_data[31:24]; - end - else if(wr_xfr_count[1:0] == 2'b10) - begin - a2x_wren_n = app_wr_en_n[2]; - a2x_wrdt = app_wr_data[23:16]; - end - else if(wr_xfr_count[1:0] == 2'b01) - begin - a2x_wren_n = app_wr_en_n[1]; - a2x_wrdt = app_wr_data[15:8]; - end - else begin - a2x_wren_n = app_wr_en_n[0]; - a2x_wrdt = app_wr_data[7:0]; - end - - app_rd_data = {x2a_rddt,saved_rd_data[23:0]}; - end - end - - - -always @(posedge clk) - begin - if(!reset_n) - begin - rd_xfr_count <= 8'b0; - wr_xfr_count <= 8'b0; - saved_rd_data <= 24'h0; - end - else begin - - // During Write Phase - if(x2a_wrlast) begin - wr_xfr_count <= 0; - end - else if(x2a_wrnext) begin - wr_xfr_count <= wr_xfr_count + 1'b1; - end - - // During Read Phase - if(x2a_rdlast) begin - rd_xfr_count <= 0; - end - else if(x2a_rdok) begin - rd_xfr_count <= rd_xfr_count + 1'b1; - end - - // Save Previous Data - if(x2a_rdok) begin - if(sdr_width == 2'b01) // 16 Bit SDR Mode - saved_rd_data[15:0] <= x2a_rddt; - else begin// 8 bit SDR Mode - - if(rd_xfr_count[1:0] == 2'b00) saved_rd_data[7:0] <= x2a_rddt[7:0]; - else if(rd_xfr_count[1:0] == 2'b01) saved_rd_data[15:8] <= x2a_rddt[7:0]; - else if(rd_xfr_count[1:0] == 2'b10) saved_rd_data[23:16] <= x2a_rddt[7:0]; - end - end - end -end - -endmodule // sdr_bs_convert
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v deleted file mode 100755 index 6c06615..0000000 --- a/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v +++ /dev/null
@@ -1,527 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> -// -/********************************************************************* - - SDRAM Controller Core File - - This file is part of the sdram controller project - https://github.com/dineshannayya/yifive_r0.git - http://www.opencores.org/cores/yifive/ - http://www.opencores.org/cores/sdr_ctrl/ - - Description: SDRAM Controller Core Module - 2 types of SDRAMs are supported, 1Mx16 2 bank, or 4Mx16 4 bank. - This block integrate following sub modules - - sdrc_bs_convert - convert the system side 32 bit into equvailent 8/16/32 SDR format - sdrc_req_gen - This module takes requests from the app, chops them to burst booundaries - if wrap=0, decodes the bank and passe the request to bank_ctl - sdrc_xfr_ctl - This module takes requests from sdr_bank_ctl, runs the transfer and - controls data flow to/from the app. At the end of the transfer it issues a - burst terminate if not at the end of a burst and another command to this - bank is not available. - - sdrc_bank_ctl - This module takes requests from sdr_req_gen, checks for page hit/miss and - issues precharge/activate commands and then passes the request to - sdr_xfr_ctl. - - - Assumption: SDRAM Pads should be placed near to this module. else - user should add a FF near the pads - - To Do: - nothing - - Author(s): - - Dinesh Annayya, dinesha@opencores.org - Version : 0.0 - 8th Jan 2012 - Initial version with 16/32 Bit SDRAM Support - : 0.1 - 24th Jan 2012 - 8 Bit SDRAM Support is added - 0.2 - 2nd Feb 2012 - Improved the command pipe structure to accept up-to - 4 command of different bank. - 0.3 - 7th Feb 2012 - Bug fix for parameter defination for request length has changed from 9 to 12 - 0.4 - 26th April 2013 - SDRAM Address Bit is Extended by 12 bit to 13 bit to support higher SDRAM - - - Copyright (C) 2000 Authors and OPENCORES.ORG - - This source file may be used and distributed without - restriction provided that this copyright statement is not - removed from the file and that any derivative work contains - the original copyright notice and the associated disclaimer. - - This source file is free software; you can redistribute it - and/or modify it under the terms of the GNU Lesser General - Public License as published by the Free Software Foundation; - either version 2.1 of the License, or (at your option) any -later version. - - This source is distributed in the hope that it will be - useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - PURPOSE. See the GNU Lesser General Public License for more - details. - - You should have received a copy of the GNU Lesser General - Public License along with this source; if not, download it - from http://www.opencores.org/lgpl.shtml - -*******************************************************************/ - - -`include "sdrc_define.v" -module sdrc_core - ( - clk, - pad_clk, - reset_n, - sdr_width, - cfg_colbits, - debug, - - /* Request from app */ - app_req, // Transfer Request - app_req_addr, // SDRAM Address - app_req_len, // Burst Length (in 16 bit words) - app_req_wrap, // Wrap mode request (xfr_len = 4) - app_req_wr_n, // 0 => Write request, 1 => read req - app_req_ack, // Request has been accepted - cfg_req_depth, //how many req. buffer should hold - - app_wr_data, - app_wr_en_n, - app_last_wr, - - app_rd_data, - app_rd_valid, - app_last_rd, - app_wr_next_req, - sdr_init_done, - app_req_dma_last, - - /* Interface to SDRAMs */ - sdr_cs_n, - sdr_cke, - sdr_ras_n, - sdr_cas_n, - sdr_we_n, - sdr_dqm, - sdr_ba, - sdr_addr, - pad_sdr_din, - sdr_dout, - sdr_den_n, - - /* Parameters */ - cfg_sdr_en, - cfg_sdr_mode_reg, - cfg_sdr_tras_d, - cfg_sdr_trp_d, - cfg_sdr_trcd_d, - cfg_sdr_cas, - cfg_sdr_trcar_d, - cfg_sdr_twr_d, - cfg_sdr_rfsh, - cfg_sdr_rfmax); - -parameter APP_AW = 26; // Application Address Width -parameter APP_DW = 32; // Application Data Width -parameter APP_BW = 4; // Application Byte Width -parameter APP_RW = 9; // Application Request Width - -parameter SDR_DW = 16; // SDR Data Width -parameter SDR_BW = 2; // SDR Byte Width - - -//----------------------------------------------- -// Global Variable -// ---------------------------------------------- -input clk ; // SDRAM Clock -input pad_clk ; // SDRAM Clock from Pad, used for registering Read Data -input reset_n ; // Reset Signal -input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit -input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits -output [21:0] debug ; - -//------------------------------------------------ -// Request from app -//------------------------------------------------ -input app_req ; // Application Request -input [APP_AW-1:0] app_req_addr ; // Address -input app_req_wr_n ; // 0 - Write, 1 - Read -input app_req_wrap ; // Address Wrap -output app_req_ack ; // Application Request Ack - -input [APP_DW-1:0] app_wr_data ; // Write Data -output app_wr_next_req ; // Next Write Data Request -input [APP_BW-1:0] app_wr_en_n ; // Byte wise Write Enable -output app_last_wr ; // Last Write trannsfer of a given Burst -output [APP_DW-1:0] app_rd_data ; // Read Data -output app_rd_valid ; // Read Valid -output app_last_rd ; // Last Read Transfer of a given Burst - -//------------------------------------------------ -// Interface to SDRAMs -//------------------------------------------------ -output sdr_cke ; // SDRAM CKE -output sdr_cs_n ; // SDRAM Chip Select -output sdr_ras_n ; // SDRAM ras -output sdr_cas_n ; // SDRAM cas -output sdr_we_n ; // SDRAM write enable -output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask -output [1:0] sdr_ba ; // SDRAM Bank Enable -output [12:0] sdr_addr ; // SDRAM Address -input [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input -output [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output -output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable - -//------------------------------------------------ -// Configuration Parameter -//------------------------------------------------ -output sdr_init_done ; // Indicate SDRAM Initialisation Done -input [3:0] cfg_sdr_tras_d ; // Active to precharge delay -input [3:0] cfg_sdr_trp_d ; // Precharge to active delay -input [3:0] cfg_sdr_trcd_d ; // Active to R/W delay -input cfg_sdr_en ; // Enable SDRAM controller -input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller -input [APP_RW-1:0] app_req_len ; // Application Burst Request length in 32 bit -input [12:0] cfg_sdr_mode_reg ; -input [2:0] cfg_sdr_cas ; // SDRAM CAS Latency -input [3:0] cfg_sdr_trcar_d ; // Auto-refresh period -input [3:0] cfg_sdr_twr_d ; // Write recovery delay -input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh; -input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax; -input app_req_dma_last; // this signal should close the bank - -/****************************************************************************/ -// Internal Nets - -// SDR_REQ_GEN -wire x2a_rdstart; -wire x2a_wrstart; -wire x2a_rdlast; -wire x2a_wrlast; -wire x2a_rdok; -wire x2a_wrnext; -wire x2b_ack; -wire x2b_refresh; -wire x2b_act_ok; -wire x2b_rdok; -wire x2b_wrok; -wire b2x_idle; -wire b2x_req; -wire b2x_start; -wire b2x_last; -wire b2x_wrap; -wire b2x_tras_ok; -wire b2r_ack; -wire b2r_arb_ok; -wire r2b_req; -wire r2b_start; -wire r2b_last; -wire r2b_wrap; -wire r2b_write; -wire [`SDR_REQ_ID_W-1:0]r2b_req_id; -wire [1:0] r2b_ba; -wire [12:0] r2b_raddr; -wire [12:0] r2b_caddr; -wire [`REQ_BW-1:0] r2b_len; - -// SDR BANK CTL -wire [`SDR_REQ_ID_W-1:0]b2x_id; -wire [1:0] b2x_ba; -wire [12:0] b2x_addr; -wire [`REQ_BW-1:0] b2x_len; -wire [1:0] b2x_cmd; - -// SDR_XFR_CTL -wire [3:0] x2b_pre_ok; -wire [`SDR_REQ_ID_W-1:0]xfr_id; -wire [APP_DW-1:0] app_rd_data; -wire sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n; -wire [SDR_BW-1:0] sdr_dqm; -wire [1:0] sdr_ba; -wire [12:0] sdr_addr; -wire [SDR_DW-1:0] sdr_dout; -wire [SDR_DW-1:0] sdr_dout_int; -wire [SDR_BW-1:0] sdr_den_n; -wire [SDR_BW-1:0] sdr_den_n_int; - -wire [1:0] xfr_bank_sel; - -wire [APP_AW-1:0] app_req_addr; -wire [APP_RW-1:0] app_req_len; - -wire [APP_DW-1:0] app_wr_data; -wire [SDR_DW-1:0] a2x_wrdt ; -wire [APP_BW-1:0] app_wr_en_n; -wire [SDR_BW-1:0] a2x_wren_n; - -wire r2x_idle; - -//wire [31:0] app_rd_data; -wire [SDR_DW-1:0] x2a_rddt; - - -// synopsys translate_off - wire [3:0] sdr_cmd; - assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n}; -// synopsys translate_on - -assign sdr_den_n = sdr_den_n_int ; -assign sdr_dout = sdr_dout_int ; - - -assign debug = {r2x_idle,r2b_req,r2b_start,r2b_last,b2r_ack,b2r_arb_ok,r2b_write, - b2x_idle,b2x_req,b2x_start,b2x_wrap,x2b_ack,b2x_tras_ok,x2b_refresh,x2b_pre_ok,x2b_act_ok, - x2b_rdok,x2b_wrok,x2a_rdstart,x2a_wrstart,x2a_rdlast,x2a_wrlast}; - -// To meet the timing at read path, read data is registered w.r.t pad_sdram_clock and register back to sdram_clk -// assumption, pad_sdram_clk is synhronous and delayed clock of sdram_clk. -// register w.r.t pad sdram clk -reg [SDR_DW-1:0] pad_sdr_din1; -reg [SDR_DW-1:0] pad_sdr_din2; -always@(posedge pad_clk) begin - pad_sdr_din1 <= pad_sdr_din; -end - -always@(posedge clk) begin - pad_sdr_din2 <= pad_sdr_din1; -end - - - /****************************************************************************/ - // Instantiate sdr_req_gen - // This module takes requests from the app, chops them to burst booundaries - // if wrap=0, decodes the bank and passe the request to bank_ctl - -sdrc_req_gen #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW),.APP_AW(APP_AW)) u_req_gen ( - .clk (clk ), - .reset_n (reset_n ), - .cfg_colbits (cfg_colbits ), - .sdr_width (sdr_width ), - - /* Req to xfr_ctl */ - .r2x_idle (r2x_idle ), - - /* Request from app */ - .req (app_req ), - .req_id (4'b0 ), - .req_addr (app_req_addr ), - .req_len (app_req_len ), - .req_wrap (app_req_wrap ), - .req_wr_n (app_req_wr_n ), - .req_ack (app_req_ack ), - - /* Req to bank_ctl */ - .r2b_req (r2b_req ), - .r2b_req_id (r2b_req_id ), - .r2b_start (r2b_start ), - .r2b_last (r2b_last ), - .r2b_wrap (r2b_wrap ), - .r2b_ba (r2b_ba ), - .r2b_raddr (r2b_raddr ), - .r2b_caddr (r2b_caddr ), - .r2b_len (r2b_len ), - .r2b_write (r2b_write ), - .b2r_ack (b2r_ack ), - .b2r_arb_ok (b2r_arb_ok ) - ); - - /****************************************************************************/ - // Instantiate sdr_bank_ctl - // This module takes requests from sdr_req_gen, checks for page hit/miss and - // issues precharge/activate commands and then passes the request to - // sdr_xfr_ctl. - -sdrc_bank_ctl #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_bank_ctl ( - .clk (clk ), - .reset_n (reset_n ), - .a2b_req_depth (cfg_req_depth ), - - /* Req from req_gen */ - .r2b_req (r2b_req ), - .r2b_req_id (r2b_req_id ), - .r2b_start (r2b_start ), - .r2b_last (r2b_last ), - .r2b_wrap (r2b_wrap ), - .r2b_ba (r2b_ba ), - .r2b_raddr (r2b_raddr ), - .r2b_caddr (r2b_caddr ), - .r2b_len (r2b_len ), - .r2b_write (r2b_write ), - .b2r_arb_ok (b2r_arb_ok ), - .b2r_ack (b2r_ack ), - - /* Transfer request to xfr_ctl */ - .b2x_idle (b2x_idle ), - .b2x_req (b2x_req ), - .b2x_start (b2x_start ), - .b2x_last (b2x_last ), - .b2x_wrap (b2x_wrap ), - .b2x_id (b2x_id ), - .b2x_ba (b2x_ba ), - .b2x_addr (b2x_addr ), - .b2x_len (b2x_len ), - .b2x_cmd (b2x_cmd ), - .x2b_ack (x2b_ack ), - - /* Status from xfr_ctl */ - .b2x_tras_ok (b2x_tras_ok ), - .x2b_refresh (x2b_refresh ), - .x2b_pre_ok (x2b_pre_ok ), - .x2b_act_ok (x2b_act_ok ), - .x2b_rdok (x2b_rdok ), - .x2b_wrok (x2b_wrok ), - - /* for generate cuurent xfr address msb */ - .sdr_req_norm_dma_last(app_req_dma_last), - .xfr_bank_sel (xfr_bank_sel ), - - /* SDRAM Timing */ - .tras_delay (cfg_sdr_tras_d ), - .trp_delay (cfg_sdr_trp_d ), - .trcd_delay (cfg_sdr_trcd_d ) - ); - - /****************************************************************************/ - // Instantiate sdr_xfr_ctl - // This module takes requests from sdr_bank_ctl, runs the transfer and - // controls data flow to/from the app. At the end of the transfer it issues a - // burst terminate if not at the end of a burst and another command to this - // bank is not available. - -sdrc_xfr_ctl #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_xfr_ctl ( - .clk (clk ), - .reset_n (reset_n ), - - /* Transfer request from bank_ctl */ - .r2x_idle (r2x_idle ), - .b2x_idle (b2x_idle ), - .b2x_req (b2x_req ), - .b2x_start (b2x_start ), - .b2x_last (b2x_last ), - .b2x_wrap (b2x_wrap ), - .b2x_id (b2x_id ), - .b2x_ba (b2x_ba ), - .b2x_addr (b2x_addr ), - .b2x_len (b2x_len ), - .b2x_cmd (b2x_cmd ), - .x2b_ack (x2b_ack ), - - /* Status to bank_ctl, req_gen */ - .b2x_tras_ok (b2x_tras_ok ), - .x2b_refresh (x2b_refresh ), - .x2b_pre_ok (x2b_pre_ok ), - .x2b_act_ok (x2b_act_ok ), - .x2b_rdok (x2b_rdok ), - .x2b_wrok (x2b_wrok ), - - /* SDRAM I/O */ - .sdr_cs_n (sdr_cs_n ), - .sdr_cke (sdr_cke ), - .sdr_ras_n (sdr_ras_n ), - .sdr_cas_n (sdr_cas_n ), - .sdr_we_n (sdr_we_n ), - .sdr_dqm (sdr_dqm ), - .sdr_ba (sdr_ba ), - .sdr_addr (sdr_addr ), - .sdr_din (pad_sdr_din2 ), - .sdr_dout (sdr_dout_int ), - .sdr_den_n (sdr_den_n_int ), - /* Data Flow to the app */ - .x2a_rdstart (x2a_rdstart ), - .x2a_wrstart (x2a_wrstart ), - .x2a_id (xfr_id ), - .x2a_rdlast (x2a_rdlast ), - .x2a_wrlast (x2a_wrlast ), - .a2x_wrdt (a2x_wrdt ), - .a2x_wren_n (a2x_wren_n ), - .x2a_wrnext (x2a_wrnext ), - .x2a_rddt (x2a_rddt ), - .x2a_rdok (x2a_rdok ), - .sdr_init_done (sdr_init_done ), - - /* SDRAM Parameters */ - .sdram_enable (cfg_sdr_en ), - .sdram_mode_reg (cfg_sdr_mode_reg ), - - /* current xfr bank */ - .xfr_bank_sel (xfr_bank_sel ), - - /* SDRAM Timing */ - .cas_latency (cfg_sdr_cas ), - .trp_delay (cfg_sdr_trp_d ), - .trcar_delay (cfg_sdr_trcar_d ), - .twr_delay (cfg_sdr_twr_d ), - .rfsh_time (cfg_sdr_rfsh ), - .rfsh_rmax (cfg_sdr_rfmax ) - ); - - /****************************************************************************/ - // Instantiate sdr_bs_convert - // This model handle the bus with transaltion from application layer to - // 8/16/32 SDRAM Memory format - // During Write Phase, this block split the data as per SDRAM Width - // During Read Phase, This block does the re-packing based on SDRAM - // Width - //--------------------------------------------------------------------------- -sdrc_bs_convert #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_bs_convert ( - .clk (clk ), - .reset_n (reset_n ), - .sdr_width (sdr_width ), - - /* Control Signal from xfr ctrl */ - // Read Interface Inputs - .x2a_rdstart (x2a_rdstart ), - .x2a_rdlast (x2a_rdlast ), - .x2a_rdok (x2a_rdok ), - // Read Interface outputs - .x2a_rddt (x2a_rddt ), - - // Write Interface, Inputs - .x2a_wrstart (x2a_wrstart ), - .x2a_wrlast (x2a_wrlast ), - .x2a_wrnext (x2a_wrnext ), - - // Write Interface, Outputs - .a2x_wrdt (a2x_wrdt ), - .a2x_wren_n (a2x_wren_n ), - - /* Control Signal from sdrc_bank_ctl */ - - /* Control Signal from/to to application i/f */ - .app_wr_data (app_wr_data ), - .app_wr_en_n (app_wr_en_n ), - .app_wr_next (app_wr_next_req ), - .app_last_wr (app_last_wr ), - .app_rd_data (app_rd_data ), - .app_rd_valid (app_rd_valid ), - .app_last_rd (app_last_rd ) - - ); - -endmodule // sdrc_core
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v deleted file mode 100755 index 8ea0148..0000000 --- a/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v +++ /dev/null
@@ -1,360 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> -// -/********************************************************************* - - SDRAM Controller Request Generation - - This file is part of the sdram controller project - https://github.com/dineshannayya/yifive_r0.git - http://www.opencores.org/cores/yifive/ - http://www.opencores.org/cores/sdr_ctrl/ - - Description: SDRAM Controller Reguest Generation - - Address Generation Based on cfg_colbits - cfg_colbits= 2'b00 - Address[7:0] - Column Address - Address[9:8] - Bank Address - Address[22:10] - Row Address - cfg_colbits= 2'b01 - Address[8:0] - Column Address - Address[10:9] - Bank Address - Address[23:11] - Row Address - cfg_colbits= 2'b10 - Address[9:0] - Column Address - Address[11:10] - Bank Address - Address[24:12] - Row Address - cfg_colbits= 2'b11 - Address[10:0] - Column Address - Address[12:11] - Bank Address - Address[25:13] - Row Address - - The SDRAMs are operated in 4 beat burst mode. - - If Wrap = 0; - If the current burst cross the page boundary, then this block split the request - into two coressponding change in address and request length - - if the current burst cross the page boundar. - This module takes requests from the memory controller, - chops them to page boundaries if wrap=0, - and passes the request to bank_ctl - - Note: With Wrap = 0, each request from Application layer will be splited into two request, - if the current burst cross the page boundary. - - To Do: - nothing - - Author(s): - - Dinesh Annayya, dinesha@opencores.org - Version : 0.0 - 8th Jan 2012 - 0.1 - 5th Feb 2012, column/row/bank address are register to improve the timing issue in FPGA synthesis - 0.2 - 19th Aug 2021, Address Mapping fix - - - - Copyright (C) 2000 Authors and OPENCORES.ORG - - This source file may be used and distributed without - restriction provided that this copyright statement is not - removed from the file and that any derivative work contains - the original copyright notice and the associated disclaimer. - - This source file is free software; you can redistribute it - and/or modify it under the terms of the GNU Lesser General - Public License as published by the Free Software Foundation; - either version 2.1 of the License, or (at your option) any -later version. - - This source is distributed in the hope that it will be - useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - PURPOSE. See the GNU Lesser General Public License for more - details. - - You should have received a copy of the GNU Lesser General - Public License along with this source; if not, download it - from http://www.opencores.org/lgpl.shtml - -*******************************************************************/ - -`include "sdrc_define.v" - -module sdrc_req_gen (clk, - reset_n, - cfg_colbits, - sdr_width, - - /* Request from app */ - req, // Transfer Request - req_id, // ID for this transfer - req_addr, // SDRAM Address - req_len, // Burst Length (in 32 bit words) - req_wrap, // Wrap mode request (xfr_len = 4) - req_wr_n, // 0 => Write request, 1 => read req - req_ack, // Request has been accepted - - /* Req to xfr_ctl */ - r2x_idle, - - /* Req to bank_ctl */ - r2b_req, // request - r2b_req_id, // ID - r2b_start, // First chunk of burst - r2b_last, // Last chunk of burst - r2b_wrap, // Wrap Mode - r2b_ba, // bank address - r2b_raddr, // row address - r2b_caddr, // col address - r2b_len, // length - r2b_write, // write request - b2r_ack, - b2r_arb_ok - ); - -parameter APP_AW = 26; // Application Address Width -parameter APP_DW = 32; // Application Data Width -parameter APP_BW = 4; // Application Byte Width -parameter APP_RW = 9; // Application Request Width - -parameter SDR_DW = 16; // SDR Data Width -parameter SDR_BW = 2; // SDR Byte Width - - -input clk ; -input reset_n ; -input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits - -/* Request from app */ -input req ; // Request -input [`SDR_REQ_ID_W-1:0] req_id ; // Request ID -input [APP_AW-1:0] req_addr ; // Request Address -input [APP_RW-1:0] req_len ; // Request length -input req_wr_n ; // 0 -Write, 1 - Read -input req_wrap ; // 1 - Wrap the Address on page boundary -output req_ack ; // Request Ack - -/* Req to bank_ctl */ -output r2x_idle ; -output r2b_req ; // Request -output r2b_start ; // First Junk of the Burst Access -output r2b_last ; // Last Junk of the Burst Access -output r2b_write ; // 1 - Write, 0 - Read -output r2b_wrap ; // 1 - Wrap the Address at the page boundary. -output [`SDR_REQ_ID_W-1:0] r2b_req_id; -output [1:0] r2b_ba ; // Bank Address -output [12:0] r2b_raddr ; // Row Address -output [12:0] r2b_caddr ; // Column Address -output [`REQ_BW-1:0] r2b_len ; // Burst Length -input b2r_ack ; // Request Ack -input b2r_arb_ok ; // Bank controller fifo is not full and ready to accept the command -// -input [1:0] sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit - - - /****************************************************************************/ - // Internal Nets - - `define REQ_IDLE 2'b00 - `define REQ_ACTIVE 2'b01 - `define REQ_PAGE_WRAP 2'b10 - - reg [1:0] req_st, next_req_st; - reg r2x_idle, req_ack, r2b_req, r2b_start, - r2b_write, req_idle, req_ld, lcl_wrap; - reg [`SDR_REQ_ID_W-1:0] r2b_req_id; - reg [`REQ_BW-1:0] lcl_req_len; - - wire r2b_last, page_ovflw; - reg page_ovflw_r; - wire [`REQ_BW-1:0] r2b_len, next_req_len; - wire [12:0] max_r2b_len; - reg [12:0] max_r2b_len_r; - - reg [1:0] r2b_ba; - reg [12:0] r2b_raddr; - reg [12:0] r2b_caddr; - - reg [APP_AW-1:0] curr_sdr_addr ; - wire [APP_AW-1:0] next_sdr_addr ; - - -//-------------------------------------------------------------------- -// Generate the internal Adress and Burst length Based on sdram width -//-------------------------------------------------------------------- -reg [APP_AW:0] req_addr_int; -reg [APP_RW-1:0] req_len_int; - -always @(*) begin - if(sdr_width == 2'b00) begin // 32 Bit SDR Mode - req_addr_int = {1'b0,req_addr}; - req_len_int = req_len; - end else if(sdr_width == 2'b01) begin // 16 Bit SDR Mode - // Changed the address and length to match the 16 bit SDR Mode - req_addr_int = {1'b0,req_addr}; - req_len_int = {req_len,1'b0}; - end else begin // 8 Bit SDR Mode - // Changed the address and length to match the 16 bit SDR Mode - req_addr_int = {1'b0,req_addr}; - req_len_int = {req_len,2'b0}; - end -end - - // - // Identify the page over flow. - // Find the Maximum Burst length allowed from the selected column - // address, If the requested burst length is more than the allowed Maximum - // burst length, then we need to handle the bank cross over case and we - // need to split the reuest. - // - assign max_r2b_len = (cfg_colbits == 2'b00) ? (12'h100 - {4'b0, req_addr_int[7:0]}) : - (cfg_colbits == 2'b01) ? (12'h200 - {3'b0, req_addr_int[8:0]}) : - (cfg_colbits == 2'b10) ? (12'h400 - {2'b0, req_addr_int[9:0]}) : (12'h800 - {1'b0, req_addr_int[10:0]}); - - - // If the wrap = 0 and current application burst length is crossing the page boundary, - // then request will be split into two with corresponding change in request address and request length. - // - // If the wrap = 0 and current burst length is not crossing the page boundary, - // then request from application layer will be transparently passed on the bank control block. - - // - // if the wrap = 1, then this block will not modify the request address and length. - // The wrapping functionality will be handle by the bank control module and - // column address will rewind back as follows XX -> FF ? 00 ? 1 - // - // Note: With Wrap = 0, each request from Application layer will be spilited into two request, - // if the current burst cross the page boundary. - assign page_ovflw = ({1'b0, req_len_int} > max_r2b_len) ? ~r2b_wrap : 1'b0; - - assign r2b_len = r2b_start ? ((page_ovflw_r) ? max_r2b_len_r : lcl_req_len) : - lcl_req_len; - - assign next_req_len = lcl_req_len - r2b_len; - - assign next_sdr_addr = curr_sdr_addr + r2b_len; - - - assign r2b_wrap = lcl_wrap; - - assign r2b_last = (r2b_start & !page_ovflw_r) | (req_st == `REQ_PAGE_WRAP); -// -// -// - always @ (posedge clk) begin - - page_ovflw_r <= (req_ack) ? page_ovflw: 'h0; - - max_r2b_len_r <= (req_ack) ? max_r2b_len: 'h0; - r2b_start <= (req_ack) ? 1'b1 : - (b2r_ack) ? 1'b0 : r2b_start; - - r2b_write <= (req_ack) ? ~req_wr_n : r2b_write; - - r2b_req_id <= (req_ack) ? req_id : r2b_req_id; - - lcl_wrap <= (req_ack) ? req_wrap : lcl_wrap; - - lcl_req_len <= (req_ack) ? req_len_int : - (req_ld) ? next_req_len : lcl_req_len; - - curr_sdr_addr <= (req_ack) ? req_addr_int : - (req_ld) ? next_sdr_addr : curr_sdr_addr; - - end // always @ (posedge clk) - - always @ (*) begin - r2x_idle = 1'b0; - req_idle = 1'b0; - req_ack = 1'b0; - req_ld = 1'b0; - r2b_req = 1'b0; - next_req_st = `REQ_IDLE; - - case (req_st) - - `REQ_IDLE : begin - r2x_idle = ~req; - req_idle = 1'b1; - req_ack = req & b2r_arb_ok; - req_ld = 1'b0; - r2b_req = 1'b0; - next_req_st = (req & b2r_arb_ok) ? `REQ_ACTIVE : `REQ_IDLE; - end // case: `REQ_IDLE - - `REQ_ACTIVE : begin - r2x_idle = 1'b0; - req_idle = 1'b0; - req_ack = 1'b0; - req_ld = b2r_ack; - r2b_req = 1'b1; // req_gen to bank_req - next_req_st = (b2r_ack ) ? ((page_ovflw_r) ? `REQ_PAGE_WRAP :`REQ_IDLE) : `REQ_ACTIVE; - end // case: `REQ_ACTIVE - `REQ_PAGE_WRAP : begin - r2x_idle = 1'b0; - req_idle = 1'b0; - req_ack = 1'b0; - req_ld = b2r_ack; - r2b_req = 1'b1; // req_gen to bank_req - next_req_st = (b2r_ack) ? `REQ_IDLE : `REQ_PAGE_WRAP; - end // case: `REQ_ACTIVE - - endcase // case(req_st) - - end // always @ (req_st or ....) - - always @ (posedge clk) - if (~reset_n) begin - req_st <= `REQ_IDLE; - end // if (~reset_n) - else begin - req_st <= next_req_st; - end // else: !if(~reset_n) -// -// addrs bits for the bank, row and column -// -// Register row/column/bank to improve fpga timing issue -wire [APP_AW-1:0] map_address ; - -assign map_address = (req_ack) ? req_addr_int : - (req_ld) ? next_sdr_addr : curr_sdr_addr; - -always @ (posedge clk) begin -// Bank Bits are always - 2 Bits - r2b_ba <= (cfg_colbits == 2'b00) ? {map_address[9:8]} : - (cfg_colbits == 2'b01) ? {map_address[10:9]} : - (cfg_colbits == 2'b10) ? {map_address[11:10]} : map_address[12:11]; - -/******************** -* Colbits Mapping: -* 2'b00 - 8 Bit -* 2'b01 - 16 Bit -* 2'b10 - 10 Bit -* 2'b11 - 11 Bits -************************/ - r2b_caddr <= (cfg_colbits == 2'b00) ? {5'b0, map_address[7:0]} : - (cfg_colbits == 2'b01) ? {4'b0, map_address[8:0]} : - (cfg_colbits == 2'b10) ? {3'b0, map_address[9:0]} : {2'b0, map_address[10:0]}; - - r2b_raddr <= (cfg_colbits == 2'b00) ? map_address[22:10] : - (cfg_colbits == 2'b01) ? map_address[23:11] : - (cfg_colbits == 2'b10) ? map_address[24:12] : map_address[25:13]; -end - -endmodule // sdr_req_gen
diff --git a/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v b/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v deleted file mode 100755 index 6ec7ad2..0000000 --- a/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v +++ /dev/null
@@ -1,791 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> -// -/********************************************************************* - - SDRAM Controller Transfer control - - This file is part of the sdram controller project - https://github.com/dineshannayya/yifive_r0.git - http://www.opencores.org/cores/yifive/ - http://www.opencores.org/cores/sdr_ctrl/ - - Description: SDRAM Controller Transfer control - - This module takes requests from sdrc_bank_ctl and runs the - transfer. The input request is guaranteed to be in a bank that is - precharged and activated. This block runs the transfer until a - burst boundary is reached, then issues another read/write command - to sequentially step thru memory if wrap=0, until the transfer is - completed. - - if a read transfer finishes and the caddr is not at a burst boundary - a burst terminate command is issued unless another read/write or - precharge to the same bank is pending. - - if a write transfer finishes and the caddr is not at a burst boundary - a burst terminate command is issued unless a read/write is pending. - - If a refresh request is made, the bank_ctl will be held off until - the number of refreshes requested are completed. - - This block also handles SDRAM initialization. - - - To Do: - nothing - - Author(s): - - Dinesh Annayya, dinesha@opencores.org - Version : 1.0 - 8th Jan 2012 - - - - Copyright (C) 2000 Authors and OPENCORES.ORG - - This source file may be used and distributed without - restriction provided that this copyright statement is not - removed from the file and that any derivative work contains - the original copyright notice and the associated disclaimer. - - This source file is free software; you can redistribute it - and/or modify it under the terms of the GNU Lesser General - Public License as published by the Free Software Foundation; - either version 2.1 of the License, or (at your option) any -later version. - - This source is distributed in the hope that it will be - useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - PURPOSE. See the GNU Lesser General Public License for more - details. - - You should have received a copy of the GNU Lesser General - Public License along with this source; if not, download it - from http://www.opencores.org/lgpl.shtml - -*******************************************************************/ - -`include "sdrc_define.v" - -module sdrc_xfr_ctl (clk, - reset_n, - - /* Transfer request from bank_ctl */ - r2x_idle, // Req is idle - b2x_idle, // All banks are idle - b2x_req, // Req from bank_ctl - b2x_start, // first chunk of transfer - b2x_last, // last chunk of transfer - b2x_id, // Transfer ID - b2x_ba, // bank address - b2x_addr, // row/col address - b2x_len, // transfer length - b2x_cmd, // transfer command - b2x_wrap, // Wrap mode transfer - x2b_ack, // command accepted - - /* Status to bank_ctl, req_gen */ - b2x_tras_ok, // Tras for all banks expired - x2b_refresh, // We did a refresh - x2b_pre_ok, // OK to do a precharge (per bank) - x2b_act_ok, // OK to do an activate - x2b_rdok, // OK to do a read - x2b_wrok, // OK to do a write - - /* SDRAM I/O */ - sdr_cs_n, - sdr_cke, - sdr_ras_n, - sdr_cas_n, - sdr_we_n, - sdr_dqm, - sdr_ba, - sdr_addr, - sdr_din, - sdr_dout, - sdr_den_n, - - /* Data Flow to the app */ - x2a_rdstart, - x2a_wrstart, - x2a_rdlast, - x2a_wrlast, - x2a_id, - a2x_wrdt, - a2x_wren_n, - x2a_wrnext, - x2a_rddt, - x2a_rdok, - sdr_init_done, - - /* SDRAM Parameters */ - sdram_enable, - sdram_mode_reg, - - /* output for generate row address of the transfer */ - xfr_bank_sel, - - /* SDRAM Timing */ - cas_latency, - trp_delay, // Precharge to refresh delay - trcar_delay, // Auto-refresh period - twr_delay, // Write recovery delay - rfsh_time, // time per row (31.25 or 15.6125 uS) - rfsh_rmax); // Number of rows to rfsh at a time (<120uS) - -parameter SDR_DW = 16; // SDR Data Width -parameter SDR_BW = 2; // SDR Byte Width - - -input clk, reset_n; - - /* Req from bank_ctl */ -input b2x_req, b2x_start, b2x_last, b2x_tras_ok, - b2x_wrap, r2x_idle, b2x_idle; -input [`SDR_REQ_ID_W-1:0] b2x_id; -input [1:0] b2x_ba; -input [12:0] b2x_addr; -input [`REQ_BW-1:0] b2x_len; -input [1:0] b2x_cmd; -output x2b_ack; - -/* Status to bank_ctl */ -output [3:0] x2b_pre_ok; -output x2b_refresh, x2b_act_ok, x2b_rdok, - x2b_wrok; -/* Data Flow to the app */ -output x2a_rdstart, x2a_wrstart, x2a_rdlast, x2a_wrlast; -output [`SDR_REQ_ID_W-1:0] x2a_id; - -input [SDR_DW-1:0] a2x_wrdt; -input [SDR_BW-1:0] a2x_wren_n; -output [SDR_DW-1:0] x2a_rddt; -output x2a_wrnext, x2a_rdok, sdr_init_done; - -/* Interface to SDRAMs */ -output sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, - sdr_we_n; -output [SDR_BW-1:0] sdr_dqm; -output [1:0] sdr_ba; -output [12:0] sdr_addr; -input [SDR_DW-1:0] sdr_din; -output [SDR_DW-1:0] sdr_dout; -output [SDR_BW-1:0] sdr_den_n; - - output [1:0] xfr_bank_sel; - - input sdram_enable; - input [12:0] sdram_mode_reg; - input [2:0] cas_latency; - input [3:0] trp_delay, trcar_delay, twr_delay; - input [`SDR_RFSH_TIMER_W-1 : 0] rfsh_time; - input [`SDR_RFSH_ROW_CNT_W-1:0] rfsh_rmax; - - - /************************************************************************/ - // Internal Nets - - `define XFR_IDLE 2'b00 - `define XFR_WRITE 2'b01 - `define XFR_READ 2'b10 - `define XFR_RDWT 2'b11 - - reg [1:0] xfr_st, next_xfr_st; - reg [12:0] xfr_caddr; - wire last_burst; - wire x2a_rdstart, x2a_wrstart, x2a_rdlast, x2a_wrlast; - reg l_start, l_last, l_wrap; - wire [`SDR_REQ_ID_W-1:0] x2a_id; - reg [`SDR_REQ_ID_W-1:0] l_id; - wire [1:0] xfr_ba; - reg [1:0] l_ba; - wire [12:0] xfr_addr; - wire [`REQ_BW-1:0] xfr_len, next_xfr_len; - reg [`REQ_BW-1:0] l_len; - - reg mgmt_idle, mgmt_req; - reg [3:0] mgmt_cmd; - reg [12:0] mgmt_addr; - reg [1:0] mgmt_ba; - - reg sel_mgmt, sel_b2x; - reg cb_pre_ok, rdok, wrok, wr_next, - rd_next, sdr_init_done, act_cmd, d_act_cmd; - wire [3:0] b2x_sdr_cmd, xfr_cmd; - reg [3:0] i_xfr_cmd; - wire mgmt_ack, x2b_ack, b2x_read, b2x_write, - b2x_prechg, d_rd_next, dt_next, xfr_end, - rd_pipe_mt, ld_xfr, rd_last, d_rd_last, - wr_last, l_xfr_end, rd_start, d_rd_start, - wr_start, page_hit, burst_bdry, xfr_wrap, - b2x_prechg_hit; - reg [6:0] l_rd_next, l_rd_start, l_rd_last; - - assign b2x_read = (b2x_cmd == `OP_RD) ? 1'b1 : 1'b0; - - assign b2x_write = (b2x_cmd == `OP_WR) ? 1'b1 : 1'b0; - - assign b2x_prechg = (b2x_cmd == `OP_PRE) ? 1'b1 : 1'b0; - - assign b2x_sdr_cmd = (b2x_cmd == `OP_PRE) ? `SDR_PRECHARGE : - (b2x_cmd == `OP_ACT) ? `SDR_ACTIVATE : - (b2x_cmd == `OP_RD) ? `SDR_READ : - (b2x_cmd == `OP_WR) ? `SDR_WRITE : `SDR_DESEL; - - assign page_hit = (b2x_ba == l_ba) ? 1'b1 : 1'b0; - - assign b2x_prechg_hit = b2x_prechg & page_hit; - - assign xfr_cmd = (sel_mgmt) ? mgmt_cmd : - (sel_b2x) ? b2x_sdr_cmd : i_xfr_cmd; - - assign xfr_addr = (sel_mgmt) ? mgmt_addr : - (sel_b2x) ? b2x_addr : xfr_caddr+1; - - assign mgmt_ack = sel_mgmt; - - assign x2b_ack = sel_b2x; - - assign ld_xfr = sel_b2x & (b2x_read | b2x_write); - - assign xfr_len = (ld_xfr) ? b2x_len : l_len; - - //assign next_xfr_len = (l_xfr_end && !ld_xfr) ? l_len : xfr_len - 1; - assign next_xfr_len = (ld_xfr) ? b2x_len : - (l_xfr_end) ? l_len: l_len - 1; - - assign d_rd_next = (cas_latency == 3'b001) ? l_rd_next[2] : - (cas_latency == 3'b010) ? l_rd_next[3] : - (cas_latency == 3'b011) ? l_rd_next[4] : - (cas_latency == 3'b100) ? l_rd_next[5] : - l_rd_next[6]; - - assign d_rd_last = (cas_latency == 3'b001) ? l_rd_last[2] : - (cas_latency == 3'b010) ? l_rd_last[3] : - (cas_latency == 3'b011) ? l_rd_last[4] : - (cas_latency == 3'b100) ? l_rd_last[5] : - l_rd_last[6]; - - assign d_rd_start = (cas_latency == 3'b001) ? l_rd_start[2] : - (cas_latency == 3'b010) ? l_rd_start[3] : - (cas_latency == 3'b011) ? l_rd_start[4] : - (cas_latency == 3'b100) ? l_rd_start[5] : - l_rd_start[6]; - - assign rd_pipe_mt = (cas_latency == 3'b001) ? ~|l_rd_next[1:0] : - (cas_latency == 3'b010) ? ~|l_rd_next[2:0] : - (cas_latency == 3'b011) ? ~|l_rd_next[3:0] : - (cas_latency == 3'b100) ? ~|l_rd_next[4:0] : - ~|l_rd_next[5:0]; - - assign dt_next = wr_next | d_rd_next; - - assign xfr_end = ~|xfr_len; - - assign l_xfr_end = ~|(l_len-1); - - assign rd_start = ld_xfr & b2x_read & b2x_start; - - assign wr_start = ld_xfr & b2x_write & b2x_start; - - assign rd_last = rd_next & last_burst & ~|xfr_len[`REQ_BW-1:1]; - - //assign wr_last = wr_next & last_burst & ~|xfr_len[APP_RW-1:1]; - - assign wr_last = last_burst & ~|xfr_len[`REQ_BW-1:1]; - - //assign xfr_ba = (ld_xfr) ? b2x_ba : l_ba; - assign xfr_ba = (sel_mgmt) ? mgmt_ba : - (sel_b2x) ? b2x_ba : l_ba; - - assign xfr_wrap = (ld_xfr) ? b2x_wrap : l_wrap; - -// assign burst_bdry = ~|xfr_caddr[2:0]; - wire [1:0] xfr_caddr_lsb = (xfr_caddr[1:0]+1); - assign burst_bdry = ~|(xfr_caddr_lsb[1:0]); - - always @ (posedge clk) begin - if (~reset_n) begin - xfr_caddr <= 13'b0; - l_start <= 1'b0; - l_last <= 1'b0; - l_wrap <= 1'b0; - l_id <= 0; - l_ba <= 0; - l_len <= 0; - l_rd_next <= 7'b0; - l_rd_start <= 7'b0; - l_rd_last <= 7'b0; - act_cmd <= 1'b0; - d_act_cmd <= 1'b0; - xfr_st <= `XFR_IDLE; - end // if (~reset_n) - - else begin - xfr_caddr <= (ld_xfr) ? b2x_addr : - (rd_next | wr_next) ? xfr_caddr + 1 : xfr_caddr; - l_start <= (dt_next) ? 1'b0 : - (ld_xfr) ? b2x_start : l_start; - l_last <= (ld_xfr) ? b2x_last : l_last; - l_wrap <= (ld_xfr) ? b2x_wrap : l_wrap; - l_id <= (ld_xfr) ? b2x_id : l_id; - l_ba <= (ld_xfr) ? b2x_ba : l_ba; - l_len <= next_xfr_len; - l_rd_next <= {l_rd_next[5:0], rd_next}; - l_rd_start <= {l_rd_start[5:0], rd_start}; - l_rd_last <= {l_rd_last[5:0], rd_last}; - act_cmd <= (xfr_cmd == `SDR_ACTIVATE) ? 1'b1 : 1'b0; - d_act_cmd <= act_cmd; - xfr_st <= next_xfr_st; - end // else: !if(~reset_n) - - end // always @ (posedge clk) - - - always @ (*) begin - case (xfr_st) - - `XFR_IDLE : begin - - sel_mgmt = mgmt_req; - sel_b2x = ~mgmt_req & sdr_init_done & b2x_req; - i_xfr_cmd = `SDR_DESEL; - rd_next = ~mgmt_req & sdr_init_done & b2x_req & b2x_read; - wr_next = ~mgmt_req & sdr_init_done & b2x_req & b2x_write; - rdok = ~mgmt_req; - cb_pre_ok = 1'b1; - wrok = ~mgmt_req; - next_xfr_st = (mgmt_req | ~sdr_init_done) ? `XFR_IDLE : - (~b2x_req) ? `XFR_IDLE : - (b2x_read) ? `XFR_READ : - (b2x_write) ? `XFR_WRITE : `XFR_IDLE; - - end // case: `XFR_IDLE - - `XFR_READ : begin - rd_next = ~l_xfr_end | - l_xfr_end & ~mgmt_req & b2x_req & b2x_read; - wr_next = 1'b0; - rdok = l_xfr_end & ~mgmt_req; - // Break the timing path for FPGA Based Design - cb_pre_ok = (`TARGET_DESIGN == `FPGA) ? 1'b0 : l_xfr_end; - wrok = 1'b0; - sel_mgmt = 1'b0; - - if (l_xfr_end) begin // end of transfer - - if (~l_wrap) begin - // Current transfer was not wrap mode, may need BT - // If next cmd is a R or W or PRE to same bank allow - // it else issue BT - // This is a little pessimistic since BT is issued - // for non-wrap mode transfers even if the transfer - // ends on a burst boundary, but is felt to be of - // minimal performance impact. - - i_xfr_cmd = `SDR_BT; - sel_b2x = b2x_req & ~mgmt_req & (b2x_read | b2x_prechg_hit); - - end // if (~l_wrap) - - else begin - // Wrap mode transfer, by definition is end of burst - // boundary - - i_xfr_cmd = `SDR_DESEL; - sel_b2x = b2x_req & ~mgmt_req & ~b2x_write; - - end // else: !if(~l_wrap) - - next_xfr_st = (sdr_init_done) ? ((b2x_req & ~mgmt_req & b2x_read) ? `XFR_READ : `XFR_RDWT) : `XFR_IDLE; - - end // if (l_xfr_end) - - else begin - // Not end of transfer - // If current transfer was not wrap mode and we are at - // the start of a burst boundary issue another R cmd to - // step sequemtially thru memory, ELSE, - // issue precharge/activate commands from the bank control - - i_xfr_cmd = (burst_bdry & ~l_wrap) ? `SDR_READ : `SDR_DESEL; - sel_b2x = ~(burst_bdry & ~l_wrap) & b2x_req; - next_xfr_st = `XFR_READ; - - end // else: !if(l_xfr_end) - - end // case: `XFR_READ - - `XFR_RDWT : begin - rd_next = ~mgmt_req & b2x_req & b2x_read; - wr_next = rd_pipe_mt & ~mgmt_req & b2x_req & b2x_write; - rdok = ~mgmt_req; - cb_pre_ok = 1'b1; - wrok = rd_pipe_mt & ~mgmt_req; - - sel_mgmt = mgmt_req; - - sel_b2x = ~mgmt_req & b2x_req; - - i_xfr_cmd = `SDR_DESEL; - - next_xfr_st = (~mgmt_req & b2x_req & b2x_read) ? `XFR_READ : - (~rd_pipe_mt) ? `XFR_RDWT : - (~mgmt_req & b2x_req & b2x_write) ? `XFR_WRITE : - `XFR_IDLE; - - end // case: `XFR_RDWT - - `XFR_WRITE : begin - rd_next = l_xfr_end & ~mgmt_req & b2x_req & b2x_read; - wr_next = ~l_xfr_end | - l_xfr_end & ~mgmt_req & b2x_req & b2x_write; - rdok = l_xfr_end & ~mgmt_req; - cb_pre_ok = 1'b0; - wrok = l_xfr_end & ~mgmt_req; - sel_mgmt = 1'b0; - - if (l_xfr_end) begin // End of transfer - - if (~l_wrap) begin - // Current transfer was not wrap mode, may need BT - // If next cmd is a R or W allow it else issue BT - // This is a little pessimistic since BT is issued - // for non-wrap mode transfers even if the transfer - // ends on a burst boundary, but is felt to be of - // minimal performance impact. - - - sel_b2x = b2x_req & ~mgmt_req & (b2x_read | b2x_write); - i_xfr_cmd = `SDR_BT; - end // if (~l_wrap) - - else begin - // Wrap mode transfer, by definition is end of burst - // boundary - - sel_b2x = b2x_req & ~mgmt_req & ~b2x_prechg_hit; - i_xfr_cmd = `SDR_DESEL; - end // else: !if(~l_wrap) - - next_xfr_st = (~mgmt_req & b2x_req & b2x_read) ? `XFR_READ : - (~mgmt_req & b2x_req & b2x_write) ? `XFR_WRITE : - `XFR_IDLE; - - end // if (l_xfr_end) - - else begin - // Not end of transfer - // If current transfer was not wrap mode and we are at - // the start of a burst boundary issue another R cmd to - // step sequemtially thru memory, ELSE, - // issue precharge/activate commands from the bank control - - if (burst_bdry & ~l_wrap) begin - sel_b2x = 1'b0; - i_xfr_cmd = `SDR_WRITE; - end // if (burst_bdry & ~l_wrap) - - else begin - sel_b2x = b2x_req & ~mgmt_req; - i_xfr_cmd = `SDR_DESEL; - end // else: !if(burst_bdry & ~l_wrap) - - next_xfr_st = `XFR_WRITE; - end // else: !if(l_xfr_end) - - end // case: `XFR_WRITE - - endcase // case(xfr_st) - - end // always @ (xfr_st or ...) - - // signals to bank_ctl (x2b_refresh, x2b_act_ok, x2b_rdok, x2b_wrok, - // x2b_pre_ok[3:0] - - assign x2b_refresh = (xfr_cmd == `SDR_REFRESH) ? 1'b1 : 1'b0; - - assign x2b_act_ok = ~act_cmd & ~d_act_cmd; - - assign x2b_rdok = rdok; - - assign x2b_wrok = wrok; - - //assign x2b_pre_ok[0] = (l_ba == 2'b00) ? cb_pre_ok : 1'b1; - //assign x2b_pre_ok[1] = (l_ba == 2'b01) ? cb_pre_ok : 1'b1; - //assign x2b_pre_ok[2] = (l_ba == 2'b10) ? cb_pre_ok : 1'b1; - //assign x2b_pre_ok[3] = (l_ba == 2'b11) ? cb_pre_ok : 1'b1; - - assign x2b_pre_ok[0] = cb_pre_ok; - assign x2b_pre_ok[1] = cb_pre_ok; - assign x2b_pre_ok[2] = cb_pre_ok; - assign x2b_pre_ok[3] = cb_pre_ok; - assign last_burst = (ld_xfr) ? b2x_last : l_last; - - /************************************************************************/ - // APP Data I/F - - wire [SDR_DW-1:0] x2a_rddt; - - //assign x2a_start = (ld_xfr) ? b2x_start : l_start; - assign x2a_rdstart = d_rd_start; - assign x2a_wrstart = wr_start; - - assign x2a_rdlast = d_rd_last; - assign x2a_wrlast = wr_last; - - assign x2a_id = (ld_xfr) ? b2x_id : l_id; - - assign x2a_rddt = sdr_din; - - assign x2a_wrnext = wr_next; - - assign x2a_rdok = d_rd_next; - - /************************************************************************/ - // SDRAM I/F - - reg sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, - sdr_we_n; - reg [SDR_BW-1:0] sdr_dqm; - reg [1:0] sdr_ba; - reg [12:0] sdr_addr; - reg [SDR_DW-1:0] sdr_dout; - reg [SDR_BW-1:0] sdr_den_n; - - always @ (posedge clk) - if (~reset_n) begin - sdr_cs_n <= 1'b1; - sdr_cke <= 1'b1; - sdr_ras_n <= 1'b1; - sdr_cas_n <= 1'b1; - sdr_we_n <= 1'b1; - sdr_dqm <= {SDR_BW{1'b1}}; - sdr_den_n <= {SDR_BW{1'b1}}; - end // if (~reset_n) - else begin - sdr_cs_n <= xfr_cmd[3]; - sdr_ras_n <= xfr_cmd[2]; - sdr_cas_n <= xfr_cmd[1]; - sdr_we_n <= xfr_cmd[0]; - sdr_cke <= (xfr_st != `XFR_IDLE) ? 1'b1 : - ~(mgmt_idle & b2x_idle & r2x_idle); - sdr_dqm <= (wr_next) ? a2x_wren_n : {SDR_BW{1'b0}}; - sdr_den_n <= (wr_next) ? {SDR_BW{1'b0}} : {SDR_BW{1'b1}}; - end // else: !if(~reset_n) - - always @ (posedge clk) begin - - if (~xfr_cmd[3]) begin - sdr_addr <= xfr_addr; - sdr_ba <= xfr_ba; - end // if (~xfr_cmd[3]) - - sdr_dout <= (wr_next) ? a2x_wrdt : sdr_dout; - - end // always @ (posedge clk) - - /************************************************************************/ - // Refresh and Initialization - - `define MGM_POWERUP 3'b000 - `define MGM_PRECHARGE 3'b001 - `define MGM_PCHWT 3'b010 - `define MGM_REFRESH 3'b011 - `define MGM_REFWT 3'b100 - `define MGM_MODE_REG 3'b101 - `define MGM_MODE_WT 3'b110 - `define MGM_ACTIVE 3'b111 - - reg [2:0] mgmt_st, next_mgmt_st; - reg [3:0] tmr0, tmr0_d; - reg [3:0] cntr1, cntr1_d; - wire tmr0_tc, cntr1_tc, rfsh_timer_tc, ref_req, precharge_ok; - reg ld_tmr0, ld_cntr1, dec_cntr1, set_sdr_init_done; - reg [`SDR_RFSH_TIMER_W-1 : 0] rfsh_timer; - reg [`SDR_RFSH_ROW_CNT_W-1:0] rfsh_row_cnt; - - always @ (posedge clk) - if (~reset_n) begin - mgmt_st <= `MGM_POWERUP; - tmr0 <= 4'b0; - cntr1 <= 4'h7; - rfsh_timer <= 0; - rfsh_row_cnt <= 0; - sdr_init_done <= 1'b0; - end // if (~reset_n) - else begin - mgmt_st <= next_mgmt_st; - tmr0 <= (ld_tmr0) ? tmr0_d : - (~tmr0_tc) ? tmr0 - 1 : tmr0; - cntr1 <= (ld_cntr1) ? cntr1_d : - (dec_cntr1) ? cntr1 - 1 : cntr1; - sdr_init_done <= (set_sdr_init_done | sdr_init_done) & sdram_enable; - rfsh_timer <= (rfsh_timer_tc) ? 0 : rfsh_timer + 1; - rfsh_row_cnt <= (~set_sdr_init_done) ? 0 : - (rfsh_timer_tc) ? rfsh_row_cnt + 1 : rfsh_row_cnt; - end // else: !if(~reset_n) - - assign tmr0_tc = ~|tmr0; - - assign cntr1_tc = ~|cntr1; - - assign rfsh_timer_tc = (rfsh_timer == rfsh_time) ? 1'b1 : 1'b0; - - assign ref_req = (rfsh_row_cnt >= rfsh_rmax) ? 1'b1 : 1'b0; - - assign precharge_ok = cb_pre_ok & b2x_tras_ok; - - assign xfr_bank_sel = l_ba; - - always @ (mgmt_st or sdram_enable or mgmt_ack or trp_delay or tmr0_tc or - cntr1_tc or trcar_delay or rfsh_row_cnt or ref_req or sdr_init_done - or precharge_ok or sdram_mode_reg) begin - - case (mgmt_st) - - `MGM_POWERUP : begin - mgmt_idle = 1'b0; - mgmt_req = 1'b0; - mgmt_cmd = `SDR_DESEL; - mgmt_ba = 2'b0; - mgmt_addr = 13'h400; // A10 = 1 => all banks - ld_tmr0 = 1'b0; - tmr0_d = 4'b0; - dec_cntr1 = 1'b0; - ld_cntr1 = 1'b1; - cntr1_d = 4'hf; // changed for sdrams with higher refresh cycles during initialization - set_sdr_init_done = 1'b0; - next_mgmt_st = (sdram_enable) ? `MGM_PRECHARGE : `MGM_POWERUP; - end // case: `MGM_POWERUP - - `MGM_PRECHARGE : begin // Precharge all banks - mgmt_idle = 1'b0; - mgmt_req = 1'b1; - mgmt_cmd = (precharge_ok) ? `SDR_PRECHARGE : `SDR_DESEL; - mgmt_ba = 2'b0; - mgmt_addr = 13'h400; // A10 = 1 => all banks - ld_tmr0 = mgmt_ack; - tmr0_d = trp_delay; - ld_cntr1 = 1'b0; - cntr1_d = 4'h7; - dec_cntr1 = 1'b0; - set_sdr_init_done = 1'b0; - next_mgmt_st = (precharge_ok & mgmt_ack) ? `MGM_PCHWT : `MGM_PRECHARGE; - end // case: `MGM_PRECHARGE - - `MGM_PCHWT : begin // Wait for Trp - mgmt_idle = 1'b0; - mgmt_req = 1'b1; - mgmt_cmd = `SDR_DESEL; - mgmt_ba = 2'b0; - mgmt_addr = 13'h400; // A10 = 1 => all banks - ld_tmr0 = 1'b0; - tmr0_d = trp_delay; - ld_cntr1 = 1'b0; - cntr1_d = 4'b0; - dec_cntr1 = 1'b0; - set_sdr_init_done = 1'b0; - next_mgmt_st = (tmr0_tc) ? `MGM_REFRESH : `MGM_PCHWT; - end // case: `MGM_PRECHARGE - - `MGM_REFRESH : begin // Refresh - mgmt_idle = 1'b0; - mgmt_req = 1'b1; - mgmt_cmd = `SDR_REFRESH; - mgmt_ba = 2'b0; - mgmt_addr = 13'h400; // A10 = 1 => all banks - ld_tmr0 = mgmt_ack; - tmr0_d = trcar_delay; - dec_cntr1 = mgmt_ack; - ld_cntr1 = 1'b0; - cntr1_d = 4'h7; - set_sdr_init_done = 1'b0; - next_mgmt_st = (mgmt_ack) ? `MGM_REFWT : `MGM_REFRESH; - end // case: `MGM_REFRESH - - `MGM_REFWT : begin // Wait for trcar - mgmt_idle = 1'b0; - mgmt_req = 1'b1; - mgmt_cmd = `SDR_DESEL; - mgmt_ba = 2'b0; - mgmt_addr = 13'h400; // A10 = 1 => all banks - ld_tmr0 = 1'b0; - tmr0_d = trcar_delay; - dec_cntr1 = 1'b0; - ld_cntr1 = 1'b0; - cntr1_d = 4'h7; - set_sdr_init_done = 1'b0; - next_mgmt_st = (~tmr0_tc) ? `MGM_REFWT : - (~cntr1_tc) ? `MGM_REFRESH : - (sdr_init_done) ? `MGM_ACTIVE : `MGM_MODE_REG; - end // case: `MGM_REFWT - - `MGM_MODE_REG : begin // Program mode Register & wait for - mgmt_idle = 1'b0; - mgmt_req = 1'b1; - mgmt_cmd = `SDR_MODE; - mgmt_ba = {1'b0, sdram_mode_reg[11]}; - mgmt_addr = sdram_mode_reg; - ld_tmr0 = mgmt_ack; - tmr0_d = 4'h7; - dec_cntr1 = 1'b0; - ld_cntr1 = 1'b0; - cntr1_d = 4'h7; - set_sdr_init_done = 1'b0; - next_mgmt_st = (mgmt_ack) ? `MGM_MODE_WT : `MGM_MODE_REG; - end // case: `MGM_MODE_REG - - `MGM_MODE_WT : begin // Wait for tMRD - mgmt_idle = 1'b0; - mgmt_req = 1'b1; - mgmt_cmd = `SDR_DESEL; - mgmt_ba = 2'bx; - mgmt_addr = 13'bx; - ld_tmr0 = 1'b0; - tmr0_d = 4'h7; - dec_cntr1 = 1'b0; - ld_cntr1 = 1'b0; - cntr1_d = 4'h7; - set_sdr_init_done = 1'b0; - next_mgmt_st = (~tmr0_tc) ? `MGM_MODE_WT : `MGM_ACTIVE; - end // case: `MGM_MODE_WT - - `MGM_ACTIVE : begin // Wait for ref_req - mgmt_idle = ~ref_req; - mgmt_req = 1'b0; - mgmt_cmd = `SDR_DESEL; - mgmt_ba = 2'bx; - mgmt_addr = 13'bx; - ld_tmr0 = 1'b0; - tmr0_d = 4'h7; - dec_cntr1 = 1'b0; - ld_cntr1 = ref_req; - cntr1_d = rfsh_row_cnt; - set_sdr_init_done = 1'b1; - next_mgmt_st = (~sdram_enable) ? `MGM_POWERUP : - (ref_req) ? `MGM_PRECHARGE : `MGM_ACTIVE; - end // case: `MGM_MODE_WT - - endcase // case(mgmt_st) - - end // always @ (mgmt_st or ....) - - - -endmodule // sdr_xfr_ctl
diff --git a/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v b/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v deleted file mode 100755 index 018c683..0000000 --- a/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v +++ /dev/null
@@ -1,50 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> -/////////////////////////////////////////////////////////////////////////// - -`define SDR_REQ_ID_W 4 - -`define SDR_RFSH_TIMER_W 12 -`define SDR_RFSH_ROW_CNT_W 3 - -// B2X Command - -`define OP_PRE 2'b00 -`define OP_ACT 2'b01 -`define OP_RD 2'b10 -`define OP_WR 2'b11 - -// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N) - -`define SDR_DESEL 4'b1111 -`define SDR_NOOP 4'b0111 -`define SDR_ACTIVATE 4'b0011 -`define SDR_READ 4'b0101 -`define SDR_WRITE 4'b0100 -`define SDR_BT 4'b0110 -`define SDR_PRECHARGE 4'b0010 -`define SDR_REFRESH 4'b0001 -`define SDR_MODE 4'b0000 - -`define ASIC 1'b1 -`define FPGA 1'b0 -// Don't Enable FPGA mode, there is functional bug in handling Active to -// Precharge timing -`define TARGET_DESIGN `ASIC -// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits -`define REQ_BW (`TARGET_DESIGN == `FPGA) ? 6 : 12 // Request Width -
diff --git a/verilog/rtl/sdram_ctrl/src/filelist_rtl.f b/verilog/rtl/sdram_ctrl/src/filelist_rtl.f deleted file mode 100755 index 9e0b35c..0000000 --- a/verilog/rtl/sdram_ctrl/src/filelist_rtl.f +++ /dev/null
@@ -1,26 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021, Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> -// ////////////////////////////////////////////////////////////////////////// -./top/sdrc_top.v -./wb2sdrc/wb2sdrc.v -../../lib/async_fifo.sv -./core/sdrc_core.v -./core/sdrc_bank_ctl.v -./core/sdrc_bank_fsm.v -./core/sdrc_bs_convert.v -./core/sdrc_req_gen.v -./core/sdrc_xfr_ctl.v
diff --git a/verilog/rtl/sdram_ctrl/src/run_modelsim b/verilog/rtl/sdram_ctrl/src/run_modelsim deleted file mode 100755 index 3a05c98..0000000 --- a/verilog/rtl/sdram_ctrl/src/run_modelsim +++ /dev/null
@@ -1,20 +0,0 @@ -# ////////////////////////////////////////////////////////////////////////////// -# // SPDX-FileCopyrightText: 2021, Dinesh Annayya -# // -# // Licensed under the Apache License, Version 2.0 (the "License"); -# // you may not use this file except in compliance with the License. -# // You may obtain a copy of the License at -# // -# // http://www.apache.org/licenses/LICENSE-2.0 -# // -# // Unless required by applicable law or agreed to in writing, software -# // distributed under the License is distributed on an "AS IS" BASIS, -# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# // See the License for the specific language governing permissions and -# // limitations under the License. -# // SPDX-License-Identifier: Apache-2.0 -# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> -# // ////////////////////////////////////////////////////////////////////////// - -vlib work -vlog -f filelist_rtl.f +incdir+./defs
diff --git a/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v b/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v deleted file mode 100755 index cff5e76..0000000 --- a/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v +++ /dev/null
@@ -1,404 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> -// -/********************************************************************* - - SDRAM Controller top File - - This file is part of the sdram controller project - https://github.com/dineshannayya/yifive_r0.git - http://www.opencores.org/cores/yifive/ - http://www.opencores.org/cores/sdr_ctrl/ - - Description: SDRAM Controller Top Module. - Support 81/6/32 Bit SDRAM. - Column Address is Programmable - Bank Bit are 2 Bit - Row Bits are 12 Bits - - This block integrate following sub modules - - sdrc_core - SDRAM Controller file - wb2sdrc - This module transalate the bus protocl from wishbone to custome - sdram controller - - To Do: - nothing - - Author(s): Dinesh Annayya, dinesha@opencores.org - Version : 0.0 - 8th Jan 2012 - Initial version with 16/32 Bit SDRAM Support - : 0.1 - 24th Jan 2012 - 8 Bit SDRAM Support is added - 0.2 - 31st Jan 2012 - sdram_dq and sdram_pad_clk are internally generated - 0.3 - 26th April 2013 - Sdram Address witdh is increased from 12 to 13bits - 0.3 - 25th June 2021 - Move the Pad logic inside the sdram to avoid combo logic - at digital core level - 0.4 - 27th June 2021 - Unused port wb_cti_i removed - 0.5 - 29th June 2021 - Wishbone Stagging FF added to break timing path - 0.6 - 6th July 2021, Dinesh A - 32 bit debug port added - 0.7 - 27th Aug 2021, Dinesh A - Disabling the `TARGET_DESIGN with FPGA define , Breaking timing path creating functional issue - Recommnended to use onlt in ASIC Mode. In FPGA mode, tRAS violation are noticed and design - has corner case between Active to Pre-charge - ERROR: tRAS violation during Precharge all bank - - Copyright (C) 2000 Authors and OPENCORES.ORG - - This source file may be used and distributed without - restriction provided that this copyright statement is not - removed from the file and that any derivative work contains - the original copyright notice and the associated disclaimer. - - This source file is free software; you can redistribute it - and/or modify it under the terms of the GNU Lesser General - Public License as published by the Free Software Foundation; - either version 2.1 of the License, or (at your option) any -later version. - - This source is distributed in the hope that it will be - useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - PURPOSE. See the GNU Lesser General Public License for more - details. - - You should have received a copy of the GNU Lesser General - Public License along with this source; if not, download it - from http://www.opencores.org/lgpl.shtml - -*******************************************************************/ - - -`include "sdrc_define.v" -module sdrc_top - ( - cfg_sdr_width , - cfg_colbits , - - sdram_debug , - - // WB bus - wb_rst_n , - wb_clk_i , - - wb_stb_i , - wb_ack_o , - wb_addr_i , - wb_we_i , - wb_dat_i , - wb_sel_i , - wb_dat_o , - wb_cyc_i , - - - /* Interface to SDRAMs */ - sdram_clk , - sdram_resetn , - - - /** Pad Interface **/ - io_in , - io_oeb , - io_out , - - /* Parameters */ - sdr_init_done , - cfg_req_depth , //how many req. buffer should hold - cfg_sdr_en , - cfg_sdr_mode_reg , - cfg_sdr_tras_d , - cfg_sdr_trp_d , - cfg_sdr_trcd_d , - cfg_sdr_cas , - cfg_sdr_trcar_d , - cfg_sdr_twr_d , - cfg_sdr_rfsh , - cfg_sdr_rfmax - ); - -parameter APP_AW = 32; // Application Address Width -parameter APP_DW = 32; // Application Data Width -parameter APP_BW = 4; // Application Byte Width -parameter APP_RW = 9; // Application Request Width - -parameter SDR_DW = 8; // SDR Data Width -parameter SDR_BW = 1; // SDR Byte Width - -parameter tw = 8; // tag id width -parameter bl = 9; // burst_lenght_width - -//----------------------------------------------- -// Global Variable -// ---------------------------------------------- -input sdram_clk ; // SDRAM Clock -input sdram_resetn ; // Reset Signal -input [1:0] cfg_sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit -input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, - // 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits -output [31:0] sdram_debug ; // SDRAM debug signals - -//-------------------------------------- -// Wish Bone Interface -// ------------------------------------- -input wb_rst_n ; -input wb_clk_i ; - -input wb_stb_i ; -output wb_ack_o ; -input [APP_AW-1:0] wb_addr_i ; -input wb_we_i ; // 1 - Write, 0 - Read -input [APP_DW-1:0] wb_dat_i ; -input [APP_DW/8-1:0] wb_sel_i ; // Byte enable -output [APP_DW-1:0] wb_dat_o ; -input wb_cyc_i ; - -//-------------------------------------- -// Pad Interface -// ------------------------------------- -input [29:0] io_in ; -output [29:0] io_oeb ; -output [29:0] io_out ; -//------------------------------------------------ -// Interface to SDRAMs -//------------------------------------------------ -wire sdram_pad_clk ; // Sdram clock loop back from pad -wire sdr_cke ; // SDRAM CKE -wire sdr_cs_n ; // SDRAM Chip Select -wire sdr_ras_n ; // SDRAM ras -wire sdr_cas_n ; // SDRAM cas -wire sdr_we_n ; // SDRAM write enable -wire [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask -wire [1:0] sdr_ba ; // SDRAM Bank Enable -wire [12:0] sdr_addr ; // SDRAM Address -wire [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input -wire [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output -wire [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable - -//------------------------------------------------ -// Configuration Parameter -//------------------------------------------------ -output sdr_init_done ; // Indicate SDRAM Initialisation Done -input [3:0] cfg_sdr_tras_d ; // Active to precharge delay -input [3:0] cfg_sdr_trp_d ; // Precharge to active delay -input [3:0] cfg_sdr_trcd_d ; // Active to R/W delay -input cfg_sdr_en ; // Enable SDRAM controller -input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller -input [12:0] cfg_sdr_mode_reg ; -input [2:0] cfg_sdr_cas ; // SDRAM CAS Latency -input [3:0] cfg_sdr_trcar_d ; // Auto-refresh period -input [3:0] cfg_sdr_twr_d ; // Write recovery delay -input [`SDR_RFSH_TIMER_W-1 : 0] cfg_sdr_rfsh; -input [`SDR_RFSH_ROW_CNT_W -1 : 0] cfg_sdr_rfmax; - -//-------------------------------------------- -// SDRAM controller Interface -//-------------------------------------------- -wire app_req ; // SDRAM request -wire [APP_AW-1:0] app_req_addr ; // SDRAM Request Address -wire [bl-1:0] app_req_len ; -wire app_req_wr_n ; // 0 - Write, 1 -> Read -wire app_req_ack ; // SDRAM request Accepted -wire app_busy_n ; // 0 -> sdr busy -wire [APP_DW/8-1:0] app_wr_en_n ; // Active low sdr byte-wise write data valid -wire app_wr_next_req ; // Ready to accept the next write -wire app_rd_valid ; // sdr read valid -wire app_last_rd ; // Indicate last Read of Burst Transfer -wire app_last_wr ; // Indicate last Write of Burst Transfer -wire [APP_DW-1:0] app_wr_data ; // sdr write data -wire [APP_DW-1:0] app_rd_data ; // sdr read data - -//-------------------------------------------------- -// WishBone Stagging FF -//-------------------------------------------------- -wire wb_stag_stb_i ; -wire wb_stag_ack_o ; -wire [APP_AW-1:0] wb_stag_addr_i ; -wire wb_stag_we_i ; // 1 - Write, 0 - Read -wire [APP_DW-1:0] wb_stag_dat_i ; -wire [APP_DW/8-1:0] wb_stag_sel_i ; // Byte enable -wire [APP_DW-1:0] wb_stag_dat_o ; -wire wb_stag_cyc_i ; -//----------------------------------------------------------------- -// To avoid the logic at digital core, pad control are brought inside the -// block to support efabless/carvel soc enviornmental support -// ----------------------------------------------------------------- -assign pad_sdr_din[7:0] = io_in[7:0] ; -assign io_out [7:0] = sdr_dout[7:0] ; -assign io_out [20:8] = sdr_addr[12:0] ; -assign io_out [22:21] = sdr_ba[1:0] ; -assign io_out [23] = sdr_dqm[0] ; -assign io_out [24] = sdr_we_n ; -assign io_out [25] = sdr_cas_n ; -assign io_out [26] = sdr_ras_n ; -assign io_out [27] = sdr_cs_n ; -assign io_out [28] = sdr_cke ; -assign io_out [29] = sdram_clk ; -assign sdram_pad_clk = io_in[29] ; - -assign io_oeb [7:0] = sdr_den_n ; -assign io_oeb [20:8] = {(13) {1'b0}} ; -assign io_oeb [22:21] = {(2) {1'b0}} ; -assign io_oeb [23] = 1'b0 ; -assign io_oeb [24] = 1'b0 ; -assign io_oeb [25] = 1'b0 ; -assign io_oeb [26] = 1'b0 ; -assign io_oeb [27] = 1'b0 ; -assign io_oeb [28] = 1'b0 ; -assign io_oeb [29] = 1'b0 ; - -//assign sdr_dq = (&sdr_den_n == 1'b0) ? sdr_dout : {SDR_DW{1'bz}}; -//assign pad_sdr_din = sdr_dq; - -// sdram pad clock is routed back through pad -// SDRAM Clock from Pad, used for registering Read Data -//wire #(1.0) sdram_pad_clk = sdram_clk; -// -wire [21:0] core_debug; -assign sdram_debug = {sdr_init_done,wb_stag_stb_i,wb_stag_we_i,wb_stag_ack_o, - app_req,app_req_wr_n,app_req_ack,app_busy_n,app_wr_next_req, app_rd_valid, - core_debug[21:0]}; - -/************** Ends Here **************************/ - -// Adding Wishbone stagging FF to break timing path -// -wb_stagging u_wb_stage ( - .clk_i (wb_clk_i ), - .rst_n (wb_rst_n ), - // WishBone Input master I/P - .m_wbd_dat_i (wb_dat_i ), - .m_wbd_adr_i (wb_addr_i ), - .m_wbd_sel_i (wb_sel_i ), - .m_wbd_we_i (wb_we_i ), - .m_wbd_cyc_i (wb_cyc_i ), - .m_wbd_stb_i (wb_stb_i ), - .m_wbd_tid_i ('h0 ), - .m_wbd_dat_o (wb_dat_o ), - .m_wbd_ack_o (wb_ack_o ), - .m_wbd_err_o ( ), - - // Slave Interface - .s_wbd_dat_i (wb_stag_dat_o ), - .s_wbd_ack_i (wb_stag_ack_o ), - .s_wbd_err_i (1'b0 ), - .s_wbd_dat_o (wb_stag_dat_i ), - .s_wbd_adr_o (wb_stag_addr_i ), - .s_wbd_sel_o (wb_stag_sel_i ), - .s_wbd_we_o (wb_stag_we_i ), - .s_wbd_cyc_o (wb_stag_cyc_i ), - .s_wbd_stb_o (wb_stag_stb_i ), - .s_wbd_tid_o ( ) - -); - - -wb2sdrc #(.dw(APP_DW),.tw(tw),.bl(bl),.APP_AW(APP_AW)) u_wb2sdrc ( - // WB bus - .wb_rst_n (wb_rst_n ) , - .wb_clk_i (wb_clk_i ) , - - .wb_stb_i (wb_stag_stb_i ) , - .wb_ack_o (wb_stag_ack_o ) , - .wb_addr_i (wb_stag_addr_i ) , - .wb_we_i (wb_stag_we_i ) , - .wb_dat_i (wb_stag_dat_i ) , - .wb_sel_i (wb_stag_sel_i ) , - .wb_dat_o (wb_stag_dat_o ) , - .wb_cyc_i (wb_stag_cyc_i ) , - - - //SDRAM Controller Hand-Shake Signal - .sdram_clk (sdram_clk ) , - .sdram_resetn (sdram_resetn ) , - .sdr_req (app_req ) , - .sdr_req_addr (app_req_addr ) , - .sdr_req_len (app_req_len ) , - .sdr_req_wr_n (app_req_wr_n ) , - .sdr_req_ack (app_req_ack ) , - .sdr_busy_n (app_busy_n ) , - .sdr_wr_en_n (app_wr_en_n ) , - .sdr_wr_next (app_wr_next_req ) , - .sdr_rd_valid (app_rd_valid ) , - .sdr_last_rd (app_last_rd ) , - .sdr_wr_data (app_wr_data ) , - .sdr_rd_data (app_rd_data ) - - ); - - -sdrc_core #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW),.APP_AW(APP_AW)) u_sdrc_core ( - .clk (sdram_clk ) , - .pad_clk (sdram_pad_clk ) , - .reset_n (sdram_resetn ) , - .sdr_width (cfg_sdr_width ) , - .cfg_colbits (cfg_colbits ) , - .debug (core_debug ) , - - /* Request from app */ - .app_req (app_req ) ,// Transfer Request - .app_req_addr (app_req_addr ) ,// SDRAM Address - .app_req_len (app_req_len ) ,// Burst Length (in 16 bit words) - .app_req_wrap (1'b0 ) ,// Wrap mode request - .app_req_wr_n (app_req_wr_n ) ,// 0 => Write request, 1 => read req - .app_req_ack (app_req_ack ) ,// Request has been accepted - .cfg_req_depth (cfg_req_depth ) ,//how many req. buffer should hold - - .app_wr_data (app_wr_data ) , - .app_wr_en_n (app_wr_en_n ) , - .app_rd_data (app_rd_data ) , - .app_rd_valid (app_rd_valid ) , - .app_last_rd (app_last_rd ) , - .app_last_wr (app_last_wr ) , - .app_wr_next_req (app_wr_next_req ) , - .sdr_init_done (sdr_init_done ) , - .app_req_dma_last (app_req ) , - - /* Interface to SDRAMs */ - .sdr_cs_n (sdr_cs_n ) , - .sdr_cke (sdr_cke ) , - .sdr_ras_n (sdr_ras_n ) , - .sdr_cas_n (sdr_cas_n ) , - .sdr_we_n (sdr_we_n ) , - .sdr_dqm (sdr_dqm ) , - .sdr_ba (sdr_ba ) , - .sdr_addr (sdr_addr ) , - .pad_sdr_din (pad_sdr_din ) , - .sdr_dout (sdr_dout ) , - .sdr_den_n (sdr_den_n ) , - - /* Parameters */ - .cfg_sdr_en (cfg_sdr_en ) , - .cfg_sdr_mode_reg (cfg_sdr_mode_reg ) , - .cfg_sdr_tras_d (cfg_sdr_tras_d ) , - .cfg_sdr_trp_d (cfg_sdr_trp_d ) , - .cfg_sdr_trcd_d (cfg_sdr_trcd_d ) , - .cfg_sdr_cas (cfg_sdr_cas ) , - .cfg_sdr_trcar_d (cfg_sdr_trcar_d ) , - .cfg_sdr_twr_d (cfg_sdr_twr_d ) , - .cfg_sdr_rfsh (cfg_sdr_rfsh ) , - .cfg_sdr_rfmax (cfg_sdr_rfmax ) - ); - -endmodule // sdrc_core
diff --git a/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v b/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v deleted file mode 100755 index f6eadc1..0000000 --- a/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v +++ /dev/null
@@ -1,389 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> -// -/********************************************************************* - - This file is part of the sdram controller project - https://github.com/dineshannayya/yifive_r0.git - http://www.opencores.org/cores/yifive/ - http://www.opencores.org/cores/sdr_ctrl/ - - Description: WISHBONE to SDRAM Controller Bus Transalator - 1. This module translate the WISHBONE protocol to custom sdram controller i/f - 2. Also Handle the clock domain change from Application layer to Sdram layer - - To Do: - nothing - - Author(s): Dinesh Annayya, dinesha@opencores.org - Version : 0.0 - Initial Release - 0.1 - 2nd Feb 2012 - Async Fifo towards the application layer is selected - with Registered Full Generation - 0.2 - 2nd Feb 2012 - Pending Read generation bug fix done to handle backto back write - followed by read request - - Copyright (C) 2000 Authors and OPENCORES.ORG - - - This source file may be used and distributed without - restriction provided that this copyright statement is not - removed from the file and that any derivative work contains - the original copyright notice and the associated disclaimer. - - This source file is free software; you can redistribute it - and/or modify it under the terms of the GNU Lesser General - Public License as published by the Free Software Foundation; - either version 2.1 of the License, or (at your option) any -later version. - - This source is distributed in the hope that it will be - useful, but WITHOUT ANY WARRANTY; without even the implied - warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - PURPOSE. See the GNU Lesser General Public License for more - details. - - You should have received a copy of the GNU Lesser General - Public License along with this source; if not, download it - from http://www.opencores.org/lgpl.shtml - -*******************************************************************/ - - -module wb2sdrc ( - // WB bus - wb_rst_n , - wb_clk_i , - - wb_stb_i , - wb_ack_o , - wb_addr_i , - wb_we_i , - wb_dat_i , - wb_sel_i , - wb_dat_o , - wb_cyc_i , - - - //SDRAM Controller Hand-Shake Signal - sdram_clk , - sdram_resetn , - sdr_req , - sdr_req_addr , - sdr_req_len , - sdr_req_wr_n , - sdr_req_ack , - sdr_busy_n , - sdr_wr_en_n , - sdr_wr_next , - sdr_rd_valid , - sdr_last_rd , - sdr_wr_data , - sdr_rd_data - - ); - -parameter dw = 32; // data width -parameter tw = 8; // tag id width -parameter bl = 9; // burst_lenght_width -parameter APP_AW = 26; // Application Address Width -//-------------------------------------- -// Wish Bone Interface -// ------------------------------------- -input wb_rst_n ; -input wb_clk_i ; - -input wb_stb_i ; -output wb_ack_o ; -input [APP_AW-1:0] wb_addr_i ; -input wb_we_i ; // 1 - Write , 0 - Read -input [dw-1:0] wb_dat_i ; -input [dw/8-1:0] wb_sel_i ; // Byte enable -output [dw-1:0] wb_dat_o ; -input wb_cyc_i ; -/*************************************************** -The Cycle Type Idenfier [CTI_IO()] Address Tag provides -additional information about the current cycle. -The MASTER sends this information to the SLAVE. The SLAVE can use this -information to prepare the response for the next cycle. -Table 4-2 Cycle Type Identifiers -CTI_O(2:0) Description -‘000’ Classic cycle. -‘001’ Constant address burst cycle -‘010’ Incrementing burst cycle -‘011’ Reserved -‘100’ Reserved -‘101 Reserved -‘110’ Reserved -‘111’ End-of-Burst -****************************************************/ -//-------------------------------------------- -// SDRAM controller Interface -//-------------------------------------------- -input sdram_clk ; // sdram clock -input sdram_resetn ; // sdram reset -output sdr_req ; // SDRAM request -output [APP_AW-1:0] sdr_req_addr ; // SDRAM Request Address -output [bl-1:0] sdr_req_len ; -output sdr_req_wr_n ; // 0 - Write, 1 -> Read -input sdr_req_ack ; // SDRAM request Accepted -input sdr_busy_n ; // 0 -> sdr busy -output [dw/8-1:0] sdr_wr_en_n ; // Active low sdr byte-wise write data valid -input sdr_wr_next ; // Ready to accept the next write -input sdr_rd_valid ; // sdr read valid -input sdr_last_rd ; // Indicate last Read of Burst Transfer -output [dw-1:0] sdr_wr_data ; // sdr write data -input [dw-1:0] sdr_rd_data ; // sdr read data - -//---------------------------------------------------- -// Wire Decleration -// --------------------------------------------------- -wire cmdfifo_full ; -wire cmdfifo_empty ; -wire wrdatafifo_full ; -wire wrdatafifo_empty ; -wire tagfifo_full ; -wire tagfifo_empty ; -wire rddatafifo_empty ; -wire rddatafifo_full ; - -reg pending_read ; - - -//----------------------------------------------------------------------------- -// Ack Generaltion Logic -// If Write Request - Acknowledge if the command and write FIFO are not full -// If Read Request - Generate the Acknowledgment once read fifo has data -// available -//----------------------------------------------------------------------------- - -assign wb_ack_o = (wb_stb_i && wb_cyc_i && wb_we_i) ? // Write Phase - ((!cmdfifo_full) && (!wrdatafifo_full)) : - (wb_stb_i && wb_cyc_i && !wb_we_i) ? // Read Phase - !rddatafifo_empty : 1'b0; - -//--------------------------------------------------------------------------- -// Command FIFO Write Generation -// If Write Request - Generate write, when Write fifo and command fifo is -// not full -// If Read Request - Generate write, when command fifo not full and there -// is no pending read request. -//--------------------------------------------------------------------------- -wire cmdfifo_wr = (wb_stb_i && wb_cyc_i && wb_we_i && (!cmdfifo_full) ) ? wb_ack_o : - (wb_stb_i && wb_cyc_i && !wb_we_i && (!cmdfifo_full)) ? !pending_read: 1'b0 ; - -//--------------------------------------------------------------------------- -// command fifo read generation -// Command FIFo read will be generated, whenever SDRAM Controller -// Acknowldge the Request -//---------------------------------------------------------------------------- - -wire cmdfifo_rd = sdr_req_ack; - -//--------------------------------------------------------------------------- -// Application layer request is generated towards the controller, whenever -// Command FIFO is not full -// -------------------------------------------------------------------------- -assign sdr_req = !cmdfifo_empty; - -//---------------------------------------------------------------------------- -// Since Burst length is not known at the start of the Burst, It's assumed as -// Single Cycle Burst. We need to improvise this ... -// -------------------------------------------------------------------------- -wire [bl-1:0] burst_length = 1; // 0 Mean 1 Transfer - -//----------------------------------------------------------------------------- -// In Wish Bone Spec, For Read Request has to be acked along with data. -// We need to identify the pending read request. -// Once we accept the read request, we should not accept one more read -// request, untill we have transmitted the read data. -// Pending Read will -// set - with Read Request -// reset - with Read Request + Ack -// ---------------------------------------------------------------------------- -always @(negedge wb_rst_n or posedge wb_clk_i) begin - if(!wb_rst_n) begin - pending_read <= 1'b0; - end else begin - //pending_read <= wb_stb_i & wb_cyc_i & !wb_we_i & !wb_ack_o; - pending_read <= (cmdfifo_wr && !wb_we_i) ? 1'b1: - (wb_stb_i & wb_cyc_i & !wb_we_i & wb_ack_o) ? 1'b0: pending_read; - end -end - -//--------------------------------------------------------------------- -// Async Command FIFO. This block handle the clock domain change from -// Application layer to SDRAM Controller -// ------------------------------------------------------------------ - // Address + Burst Length + W/R Request - async_fifo #(.W(APP_AW+bl+1),.DP(4),.WR_FAST(1'b0), .RD_FAST(1'b0)) u_cmdfifo ( - // Write Path Sys CLock Domain - .wr_clk (wb_clk_i ), - .wr_reset_n (wb_rst_n ), - .wr_en (cmdfifo_wr ), - .wr_data ({burst_length, - !wb_we_i, - wb_addr_i} ), - .afull ( ), - .full (cmdfifo_full ), - - // Read Path, SDRAM clock domain - .rd_clk (sdram_clk ), - .rd_reset_n (sdram_resetn ), - .aempty ( ), - .empty (cmdfifo_empty ), - .rd_en (cmdfifo_rd ), - .rd_data ({sdr_req_len, - sdr_req_wr_n, - sdr_req_addr} ) - ); - -// synopsys translate_off -always @(posedge wb_clk_i) begin - if (cmdfifo_full == 1'b1 && cmdfifo_wr == 1'b1) begin - $display("ERROR:%m COMMAND FIFO WRITE OVERFLOW"); - end -end -// synopsys translate_on -// synopsys translate_off -always @(posedge sdram_clk) begin - if (cmdfifo_empty == 1'b1 && cmdfifo_rd == 1'b1) begin - $display("ERROR:%m COMMAND FIFO READ OVERFLOW"); - end -end -// synopsys translate_on - -//--------------------------------------------------------------------- -// Write Data FIFO Write Generation, when ever Acked + Write Request -// Note: Ack signal generation already taking account of FIFO full condition -// --------------------------------------------------------------------- - -wire wrdatafifo_wr = wb_ack_o & wb_we_i ; - -//------------------------------------------------------------------------ -// Write Data FIFO Read Generation, When ever Next Write request generated -// from SDRAM Controller -// ------------------------------------------------------------------------ -wire wrdatafifo_rd = sdr_wr_next; - - -//------------------------------------------------------------------------ -// Async Write Data FIFO -// This block handle the clock domain change over + Write Data + Byte mask -// From Application layer to SDRAM controller layer -//------------------------------------------------------------------------ - - // Write DATA + Data Mask FIFO - async_fifo #(.W(dw+(dw/8)), .DP(8), .WR_FAST(1'b0), .RD_FAST(1'b1)) u_wrdatafifo ( - // Write Path , System clock domain - .wr_clk (wb_clk_i ), - .wr_reset_n (wb_rst_n ), - .wr_en (wrdatafifo_wr ), - .wr_data ({~wb_sel_i, - wb_dat_i} ), - .afull ( ), - .full (wrdatafifo_full ), - - - // Read Path , SDRAM clock domain - .rd_clk (sdram_clk ), - .rd_reset_n (sdram_resetn ), - .aempty ( ), - .empty (wrdatafifo_empty ), - .rd_en (wrdatafifo_rd ), - .rd_data ({sdr_wr_en_n, - sdr_wr_data} ) - ); -// synopsys translate_off -always @(posedge wb_clk_i) begin - if (wrdatafifo_full == 1'b1 && wrdatafifo_wr == 1'b1) begin - $display("ERROR:%m WRITE DATA FIFO WRITE OVERFLOW"); - end -end - -always @(posedge sdram_clk) begin - if (wrdatafifo_empty == 1'b1 && wrdatafifo_rd == 1'b1) begin - $display("ERROR:%m WRITE DATA FIFO READ OVERFLOW"); - end -end -// synopsys translate_on - -// ------------------------------------------------------------------- -// READ DATA FIFO -// ------------------------------------------------------------------ -wire rd_eop; // last read indication - -// Read FIFO write generation, when ever SDRAM controller issues the read -// valid signal -wire rddatafifo_wr = sdr_rd_valid; - -// Read FIFO read generation, when ever ack is generated along with read -// request. -// Note: Ack generation is already accounted the write FIFO Not Empty -// condition -wire rddatafifo_rd = wb_ack_o & !wb_we_i; - -//------------------------------------------------------------------------- -// Async Read FIFO -// This block handles the clock domain change over + Read data from SDRAM -// controller to Application layer. -// Note: -// 1. READ DATA FIFO depth is kept small, assuming that Sys-CLock > SDRAM Clock -// READ DATA + EOP -// 2. EOP indicate, last transfer of Burst Read Access. use-full for future -// Tag handling per burst -// -// ------------------------------------------------------------------------ - async_fifo #(.W(dw+1), .DP(4), .WR_FAST(1'b0), .RD_FAST(1'b1) ) u_rddatafifo ( - // Write Path , SDRAM clock domain - .wr_clk (sdram_clk ), - .wr_reset_n (sdram_resetn ), - .wr_en (rddatafifo_wr ), - .wr_data ({sdr_last_rd, - sdr_rd_data} ), - .afull ( ), - .full (rddatafifo_full ), - - - // Read Path , SYS clock domain - .rd_clk (wb_clk_i ), - .rd_reset_n (wb_rst_n ), - .empty (rddatafifo_empty ), - .aempty ( ), - .rd_en (rddatafifo_rd ), - .rd_data ({rd_eop, - wb_dat_o} ) - ); - -// synopsys translate_off -always @(posedge sdram_clk) begin - if (rddatafifo_full == 1'b1 && rddatafifo_wr == 1'b1) begin - $display("ERROR:%m READ DATA FIFO WRITE OVERFLOW"); - end -end - -always @(posedge wb_clk_i) begin - if (rddatafifo_empty == 1'b1 && rddatafifo_rd == 1'b1) begin - $display("ERROR:%m READ DATA FIFO READ OVERFLOW"); - end -end -// synopsys translate_on - - -endmodule -
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/Makefile b/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/Makefile deleted file mode 100644 index 3903cd9..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/Makefile +++ /dev/null
@@ -1,26 +0,0 @@ -src_dir := $(dir $(lastword $(MAKEFILE_LIST))) -depend_dir := $(src_dir)/../../../../dependencies/coremark - -ifeq ("$(ITERATIONS)","") -ITERATIONS=1 -endif - -ADD_CFLAGS += -DITERATIONS=$(ITERATIONS) -ADD_VPATH := $(depend_dir) -ADD_incs := -I$(src_dir)/src -I$(depend_dir) - -c_src := core_portme.c sc_print.c -coremark_src := ./src/core_list_join.c ./src/core_matrix.c ./src/core_main.c ./src/core_util.c ./src/core_state.c -c_src += core_list_join.c core_matrix.c core_main.c core_util.c core_state.c - -include $(inc_dir)/common.mk - - -default: log_requested_tgt $(bld_dir)/coremark.elf $(bld_dir)/coremark.hex $(bld_dir)/coremark.dump - -log_requested_tgt: - echo coremark.hex>> $(bld_dir)/test_info - echo $(inc_dir)/common.mk - -clean: - $(RM) $(c_objs) $(asm_objs) $(bld_dir)/coremark.hex $(bld_dir)/coremark.dump
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/core_portme.c b/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/core_portme.c deleted file mode 100644 index 3c801f7..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/core_portme.c +++ /dev/null
@@ -1,141 +0,0 @@ -/* - File : core_portme.c -*/ -/* - Author : Shay Gal-On, EEMBC - Legal : TODO! -*/ -#include <stdio.h> -#include <stdlib.h> -#include "coremark.h" -#include "core_portme.h" -#include "riscv_csr_encoding.h" -#include "sc_test.h" - -#if VALIDATION_RUN - volatile ee_s32 seed1_volatile=0x3415; - volatile ee_s32 seed2_volatile=0x3415; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PERFORMANCE_RUN - volatile ee_s32 seed1_volatile=0x0; - volatile ee_s32 seed2_volatile=0x0; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PROFILE_RUN - volatile ee_s32 seed1_volatile=0x8; - volatile ee_s32 seed2_volatile=0x8; - volatile ee_s32 seed3_volatile=0x8; -#endif - volatile ee_s32 seed4_volatile=ITERATIONS; - volatile ee_s32 seed5_volatile=0; - -/* Porting : Timing functions - How to capture time and convert to seconds must be ported to whatever is supported by the platform. - e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc. - Sample implementation for standard time.h and windows.h definitions included. -*/ -#if 1 -CORETIMETYPE barebones_clock() { - unsigned long n; - __asm__ __volatile__ ( - "rdtime %0" - : "=r" (n)); - return n; -} -#define CLOCKS_PER_SEC 10000000 - -/* Define : TIMER_RES_DIVIDER - Divider to trade off timer resolution and total time that can be measured. - - Use lower values to increase resolution, but make sure that overflow does not occur. - If there are issues with the return value overflowing, increase this value. - */ -/* #define NSECS_PER_SEC CLOCKS_PER_SEC */ -/* #define CORETIMETYPE clock_t */ -#define GETMYTIME(_t) (*_t=barebones_clock()) -#define MYTIMEDIFF(fin,ini) ((fin)-(ini)) -#define TIMER_RES_DIVIDER 1 -#define SAMPLE_TIME_IMPLEMENTATION 1 -#define EE_TICKS_PER_SEC (CLOCKS_PER_SEC / TIMER_RES_DIVIDER) -#else - -#endif - -/** Define Host specific (POSIX), or target specific global time variables. */ -static CORETIMETYPE start_time_val, stop_time_val; - -/* Function : start_time - This function will be called right before starting the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0. -*/ -void start_time(void) { - GETMYTIME(&start_time_val ); -} -/* Function : stop_time - This function will be called right after ending the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or other system parameters - e.g. reading the current value of cpu cycles counter. -*/ -void stop_time(void) { - GETMYTIME(&stop_time_val ); -} -/* Function : get_time - Return an abstract "ticks" number that signifies time on the system. - - Actual value returned may be cpu cycles, milliseconds or any other value, - as long as it can be converted to seconds by <time_in_secs>. - This methodology is taken to accomodate any hardware or simulated platform. - The sample implementation returns millisecs by default, - and the resolution is controlled by <TIMER_RES_DIVIDER> -*/ -CORE_TICKS get_time(void) { - CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); - return elapsed; -} -/* Function : time_in_secs - Convert the value returned by get_time to seconds. - - The <secs_ret> type is used to accomodate systems with no support for floating point. - Default implementation implemented by the EE_TICKS_PER_SEC macro above. -*/ -secs_ret time_in_secs(CORE_TICKS ticks) { - secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; - return retval; -} - -ee_u32 default_num_contexts=1; - -/* Function : portable_init - Target specific initialization code - Test for some common mistakes. -*/ -void portable_init(core_portable *p, int *argc, char *argv[]) -{ - ee_printf("CoreMark 1.0\n"); - if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) { - ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer! (%u != %u)\n", sizeof(ee_ptr_int), sizeof(ee_u8 *)); - } - if (sizeof(ee_u32) != 4) { - ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type! (%u)\n", sizeof(ee_u32)); - } - p->portable_id=1; -} -/* Function : portable_fini - Target specific final code -*/ -void portable_fini(core_portable *p) -{ - p->portable_id=0; - - report_results(0, 0, 0, 0, 0); - - /* results[0].iterations * 10000000/(total_time) */ - - /* extern void tohost_exit(long code); */ - - /* tohost_exit(0); */ -}
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/core_portme.h b/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/core_portme.h deleted file mode 100644 index 857930f..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/coremark/core_portme.h +++ /dev/null
@@ -1,210 +0,0 @@ -/* File : core_portme.h */ - -/* - Author : Shay Gal-On, EEMBC - Legal : TODO! -*/ -/* Topic : Description - This file contains configuration constants required to execute on different platforms -*/ -#ifndef CORE_PORTME_H -#define CORE_PORTME_H -/************************/ -/* Data types and settings */ -/************************/ -/* Configuration : HAS_FLOAT - Define to 1 if the platform supports floating point. -*/ -#ifndef HAS_FLOAT -#define HAS_FLOAT 0 -#endif -/* Configuration : HAS_TIME_H - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef HAS_TIME_H -#define HAS_TIME_H 0 -#endif -/* Configuration : USE_CLOCK - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef USE_CLOCK -#define USE_CLOCK 0 -#endif -/* Configuration : HAS_STDIO - Define to 1 if the platform has stdio.h. -*/ -#ifndef HAS_STDIO -#define HAS_STDIO 1 -#endif -/* Configuration : HAS_PRINTF - Define to 1 if the platform has stdio.h and implements the printf function. -*/ -#ifndef HAS_PRINTF -#define HAS_PRINTF 0 -#endif - -#include "sc_print.h" -#define ee_printf sc_printf - -/* static inline int ee_printf(const char *fmt, ...) {} */ - -/* Configuration : CORE_TICKS - Define type of return from the timing functions. - */ -/* #include <time.h> */ -/* typedef clock_t CORE_TICKS; */ -#include <stdint.h> -#include <stddef.h> -#define CORETIMETYPE uint32_t -typedef uint32_t CORE_TICKS; - -/* Definitions : COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION - Initialize these strings per platform -*/ -#ifndef COMPILER_VERSION - #ifdef __GNUC__ - #define COMPILER_VERSION "GCC"__VERSION__ - #else - #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)" - #endif -#endif -#ifndef COMPILER_FLAGS - #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */ -#endif -#ifndef MEM_LOCATION - /* #define MEM_LOCATION "STACK" */ - #define MEM_LOCATION "STATIC" -#endif - -/* Data Types : - To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in <core_portme.h>. - - *Imprtant* : - ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!! -*/ -typedef int16_t ee_s16; -typedef uint16_t ee_u16; -typedef int32_t ee_s32; -typedef float ee_f32; -typedef uint8_t ee_u8; -typedef uint32_t ee_u32; -typedef uintptr_t ee_ptr_int; -typedef size_t ee_size_t; -/* align_mem : - This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks. -*/ -#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3)) - -/* Configuration : SEED_METHOD - Defines method to get seed values that cannot be computed at compile time. - - Valid values : - SEED_ARG - from command line. - SEED_FUNC - from a system function. - SEED_VOLATILE - from volatile variables. -*/ -#ifndef SEED_METHOD -#define SEED_METHOD SEED_VOLATILE -#endif - -/* Configuration : MEM_METHOD - Defines method to get a block of memry. - - Valid values : - MEM_MALLOC - for platforms that implement malloc and have malloc.h. - MEM_STATIC - to use a static memory array. - MEM_STACK - to allocate the data block on the stack (NYI). -*/ -#ifndef MEM_METHOD -/* #define MEM_METHOD MEM_STACK */ -#define MEM_METHOD MEM_STATIC -#endif - -/* Configuration : MULTITHREAD - Define for parallel execution - - Valid values : - 1 - only one context (default). - N>1 - will execute N copies in parallel. - - Note : - If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined. - - Two sample implementations are provided. Use <USE_PTHREAD> or <USE_FORK> to enable them. - - It is valid to have a different implementation of <core_start_parallel> and <core_end_parallel> in <core_portme.c>, - to fit a particular architecture. -*/ -#ifndef MULTITHREAD -#define MULTITHREAD 1 -#define USE_PTHREAD 0 -#define USE_FORK 0 -#define USE_SOCKET 0 -#endif - -/* Configuration : MAIN_HAS_NOARGC - Needed if platform does not support getting arguments to main. - - Valid values : - 0 - argc/argv to main is supported - 1 - argc/argv to main is not supported - - Note : - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef MAIN_HAS_NOARGC -#define MAIN_HAS_NOARGC 1 -#endif - -/* Configuration : MAIN_HAS_NORETURN - Needed if platform does not support returning a value from main. - - Valid values : - 0 - main returns an int, and return value will be 0. - 1 - platform does not support returning a value from main -*/ -#ifndef MAIN_HAS_NORETURN -#define MAIN_HAS_NORETURN 0 -#endif - -/* Variable : default_num_contexts - Not used for this simple port, must cintain the value 1. -*/ -extern ee_u32 default_num_contexts; - -typedef struct CORE_PORTABLE_S { - ee_u8 portable_id; -} core_portable; - -/* target specific init/fini */ -void portable_init(core_portable *p, int *argc, char *argv[]); -void portable_fini(core_portable *p); - -#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) && !defined(VALIDATION_RUN) -#if (TOTAL_DATA_SIZE==1200) -#define PROFILE_RUN 1 -#elif (TOTAL_DATA_SIZE==2000) -#define PERFORMANCE_RUN 1 -#else -#define VALIDATION_RUN 1 -#endif -#endif - -typedef ee_s16 MATDAT; -typedef ee_s32 MATRES; - - -ee_u16 crcu8(ee_u8 data, ee_u16 crc ) __attribute__ ((hot)); -ee_u16 crcu16(ee_u16 newval, ee_u16 crc) __attribute__ ((hot)); -ee_u16 crcu32(ee_u32 newval, ee_u16 crc) __attribute__ ((hot)); -ee_u16 crc16(ee_s16 newval, ee_u16 crc) __attribute__ ((hot)); -ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval) __attribute__ ((hot)); -void matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val) __attribute__ ((hot)); -void matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) __attribute__ ((hot)); -void matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) __attribute__ ((hot)); -void matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) __attribute__ ((hot)); -void matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val) __attribute__ ((hot)); - -#endif /* CORE_PORTME_H */
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/Makefile b/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/Makefile deleted file mode 100644 index 7056489..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/Makefile +++ /dev/null
@@ -1,16 +0,0 @@ -src_dir := $(dir $(lastword $(MAKEFILE_LIST))) - -ADD_FLAGS := -flto -ADD_CFLAGS := -DSELF_TIMED=1 -DTIME=1 - -c_src := sc_print.c dhry_1.c dhry_2.c - -include $(inc_dir)/common.mk - -default: log_requested_tgt $(bld_dir)/dhrystone21.elf $(bld_dir)/dhrystone21.hex $(bld_dir)/dhrystone21.dump - -log_requested_tgt: - @echo dhrystone21.hex>> $(bld_dir)/test_info - -clean: - $(RM) $(c_objs) $(asm_objs) $(bld_dir)/dhrystone21.elf $(bld_dir)/dhrystone21.hex $(bld_dir)/dhrystone21.dump \ No newline at end of file
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry.h b/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry.h deleted file mode 100644 index cba0059..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry.h +++ /dev/null
@@ -1,446 +0,0 @@ -/***************************************************************************** - * The BYTE UNIX Benchmarks - Release 3 - * Module: dhry.h SID: 3.4 5/15/91 19:30:21 - * - ***************************************************************************** - * Bug reports, patches, comments, suggestions should be sent to: - * - * Ben Smith, Rick Grehan or Tom Yager - * ben@bytepb.byte.com rick_g@bytepb.byte.com tyager@bytepb.byte.com - * - ***************************************************************************** - * Modification Log: - * addapted from: - * - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * Version: C, Version 2.1 - * - * File: dhry.h (part 1 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * Siemens AG, AUT E 51 - * Postfach 3220 - * 8520 Erlangen - * Germany (West) - * Phone: [+49]-9131-7-20330 - * (8-17 Central European Time) - * Usenet: ..!mcvax!unido!estevax!weicker - * - * Original Version (in Ada) published in - * "Communications of the ACM" vol. 27., no. 10 (Oct. 1984), - * pp. 1013 - 1030, together with the statistics - * on which the distribution of statements etc. is based. - * - * In this C version, the following C library functions are used: - * - strcpy, strcmp (inside the measurement loop) - * - printf, scanf (outside the measurement loop) - * In addition, Berkeley UNIX system calls "times ()" or "time ()" - * are used for execution time measurement. For measurements - * on other systems, these calls have to be changed. - * - * Collection of Results: - * Reinhold Weicker (address see above) and - * - * Rick Richardson - * PC Research. Inc. - * 94 Apple Orchard Drive - * Tinton Falls, NJ 07724 - * Phone: (201) 834-1378 (9-17 EST) - * Usenet: ...!seismo!uunet!pcrat!rick - * - * Please send results to Rick Richardson and/or Reinhold Weicker. - * Complete information should be given on hardware and software used. - * Hardware information includes: Machine type, CPU, type and size - * of caches; for microprocessors: clock frequency, memory speed - * (number of wait states). - * Software information includes: Compiler (and runtime library) - * manufacturer and version, compilation switches, OS version. - * The Operating System version may give an indication about the - * compiler; Dhrystone itself performs no OS calls in the measurement loop. - * - * The complete output generated by the program should be mailed - * such that at least some checks for correctness can be made. - * - *************************************************************************** - * - * History: This version C/2.1 has been made for two reasons: - * - * 1) There is an obvious need for a common C version of - * Dhrystone, since C is at present the most popular system - * programming language for the class of processors - * (microcomputers, minicomputers) where Dhrystone is used most. - * There should be, as far as possible, only one C version of - * Dhrystone such that results can be compared without - * restrictions. In the past, the C versions distributed - * by Rick Richardson (Version 1.1) and by Reinhold Weicker - * had small (though not significant) differences. - * - * 2) As far as it is possible without changes to the Dhrystone - * statistics, optimizing compilers should be prevented from - * removing significant statements. - * - * This C version has been developed in cooperation with - * Rick Richardson (Tinton Falls, NJ), it incorporates many - * ideas from the "Version 1.1" distributed previously by - * him over the UNIX network Usenet. - * I also thank Chaim Benedelac (National Semiconductor), - * David Ditzel (SUN), Earl Killian and John Mashey (MIPS), - * Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley) - * for their help with comments on earlier versions of the - * benchmark. - * - * Changes: In the initialization part, this version follows mostly - * Rick Richardson's version distributed via Usenet, not the - * version distributed earlier via floppy disk by Reinhold Weicker. - * As a concession to older compilers, names have been made - * unique within the first 8 characters. - * Inside the measurement loop, this version follows the - * version previously distributed by Reinhold Weicker. - * - * At several places in the benchmark, code has been added, - * but within the measurement loop only in branches that - * are not executed. The intention is that optimizing compilers - * should be prevented from moving code out of the measurement - * loop, or from removing code altogether. Since the statements - * that are executed within the measurement loop have NOT been - * changed, the numbers defining the "Dhrystone distribution" - * (distribution of statements, operand types and locality) - * still hold. Except for sophisticated optimizing compilers, - * execution times for this version should be the same as - * for previous versions. - * - * Since it has proven difficult to subtract the time for the - * measurement loop overhead in a correct way, the loop check - * has been made a part of the benchmark. This does have - * an impact - though a very minor one - on the distribution - * statistics which have been updated for this version. - * - * All changes within the measurement loop are described - * and discussed in the companion paper "Rationale for - * Dhrystone version 2". - * - * Because of the self-imposed limitation that the order and - * distribution of the executed statements should not be - * changed, there are still cases where optimizing compilers - * may not generate code for some statements. To a certain - * degree, this is unavoidable for small synthetic benchmarks. - * Users of the benchmark are advised to check code listings - * whether code is generated for all statements of Dhrystone. - * - * Version 2.1 is identical to version 2.0 distributed via - * the UNIX network Usenet in March 1988 except that it corrects - * some minor deficiencies that were found by users of version 2.0. - * The only change within the measurement loop is that a - * non-executed "else" part was added to the "if" statement in - * Func_3, and a non-executed "else" part removed from Proc_3. - * - *************************************************************************** - * - * Defines: The following "Defines" are possible: - * -DREG=register (default: Not defined) - * As an approximation to what an average C programmer - * might do, the "register" storage class is applied - * (if enabled by -DREG=register) - * - for local variables, if they are used (dynamically) - * five or more times - * - for parameters if they are used (dynamically) - * six or more times - * Note that an optimal "register" strategy is - * compiler-dependent, and that "register" declarations - * do not necessarily lead to faster execution. - * -DNOSTRUCTASSIGN (default: Not defined) - * Define if the C compiler does not support - * assignment of structures. - * -DNOENUMS (default: Not defined) - * Define if the C compiler does not support - * enumeration types. - * -DTIMES (default) - * -DTIME - * The "times" function of UNIX (returning process times) - * or the "time" function (returning wallclock time) - * is used for measurement. - * For single user machines, "time ()" is adequate. For - * multi-user machines where you cannot get single-user - * access, use the "times ()" function. If you have - * neither, use a stopwatch in the dead of night. - * "printf"s are provided marking the points "Start Timer" - * and "Stop Timer". DO NOT use the UNIX "time(1)" - * command, as this will measure the total time to - * run this program, which will (erroneously) include - * the time to allocate storage (malloc) and to perform - * the initialization. - * -DHZ=nnn - * In Berkeley UNIX, the function "times" returns process - * time in 1/HZ seconds, with HZ = 60 for most systems. - * CHECK YOUR SYSTEM DESCRIPTION BEFORE YOU JUST APPLY - * A VALUE. - * - *************************************************************************** - * - * Compilation model and measurement (IMPORTANT): - * - * This C version of Dhrystone consists of three files: - * - dhry.h (this file, containing global definitions and comments) - * - dhry_1.c (containing the code corresponding to Ada package Pack_1) - * - dhry_2.c (containing the code corresponding to Ada package Pack_2) - * - * The following "ground rules" apply for measurements: - * - Separate compilation - * - No procedure merging - * - Otherwise, compiler optimizations are allowed but should be indicated - * - Default results are those without register declarations - * See the companion paper "Rationale for Dhrystone Version 2" for a more - * detailed discussion of these ground rules. - * - * For 16-Bit processors (e.g. 80186, 80286), times for all compilation - * models ("small", "medium", "large" etc.) should be given if possible, - * together with a definition of these models for the compiler system used. - * - ************************************************************************** - * - * Dhrystone (C version) statistics: - * - * [Comment from the first distribution, updated for version 2. - * Note that because of language differences, the numbers are slightly - * different from the Ada version.] - * - * The following program contains statements of a high level programming - * language (here: C) in a distribution considered representative: - * - * assignments 52 (51.0 %) - * control statements 33 (32.4 %) - * procedure, function calls 17 (16.7 %) - * - * 103 statements are dynamically executed. The program is balanced with - * respect to the three aspects: - * - * - statement type - * - operand type - * - operand locality - * operand global, local, parameter, or constant. - * - * The combination of these three aspects is balanced only approximately. - * - * 1. Statement Type: - * ----------------- number - * - * V1 = V2 9 - * (incl. V1 = F(..) - * V = Constant 12 - * Assignment, 7 - * with array element - * Assignment, 6 - * with record component - * -- - * 34 34 - * - * X = Y +|-|"&&"|"|" Z 5 - * X = Y +|-|"==" Constant 6 - * X = X +|- 1 3 - * X = Y *|/ Z 2 - * X = Expression, 1 - * two operators - * X = Expression, 1 - * three operators - * -- - * 18 18 - * - * if .... 14 - * with "else" 7 - * without "else" 7 - * executed 3 - * not executed 4 - * for ... 7 | counted every time - * while ... 4 | the loop condition - * do ... while 1 | is evaluated - * switch ... 1 - * break 1 - * declaration with 1 - * initialization - * -- - * 34 34 - * - * P (...) procedure call 11 - * user procedure 10 - * library procedure 1 - * X = F (...) - * function call 6 - * user function 5 - * library function 1 - * -- - * 17 17 - * --- - * 103 - * - * The average number of parameters in procedure or function calls - * is 1.82 (not counting the function values as implicit parameters). - * - * - * 2. Operators - * ------------ - * number approximate - * percentage - * - * Arithmetic 32 50.8 - * - * + 21 33.3 - * - 7 11.1 - * * 3 4.8 - * / (int div) 1 1.6 - * - * Comparison 27 42.8 - * - * == 9 14.3 - * /= 4 6.3 - * > 1 1.6 - * < 3 4.8 - * >= 1 1.6 - * <= 9 14.3 - * - * Logic 4 6.3 - * - * && (AND-THEN) 1 1.6 - * | (OR) 1 1.6 - * ! (NOT) 2 3.2 - * - * -- ----- - * 63 100.1 - * - * - * 3. Operand Type (counted once per operand reference): - * --------------- - * number approximate - * percentage - * - * Integer 175 72.3 % - * Character 45 18.6 % - * Pointer 12 5.0 % - * String30 6 2.5 % - * Array 2 0.8 % - * Record 2 0.8 % - * --- ------- - * 242 100.0 % - * - * When there is an access path leading to the final operand (e.g. a record - * component), only the final data type on the access path is counted. - * - * - * 4. Operand Locality: - * ------------------- - * number approximate - * percentage - * - * local variable 114 47.1 % - * global variable 22 9.1 % - * parameter 45 18.6 % - * value 23 9.5 % - * reference 22 9.1 % - * function result 6 2.5 % - * constant 55 22.7 % - * --- ------- - * 242 100.0 % - * - * - * The program does not compute anything meaningful, but it is syntactically - * and semantically correct. All variables have a value assigned to them - * before they are used as a source operand. - * - * There has been no explicit effort to account for the effects of a - * cache, or to balance the use of long or short displacements for code or - * data. - * - *************************************************************************** - */ - - -/* Compiler and system dependent definitions: */ - -#ifndef TIME -#define TIMES -#endif - /* Use times(2) time function unless */ - /* explicitly defined otherwise */ - -#ifdef TIMES -#include <sys/types.h> -#include <sys/times.h> - /* for "times" */ -#endif - -#define Mic_secs_Per_Second 1000000 - /* Berkeley UNIX C returns process times in seconds/HZ */ - -#ifdef NOSTRUCTASSIGN -#define structassign(d, s) memcpy(&(d), &(s), sizeof(d)) -#else -#define structassign(d, s) d = s -#endif - -#ifdef NOENUM -#define Ident_1 0 -#define Ident_2 1 -#define Ident_3 2 -#define Ident_4 3 -#define Ident_5 4 - typedef int Enumeration; -#else - typedef enum {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5} - Enumeration; -#endif - /* for boolean and enumeration types in Ada, Pascal */ - -/* General definitions: */ - -#include <stdio.h> -#include <string.h> - /* for strcpy, strcmp */ - -#define Null 0 - /* Value of a Null pointer */ -#define true 1 -#define false 0 - -typedef int One_Thirty; -typedef int One_Fifty; -typedef char Capital_Letter; -typedef int Boolean; -typedef char Str_30 [31]; -typedef int Arr_1_Dim [50]; -typedef int Arr_2_Dim [50] [50]; - -typedef struct record - { - struct record *Ptr_Comp; - Enumeration Discr; - union { - struct { - Enumeration Enum_Comp; - int Int_Comp; - char Str_Comp [31]; - } var_1; - struct { - Enumeration E_Comp_2; - char Str_2_Comp [31]; - } var_2; - struct { - char Ch_1_Comp; - char Ch_2_Comp; - } var_3; - } variant; - } Rec_Type, *Rec_Pointer; - -#include "sc_print.h" -#include "csr.h" - -# define printf sc_printf - -#define HZ 1000000 -static long time(long *x) -{ - return rdcycle(); -}
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry_1.c b/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry_1.c deleted file mode 100644 index d52acbb..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry_1.c +++ /dev/null
@@ -1,461 +0,0 @@ -/***************************************************************************** - * The BYTE UNIX Benchmarks - Release 3 - * Module: dhry_1.c SID: 3.4 5/15/91 19:30:21 - * - ***************************************************************************** - * Bug reports, patches, comments, suggestions should be sent to: - * - * Ben Smith, Rick Grehan or Tom Yager - * ben@bytepb.byte.com rick_g@bytepb.byte.com tyager@bytepb.byte.com - * - ***************************************************************************** - * - * *** WARNING **** With BYTE's modifications applied, results obtained with - * ******* this version of the Dhrystone program may not be applicable - * to other versions. - * - * Modification Log: - * 10/22/97 - code cleanup to remove ANSI C compiler warnings - * Andy Kahn <kahn@zk3.dec.com> - * - * Adapted from: - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * Version: C, Version 2.1 - * - * File: dhry_1.c (part 2 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * - ***************************************************************************/ -char SCCSid[] = "@(#) @(#)dhry_1.c:3.4 -- 5/15/91 19:30:21"; - -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include "dhry.h" -//#include "timeit.c" - -unsigned long Run_Index; -/* -void report() -{ - fprintf(stderr,"COUNT|%ld|1|lps\n", Run_Index); - exit(0); -} -*/ -/* Global Variables: */ - -Rec_Pointer Ptr_Glob, - Next_Ptr_Glob; -int Int_Glob; -Boolean Bool_Glob; -char Ch_1_Glob, - Ch_2_Glob; -int Arr_1_Glob [50]; -int Arr_2_Glob [50] [50]; - -Enumeration Func_1 (); - /* forward declaration necessary since Enumeration may not simply be int */ - -#ifndef REG - Boolean Reg = false; -#define REG - /* REG becomes defined as empty */ - /* i.e. no register variables */ -#else - Boolean Reg = true; -#endif - -/* variables for time measurement: */ - -#ifdef TIMES -struct tms time_info; -/* extern int times (); */ - /* see library function "times" */ -#define Too_Small_Time 120 - /* Measurements should last at least about 2 seconds */ -#endif -#ifdef TIME -extern long time(); - /* see library function "time" */ -#define Too_Small_Time 2 - /* Measurements should last at least 2 seconds */ -#endif - -long Begin_Time, - End_Time, - User_Time; -#if 0 -float Microseconds, - Dhrystones_Per_Second; -#else -long Microseconds, - Dhrystones_Per_Second; -#endif - -/* end of variables for time measurement */ - -void Proc_1 (REG Rec_Pointer Ptr_Val_Par); -void Proc_2 (One_Fifty *Int_Par_Ref); -void Proc_3 (Rec_Pointer *Ptr_Ref_Par); -void Proc_4 (void); -void Proc_5 (void); - - -extern Boolean Func_2(Str_30, Str_30); -extern void Proc_6(Enumeration, Enumeration *); -extern void Proc_7(One_Fifty, One_Fifty, One_Fifty *); -extern void Proc_8(Arr_1_Dim, Arr_2_Dim, int, int); - -int main (argc, argv) -int argc; -char *argv[]; - /* main program, corresponds to procedures */ - /* Main and Proc_0 in the Ada version */ -{ -#ifdef SELF_TIMED - int Number_Of_Runs; -#else /* SELF_TIMED */ - int duration; -#endif /* SELF_TIMED */ - One_Fifty Int_1_Loc; - REG One_Fifty Int_2_Loc; - One_Fifty Int_3_Loc; - REG char Ch_Index; - Enumeration Enum_Loc; - Str_30 Str_1_Loc; - Str_30 Str_2_Loc; - - /* Initializations */ -#if 0 - Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); - Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type)); -#else - static Rec_Type glob1, glob2; - Next_Ptr_Glob = &glob1; - Ptr_Glob = &glob2; -#endif - - Ptr_Glob->Ptr_Comp = Next_Ptr_Glob; - Ptr_Glob->Discr = Ident_1; - Ptr_Glob->variant.var_1.Enum_Comp = Ident_3; - Ptr_Glob->variant.var_1.Int_Comp = 40; - strcpy (Ptr_Glob->variant.var_1.Str_Comp, - "DHRYSTONE PROGRAM, SOME STRING"); - strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING"); - - Arr_2_Glob [8][7] = 10; - /* Was missing in published program. Without this statement, */ - /* Arr_2_Glob [8][7] would have an undefined value. */ - /* Warning: With 16-Bit processors and Number_Of_Runs > 32000, */ - /* overflow may occur for this array element. */ - -#ifdef SELF_TIMED - Number_Of_Runs = 500;//500000; - if (argc >= 2) { - Number_Of_Runs = atoi(argv[1]); - } - printf ("\n"); - printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n"); - printf ("\n"); - if (Reg) - { - printf ("Program compiled with 'register' attribute\n"); - printf ("\n"); - } - else - { - printf ("Program compiled without 'register' attribute\n"); - printf ("\n"); - } -#ifdef PRATTLE - printf ("Please give the number of runs through the benchmark: "); - { - int n; - scanf ("%d", &n); - Number_Of_Runs = n; - } - printf ("\n"); -#endif /* PRATTLE */ - - printf ("Execution starts, %d runs through Dhrystone\n", Number_Of_Runs); - - Run_Index = 0; -#else /* SELF_TIMED */ - if (argc != 2) { - fprintf(stderr, "Usage: %s duration\n", argv[0]); - exit(1); - } - - duration = atoi(argv[1]); - Run_Index = 0; - wake_me(duration, report); -#endif /* SELF_TIMED */ - - /***************/ - /* Start timer */ - /***************/ - -#ifdef SELF_TIMED -#ifdef TIMES - times (&time_info); - Begin_Time = (long) time_info.tms_utime; -#endif -#ifdef TIME - Begin_Time = time ( (long *) 0); -#endif -#endif /* SELF_TIMED */ - -#ifdef SELF_TIMED - for (Run_Index = 1; Run_Index <= Number_Of_Runs ; ++Run_Index) -#else /* SELF_TIMED */ - for (Run_Index = 1; ; ++Run_Index) -#endif /* SELF_TIMED */ - { - - Proc_5(); - Proc_4(); - /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */ - Int_1_Loc = 2; - Int_2_Loc = 3; - strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING"); - Enum_Loc = Ident_2; - Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc); - /* Bool_Glob == 1 */ - while (Int_1_Loc < Int_2_Loc) /* loop body executed once */ - { - Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc; - /* Int_3_Loc == 7 */ - Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc); - /* Int_3_Loc == 7 */ - Int_1_Loc += 1; - } /* while */ - /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ - Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc); - /* Int_Glob == 5 */ - Proc_1 (Ptr_Glob); - for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index) - /* loop body executed twice */ - { - if (Enum_Loc == Func_1 (Ch_Index, 'C')) - /* then, not executed */ - { - Proc_6 (Ident_1, &Enum_Loc); - strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING"); - Int_2_Loc = Run_Index; - Int_Glob = Run_Index; - } - } - /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */ - Int_2_Loc = Int_2_Loc * Int_1_Loc; - Int_1_Loc = Int_2_Loc / Int_3_Loc; - Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc; - /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */ - Proc_2 (&Int_1_Loc); - /* Int_1_Loc == 5 */ - - } /* loop "for Run_Index" */ - - /**************/ - /* Stop timer */ - /**************/ -#ifdef SELF_TIMED -#ifdef TIMES - times (&time_info); - End_Time = (long) time_info.tms_utime; -#endif -#ifdef TIME - End_Time = time ( (long *) 0); -#endif -#endif /* SELF_TIMED */ - - /* BYTE version never executes this stuff */ -#ifdef SELF_TIMED - printf ("Execution ends\n"); - printf ("\n"); - printf ("Final values of the variables used in the benchmark:\n"); - printf ("\n"); - printf ("Int_Glob: %d\n", Int_Glob); - printf (" should be: %d\n", 5); - printf ("Bool_Glob: %d\n", Bool_Glob); - printf (" should be: %d\n", 1); - printf ("Ch_1_Glob: %c\n", Ch_1_Glob); - printf (" should be: %c\n", 'A'); - printf ("Ch_2_Glob: %c\n", Ch_2_Glob); - printf (" should be: %c\n", 'B'); - printf ("Arr_1_Glob[8]: %d\n", Arr_1_Glob[8]); - printf (" should be: %d\n", 7); - printf ("Arr_2_Glob[8][7]: %d\n", Arr_2_Glob[8][7]); - printf (" should be: Number_Of_Runs + 10\n"); - printf ("Ptr_Glob->\n"); - printf (" Ptr_Comp: %d\n", (int) Ptr_Glob->Ptr_Comp); - printf (" should be: (implementation-dependent)\n"); - printf (" Discr: %d\n", Ptr_Glob->Discr); - printf (" should be: %d\n", 0); - printf (" Enum_Comp: %d\n", Ptr_Glob->variant.var_1.Enum_Comp); - printf (" should be: %d\n", 2); - printf (" Int_Comp: %d\n", Ptr_Glob->variant.var_1.Int_Comp); - printf (" should be: %d\n", 17); - printf (" Str_Comp: %s\n", Ptr_Glob->variant.var_1.Str_Comp); - printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); - printf ("Next_Ptr_Glob->\n"); - printf (" Ptr_Comp: %d\n", (int) Next_Ptr_Glob->Ptr_Comp); - printf (" should be: (implementation-dependent), same as above\n"); - printf (" Discr: %d\n", Next_Ptr_Glob->Discr); - printf (" should be: %d\n", 0); - printf (" Enum_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp); - printf (" should be: %d\n", 1); - printf (" Int_Comp: %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp); - printf (" should be: %d\n", 18); - printf (" Str_Comp: %s\n", - Next_Ptr_Glob->variant.var_1.Str_Comp); - printf (" should be: DHRYSTONE PROGRAM, SOME STRING\n"); - printf ("Int_1_Loc: %d\n", Int_1_Loc); - printf (" should be: %d\n", 5); - printf ("Int_2_Loc: %d\n", Int_2_Loc); - printf (" should be: %d\n", 13); - printf ("Int_3_Loc: %d\n", Int_3_Loc); - printf (" should be: %d\n", 7); - printf ("Enum_Loc: %d\n", Enum_Loc); - printf (" should be: %d\n", 1); - printf ("Str_1_Loc: %s\n", Str_1_Loc); - printf (" should be: DHRYSTONE PROGRAM, 1'ST STRING\n"); - printf ("Str_2_Loc: %s\n", Str_2_Loc); - printf (" should be: DHRYSTONE PROGRAM, 2'ND STRING\n"); - printf ("\n"); - - User_Time = End_Time - Begin_Time; - - if (User_Time < Too_Small_Time) - { - printf ("Measured time too small to obtain meaningful results\n"); - printf ("Please increase number of runs\n"); - printf ("\n"); - } - else - { -#if 0 -#ifdef TIME - Microseconds = (float) User_Time * Mic_secs_Per_Second - / (float) Number_Of_Runs; - Dhrystones_Per_Second = (float) Number_Of_Runs / (float) User_Time; -#else - Microseconds = (float) User_Time * Mic_secs_Per_Second - / ((float) HZ * ((float) Number_Of_Runs)); - Dhrystones_Per_Second = ((float) HZ * (float) Number_Of_Runs) - / (float) User_Time; -#endif -#else - Microseconds = ((User_Time / Number_Of_Runs) * Mic_secs_Per_Second) / HZ; - Dhrystones_Per_Second = (HZ * Number_Of_Runs) / User_Time; - - sc_printf("Number_Of_Runs= %ld, HZ= %ld\n", Number_Of_Runs, HZ); - sc_printf("Time: begin= %ld, end= %ld, diff= %ld\n", Begin_Time, End_Time, User_Time); - sc_printf("Microseconds for one run through Dhrystone: %ld\n", Microseconds); - sc_printf("Dhrystones per Second: %ld\n", Dhrystones_Per_Second); - -#endif - } -#endif /* SELF_TIMED */ -} - - -void Proc_1 (REG Rec_Pointer Ptr_Val_Par) - /* executed once */ -{ - REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp; - /* == Ptr_Glob_Next */ - /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp, */ - /* corresponds to "rename" in Ada, "with" in Pascal */ - - structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob); - Ptr_Val_Par->variant.var_1.Int_Comp = 5; - Next_Record->variant.var_1.Int_Comp - = Ptr_Val_Par->variant.var_1.Int_Comp; - Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp; - Proc_3 (&Next_Record->Ptr_Comp); - /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp - == Ptr_Glob->Ptr_Comp */ - if (Next_Record->Discr == Ident_1) - /* then, executed */ - { - Next_Record->variant.var_1.Int_Comp = 6; - Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, - &Next_Record->variant.var_1.Enum_Comp); - Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp; - Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, - &Next_Record->variant.var_1.Int_Comp); - } - else /* not executed */ - structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp); -} /* Proc_1 */ - - -void Proc_2 (One_Fifty *Int_Par_Ref) - /* executed once */ - /* *Int_Par_Ref == 1, becomes 4 */ -{ - One_Fifty Int_Loc; - Enumeration Enum_Loc; - - Enum_Loc = 0; - - Int_Loc = *Int_Par_Ref + 10; - do /* executed once */ - if (Ch_1_Glob == 'A') - /* then, executed */ - { - Int_Loc -= 1; - *Int_Par_Ref = Int_Loc - Int_Glob; - Enum_Loc = Ident_1; - } /* if */ - while (Enum_Loc != Ident_1); /* true */ -} /* Proc_2 */ - - -void Proc_3 (Rec_Pointer *Ptr_Ref_Par) - /* executed once */ - /* Ptr_Ref_Par becomes Ptr_Glob */ -{ - if (Ptr_Glob != Null) - /* then, executed */ - *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp; - Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp); -} /* Proc_3 */ - - -void Proc_4 (void) /* without parameters */ - /* executed once */ -{ - Boolean Bool_Loc; - - Bool_Loc = Ch_1_Glob == 'A'; - Bool_Glob = Bool_Loc | Bool_Glob; - Ch_2_Glob = 'B'; -} /* Proc_4 */ - -void Proc_5 (void) /* without parameters */ -/*******/ - /* executed once */ -{ - Ch_1_Glob = 'A'; - Bool_Glob = false; -} /* Proc_5 */ - - - /* Procedure for the assignment of structures, */ - /* if the C compiler doesn't support this feature */ -#ifdef NOSTRUCTASSIGN -memcpy (d, s, l) -register char *d; -register char *s; -register int l; -{ - while (l--) *d++ = *s++; -} -#endif
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry_2.c b/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry_2.c deleted file mode 100644 index 140161f..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/benchmarks/dhrystone21/dhry_2.c +++ /dev/null
@@ -1,209 +0,0 @@ -/***************************************************************************** - * The BYTE UNIX Benchmarks - Release 3 - * Module: dhry_2.c SID: 3.4 5/15/91 19:30:22 - * - ***************************************************************************** - * Bug reports, patches, comments, suggestions should be sent to: - * - * Ben Smith, Rick Grehan or Tom Yager - * ben@bytepb.byte.com rick_g@bytepb.byte.com tyager@bytepb.byte.com - * - ***************************************************************************** - * Modification Log: - * 10/22/97 - code cleanup to remove ANSI C compiler warnings - * Andy Kahn <kahn@zk3.dec.com> - * - * Adapted from: - * - * "DHRYSTONE" Benchmark Program - * ----------------------------- - * - * **** WARNING **** See warning in n.dhry_1.c - * - * Version: C, Version 2.1 - * - * File: dhry_2.c (part 3 of 3) - * - * Date: May 25, 1988 - * - * Author: Reinhold P. Weicker - * - ****************************************************************************/ -/* SCCSid is defined in dhry_1.c */ - -#include <string.h> -#include "dhry.h" - -#ifndef REG -#define REG - /* REG becomes defined as empty */ - /* i.e. no register variables */ -#endif - -extern int Int_Glob; -extern char Ch_1_Glob; - -void Proc_6(Enumeration, Enumeration *); -void Proc_7(One_Fifty, One_Fifty, One_Fifty *); -void Proc_8(Arr_1_Dim, Arr_2_Dim, int, int); -Enumeration Func_1(Capital_Letter, Capital_Letter); -Boolean Func_2(Str_30, Str_30); -Boolean Func_3(Enumeration); - -void Proc_6 (Enumeration Enum_Val_Par, Enumeration *Enum_Ref_Par) - /* executed once */ - /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */ -{ - *Enum_Ref_Par = Enum_Val_Par; - if (! Func_3 (Enum_Val_Par)) - /* then, not executed */ - *Enum_Ref_Par = Ident_4; - switch (Enum_Val_Par) - { - case Ident_1: - *Enum_Ref_Par = Ident_1; - break; - case Ident_2: - if (Int_Glob > 100) - /* then */ - *Enum_Ref_Par = Ident_1; - else *Enum_Ref_Par = Ident_4; - break; - case Ident_3: /* executed */ - *Enum_Ref_Par = Ident_2; - break; - case Ident_4: break; - case Ident_5: - *Enum_Ref_Par = Ident_3; - break; - } /* switch */ -} /* Proc_6 */ - -void Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref) -One_Fifty Int_1_Par_Val; -One_Fifty Int_2_Par_Val; -One_Fifty *Int_Par_Ref; -/**********************************************/ - /* executed three times */ - /* first call: Int_1_Par_Val == 2, Int_2_Par_Val == 3, */ - /* Int_Par_Ref becomes 7 */ - /* second call: Int_1_Par_Val == 10, Int_2_Par_Val == 5, */ - /* Int_Par_Ref becomes 17 */ - /* third call: Int_1_Par_Val == 6, Int_2_Par_Val == 10, */ - /* Int_Par_Ref becomes 18 */ -{ - One_Fifty Int_Loc; - - Int_Loc = Int_1_Par_Val + 2; - *Int_Par_Ref = Int_2_Par_Val + Int_Loc; -} /* Proc_7 */ - - -void Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val) -/*********************************************************************/ - /* executed once */ - /* Int_Par_Val_1 == 3 */ - /* Int_Par_Val_2 == 7 */ -Arr_1_Dim Arr_1_Par_Ref; -Arr_2_Dim Arr_2_Par_Ref; -int Int_1_Par_Val; -int Int_2_Par_Val; -{ - REG One_Fifty Int_Index; - REG One_Fifty Int_Loc; - - Int_Loc = Int_1_Par_Val + 5; - Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val; - Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc]; - Arr_1_Par_Ref [Int_Loc+30] = Int_Loc; - for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index) - Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc; - Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1; - Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc]; - Int_Glob = 5; -} /* Proc_8 */ - - -Enumeration Func_1 (Capital_Letter Ch_1_Par_Val, Capital_Letter Ch_2_Par_Val) -/*************************************************/ - /* executed three times */ - /* first call: Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R' */ - /* second call: Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C' */ - /* third call: Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C' */ -{ - Capital_Letter Ch_1_Loc; - Capital_Letter Ch_2_Loc; - - Ch_1_Loc = Ch_1_Par_Val; - Ch_2_Loc = Ch_1_Loc; - if (Ch_2_Loc != Ch_2_Par_Val) - /* then, executed */ - return (Ident_1); - else /* not executed */ - { - Ch_1_Glob = Ch_1_Loc; - return (Ident_2); - } -} /* Func_1 */ - - - -Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref) -/*************************************************/ - /* executed once */ - /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */ - /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */ - -Str_30 Str_1_Par_Ref; -Str_30 Str_2_Par_Ref; -{ - REG One_Thirty Int_Loc; - Capital_Letter Ch_Loc; - - Ch_Loc = 'A'; - Int_Loc = 2; - while (Int_Loc <= 2) /* loop body executed once */ - if (Func_1 (Str_1_Par_Ref[Int_Loc], - Str_2_Par_Ref[Int_Loc+1]) == Ident_1) - /* then, executed */ - { - Ch_Loc = 'A'; - Int_Loc += 1; - } /* if, while */ - if (Ch_Loc >= 'W' && Ch_Loc < 'Z') - /* then, not executed */ - Int_Loc = 7; - if (Ch_Loc == 'R') - /* then, not executed */ - return (true); - else /* executed */ - { - if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0) - /* then, not executed */ - { - Int_Loc += 7; - Int_Glob = Int_Loc; - return (true); - } - else /* executed */ - return (false); - } /* if Ch_Loc */ -} /* Func_2 */ - - -Boolean Func_3 (Enum_Par_Val) -/***************************/ - /* executed once */ - /* Enum_Par_Val == Ident_3 */ -Enumeration Enum_Par_Val; -{ - Enumeration Enum_Loc; - - Enum_Loc = Enum_Par_Val; - if (Enum_Loc == Ident_3) - /* then, executed */ - return (true); - else /* not executed */ - return (false); -} /* Func_3 */ -
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/LICENSE b/verilog/rtl/syntacore/scr1/sim/tests/common/LICENSE deleted file mode 100644 index 48fe522..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/LICENSE +++ /dev/null
@@ -1,24 +0,0 @@ -Copyright (c) 2012-2015, The Regents of the University of California (Regents). -All Rights Reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: -1. Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. -2. Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. -3. Neither the name of the Regents nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - -IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, -SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING -OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS -BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED -HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE -MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk b/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk deleted file mode 100644 index 6075f73..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk +++ /dev/null
@@ -1,66 +0,0 @@ -# ////////////////////////////////////////////////////////////////////////////// -# // SPDX-FileCopyrightText: 2021, Dinesh Annayya -# // -# // Licensed under the Apache License, Version 2.0 (the "License"); -# // you may not use this file except in compliance with the License. -# // You may obtain a copy of the License at -# // -# // http://www.apache.org/licenses/LICENSE-2.0 -# // -# // Unless required by applicable law or agreed to in writing, software -# // distributed under the License is distributed on an "AS IS" BASIS, -# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# // See the License for the specific language governing permissions and -# // limitations under the License. -# // SPDX-License-Identifier: Apache-2.0 -# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> -# // ////////////////////////////////////////////////////////////////////////// - -ADD_ASM_MACRO ?= -D__ASSEMBLY__=1 - -FLAGS = -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las $(ADD_FLAGS) -FLAGS_STR = "$(FLAGS)" - -CFLAGS_COMMON = -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=$(TCM) -CFLAGS_ARCH = -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=$(ABI) - -CFLAGS := $(FLAGS) $(EXT_CFLAGS) \ -$(CFLAGS_COMMON) \ -$(CFLAGS_ARCH) \ --DFLAGS_STR=\"$(FLAGS_STR)\" \ -$(ADD_CFLAGS) - -LDFLAGS ?= -nostartfiles -nostdlib -lc -lgcc -march=rv32$(ARCH) -mabi=$(ABI) - -ifeq (,$(findstring 0,$(TCM))) -ld_script ?= $(inc_dir)/link_tcm.ld -asm_src ?= crt_tcm.S -else -ld_script ?= $(inc_dir)/link.ld -asm_src ?= crt.S -endif - -VPATH += $(src_dir) $(inc_dir) $(ADD_VPATH) -incs += -I$(src_dir) -I$(inc_dir) $(ADD_incs) - -c_objs := $(addprefix $(bld_dir)/,$(patsubst %.c, %.o, $(c_src))) -asm_objs := $(addprefix $(bld_dir)/,$(patsubst %.S, %.o, $(asm_src))) - -$(bld_dir)/%.o: %.S - $(RISCV_GCC) $(CFLAGS) $(ADD_ASM_MACRO) -c $(incs) $< -o $@ - -$(bld_dir)/%.o: %.c - $(RISCV_GCC) $(CFLAGS) -c $(incs) $< -o $@ - -$(bld_dir)/%.elf: $(ld_script) $(c_objs) $(asm_objs) - $(RISCV_GCC) -o $@ -T $^ $(LDFLAGS) - -$(bld_dir)/%.hex: $(bld_dir)/%.elf - $(RISCV_ROM_OBJCOPY) $^ $@ - $(RISCV_RAM_OBJCOPY) $^ $@.ram - #assign 0x0048_0xxx to 0x0000_0xxx to map to TCM Memory - sed -i 's/@00480/@00000/g' $@.ram - - -$(bld_dir)/%.dump: $(bld_dir)/%.elf - $(RISCV_OBJDUMP) $^ > $@
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/crt.S b/verilog/rtl/syntacore/scr1/sim/tests/common/crt.S deleted file mode 100644 index 6b18c76..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/crt.S +++ /dev/null
@@ -1,162 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Syntacore LLC -// ////////////////////////////////////////////////////////////////////////// -/// @file <crt.S> -/// - -#include "riscv_csr_encoding.h" -#include "sc_test.h" - -# define LREG lw -# define SREG sw -# define REGBYTES 4 - - .globl _start - .globl main - .globl trap_entry - .globl handle_trap - .globl sc_exit - .weak trap_entry, handle_trap - - .text - .org (64*3) - .balign 64 -machine_trap_entry: - j trap_entry - - .balign 64 - -_start: -#ifndef __RVE_EXT - zero_int_regs 1, 31 -#else - zero_int_regs 1, 15 -#endif - # Global pointer init - .option push - .option norelax - la gp, __global_pointer$ - .option pop - # clear bss - la a1, __BSS_START__ - la a2, __BSS_END__ - j 4f -3: sw zero, 0(a1) - add a1, a1, 4 -4: bne a1, a2, 3b - la sp, __C_STACK_TOP__ - - // Timer init - li t0, mtime_ctrl - li t1, (1 << SCR1_MTIME_CTRL_EN) // enable, use internal clock - sw t1, (t0) - li t0, mtime_div - li t1, (100-1) // divide by 100 - sw t1, (t0) - li t0, mtimecmp - li t1, -1 - sw t1, (t0) // max value for mtimecmp - sw t1, 4(t0) - - li a0, 0 - li a1, 0 - jal main - j sc_exit - -trap_entry: - addi sp, sp, -272 - - SREG x1, 1*REGBYTES(sp) - SREG x2, 2*REGBYTES(sp) - SREG x3, 3*REGBYTES(sp) - SREG x4, 4*REGBYTES(sp) - SREG x5, 5*REGBYTES(sp) - SREG x6, 6*REGBYTES(sp) - SREG x7, 7*REGBYTES(sp) - SREG x8, 8*REGBYTES(sp) - SREG x9, 9*REGBYTES(sp) - SREG x10, 10*REGBYTES(sp) - SREG x11, 11*REGBYTES(sp) - SREG x12, 12*REGBYTES(sp) - SREG x13, 13*REGBYTES(sp) - SREG x14, 14*REGBYTES(sp) - SREG x15, 15*REGBYTES(sp) -#ifndef __RVE_EXT - SREG x16, 16*REGBYTES(sp) - SREG x17, 17*REGBYTES(sp) - SREG x18, 18*REGBYTES(sp) - SREG x19, 19*REGBYTES(sp) - SREG x20, 20*REGBYTES(sp) - SREG x21, 21*REGBYTES(sp) - SREG x22, 22*REGBYTES(sp) - SREG x23, 23*REGBYTES(sp) - SREG x24, 24*REGBYTES(sp) - SREG x25, 25*REGBYTES(sp) - SREG x26, 26*REGBYTES(sp) - SREG x27, 27*REGBYTES(sp) - SREG x28, 28*REGBYTES(sp) - SREG x29, 29*REGBYTES(sp) - SREG x30, 30*REGBYTES(sp) - SREG x31, 31*REGBYTES(sp) -#endif // __RVE_EXT - - csrr a0, mcause - csrr a1, mepc - mv a2, sp - jal handle_trap - - LREG x1, 1*REGBYTES(sp) - LREG x2, 2*REGBYTES(sp) - LREG x3, 3*REGBYTES(sp) - LREG x4, 4*REGBYTES(sp) - LREG x5, 5*REGBYTES(sp) - LREG x6, 6*REGBYTES(sp) - LREG x7, 7*REGBYTES(sp) - LREG x8, 8*REGBYTES(sp) - LREG x9, 9*REGBYTES(sp) - LREG x10, 10*REGBYTES(sp) - LREG x11, 11*REGBYTES(sp) - LREG x12, 12*REGBYTES(sp) - LREG x13, 13*REGBYTES(sp) - LREG x14, 14*REGBYTES(sp) - LREG x15, 15*REGBYTES(sp) -#ifndef __RVE_EXT - LREG x16, 16*REGBYTES(sp) - LREG x17, 17*REGBYTES(sp) - LREG x18, 18*REGBYTES(sp) - LREG x19, 19*REGBYTES(sp) - LREG x20, 20*REGBYTES(sp) - LREG x21, 21*REGBYTES(sp) - LREG x22, 22*REGBYTES(sp) - LREG x23, 23*REGBYTES(sp) - LREG x24, 24*REGBYTES(sp) - LREG x25, 25*REGBYTES(sp) - LREG x26, 26*REGBYTES(sp) - LREG x27, 27*REGBYTES(sp) - LREG x28, 28*REGBYTES(sp) - LREG x29, 29*REGBYTES(sp) - LREG x30, 30*REGBYTES(sp) - LREG x31, 31*REGBYTES(sp) -#endif // __RVE_EXT - - addi sp, sp, 272 - mret - -handle_trap: - j SIM_EXIT - -// end of crt.S
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/crt_tcm.S b/verilog/rtl/syntacore/scr1/sim/tests/common/crt_tcm.S deleted file mode 100644 index 5f2eba4..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/crt_tcm.S +++ /dev/null
@@ -1,173 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Syntacore LLC -// ////////////////////////////////////////////////////////////////////////// -/// @file <crt_tcm.S> -/// - -#include "riscv_csr_encoding.h" -#include "reloc.h" -#include "sc_test.h" - -# define LREG lw -# define SREG sw -# define REGBYTES 4 - - .globl _start - .globl main - .globl trap_entry - .globl handle_trap - .globl sc_exit - .weak trap_entry, handle_trap - - .section .text.init - .org (64*3) - .align 6; -machine_trap_entry: - j trap_entry - - .align 6 -_start: -#ifndef __RVE_EXT - zero_int_regs 1, 31 -#else - zero_int_regs 1, 15 -#endif - # Global pointer init - .option push - .option norelax - la gp, __global_pointer$ - .option pop - - RELOC_PROC; - - // init tdata - mv a1, tp - la a2, _tdata_end - j 6f -5: lw a3, 0(a0) - sw a3, 0(a1) - add a0, a0, 4 - add a1, a1, 4 -6: bne a0, a2, 5b - // clear tbss - j 8f -7: sw zero, 0(a1) - add a1, a1, 4 -8: bne a1, a4, 7b - - // Timer init - li t0, mtime_ctrl - li t1, (1 << SCR1_MTIME_CTRL_EN) // enable, use internal clock - sw t1, (t0) - li t0, mtime_div - li t1, (100-1) // divide by 100 - sw t1, (t0) - li t0, mtimecmp - li t1, -1 - sw t1, (t0) // max value for mtimecmp - sw t1, 4(t0) - - li a0, 0 - li a1, 0 -9: auipc t0, %pcrel_hi(main) - jalr t0, %pcrel_lo(9b) - la t0, sc_exit - //j sc_exit - -trap_entry: - addi sp, sp, -272 - - SREG x1, 1*REGBYTES(sp) - SREG x2, 2*REGBYTES(sp) - SREG x3, 3*REGBYTES(sp) - SREG x4, 4*REGBYTES(sp) - SREG x5, 5*REGBYTES(sp) - SREG x6, 6*REGBYTES(sp) - SREG x7, 7*REGBYTES(sp) - SREG x8, 8*REGBYTES(sp) - SREG x9, 9*REGBYTES(sp) - SREG x10, 10*REGBYTES(sp) - SREG x11, 11*REGBYTES(sp) - SREG x12, 12*REGBYTES(sp) - SREG x13, 13*REGBYTES(sp) - SREG x14, 14*REGBYTES(sp) - SREG x15, 15*REGBYTES(sp) -#ifndef __RVE_EXT - SREG x16, 16*REGBYTES(sp) - SREG x17, 17*REGBYTES(sp) - SREG x18, 18*REGBYTES(sp) - SREG x19, 19*REGBYTES(sp) - SREG x20, 20*REGBYTES(sp) - SREG x21, 21*REGBYTES(sp) - SREG x22, 22*REGBYTES(sp) - SREG x23, 23*REGBYTES(sp) - SREG x24, 24*REGBYTES(sp) - SREG x25, 25*REGBYTES(sp) - SREG x26, 26*REGBYTES(sp) - SREG x27, 27*REGBYTES(sp) - SREG x28, 28*REGBYTES(sp) - SREG x29, 29*REGBYTES(sp) - SREG x30, 30*REGBYTES(sp) - SREG x31, 31*REGBYTES(sp) -#endif // __RVE_EXT - - csrr a0, mcause - csrr a1, mepc - mv a2, sp - jal handle_trap - - LREG x1, 1*REGBYTES(sp) - LREG x2, 2*REGBYTES(sp) - LREG x3, 3*REGBYTES(sp) - LREG x4, 4*REGBYTES(sp) - LREG x5, 5*REGBYTES(sp) - LREG x6, 6*REGBYTES(sp) - LREG x7, 7*REGBYTES(sp) - LREG x8, 8*REGBYTES(sp) - LREG x9, 9*REGBYTES(sp) - LREG x10, 10*REGBYTES(sp) - LREG x11, 11*REGBYTES(sp) - LREG x12, 12*REGBYTES(sp) - LREG x13, 13*REGBYTES(sp) - LREG x14, 14*REGBYTES(sp) - LREG x15, 15*REGBYTES(sp) -#ifndef __RVE_EXT - LREG x16, 16*REGBYTES(sp) - LREG x17, 17*REGBYTES(sp) - LREG x18, 18*REGBYTES(sp) - LREG x19, 19*REGBYTES(sp) - LREG x20, 20*REGBYTES(sp) - LREG x21, 21*REGBYTES(sp) - LREG x22, 22*REGBYTES(sp) - LREG x23, 23*REGBYTES(sp) - LREG x24, 24*REGBYTES(sp) - LREG x25, 25*REGBYTES(sp) - LREG x26, 26*REGBYTES(sp) - LREG x27, 27*REGBYTES(sp) - LREG x28, 28*REGBYTES(sp) - LREG x29, 29*REGBYTES(sp) - LREG x30, 30*REGBYTES(sp) - LREG x31, 31*REGBYTES(sp) -#endif // __RVE_EXT - - addi sp, sp, 272 - mret - -handle_trap: - j SIM_EXIT - -// end of crt.S
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/csr.h b/verilog/rtl/syntacore/scr1/sim/tests/common/csr.h deleted file mode 100644 index 669dac5..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/csr.h +++ /dev/null
@@ -1,129 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Syntacore LLC -// ////////////////////////////////////////////////////////////////////////// -/// @file <csr.h> -/// Architecture specific CSR's defs and inlines - -#ifndef SCR_CSR_H -#define SCR_CSR_H - -#include <stdint.h> -#include <stdbool.h> - -#define __xstringify(s) __stringify(s) -#define __stringify(s) #s - -#ifdef read_csr -#undef read_csr -#endif - -#ifdef write_csr -#undef write_csr -#endif - -#ifdef swap_csr -#undef swap_csr -#endif - -#ifdef set_csr -#undef set_csr -#endif - -#ifdef clear_csr -#undef clear_csr -#endif - -#ifdef rdtime -#undef rdtime -#endif - -#ifdef rdcycle -#undef rdcycle -#endif - -#ifdef rdinstret -#undef rdinstret -#endif - -#define read_csr(reg) \ - ({ \ - unsigned long __tmp; \ - asm volatile ("csrr %0, " __xstringify(reg) : "=r"(__tmp)); \ - __tmp; \ - }) - -#define write_csr(reg, val) \ - do { \ - if (__builtin_constant_p(val) && (val) == 0) \ - asm volatile ("csrw " __xstringify(reg) ", zero" ::); \ - else if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrw " __xstringify(reg) ", %0" :: "i"(val)); \ - else \ - asm volatile ("csrw " __xstringify(reg) ", %0" :: "r"(val)); \ - } while (0) - -#define swap_csr(reg, val) \ - ({ \ - unsigned long __tmp; \ - if (__builtin_constant_p(val) && (val) == 0) \ - asm volatile ("csrrw %0, " __xstringify(reg) ", zero" : "=r"(__tmp) :); \ - else if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrrw %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(val)); \ - else \ - asm volatile ("csrrw %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(val)); \ - __tmp; \ - }) - -#define set_csr(reg, bit) \ - ({ \ - unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (bit) < 32) \ - asm volatile ("csrrs %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrs %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; \ - }) - -#define clear_csr(reg, bit) \ - ({ \ - unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (bit) < 32) \ - asm volatile ("csrrc %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrc %0, " __xstringify(reg) ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; \ - }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) - -static inline unsigned long __attribute__((const)) cpuid() -{ - unsigned long res; - asm ("csrr %0, mcpuid" : "=r"(res)); - return res; -} - -static inline unsigned long __attribute__((const)) impid() -{ - unsigned long res; - asm ("csrr %0, mimpid" : "=r"(res)); - return res; -} - -#endif // SCR_CSR_H
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld b/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld deleted file mode 100644 index 92f3893..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld +++ /dev/null
@@ -1,120 +0,0 @@ -/* -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Syntacore LLC -// ////////////////////////////////////////////////////////////////////////// -**/ -/* -* Copyright by Syntacore LLC © 2016, 2017. See LICENSE for details -* @file <link.ld> -* @brief bare metal tests' linker script -*/ - -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -MEMORY { - ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K - TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 4K - RAM (rwx) : ORIGIN = 0x10030000, LENGTH = 8K -} - -STACK_SIZE = 1024; - -CL_SIZE = 32; - -SECTIONS { - - /* code segment */ - .text.init 0 : { - FILL(0); - . = 0x100 - 12; - SIM_EXIT = .; - LONG(0x13); - SIM_STOP = .; - LONG(0x6F); - LONG(-1); - . = 0x100; - PROVIDE(__TEXT_START__ = .); - *(.text.init) - } >ROM - - .text : { - *crt.o(.text .text.*) - *(.text .text.*) - *(sc_test_section) - . = ALIGN(CL_SIZE); - PROVIDE(__TEXT_END__ = .); - } >ROM - - /* data segment */ - .data : { - *(.data .data.*) - . = ALIGN(CL_SIZE); - } >TCM - - .sdata : { - __global_pointer$ = . + 0x800; - *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) - *(.sdata .sdata.* .gnu.linkonce.s.*) - . = ALIGN(CL_SIZE); - } >TCM - - /* thread-local data segment */ - .tdata : { - PROVIDE(_tls_data = .); - PROVIDE(_tdata_begin = .); - *(.tdata .tdata.*) - PROVIDE(_tdata_end = .); - . = ALIGN(CL_SIZE); - } >TCM - - .tbss : { - PROVIDE(__BSS_START__ = .); - *(.tbss .tbss.*) - . = ALIGN(CL_SIZE); - PROVIDE(_tbss_end = .); - } >TCM - - /* bss segment */ - .sbss : { - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - } >RAM - - .bss : { - *(.bss .bss.*) - . = ALIGN(CL_SIZE); - PROVIDE(__BSS_END__ = .); - } >RAM - - _end = .; - PROVIDE(__end = .); - - /* End of uninitalized data segement */ - - .stack ORIGIN(TCM) + LENGTH(TCM) - STACK_SIZE : { - FILL(0); - PROVIDE(__STACK_START__ = .); - . += STACK_SIZE; - PROVIDE(__C_STACK_TOP__ = .); - PROVIDE(__STACK_END__ = .); - } >TCM - - /DISCARD/ : { - *(.eh_frame .eh_frame.*) - } -}
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld b/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld deleted file mode 100644 index 3840ec3..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld +++ /dev/null
@@ -1,132 +0,0 @@ -/* -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Syntacore LLC -// ////////////////////////////////////////////////////////////////////////// -*/ -/* -* @file <link.ld> -* @brief bare metal tests' linker script -*/ - -OUTPUT_ARCH( "riscv" ) -ENTRY(_start) - -MEMORY { - ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K - TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 4K -} - -STACK_SIZE = 256; - -CL_SIZE = 32; - -SECTIONS { - - /* code segment */ - .text.init ORIGIN(ROM) : { - FILL(0); - . = 0x100 - 12; - SIM_EXIT = .; - LONG(0x13); - SIM_STOP = .; - LONG(0x6F); - LONG(-1); - . = 0x100; - *crt_tcm.o(.text .text.*) - *(.text.init) - . = ALIGN(CL_SIZE); - } >ROM - - __reloc_start = .; - - .text : { - PROVIDE(__TEXT_START__ = .); - *(.text .text.*) - *(sc_test_section) - . = ALIGN(CL_SIZE); - PROVIDE(__TEXT_END__ = .); - } >TCM AT>ROM - - - .rodata ALIGN(CL_SIZE) : { - __global_pointer$ = . + 0x800; - *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) - . = ALIGN(CL_SIZE); - LONG(0x13); - . = ALIGN(CL_SIZE); - } >TCM AT>ROM - - - /* data segment */ - .data ALIGN(CL_SIZE) : { - PROVIDE(__DATA_START__ = .); - *(.data .data.*) - . = ALIGN(CL_SIZE); - } >TCM - - .sdata ALIGN(CL_SIZE) : { - *(.sdata .sdata.* .gnu.linkonce.s.*) - . = ALIGN(CL_SIZE); - PROVIDE(__DATA_END__ = .); - } >TCM - - /* thread-local data segment */ - .tdata ALIGN(CL_SIZE) : { - PROVIDE(_tls_data = .); - PROVIDE(_tdata_begin = .); - *(.tdata .tdata.*) - PROVIDE(_tdata_end = .); - . = ALIGN(CL_SIZE); - } >TCM - - .tbss ALIGN(CL_SIZE) : { - PROVIDE(_tbss_begin = .); - *(.tbss .tbss.*) - . = ALIGN(CL_SIZE); - PROVIDE(_tbss_end = .); - } >TCM - - /* bss segment */ - .sbss ALIGN(CL_SIZE) : { - PROVIDE(__BSS_START__ = .); - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - . = ALIGN(CL_SIZE); - } >TCM - - .bss ALIGN(CL_SIZE) : { - *(.dynbss) *(.bss .bss.* .gnu.linkonce.b.*) *(COMMON) - . = ALIGN(CL_SIZE); - PROVIDE(__BSS_END__ = .); - } >TCM - - _end = .; - PROVIDE(__end = .); - - /* End of uninitalized data segement */ - - .stack ORIGIN(TCM) + LENGTH(TCM) - STACK_SIZE : { - PROVIDE(__STACK_START__ = .); - . += STACK_SIZE; - PROVIDE(__C_STACK_TOP__ = .); - PROVIDE(__STACK_END__ = .); - } >TCM - - /DISCARD/ : { - *(.eh_frame .eh_frame.*) - } -}
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/reloc.h b/verilog/rtl/syntacore/scr1/sim/tests/common/reloc.h deleted file mode 100644 index 67dba7a..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/reloc.h +++ /dev/null
@@ -1,56 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Syntacore LLC -// ////////////////////////////////////////////////////////////////////////// - - -#ifndef RELOC_H -#define RELOC_H - -#if (TCM == 1) -#define RELOC_PROC \ - la a0, __reloc_start; \ - la a1, __TEXT_START__; \ - la a2, __DATA_END__; \ - beq a0, a1, 21f; \ - j 2f; \ -1: lw a3, 0(a0); \ - sw a3, 0(a1); \ - add a0, a0, 4; \ - add a1, a1, 4; \ -2: bne a1, a2, 1b; \ - /* clear bss */ \ - la a2, __BSS_START__; \ -21: la a1, __BSS_END__; \ - j 4f; \ -3: sw zero, 0(a2); \ - add a2, a2, 4; \ -4: bne a1, a2, 3b; \ - /* init stack */ \ - la sp, __C_STACK_TOP__; \ - /* init hart0 TLS */ \ - la a0, _tdata_begin; \ - la a2, _tbss_end; \ - sub a1, a2, a0; \ - la a4, __STACK_START__; \ - sub tp, a4, a1; -#else // #if TCM - -#define RELOC_PROC - -#endif // #else #if TCM - -#endif //
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_csr_encoding.h b/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_csr_encoding.h deleted file mode 100644 index 19d3805..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_csr_encoding.h +++ /dev/null
@@ -1,1490 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Syntacore LLC -// ////////////////////////////////////////////////////////////////////////// -// See LICENSE for license details. - -#ifndef RISCV_CSR_ENCODING_H -#define RISCV_CSR_ENCODING_H - -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_HPIE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_HPP 0x00000600 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_SUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_TVM 0x00100000 -#define MSTATUS_TW 0x00200000 -#define MSTATUS_TSR 0x00400000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS_UXL 0x0000000300000000 -#define MSTATUS_SXL 0x0000000C00000000 -#define MSTATUS64_SD 0x8000000000000000 - -#define SSTATUS_UIE 0x00000001 -#define SSTATUS_SIE 0x00000002 -#define SSTATUS_UPIE 0x00000010 -#define SSTATUS_SPIE 0x00000020 -#define SSTATUS_SPP 0x00000100 -#define SSTATUS_FS 0x00006000 -#define SSTATUS_XS 0x00018000 -#define SSTATUS_SUM 0x00040000 -#define SSTATUS_MXR 0x00080000 -#define SSTATUS32_SD 0x80000000 -#define SSTATUS_UXL 0x0000000300000000 -#define SSTATUS64_SD 0x8000000000000000 - -#define DCSR_XDEBUGVER (3U<<30) -#define DCSR_NDRESET (1<<29) -#define DCSR_FULLRESET (1<<28) -#define DCSR_EBREAKM (1<<15) -#define DCSR_EBREAKH (1<<14) -#define DCSR_EBREAKS (1<<13) -#define DCSR_EBREAKU (1<<12) -#define DCSR_STOPCYCLE (1<<10) -#define DCSR_STOPTIME (1<<9) -#define DCSR_CAUSE (7<<6) -#define DCSR_DEBUGINT (1<<5) -#define DCSR_HALT (1<<3) -#define DCSR_STEP (1<<2) -#define DCSR_PRV (3<<0) - -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 -#define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 - -#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) - -#define MCONTROL_SELECT (1<<19) -#define MCONTROL_TIMING (1<<18) -#define MCONTROL_ACTION (0x3f<<12) -#define MCONTROL_CHAIN (1<<11) -#define MCONTROL_MATCH (0xf<<7) -#define MCONTROL_M (1<<6) -#define MCONTROL_H (1<<5) -#define MCONTROL_S (1<<4) -#define MCONTROL_U (1<<3) -#define MCONTROL_EXECUTE (1<<2) -#define MCONTROL_STORE (1<<1) -#define MCONTROL_LOAD (1<<0) - -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 - -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 - -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 -#define MCONTROL_MATCH_MASK_HIGH 5 - -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_HSIP (1 << IRQ_H_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_HTIP (1 << IRQ_H_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_HEIP (1 << IRQ_H_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) - -#define SIP_SSIP MIP_SSIP -#define SIP_STIP MIP_STIP - -#define PRV_U 0 -#define PRV_S 1 -#define PRV_H 2 -#define PRV_M 3 - -#define SPTBR32_MODE 0x80000000 -#define SPTBR32_ASID 0x7FC00000 -#define SPTBR32_PPN 0x003FFFFF -#define SPTBR64_MODE 0xF000000000000000 -#define SPTBR64_ASID 0x0FFFF00000000000 -#define SPTBR64_PPN 0x00000FFFFFFFFFFF - -#define SPTBR_MODE_OFF 0 -#define SPTBR_MODE_SV32 1 -#define SPTBR_MODE_SV39 8 -#define SPTBR_MODE_SV48 9 -#define SPTBR_MODE_SV57 10 -#define SPTBR_MODE_SV64 11 - -#define PMP_R 0x01 -#define PMP_W 0x02 -#define PMP_X 0x04 -#define PMP_A 0x18 -#define PMP_L 0x80 -#define PMP_SHIFT 2 - -#define PMP_TOR 0x08 -#define PMP_NA4 0x10 -#define PMP_NAPOT 0x18 - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -#define DEFAULT_RSTVEC 0x00001000 -#define CLINT_BASE 0x02000000 -#define CLINT_SIZE 0x000c0000 -#define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 - -// page table entry (PTE) fields -#define PTE_V 0x001 // Valid -#define PTE_R 0x002 // Read -#define PTE_W 0x004 // Write -#define PTE_X 0x008 // Execute -#define PTE_U 0x010 // User -#define PTE_G 0x020 // Global -#define PTE_A 0x040 // Accessed -#define PTE_D 0x080 // Dirty -#define PTE_SOFT 0x300 // Reserved for Software - -#define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) - -#ifdef __riscv - -#if __riscv_xlen == 64 -# define MSTATUS_SD MSTATUS64_SD -# define SSTATUS_SD SSTATUS64_SD -# define RISCV_PGLEVEL_BITS 9 -# define SPTBR_MODE SPTBR64_MODE -#else -# define MSTATUS_SD MSTATUS32_SD -# define SSTATUS_SD SSTATUS32_SD -# define RISCV_PGLEVEL_BITS 10 -# define SPTBR_MODE SPTBR32_MODE -#endif -#define RISCV_PGSHIFT 12 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#ifdef __GNUC__ - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, val) ({ \ - asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) - -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ - __tmp; }) - -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) - -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ - __tmp; }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) - -#endif - -#endif - -#endif - -#endif -/* Automatically generated by parse-opcodes. */ -#ifndef RISCV_ENCODING_H -#define RISCV_ENCODING_H -#define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f -#define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f -#define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f -#define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f -#define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f -#define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f -#define MATCH_JALR 0x67 -#define MASK_JALR 0x707f -#define MATCH_JAL 0x6f -#define MASK_JAL 0x7f -#define MATCH_LUI 0x37 -#define MASK_LUI 0x7f -#define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f -#define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f -#define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f -#define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f -#define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f -#define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f -#define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f -#define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f -#define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f -#define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f -#define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f -#define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f -#define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f -#define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f -#define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f -#define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f -#define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f -#define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f -#define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f -#define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f -#define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f -#define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f -#define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f -#define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f -#define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f -#define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f -#define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f -#define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f -#define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f -#define MATCH_LB 0x3 -#define MASK_LB 0x707f -#define MATCH_LH 0x1003 -#define MASK_LH 0x707f -#define MATCH_LW 0x2003 -#define MASK_LW 0x707f -#define MATCH_LD 0x3003 -#define MASK_LD 0x707f -#define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f -#define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f -#define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f -#define MATCH_SB 0x23 -#define MASK_SB 0x707f -#define MATCH_SH 0x1023 -#define MASK_SH 0x707f -#define MATCH_SW 0x2023 -#define MASK_SW 0x707f -#define MATCH_SD 0x3023 -#define MASK_SD 0x707f -#define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f -#define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f -#define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f -#define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f -#define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f -#define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f -#define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f -#define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f -#define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f -#define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f -#define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f -#define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f -#define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f -#define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f -#define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f -#define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f -#define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f -#define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f -#define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f -#define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f -#define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f -#define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f -#define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f -#define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f -#define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f -#define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f -#define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f -#define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f -#define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f -#define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f -#define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f -#define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f -#define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f -#define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f -#define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f -#define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f -#define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f -#define MATCH_ECALL 0x73 -#define MASK_ECALL 0xffffffff -#define MATCH_EBREAK 0x100073 -#define MASK_EBREAK 0xffffffff -#define MATCH_URET 0x200073 -#define MASK_URET 0xffffffff -#define MATCH_SRET 0x10200073 -#define MASK_SRET 0xffffffff -#define MATCH_MRET 0x30200073 -#define MASK_MRET 0xffffffff -#define MATCH_DRET 0x7b200073 -#define MASK_DRET 0xffffffff -#define MATCH_SFENCE_VMA 0x12000073 -#define MASK_SFENCE_VMA 0xfe007fff -#define MATCH_WFI 0x10500073 -#define MASK_WFI 0xffffffff -#define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f -#define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f -#define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f -#define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f -#define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f -#define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f -#define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f -#define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f -#define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f -#define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f -#define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f -#define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f -#define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f -#define MATCH_FMIN_S 0x28000053 -#define MASK_FMIN_S 0xfe00707f -#define MATCH_FMAX_S 0x28001053 -#define MASK_FMAX_S 0xfe00707f -#define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f -#define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f -#define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f -#define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f -#define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f -#define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f -#define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f -#define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f -#define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f -#define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f -#define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f -#define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f -#define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f -#define MATCH_FADD_Q 0x6000053 -#define MASK_FADD_Q 0xfe00007f -#define MATCH_FSUB_Q 0xe000053 -#define MASK_FSUB_Q 0xfe00007f -#define MATCH_FMUL_Q 0x16000053 -#define MASK_FMUL_Q 0xfe00007f -#define MATCH_FDIV_Q 0x1e000053 -#define MASK_FDIV_Q 0xfe00007f -#define MATCH_FSGNJ_Q 0x26000053 -#define MASK_FSGNJ_Q 0xfe00707f -#define MATCH_FSGNJN_Q 0x26001053 -#define MASK_FSGNJN_Q 0xfe00707f -#define MATCH_FSGNJX_Q 0x26002053 -#define MASK_FSGNJX_Q 0xfe00707f -#define MATCH_FMIN_Q 0x2e000053 -#define MASK_FMIN_Q 0xfe00707f -#define MATCH_FMAX_Q 0x2e001053 -#define MASK_FMAX_Q 0xfe00707f -#define MATCH_FCVT_S_Q 0x40300053 -#define MASK_FCVT_S_Q 0xfff0007f -#define MATCH_FCVT_Q_S 0x46000053 -#define MASK_FCVT_Q_S 0xfff0007f -#define MATCH_FCVT_D_Q 0x42300053 -#define MASK_FCVT_D_Q 0xfff0007f -#define MATCH_FCVT_Q_D 0x46100053 -#define MASK_FCVT_Q_D 0xfff0007f -#define MATCH_FSQRT_Q 0x5e000053 -#define MASK_FSQRT_Q 0xfff0007f -#define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f -#define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f -#define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f -#define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f -#define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f -#define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f -#define MATCH_FLE_Q 0xa6000053 -#define MASK_FLE_Q 0xfe00707f -#define MATCH_FLT_Q 0xa6001053 -#define MASK_FLT_Q 0xfe00707f -#define MATCH_FEQ_Q 0xa6002053 -#define MASK_FEQ_Q 0xfe00707f -#define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f -#define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f -#define MATCH_FCVT_L_S 0xc0200053 -#define MASK_FCVT_L_S 0xfff0007f -#define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FMV_X_W 0xe0000053 -#define MASK_FMV_X_W 0xfff0707f -#define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f -#define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f -#define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f -#define MATCH_FCVT_L_D 0xc2200053 -#define MASK_FCVT_L_D 0xfff0007f -#define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f -#define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f -#define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f -#define MATCH_FCVT_W_Q 0xc6000053 -#define MASK_FCVT_W_Q 0xfff0007f -#define MATCH_FCVT_WU_Q 0xc6100053 -#define MASK_FCVT_WU_Q 0xfff0007f -#define MATCH_FCVT_L_Q 0xc6200053 -#define MASK_FCVT_L_Q 0xfff0007f -#define MATCH_FCVT_LU_Q 0xc6300053 -#define MASK_FCVT_LU_Q 0xfff0007f -#define MATCH_FMV_X_Q 0xe6000053 -#define MASK_FMV_X_Q 0xfff0707f -#define MATCH_FCLASS_Q 0xe6001053 -#define MASK_FCLASS_Q 0xfff0707f -#define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f -#define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f -#define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f -#define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_FMV_W_X 0xf0000053 -#define MASK_FMV_W_X 0xfff0707f -#define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f -#define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f -#define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f -#define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f -#define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f -#define MATCH_FCVT_Q_W 0xd6000053 -#define MASK_FCVT_Q_W 0xfff0007f -#define MATCH_FCVT_Q_WU 0xd6100053 -#define MASK_FCVT_Q_WU 0xfff0007f -#define MATCH_FCVT_Q_L 0xd6200053 -#define MASK_FCVT_Q_L 0xfff0007f -#define MATCH_FCVT_Q_LU 0xd6300053 -#define MASK_FCVT_Q_LU 0xfff0007f -#define MATCH_FMV_Q_X 0xf6000053 -#define MASK_FMV_Q_X 0xfff0707f -#define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f -#define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f -#define MATCH_FLQ 0x4007 -#define MASK_FLQ 0x707f -#define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f -#define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f -#define MATCH_FSQ 0x4027 -#define MASK_FSQ 0x707f -#define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f -#define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f -#define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f -#define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f -#define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f -#define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f -#define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f -#define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f -#define MATCH_FMADD_Q 0x6000043 -#define MASK_FMADD_Q 0x600007f -#define MATCH_FMSUB_Q 0x6000047 -#define MASK_FMSUB_Q 0x600007f -#define MATCH_FNMSUB_Q 0x600004b -#define MASK_FNMSUB_Q 0x600007f -#define MATCH_FNMADD_Q 0x600004f -#define MASK_FNMADD_Q 0x600007f -#define MATCH_C_NOP 0x1 -#define MASK_C_NOP 0xffff -#define MATCH_C_ADDI16SP 0x6101 -#define MASK_C_ADDI16SP 0xef83 -#define MATCH_C_JR 0x8002 -#define MASK_C_JR 0xf07f -#define MATCH_C_JALR 0x9002 -#define MASK_C_JALR 0xf07f -#define MATCH_C_EBREAK 0x9002 -#define MASK_C_EBREAK 0xffff -#define MATCH_C_LD 0x6000 -#define MASK_C_LD 0xe003 -#define MATCH_C_SD 0xe000 -#define MASK_C_SD 0xe003 -#define MATCH_C_ADDIW 0x2001 -#define MASK_C_ADDIW 0xe003 -#define MATCH_C_LDSP 0x6002 -#define MASK_C_LDSP 0xe003 -#define MATCH_C_SDSP 0xe002 -#define MASK_C_SDSP 0xe003 -#define MATCH_C_ADDI4SPN 0x0 -#define MASK_C_ADDI4SPN 0xe003 -#define MATCH_C_FLD 0x2000 -#define MASK_C_FLD 0xe003 -#define MATCH_C_LW 0x4000 -#define MASK_C_LW 0xe003 -#define MATCH_C_FLW 0x6000 -#define MASK_C_FLW 0xe003 -#define MATCH_C_FSD 0xa000 -#define MASK_C_FSD 0xe003 -#define MATCH_C_SW 0xc000 -#define MASK_C_SW 0xe003 -#define MATCH_C_FSW 0xe000 -#define MASK_C_FSW 0xe003 -#define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0xe003 -#define MATCH_C_JAL 0x2001 -#define MASK_C_JAL 0xe003 -#define MATCH_C_LI 0x4001 -#define MASK_C_LI 0xe003 -#define MATCH_C_LUI 0x6001 -#define MASK_C_LUI 0xe003 -#define MATCH_C_SRLI 0x8001 -#define MASK_C_SRLI 0xec03 -#define MATCH_C_SRAI 0x8401 -#define MASK_C_SRAI 0xec03 -#define MATCH_C_ANDI 0x8801 -#define MASK_C_ANDI 0xec03 -#define MATCH_C_SUB 0x8c01 -#define MASK_C_SUB 0xfc63 -#define MATCH_C_XOR 0x8c21 -#define MASK_C_XOR 0xfc63 -#define MATCH_C_OR 0x8c41 -#define MASK_C_OR 0xfc63 -#define MATCH_C_AND 0x8c61 -#define MASK_C_AND 0xfc63 -#define MATCH_C_SUBW 0x9c01 -#define MASK_C_SUBW 0xfc63 -#define MATCH_C_ADDW 0x9c21 -#define MASK_C_ADDW 0xfc63 -#define MATCH_C_J 0xa001 -#define MASK_C_J 0xe003 -#define MATCH_C_BEQZ 0xc001 -#define MASK_C_BEQZ 0xe003 -#define MATCH_C_BNEZ 0xe001 -#define MASK_C_BNEZ 0xe003 -#define MATCH_C_SLLI 0x2 -#define MASK_C_SLLI 0xe003 -#define MATCH_C_FLDSP 0x2002 -#define MASK_C_FLDSP 0xe003 -#define MATCH_C_LWSP 0x4002 -#define MASK_C_LWSP 0xe003 -#define MATCH_C_FLWSP 0x6002 -#define MASK_C_FLWSP 0xe003 -#define MATCH_C_MV 0x8002 -#define MASK_C_MV 0xf003 -#define MATCH_C_ADD 0x9002 -#define MASK_C_ADD 0xf003 -#define MATCH_C_FSDSP 0xa002 -#define MASK_C_FSDSP 0xe003 -#define MATCH_C_SWSP 0xc002 -#define MASK_C_SWSP 0xe003 -#define MATCH_C_FSWSP 0xe002 -#define MASK_C_FSWSP 0xe003 -#define MATCH_CUSTOM0 0xb -#define MASK_CUSTOM0 0x707f -#define MATCH_CUSTOM0_RS1 0x200b -#define MASK_CUSTOM0_RS1 0x707f -#define MATCH_CUSTOM0_RS1_RS2 0x300b -#define MASK_CUSTOM0_RS1_RS2 0x707f -#define MATCH_CUSTOM0_RD 0x400b -#define MASK_CUSTOM0_RD 0x707f -#define MATCH_CUSTOM0_RD_RS1 0x600b -#define MASK_CUSTOM0_RD_RS1 0x707f -#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b -#define MASK_CUSTOM0_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM1 0x2b -#define MASK_CUSTOM1 0x707f -#define MATCH_CUSTOM1_RS1 0x202b -#define MASK_CUSTOM1_RS1 0x707f -#define MATCH_CUSTOM1_RS1_RS2 0x302b -#define MASK_CUSTOM1_RS1_RS2 0x707f -#define MATCH_CUSTOM1_RD 0x402b -#define MASK_CUSTOM1_RD 0x707f -#define MATCH_CUSTOM1_RD_RS1 0x602b -#define MASK_CUSTOM1_RD_RS1 0x707f -#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b -#define MASK_CUSTOM1_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM2 0x5b -#define MASK_CUSTOM2 0x707f -#define MATCH_CUSTOM2_RS1 0x205b -#define MASK_CUSTOM2_RS1 0x707f -#define MATCH_CUSTOM2_RS1_RS2 0x305b -#define MASK_CUSTOM2_RS1_RS2 0x707f -#define MATCH_CUSTOM2_RD 0x405b -#define MASK_CUSTOM2_RD 0x707f -#define MATCH_CUSTOM2_RD_RS1 0x605b -#define MASK_CUSTOM2_RD_RS1 0x707f -#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b -#define MASK_CUSTOM2_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM3 0x7b -#define MASK_CUSTOM3 0x707f -#define MATCH_CUSTOM3_RS1 0x207b -#define MASK_CUSTOM3_RS1 0x707f -#define MATCH_CUSTOM3_RS1_RS2 0x307b -#define MASK_CUSTOM3_RS1_RS2 0x707f -#define MATCH_CUSTOM3_RD 0x407b -#define MASK_CUSTOM3_RD 0x707f -#define MATCH_CUSTOM3_RD_RS1 0x607b -#define MASK_CUSTOM3_RD_RS1 0x707f -#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b -#define MASK_CUSTOM3_RD_RS1_RS2 0x707f -#define CSR_FFLAGS 0x1 -#define CSR_FRM 0x2 -#define CSR_FCSR 0x3 -#define CSR_CYCLE 0xc00 -#define CSR_TIME 0xc01 -#define CSR_INSTRET 0xc02 -#define CSR_HPMCOUNTER3 0xc03 -#define CSR_HPMCOUNTER4 0xc04 -#define CSR_HPMCOUNTER5 0xc05 -#define CSR_HPMCOUNTER6 0xc06 -#define CSR_HPMCOUNTER7 0xc07 -#define CSR_HPMCOUNTER8 0xc08 -#define CSR_HPMCOUNTER9 0xc09 -#define CSR_HPMCOUNTER10 0xc0a -#define CSR_HPMCOUNTER11 0xc0b -#define CSR_HPMCOUNTER12 0xc0c -#define CSR_HPMCOUNTER13 0xc0d -#define CSR_HPMCOUNTER14 0xc0e -#define CSR_HPMCOUNTER15 0xc0f -#define CSR_HPMCOUNTER16 0xc10 -#define CSR_HPMCOUNTER17 0xc11 -#define CSR_HPMCOUNTER18 0xc12 -#define CSR_HPMCOUNTER19 0xc13 -#define CSR_HPMCOUNTER20 0xc14 -#define CSR_HPMCOUNTER21 0xc15 -#define CSR_HPMCOUNTER22 0xc16 -#define CSR_HPMCOUNTER23 0xc17 -#define CSR_HPMCOUNTER24 0xc18 -#define CSR_HPMCOUNTER25 0xc19 -#define CSR_HPMCOUNTER26 0xc1a -#define CSR_HPMCOUNTER27 0xc1b -#define CSR_HPMCOUNTER28 0xc1c -#define CSR_HPMCOUNTER29 0xc1d -#define CSR_HPMCOUNTER30 0xc1e -#define CSR_HPMCOUNTER31 0xc1f -#define CSR_SSTATUS 0x100 -#define CSR_SIE 0x104 -#define CSR_STVEC 0x105 -#define CSR_SCOUNTEREN 0x106 -#define CSR_SSCRATCH 0x140 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_SBADADDR 0x143 -#define CSR_SIP 0x144 -#define CSR_SPTBR 0x180 -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MCOUNTEREN 0x306 -#define CSR_MSCRATCH 0x340 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MBADADDR 0x343 -#define CSR_MIP 0x344 -#define CSR_PMPCFG0 0x3a0 -#define CSR_PMPCFG1 0x3a1 -#define CSR_PMPCFG2 0x3a2 -#define CSR_PMPCFG3 0x3a3 -#define CSR_PMPADDR0 0x3b0 -#define CSR_PMPADDR1 0x3b1 -#define CSR_PMPADDR2 0x3b2 -#define CSR_PMPADDR3 0x3b3 -#define CSR_PMPADDR4 0x3b4 -#define CSR_PMPADDR5 0x3b5 -#define CSR_PMPADDR6 0x3b6 -#define CSR_PMPADDR7 0x3b7 -#define CSR_PMPADDR8 0x3b8 -#define CSR_PMPADDR9 0x3b9 -#define CSR_PMPADDR10 0x3ba -#define CSR_PMPADDR11 0x3bb -#define CSR_PMPADDR12 0x3bc -#define CSR_PMPADDR13 0x3bd -#define CSR_PMPADDR14 0x3be -#define CSR_PMPADDR15 0x3bf -#define CSR_TSELECT 0x7a0 -#define CSR_TDATA1 0x7a1 -#define CSR_TDATA2 0x7a2 -#define CSR_TDATA3 0x7a3 -#define CSR_DCSR 0x7b0 -#define CSR_DPC 0x7b1 -#define CSR_DSCRATCH 0x7b2 -#define CSR_MCYCLE 0xb00 -#define CSR_MINSTRET 0xb02 -#define CSR_MHPMCOUNTER3 0xb03 -#define CSR_MHPMCOUNTER4 0xb04 -#define CSR_MHPMCOUNTER5 0xb05 -#define CSR_MHPMCOUNTER6 0xb06 -#define CSR_MHPMCOUNTER7 0xb07 -#define CSR_MHPMCOUNTER8 0xb08 -#define CSR_MHPMCOUNTER9 0xb09 -#define CSR_MHPMCOUNTER10 0xb0a -#define CSR_MHPMCOUNTER11 0xb0b -#define CSR_MHPMCOUNTER12 0xb0c -#define CSR_MHPMCOUNTER13 0xb0d -#define CSR_MHPMCOUNTER14 0xb0e -#define CSR_MHPMCOUNTER15 0xb0f -#define CSR_MHPMCOUNTER16 0xb10 -#define CSR_MHPMCOUNTER17 0xb11 -#define CSR_MHPMCOUNTER18 0xb12 -#define CSR_MHPMCOUNTER19 0xb13 -#define CSR_MHPMCOUNTER20 0xb14 -#define CSR_MHPMCOUNTER21 0xb15 -#define CSR_MHPMCOUNTER22 0xb16 -#define CSR_MHPMCOUNTER23 0xb17 -#define CSR_MHPMCOUNTER24 0xb18 -#define CSR_MHPMCOUNTER25 0xb19 -#define CSR_MHPMCOUNTER26 0xb1a -#define CSR_MHPMCOUNTER27 0xb1b -#define CSR_MHPMCOUNTER28 0xb1c -#define CSR_MHPMCOUNTER29 0xb1d -#define CSR_MHPMCOUNTER30 0xb1e -#define CSR_MHPMCOUNTER31 0xb1f -#define CSR_MHPMEVENT3 0x323 -#define CSR_MHPMEVENT4 0x324 -#define CSR_MHPMEVENT5 0x325 -#define CSR_MHPMEVENT6 0x326 -#define CSR_MHPMEVENT7 0x327 -#define CSR_MHPMEVENT8 0x328 -#define CSR_MHPMEVENT9 0x329 -#define CSR_MHPMEVENT10 0x32a -#define CSR_MHPMEVENT11 0x32b -#define CSR_MHPMEVENT12 0x32c -#define CSR_MHPMEVENT13 0x32d -#define CSR_MHPMEVENT14 0x32e -#define CSR_MHPMEVENT15 0x32f -#define CSR_MHPMEVENT16 0x330 -#define CSR_MHPMEVENT17 0x331 -#define CSR_MHPMEVENT18 0x332 -#define CSR_MHPMEVENT19 0x333 -#define CSR_MHPMEVENT20 0x334 -#define CSR_MHPMEVENT21 0x335 -#define CSR_MHPMEVENT22 0x336 -#define CSR_MHPMEVENT23 0x337 -#define CSR_MHPMEVENT24 0x338 -#define CSR_MHPMEVENT25 0x339 -#define CSR_MHPMEVENT26 0x33a -#define CSR_MHPMEVENT27 0x33b -#define CSR_MHPMEVENT28 0x33c -#define CSR_MHPMEVENT29 0x33d -#define CSR_MHPMEVENT30 0x33e -#define CSR_MHPMEVENT31 0x33f -#define CSR_MVENDORID 0xf11 -#define CSR_MARCHID 0xf12 -#define CSR_MIMPID 0xf13 -#define CSR_MHARTID 0xf14 -#define CSR_CYCLEH 0xc80 -#define CSR_TIMEH 0xc81 -#define CSR_INSTRETH 0xc82 -#define CSR_HPMCOUNTER3H 0xc83 -#define CSR_HPMCOUNTER4H 0xc84 -#define CSR_HPMCOUNTER5H 0xc85 -#define CSR_HPMCOUNTER6H 0xc86 -#define CSR_HPMCOUNTER7H 0xc87 -#define CSR_HPMCOUNTER8H 0xc88 -#define CSR_HPMCOUNTER9H 0xc89 -#define CSR_HPMCOUNTER10H 0xc8a -#define CSR_HPMCOUNTER11H 0xc8b -#define CSR_HPMCOUNTER12H 0xc8c -#define CSR_HPMCOUNTER13H 0xc8d -#define CSR_HPMCOUNTER14H 0xc8e -#define CSR_HPMCOUNTER15H 0xc8f -#define CSR_HPMCOUNTER16H 0xc90 -#define CSR_HPMCOUNTER17H 0xc91 -#define CSR_HPMCOUNTER18H 0xc92 -#define CSR_HPMCOUNTER19H 0xc93 -#define CSR_HPMCOUNTER20H 0xc94 -#define CSR_HPMCOUNTER21H 0xc95 -#define CSR_HPMCOUNTER22H 0xc96 -#define CSR_HPMCOUNTER23H 0xc97 -#define CSR_HPMCOUNTER24H 0xc98 -#define CSR_HPMCOUNTER25H 0xc99 -#define CSR_HPMCOUNTER26H 0xc9a -#define CSR_HPMCOUNTER27H 0xc9b -#define CSR_HPMCOUNTER28H 0xc9c -#define CSR_HPMCOUNTER29H 0xc9d -#define CSR_HPMCOUNTER30H 0xc9e -#define CSR_HPMCOUNTER31H 0xc9f -#define CSR_MCYCLEH 0xb80 -#define CSR_MINSTRETH 0xb82 -#define CSR_MHPMCOUNTER3H 0xb83 -#define CSR_MHPMCOUNTER4H 0xb84 -#define CSR_MHPMCOUNTER5H 0xb85 -#define CSR_MHPMCOUNTER6H 0xb86 -#define CSR_MHPMCOUNTER7H 0xb87 -#define CSR_MHPMCOUNTER8H 0xb88 -#define CSR_MHPMCOUNTER9H 0xb89 -#define CSR_MHPMCOUNTER10H 0xb8a -#define CSR_MHPMCOUNTER11H 0xb8b -#define CSR_MHPMCOUNTER12H 0xb8c -#define CSR_MHPMCOUNTER13H 0xb8d -#define CSR_MHPMCOUNTER14H 0xb8e -#define CSR_MHPMCOUNTER15H 0xb8f -#define CSR_MHPMCOUNTER16H 0xb90 -#define CSR_MHPMCOUNTER17H 0xb91 -#define CSR_MHPMCOUNTER18H 0xb92 -#define CSR_MHPMCOUNTER19H 0xb93 -#define CSR_MHPMCOUNTER20H 0xb94 -#define CSR_MHPMCOUNTER21H 0xb95 -#define CSR_MHPMCOUNTER22H 0xb96 -#define CSR_MHPMCOUNTER23H 0xb97 -#define CSR_MHPMCOUNTER24H 0xb98 -#define CSR_MHPMCOUNTER25H 0xb99 -#define CSR_MHPMCOUNTER26H 0xb9a -#define CSR_MHPMCOUNTER27H 0xb9b -#define CSR_MHPMCOUNTER28H 0xb9c -#define CSR_MHPMCOUNTER29H 0xb9d -#define CSR_MHPMCOUNTER30H 0xb9e -#define CSR_MHPMCOUNTER31H 0xb9f -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FETCH_ACCESS 0x1 -#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_LOAD_ACCESS 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_STORE_ACCESS 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_HYPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#define CAUSE_FETCH_PAGE_FAULT 0xc -#define CAUSE_LOAD_PAGE_FAULT 0xd -#define CAUSE_STORE_PAGE_FAULT 0xf -#endif -#ifdef DECLARE_INSN -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN(or, MATCH_OR, MASK_OR) -DECLARE_INSN(and, MATCH_AND, MASK_AND) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) -DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) -DECLARE_INSN(uret, MATCH_URET, MASK_URET) -DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) -DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) -DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) -DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) -DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) -DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) -DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) -DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) -DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) -DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) -DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) -DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) -DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) -DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) -DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) -DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) -DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) -DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) -DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) -DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) -DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) -DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) -DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) -DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) -DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) -DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) -DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) -DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) -DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) -DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) -DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) -DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) -DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) -DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) -DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) -DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) -DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) -DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) -DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) -DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) -DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) -DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) -DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) -DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) -DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) -DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) -DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) -DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) -DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) -DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) -DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) -DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) -DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) -DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) -DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) -DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) -DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) -DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) -DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) -DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) -DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) -#endif -#ifdef DECLARE_CSR -DECLARE_CSR(fflags, CSR_FFLAGS) -DECLARE_CSR(frm, CSR_FRM) -DECLARE_CSR(fcsr, CSR_FCSR) -DECLARE_CSR(cycle, CSR_CYCLE) -DECLARE_CSR(time, CSR_TIME) -DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) -DECLARE_CSR(sstatus, CSR_SSTATUS) -DECLARE_CSR(sie, CSR_SIE) -DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(scounteren, CSR_SCOUNTEREN) -DECLARE_CSR(sscratch, CSR_SSCRATCH) -DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(sbadaddr, CSR_SBADADDR) -DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(sptbr, CSR_SPTBR) -DECLARE_CSR(mstatus, CSR_MSTATUS) -DECLARE_CSR(misa, CSR_MISA) -DECLARE_CSR(medeleg, CSR_MEDELEG) -DECLARE_CSR(mideleg, CSR_MIDELEG) -DECLARE_CSR(mie, CSR_MIE) -DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) -DECLARE_CSR(mscratch, CSR_MSCRATCH) -DECLARE_CSR(mepc, CSR_MEPC) -DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mbadaddr, CSR_MBADADDR) -DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) -DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) -DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) -DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) -DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) -DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) -DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) -DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) -DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) -DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) -DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) -DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) -DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) -DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) -DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) -DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) -DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) -DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) -DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) -DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) -DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata1, CSR_TDATA1) -DECLARE_CSR(tdata2, CSR_TDATA2) -DECLARE_CSR(tdata3, CSR_TDATA3) -DECLARE_CSR(dcsr, CSR_DCSR) -DECLARE_CSR(dpc, CSR_DPC) -DECLARE_CSR(dscratch, CSR_DSCRATCH) -DECLARE_CSR(mcycle, CSR_MCYCLE) -DECLARE_CSR(minstret, CSR_MINSTRET) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) -DECLARE_CSR(mvendorid, CSR_MVENDORID) -DECLARE_CSR(marchid, CSR_MARCHID) -DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) -DECLARE_CSR(mcycleh, CSR_MCYCLEH) -DECLARE_CSR(minstreth, CSR_MINSTRETH) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -#endif -#ifdef DECLARE_CAUSE -DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) -DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) -DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) -DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) -DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) -DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) -DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) -DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) -DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) -DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) -DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) -DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) -#endif - -#include "scr1_specific.h"
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_macros.h b/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_macros.h deleted file mode 100644 index 7f5ae94..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_macros.h +++ /dev/null
@@ -1,836 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Syntacore LLC -// ////////////////////////////////////////////////////////////////////////// -// See LICENSE for license details. - -#ifndef __RISCV_MACROS_H -#define __RISCV_MACROS_H - -#include "riscv_csr_encoding.h" -#include "sc_test.h" - -//----------------------------------------------------------------------- -// Begin Macro -//----------------------------------------------------------------------- - -#define RVTEST_RV64U \ - .macro init; \ - .endm - -#define RVTEST_RV64UF \ - .macro init; \ - RVTEST_FP_ENABLE; \ - .endm - -#define RVTEST_RV32U \ - .macro init; \ - .endm - -#define RVTEST_RV32UF \ - .macro init; \ - RVTEST_FP_ENABLE; \ - .endm - -#define RVTEST_RV64M \ - .macro init; \ - RVTEST_ENABLE_MACHINE; \ - .endm - -#define RVTEST_RV64S \ - .macro init; \ - RVTEST_ENABLE_SUPERVISOR; \ - .endm - -#define RVTEST_RV32M \ - .macro init; \ - RVTEST_ENABLE_MACHINE; \ - .endm - -#define RVTEST_RV32S \ - .macro init; \ - RVTEST_ENABLE_SUPERVISOR; \ - .endm - -#if __riscv_xlen == 64 -# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1: -#else -# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: -#endif - -#define INIT_PMP \ - la t0, 1f; \ - csrw mtvec, t0; \ - li t0, -1; /* Set up a PMP to permit all accesses */ \ - csrw pmpaddr0, t0; \ - li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \ - csrw pmpcfg0, t0; \ - .balign 4; \ -1: - -#define INIT_SPTBR \ - la t0, 1f; \ - csrw mtvec, t0; \ - csrwi sptbr, 0; \ - .balign 4; \ -1: - -#define DELEGATE_NO_TRAPS - -#define RVTEST_ENABLE_SUPERVISOR \ - li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \ - csrs mstatus, a0; \ - li a0, SIP_SSIP | SIP_STIP; \ - csrs mideleg, a0; \ - -#define RVTEST_ENABLE_MACHINE \ - li a0, MSTATUS_MPP; \ - csrs mstatus, a0; \ - -#define RVTEST_FP_ENABLE \ - li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \ - csrs mstatus, a0; \ - csrwi fcsr, 0 - -#define RISCV_MULTICORE_DISABLE \ - csrr a0, mhartid; \ - 1: bnez a0, 1b - -#define EXTRA_TVEC_USER -#define EXTRA_TVEC_SUPERVISOR -#define EXTRA_TVEC_HYPERVISOR -#define EXTRA_TVEC_MACHINE -#define EXTRA_INIT -#define EXTRA_INIT_TIMER - -#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */ - -#define RVTEST_CODE_BEGIN \ - .section .text.init; \ - .org 0xC0, 0x00; \ - .balign 64; \ - .weak stvec_handler; \ - .weak mtvec_handler; \ -trap_vector: \ - /* test whether the test came from pass/fail */ \ - csrr a4, mcause; \ - li a5, CAUSE_USER_ECALL; \ - beq a4, a5, _report; \ - li a5, CAUSE_SUPERVISOR_ECALL; \ - beq a4, a5, _report; \ - li a5, CAUSE_MACHINE_ECALL; \ - beq a4, a5, _report; \ - /* if an mtvec_handler is defined, jump to it */ \ - la a4, mtvec_handler; \ - beqz a4, 1f; \ - jr a4; \ - /* was it an interrupt or an exception? */ \ -1: csrr a4, mcause; \ - bgez a4, handle_exception; \ - INTERRUPT_HANDLER; \ -handle_exception: \ - /* we don't know how to handle whatever the exception was */ \ -other_exception: \ - /* some unhandlable exception occurred */ \ - li a0, 0x1; \ -_report: \ - j sc_exit; \ - .balign 64; \ - .globl _start; \ -_start: \ - RISCV_MULTICORE_DISABLE; \ - /*INIT_SPTBR;*/ \ - /*INIT_PMP;*/ \ - DELEGATE_NO_TRAPS; \ - li TESTNUM, 0; \ - la t0, trap_vector; \ - csrw mtvec, t0; \ - CHECK_XLEN; \ - /* if an stvec_handler is defined, delegate exceptions to it */ \ - la t0, stvec_handler; \ - beqz t0, 1f; \ - csrw stvec, t0; \ - li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \ - (1 << CAUSE_STORE_PAGE_FAULT) | \ - (1 << CAUSE_FETCH_PAGE_FAULT) | \ - (1 << CAUSE_MISALIGNED_FETCH) | \ - (1 << CAUSE_USER_ECALL) | \ - (1 << CAUSE_BREAKPOINT); \ - csrw medeleg, t0; \ - csrr t1, medeleg; \ - bne t0, t1, other_exception; \ -1: csrwi mstatus, 0; \ - init; \ - EXTRA_INIT; \ - EXTRA_INIT_TIMER; \ - la t0, _run_test; \ - csrw mepc, t0; \ - csrr a0, mhartid; \ - mret; \ - .section .text; \ -_run_test: - -//----------------------------------------------------------------------- -// End Macro -//----------------------------------------------------------------------- - -#define RVTEST_CODE_END ecall: ecall - -//----------------------------------------------------------------------- -// Pass/Fail Macro -//----------------------------------------------------------------------- - -#define RVTEST_PASS \ - fence; \ - mv a1, TESTNUM; \ - li a0, 0x0; \ - ecall - -#define TESTNUM x28 -#define RVTEST_FAIL \ - fence; \ - mv a1, TESTNUM; \ - li a0, 0x1; \ - ecall - -//----------------------------------------------------------------------- -// Data Section Macro -//----------------------------------------------------------------------- - -#define EXTRA_DATA - -#define RVTEST_DATA_BEGIN \ - EXTRA_DATA \ - .pushsection .tohost,"aw",@progbits; \ - .balign 64; .global tohost; tohost: .dword 0; \ - .balign 64; .global fromhost; fromhost: .dword 0; \ - .popsection; \ - .balign 16; \ - .global begin_regstate; begin_regstate: .dword 0; .dword 0; .dword 0; \ - .balign 16; \ - .global begin_signature; begin_signature: - -#define RVTEST_DATA_END .balign 16; .global end_signature; end_signature: - -#----------------------------------------------------------------------- -# Helper macros -#----------------------------------------------------------------------- - -#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1)) - -#define TEST_CASE( testnum, testreg, correctval, code... ) \ -test_ ## testnum: \ - code; \ - li x29, MASK_XLEN(correctval); \ - li TESTNUM, testnum; \ - bne testreg, x29, fail; - -# We use a macro hack to simpify code generation for various numbers -# of bubble cycles. - -#define TEST_INSERT_NOPS_0 -#define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0 -#define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1 -#define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2 -#define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3 -#define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4 -#define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5 -#define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6 -#define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7 -#define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8 -#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9 - - -#----------------------------------------------------------------------- -# RV64UI MACROS -#----------------------------------------------------------------------- - -#----------------------------------------------------------------------- -# Tests for instructions with immediate operand -#----------------------------------------------------------------------- - -#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) - -#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \ - TEST_CASE( testnum, x3, result, \ - li x1, MASK_XLEN(val1); \ - inst x3, x1, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_OP_RVC( testnum, inst, result, val1, imm ) \ - TEST_CASE( testnum, x1, result, \ - li x1, val1; \ - inst x1, imm; \ - ) - -#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \ - TEST_CASE( testnum, x1, result, \ - li x1, MASK_XLEN(val1); \ - inst x1, x1, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ - TEST_CASE( testnum, x6, result, \ - li x4, 0; \ -1: li x1, MASK_XLEN(val1); \ - inst x3, x1, SEXT_IMM(imm); \ - TEST_INSERT_NOPS_ ## nop_cycles \ - addi x6, x3, 0; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ - TEST_CASE( testnum, x3, result, \ - li x4, 0; \ -1: li x1, MASK_XLEN(val1); \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x3, x1, SEXT_IMM(imm); \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \ - TEST_CASE( testnum, x1, result, \ - inst x1, x0, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \ - TEST_CASE( testnum, x0, 0, \ - li x1, MASK_XLEN(val1); \ - inst x0, x1, SEXT_IMM(imm); \ - ) - -#----------------------------------------------------------------------- -# Tests for vector config instructions -#----------------------------------------------------------------------- - -#define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \ - TEST_CASE( testnum, x1, result, \ - li x1, (bank << 12); \ - vsetcfg x1,nxpr,nfpr; \ - li x1, vl; \ - vsetvl x1,x1; \ - ) - -#define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \ - TEST_CASE( testnum, x1, result, \ - li x1, (bank << 12) | (nfpr << 6) | nxpr; \ - vsetcfg x1; \ - li x1, vl; \ - vsetvl x1,x1; \ - ) - -#define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \ - TEST_CASE( testnum, x1, result, \ - li x1, (bank << 12); \ - vsetcfg x1,nxpr,nfpr; \ - li x1, vl; \ - vsetvl x1, x1; \ - ) - -#----------------------------------------------------------------------- -# Tests for an instruction with register operands -#----------------------------------------------------------------------- - -#define TEST_R_OP( testnum, inst, result, val1 ) \ - TEST_CASE( testnum, x3, result, \ - li x1, val1; \ - inst x3, x1; \ - ) - -#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \ - TEST_CASE( testnum, x1, result, \ - li x1, val1; \ - inst x1, x1; \ - ) - -#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \ - TEST_CASE( testnum, x6, result, \ - li x4, 0; \ -1: li x1, val1; \ - inst x3, x1; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - addi x6, x3, 0; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#----------------------------------------------------------------------- -# Tests for an instruction with register-register operands -#----------------------------------------------------------------------- - -#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x3, result, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x3, x1, x2; \ - ) - -#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x1, result, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x1, x1, x2; \ - ) - -#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x2, result, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x2, x1, x2; \ - ) - -#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \ - TEST_CASE( testnum, x1, result, \ - li x1, MASK_XLEN(val1); \ - inst x1, x1, x1; \ - ) - -#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x6, result, \ - li x4, 0; \ -1: li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x3, x1, x2; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - addi x6, x3, 0; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x3, result, \ - li x4, 0; \ -1: li x1, MASK_XLEN(val1); \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x2, MASK_XLEN(val2); \ - TEST_INSERT_NOPS_ ## src2_nops \ - inst x3, x1, x2; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x3, result, \ - li x4, 0; \ -1: li x2, MASK_XLEN(val2); \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x1, MASK_XLEN(val1); \ - TEST_INSERT_NOPS_ ## src2_nops \ - inst x3, x1, x2; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \ - TEST_CASE( testnum, x2, result, \ - li x1, MASK_XLEN(val); \ - inst x2, x0, x1; \ - ) - -#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \ - TEST_CASE( testnum, x2, result, \ - li x1, MASK_XLEN(val); \ - inst x2, x1, x0; \ - ) - -#define TEST_RR_ZEROSRC12( testnum, inst, result ) \ - TEST_CASE( testnum, x1, result, \ - inst x1, x0, x0; \ - ) - -#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \ - TEST_CASE( testnum, x0, 0, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x0, x1, x2; \ - ) - -#----------------------------------------------------------------------- -# Test memory instructions -#----------------------------------------------------------------------- - -#define TEST_LD_OP( testnum, inst, result, offset, base ) \ - TEST_CASE( testnum, x3, result, \ - la x1, base; \ - inst x3, offset(x1); \ - ) - -#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \ - TEST_CASE( testnum, x3, result, \ - la x1, base; \ - li x2, result; \ - store_inst x2, offset(x1); \ - load_inst x3, offset(x1); \ - ) - -#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: la x1, base; \ - inst x3, offset(x1); \ - TEST_INSERT_NOPS_ ## nop_cycles \ - addi x6, x3, 0; \ - li x29, result; \ - bne x6, x29, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b; \ - -#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: la x1, base; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x3, offset(x1); \ - li x29, result; \ - bne x3, x29, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: li x1, result; \ - TEST_INSERT_NOPS_ ## src1_nops \ - la x2, base; \ - TEST_INSERT_NOPS_ ## src2_nops \ - store_inst x1, offset(x2); \ - load_inst x3, offset(x2); \ - li x29, result; \ - bne x3, x29, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: la x2, base; \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x1, result; \ - TEST_INSERT_NOPS_ ## src2_nops \ - store_inst x1, offset(x2); \ - load_inst x3, offset(x2); \ - li x29, result; \ - bne x3, x29, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#----------------------------------------------------------------------- -# Test branch instructions -#----------------------------------------------------------------------- - -#define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x1, val1; \ - inst x1, 2f; \ - bne x0, TESTNUM, fail; \ -1: bne x0, TESTNUM, 3f; \ -2: inst x1, 1b; \ - bne x0, TESTNUM, fail; \ -3: - -#define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x1, val1; \ - inst x1, 1f; \ - bne x0, TESTNUM, 2f; \ -1: bne x0, TESTNUM, fail; \ -2: inst x1, 1b; \ -3: - -#define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: li x1, val1; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x1, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x1, val1; \ - li x2, val2; \ - inst x1, x2, 2f; \ - bne x0, TESTNUM, fail; \ -1: bne x0, TESTNUM, 3f; \ -2: inst x1, x2, 1b; \ - bne x0, TESTNUM, fail; \ -3: - -#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x1, val1; \ - li x2, val2; \ - inst x1, x2, 1f; \ - bne x0, TESTNUM, 2f; \ -1: bne x0, TESTNUM, fail; \ -2: inst x1, x2, 1b; \ -3: - -#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: li x1, val1; \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x2, val2; \ - TEST_INSERT_NOPS_ ## src2_nops \ - inst x1, x2, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: li x2, val2; \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x1, val1; \ - TEST_INSERT_NOPS_ ## src2_nops \ - inst x1, x2, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#----------------------------------------------------------------------- -# Test jump instructions -#----------------------------------------------------------------------- - -#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: la x6, 2f; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x6; \ - bne x0, TESTNUM, fail; \ -2: addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - li x4, 0; \ -1: la x6, 2f; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x19, x6, 0; \ - bne x0, TESTNUM, fail; \ -2: addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - - -#----------------------------------------------------------------------- -# RV64UF MACROS -#----------------------------------------------------------------------- - -#----------------------------------------------------------------------- -# Tests floating-point instructions -#----------------------------------------------------------------------- - -#define qNaNf 0f:7fc00000 -#define sNaNf 0f:7f800001 -#define qNaN 0d:7ff8000000000000 -#define sNaN 0d:7ff0000000000001 - -#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - flw f0, 0(a0); \ - flw f1, 4(a0); \ - flw f2, 8(a0); \ - lw a3, 12(a0); \ - code; \ - fsflags a1, x0; \ - li a2, flags; \ - bne a0, a3, fail; \ - bne a1, a2, fail; \ - j 2f; \ - .balign 4; \ - .data; \ - test_ ## testnum ## _data: \ - .float val1; \ - .float val2; \ - .float val3; \ - .result; \ - .text; \ -2: - -#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - fld f0, 0(a0); \ - fld f1, 8(a0); \ - fld f2, 16(a0); \ - ld a3, 24(a0); \ - code; \ - fsflags a1, x0; \ - li a2, flags; \ - bne a0, a3, fail; \ - bne a1, a2, fail; \ - j 2f; \ - .data; \ - .balign 8; \ - test_ ## testnum ## _data: \ - .double val1; \ - .double val2; \ - .double val3; \ - .result; \ - .text; \ -2: - -#define TEST_FCVT_S_D( testnum, result, val1 ) \ - TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ - fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3) - -#define TEST_FCVT_D_S( testnum, result, val1 ) \ - TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \ - fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3) - -#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.s a0, f3) - -#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.d a0, f3) - -#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.s a0, f3) - -#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.d a0, f3) - -#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \ - inst f3, f0, f1; fmv.x.s a0, f3) - -#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ - inst f3, f0, f1; fmv.x.d a0, f3) - -#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \ - inst f3, f0, f1, f2; fmv.x.s a0, f3) - -#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \ - inst f3, f0, f1, f2; fmv.x.d a0, f3) - -#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ - inst a0, f0, rm) - -#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst a0, f0, rm) - -#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \ - inst a0, f0, f1) - -#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ - inst a0, f0, f1) - -#define TEST_FCLASS_S(testnum, correct, input) \ - TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \ - fclass.s a0, fa0) - -#define TEST_FCLASS_D(testnum, correct, input) \ - TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \ - fclass.d a0, fa0) - -#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - lw a3, 0(a0); \ - li a0, val1; \ - inst f0, a0; \ - fsflags x0; \ - fmv.x.s a0, f0; \ - bne a0, a3, fail; \ - j 1f; \ - .balign 4; \ - test_ ## testnum ## _data: \ - .float result; \ -1: - -#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - ld a3, 0(a0); \ - li a0, val1; \ - inst f0, a0; \ - fsflags x0; \ - fmv.x.d a0, f0; \ - bne a0, a3, fail; \ - j 1f; \ - .balign 8; \ - test_ ## testnum ## _data: \ - .double result; \ -1: - -#----------------------------------------------------------------------- -# Pass and fail code (assumes test num is in TESTNUM) -#----------------------------------------------------------------------- - -#define TEST_PASSFAIL \ - bne x0, TESTNUM, pass; \ -fail: \ - RVTEST_FAIL; \ -pass: \ - RVTEST_PASS \ - - -#----------------------------------------------------------------------- -# Test data section -#----------------------------------------------------------------------- - -#define TEST_DATA - -#endif -
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.c b/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.c deleted file mode 100644 index 5131e3b..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.c +++ /dev/null
@@ -1,298 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Syntacore LLC -// ////////////////////////////////////////////////////////////////////////// -/// @file <sc_print.c> -/// - -#include <string.h> -#include <stdarg.h> -#include "sc_print.h" - -#define SC_SIM_OUTPORT (0xf0000000) -#define CHAR_BIT (8) - -static void -sc_puts(long str, long strlen) { - volatile char *out_ptr = (volatile char*)SC_SIM_OUTPORT; - const char *in_ptr = (const char*)str; - for (long len = strlen; len > 0; --len) - *out_ptr = *in_ptr++; -} - -#undef putchar -int -putchar(int ch) { - static __thread char buf[64] __attribute__((aligned(64))); - static __thread int buflen = 0; - - buf[buflen++] = ch; - - if ( ch == '\n' || buflen == sizeof(buf) ) { - sc_puts((long)buf, buflen); - buflen = 0; - } - - return 0; -} - -static void -printf_putch(int ch, void** data) -{ - putchar(ch); -} - -static void -print(const char *str) -{ - sc_puts((long)str, strlen(str)); -} - - -static long long -getint(va_list *ap, int lflag) -{ - if ( lflag >= 2 ) - return va_arg(*ap, long long); - else if ( lflag ) - return va_arg(*ap, long); - else - return va_arg(*ap, int); -} - - -static unsigned long long -getuint(va_list *ap, int lflag) -{ - if ( lflag >= 2 ) - return va_arg(*ap, unsigned long long); - else if ( lflag ) - return va_arg(*ap, unsigned long); - else - return va_arg(*ap, unsigned int); -} - -static inline void -printnum(void(*putch)(int, void**), -void **putdat, -unsigned long long num, -unsigned base, -int width, -int padc, -int hex_A) -{ - unsigned digs[sizeof(num) * CHAR_BIT]; - int pos = 0; - - for ( ;; ) { - digs[pos++] = num % base; - if ( num < base ) - break; - num /= base; - } - - while ( width-- > pos ) - putch(padc, putdat); - - while ( pos-- > 0 ) - putch(digs[pos] + (digs[pos] >= 10 ? hex_A - 10 : '0'), putdat); -} - -static void -vprintfmt(void(*putch)(int, void**), void **putdat, const char *fmt, va_list ap) -{ - register const char* p; - const char* last_fmt; - register int ch; - int err; - unsigned long long num; - int base; - int lflag; - int width; - int precision; - int altflag; - char padc; - int hex_A = 'a'; - for ( ;; ) { - while ( (ch = *(unsigned char *)fmt) != '%' ) { - if ( ch == '\0' ) - return; - ++fmt; - putch(ch, putdat); - } - ++fmt; - - // Process a %-escape sequence - last_fmt = fmt; - padc = ' '; - width = -1; - precision = -1; - lflag = 0; - altflag = 0; - -reswitch: - switch ( ch = *(unsigned char *)fmt++ ) { - // flag to pad on the right - case '-': - padc = '-'; - goto reswitch; - - // flag to pad with 0's instead of spaces - case '0': - padc = '0'; - goto reswitch; - - // width field - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - for ( precision = 0;; ++fmt ) { - precision = precision * 10 + ch - '0'; - ch = *fmt; - if ( ch < '0' || ch > '9' ) - break; - } - goto process_precision; - - case '*': - precision = va_arg(ap, int); - goto process_precision; - - case '.': - if ( width < 0 ) - width = 0; - goto reswitch; - - case '#': - altflag = 1; - goto reswitch; - -process_precision: - if ( width < 0 ) { - width = precision; - precision = -1; - } - goto reswitch; - - // long flag (doubled for long long) - case 'l': - lflag++; - goto reswitch; - - // character - case 'c': - putch(va_arg(ap, int), putdat); - break; - - // string - case 's': - if ( (p = va_arg(ap, char *)) == NULL ) - p = "(null)"; - if ( width > 0 && padc != '-' ) - for ( width -= strnlen(p, precision); width > 0; width-- ) - putch(padc, putdat); - for ( ; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width-- ) { - putch(ch, putdat); - p++; - } - for ( ; width > 0; width-- ) - putch(' ', putdat); - break; - - // (signed) decimal - case 'd': - num = getint(&ap, lflag); - if ( (long long)num < 0 ) { - putch('-', putdat); - num = -(long long)num; - } - base = 10; - goto signed_number; - - case 'f': - { - // #ifndef nopfloat - // double num = getdouble(&ap, lflag); - // printdoubleF(putch, putdat, num, width, precision, padc); - // #endif - } - break; - - // unsigned decimal - case 'u': - base = 10; - goto unsigned_number; - - // (unsigned) octal - case 'o': - // should do something with padding so it's always 3 octits - base = 8; - goto unsigned_number; - - // pointer - case 'p': - // static_assert(sizeof(long) == sizeof(void*)); - lflag = 1; - putch('0', putdat); - putch('x', putdat); - /* fall through to 'x' */ - - // (unsigned) hexadecimal - case 'x': - hex_A = 'a'; - base = 16; - goto unsigned_number; - - case 'X': - hex_A = 'A'; - base = 16; -unsigned_number: - num = getuint(&ap, lflag); -signed_number: - printnum(putch, putdat, num, base, width, padc, hex_A); - break; - - // escaped '%' character - case '%': - putch(ch, putdat); - break; - - // unrecognized escape sequence - just print it literally - default: - putch('%', putdat); - fmt = last_fmt; - break; - } - } -} - -int -sc_printf(const char* fmt, ...) -{ - va_list ap; - va_start(ap, fmt); - - vprintfmt(printf_putch, NULL, fmt, ap); - - va_end(ap); - return 0; // incorrect return value, but who cares, anyway? -}
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.h b/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.h deleted file mode 100644 index cc204cd..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.h +++ /dev/null
@@ -1,26 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Syntacore LLC -// ////////////////////////////////////////////////////////////////////////// -/// @file <sc_print.h> -/// - -#ifndef SC_PRINT_H -#define SC_PRINT_H - -extern int sc_printf(const char* fmt, ...); - -#endif // SC_PRINT_H
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/sc_test.h b/verilog/rtl/syntacore/scr1/sim/tests/common/sc_test.h deleted file mode 100644 index 032de7c..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/sc_test.h +++ /dev/null
@@ -1,64 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Syntacore LLC -// ////////////////////////////////////////////////////////////////////////// -/// @file <sc_test.h> -/// - -#ifndef SC_TEST_H -#define SC_TEST_H - -#if defined(__ASSEMBLER__) -.altmacro - -.macro zero_int_reg regn -mv x\regn, zero -.endm - -.macro zero_int_regs reg_first, reg_last -.set regn, \reg_first -.rept \reg_last - \reg_first + 1 -zero_int_reg %(regn) -.set regn, regn+1 -.endr -.endm - -#define report_results(result) \ -li a0, result; \ -la t0, sc_exit; \ -jr t0; - -.pushsection sc_test_section, "ax" -sc_exit: la t0, SIM_EXIT; jr t0; -.balign 32 -.popsection -#define sc_pass report_results(0x0) -#define sc_fail report_results(0x1) - -#else - -extern void sc_exit(unsigned result, unsigned res0, unsigned res1, unsigned res2, unsigned res3) - __attribute__ ((noinline, noreturn)); - -static inline void __attribute__ ((noreturn)) -report_results(unsigned result, unsigned res0, unsigned res1, unsigned res2, unsigned res3) -{ - sc_exit(result, res0, res1, res2, res3); -} - -#endif - -#endif // SC_TEST_H
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/scr1_specific.h b/verilog/rtl/syntacore/scr1/sim/tests/common/scr1_specific.h deleted file mode 100644 index e9fe5ae..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/scr1_specific.h +++ /dev/null
@@ -1,37 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: Syntacore LLC © 2016-2021 -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Syntacore LLC -// ////////////////////////////////////////////////////////////////////////// -#ifndef __SCR1__SPECIFIC -#define __SCR1__SPECIFIC - -#define mcounten 0x7E0 - -// Memory-mapped registers -#define mtime_ctrl 0x00490000 -#define mtime_div 0x00490004 -#define mtime 0x00490008 -#define mtimeh 0x0049000C -#define mtimecmp 0x00490010 -#define mtimecmph 0x00490014 - -#define SCR1_MTIME_CTRL_EN 0 -#define SCR1_MTIME_CTRL_CLKSRC 1 - -#define SCR1_MTIME_CTRL_WR_MASK 0x3 -#define SCR1_MTIME_DIV_WR_MASK 0x3FF - -#endif // _SCR1__SPECIFIC
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/hello/Makefile b/verilog/rtl/syntacore/scr1/sim/tests/hello/Makefile deleted file mode 100644 index 0f55d60..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/hello/Makefile +++ /dev/null
@@ -1,13 +0,0 @@ -src_dir := $(dir $(lastword $(MAKEFILE_LIST))) - -c_src := sc_print.c hello.c - -include $(inc_dir)/common.mk - -default: log_requested_tgt $(bld_dir)/hello.elf $(bld_dir)/hello.hex $(bld_dir)/hello.dump - -log_requested_tgt: - echo hello.hex>> $(bld_dir)/test_info - -clean: - $(RM) $(c_objs) $(asm_objs) $(bld_dir)/hello.elf $(bld_dir)/hello.hex $(bld_dir)/hello.dump \ No newline at end of file
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/hello/hello.c b/verilog/rtl/syntacore/scr1/sim/tests/hello/hello.c deleted file mode 100644 index 52cf1bc..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/hello/hello.c +++ /dev/null
@@ -1,7 +0,0 @@ -#include "sc_print.h" - -int main() -{ - sc_printf("Hello from SCR1!\n"); - return 0; -} \ No newline at end of file
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/Makefile b/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/Makefile deleted file mode 100644 index 1c95e74..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/Makefile +++ /dev/null
@@ -1,26 +0,0 @@ -src_dir := $(dir $(lastword $(MAKEFILE_LIST))) - -LDFLAGS := -nostartfiles -nostdlib -march=rv32$(ARCH) -mabi=$(ABI) -ADD_ASM_MACRO := -DASM - -ifeq ($(IPIC) ,1) - ADD_ASM_MACRO += -DIPIC_ENABLED -endif - -ifeq ($(VECT_IRQ) ,1) - ADD_ASM_MACRO += -DVECT_IRQ_ENABLED -endif -asm_src := isr_sample.S - -# override ld script -ld_script := $(inc_dir)/link.ld - -include $(inc_dir)/common.mk - -default: log_requested_tgt $(bld_dir)/isr_sample.elf $(bld_dir)/isr_sample.hex $(bld_dir)/isr_sample.dump - -log_requested_tgt: - echo isr_sample.hex >> $(bld_dir)/test_info - -clean: - $(RM)$(asm_objs) $(bld_dir)/isr_sample.elf $(bld_dir)/isr_sample.hex $(bld_dir)/isr_sample.dump \ No newline at end of file
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S b/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S deleted file mode 100644 index d7b3d63..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S +++ /dev/null
@@ -1,291 +0,0 @@ -#include "riscv_macros.h" -#include "sc_test.h" - -.altmacro -// global interrupt bit -#define MSIE (1 << IRQ_M_SOFT) //machine software interrupt enable -#define MTIE (1 << IRQ_M_TIMER) //machine timer interrupt enable -#define MEIE (1 << IRQ_M_EXT) //machine external interrupt enable -#define MCAUSE_EXT_IRQ (1 << 31 | IRQ_M_EXT) -#define MCAUSE_SOFT_IRQ (1 << 31 | IRQ_M_SOFT) -#define MCAUSE_TMR_IRQ (1 << 31 | IRQ_M_TIMER) - -// IPIC -#define IRQ_LINES_ADDR 0x10020018 // simulation -#define TRIG_EXT_IRQ_ADDR 0x10020018 // external irq is triggered when tb memory is set to non-zero // Bit [15:0] -#define TRIG_SW_IRQ_ADDR 0x10020018 // software irq is triggered when tb memory is set to non-zero // Bit [16] - -#define IPIC_EOI 0xBF4 // end of interrupt -#define IPIC_SOI 0xBF5 // start of interrupt -#define IPIC_IDX 0xBF6 // index register -#define IPIC_ICSR 0xBF7 // interrupt control status register - -// IPIC Interrupt Constrol Status Register -#define IPIC_ICSR_IP (1 << 0) // interrupt pending -#define IPIC_ICSR_IE (1 << 1) // interrupt enable -#define IPIC_ICSR_IM (1 << 2) // interrupt mode (0/1: level/edge) -#define IPIC_ICSR_INV (1 << 3) // line inversion -#define IPIC_ICSR_IS (1 << 4) // in service - -// Interrupt lines in use -#define IPIC_IRQ_LINE9 9 -#define EXT_IRQ_LINE_COMMON 0 - -#include "timer.h" -#include "reloc.h" - -.macro jmp_sc_exit - la t0, sc_exit - jr t0 -.endm - - .section .text.init - .option norvc - .globl _start -// ----------------------------------------------------------------- -// Trap handlers -// 0xXXXXXX00 - .option norvc -.org (64*3) - -//0xXXXXXXC0 - .balign 64 -machine_trap_entry: -vec_usr_soft: -#ifdef VECT_IRQ_ENABLED - trap_entry: - j _trap_fail - vec_supervisor_soft: - j _trap_fail - vec_reserved1: - j _trap_fail - vec_machine_soft: - j vec_machine_soft_handler - vec_usr_tmr: - j _trap_fail - vec_supervisor_tmr: - j _trap_fail - vec_reserved2: - j _trap_fail - vec_machine_tmr: - j vec_machine_tmr_handler - vec_usr_ext: - j _trap_fail - vec_supervisor_ext: - j _trap_fail - vec_reserved3: - j _trap_fail - vec_machine_ext: - j vec_machine_ext_handler - vec_reserved4: - j _trap_fail - j _trap_fail - j _trap_fail - j _trap_fail -#else - trap_entry: - j direct_irq_handler - vec_supervisor_soft: - j _trap_fail - vec_reserved1: - j _trap_fail - vec_machine_soft: - j _trap_fail - vec_usr_tmr: - j _trap_fail - vec_supervisor_tmr: - j _trap_fail - vec_reserved2: - j _trap_fail - vec_machine_tmr: - j _trap_fail - vec_usr_ext: - j _trap_fail - vec_supervisor_ext: - j _trap_fail - vec_reserved3: - j _trap_fail - vec_machine_ext: - j _trap_fail - vec_reserved4: - j _trap_fail - j _trap_fail - j _trap_fail - j _trap_fail - -#endif // ifdef VECT_IRQ_ENABLED - - - .balign 64 -_start: - la t0, machine_trap_entry - csrw mtvec, t0 - - la t0, test_start - jr (t0) - -// ----------------------------------------------------------------- - .option norvc - .balign 64 -test_start: - - la t0, trap_entry - csrw mtvec, t0 // set mtvec to trap_entry - #ifdef VECT_IRQ_ENABLED - csrsi mtvec, 1 // set vectored mode - #else - csrsi mtvec, 0 // set direct mode - #endif - - /// configuring timer interrupt /// - _reset_mtimecmp; // reset timer - _run_timer; // run timer - csrs mstatus, MSTATUS_MIE // enable global interrupt - li a0, MTIE - csrs mie, a0 // enable timer interrupt - li t2, 0 // reset timer counter = 0 (updated in isr) - _read_mtime s1 // read timer value - addi s1, s1, 256 - _write_mtimecmp_32 s1 - wfi - - - /// configuring external interrupt /// - csrw mie, zero // disable all interrupts - li t0, IRQ_LINES_ADDR - sh zero, (t0) // set all exterinal interrupt lines low - #ifdef IPIC_ENABLED - li t0, IPIC_IRQ_LINE9 - csrw IPIC_IDX, t0 // set IPIC to expect interupt on line 9... - li t0, (IPIC_ICSR_IE | IPIC_ICSR_IM) - csrw IPIC_ICSR, t0 // ....enable interrupt,set edge interrupt mode - #endif - li t0, MEIE - csrs mie, t0 // enable external interrupt - li t0, TRIG_EXT_IRQ_ADDR - #ifdef IPIC_ENABLED - li t1, (1 << IPIC_IRQ_LINE9) - #else - li t1, (1 << EXT_IRQ_LINE_COMMON) - #endif - sh t1, (t0) //send command to generate external interrupt on line 9 to testbench - nop - nop - nop - nop //wait for external interrupt - - - /// configuring software interrupt /// - csrw mie, zero // disable all interrupts - li t0, TRIG_SW_IRQ_ADDR - li t1, 0x00010000 // Soft ireq bit [16] - sw t1, (t0) //send command to generate software interrupt - li t0, MSIE - csrs mie, t0 // enable software interrupt - nop - nop - nop - nop //wait for software interrupt - - li s1, 3 - li a0, 0 - beq t2, s1, 1f - li a0, -1 -1: - jmp_sc_exit - - -#ifndef VECT_IRQ_ENABLED - -direct_irq_handler: - csrr a1, mcause - li a5, MCAUSE_TMR_IRQ //0x80000007 -- mcause = tmr.irq - beq a1, a5, vec_machine_tmr_handler - li a5, MCAUSE_SOFT_IRQ //0x80000003 -- mcause = soft.irq - beq a1, a5, vec_machine_soft_handler - li a5, MCAUSE_EXT_IRQ //0x8000000B -- mcause = ext.irq - beq a1, a5, vec_machine_ext_handler - mret -#endif - -vec_machine_tmr_handler: - csrr a1, mcause - li a5, MCAUSE_TMR_IRQ //0x80000007 -- mcause = tmr.irq - li a0, -1 - bne a1, a5, check_fail - csrr t1, mip - li t0, MIP_MTIP - and t0, t1, t0 - beqz t0, check_fail -#ifdef IPIC_ENABLED - csrw IPIC_SOI, zero - csrw IPIC_EOI, zero -#endif - _reset_mtimecmp - csrr t1, mip - andi t1, t1, MIP_MTIP - bne t1, zero, check_fail - addi t2, t2, 1 // tmr irq counter update - mret - -vec_machine_ext_handler: - - csrr a1, mcause - li a5, MCAUSE_EXT_IRQ //0x8000000B -- mcause = ext.irq - li a0, -1 - bne a1, a5, check_fail - csrr t1, mip - li t0, MIP_MEIP - and t0, t1, t0 - beqz t0, check_fail -#ifdef IPIC_ENABLED - csrw IPIC_SOI, zero - csrw IPIC_EOI, zero -#endif - li t0, MEIE - csrc mie, t0 // disable software interrupt - - li t0, TRIG_EXT_IRQ_ADDR - li t1, EXT_IRQ_LINE_COMMON - sh t1, (t0) // send command to disable external interrupt - - csrr t1, mip - li t0, MIP_MEIP - bne t1, zero, check_fail - addi t2, t2, 1 // ext irq counter update - mret - -vec_machine_soft_handler: - csrr a1, mcause - li a5, MCAUSE_SOFT_IRQ //0x80000003 -- mcause = soft.irq - li a0, -1 - bne a1, a5, check_fail - csrr t1, mip - li t0, MIP_MSIP - and t0, t1, t0 - beqz t0, check_fail - #ifdef IPIC_ENABLED - csrw IPIC_SOI, zero - csrw IPIC_EOI, zero - #endif - li t0, MSIE - csrc mie, t0 // disable software interrupt - li t0, TRIG_SW_IRQ_ADDR - li t1, 0x00000000 - sw t1, (t0) // send command to stop generating software interrupt - li t0, MIP_MSIP - csrc mip, t0 - csrr t1, mip - li t0, MIP_MSIP - and t1, t1, t0 - bne t1, zero, check_fail - addi t2, t2, 1 // ext irq counter update - mret - -check_fail: - la t0, sc_exit - jr t0 - -_trap_fail: - li a0, -1 - j check_fail
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/timer.h b/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/timer.h deleted file mode 100644 index b81bcc8..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/timer.h +++ /dev/null
@@ -1,97 +0,0 @@ -#ifndef __TIMER__H -#define __TIMER__H - - - -#define MEM_MTIME_MASK 0xF0000000 -#define MEM_MTIME_CTRL 0x00490000 -#define MEM_MTIME_DIV 0x00490004 -#define MEM_MTIME 0x00490008 -#define MEM_MTIMEH 0x0049000C -#define MEM_MTIMECMP 0x00490010 -#define MEM_MTIMECMPH 0x00490014 - -#define TMP t0 -#define TMP2 t1 -#define TMP3 t2 - -// Reset -.macro _reset_mtime - li TMP, MEM_MTIME - sw zero, 0(TMP) - sw zero, 4(TMP) -.endm - -.macro _reset_mtimecmp - li TMP, MEM_MTIMECMP - not TMP2, zero - sw TMP2, 0(TMP) - sw TMP2, 4(TMP) -.endm - -// Write -.macro _write_mtime_ctrl reg - li TMP, MEM_MTIME_CTRL - sw \reg, 0(TMP) -.endm - -.macro _write_mtime_div reg - li TMP, MEM_MTIME_DIV - sw \reg, 0(TMP) -.endm - -.macro _write_mtimecmp_32 reg - li TMP, MEM_MTIMECMP - li TMP2, -1 - sw TMP2, 0(TMP) - sw zero, 4(TMP) - sw \reg, 0(TMP) -.endm - -.macro _write_mtime reg - li TMP, MEM_MTIME - sw \reg, 0(TMP) -.endm - -.macro _read_mtime reg - li TMP, MEM_MTIME - lw \reg, 0(TMP) -.endm - -// Read -.macro _read_mtimecmp reg - li TMP, MEM_MTIMECMP - lw \reg, 0(TMP) -.endm - -.macro _read_mtime_ctrl reg - li TMP, MEM_MTIME_CTRL - lw \reg, 0(TMP) -.endm - -.macro _read_mtime_div reg - li TMP, MEM_MTIME_DIV - lw \reg, 0(TMP) -.endm - -// Misc -.macro _run_timer - li TMP, MEM_MTIME_CTRL - lw TMP2, 0(TMP) - li TMP3, (1 << SCR1_MTIME_CTRL_EN) - or TMP2, TMP2, TMP3 - sw TMP2, 0(TMP) -.endm - -.macro _stop_timer - li TMP, MEM_MTIME_CTRL - lw TMP2, 0(TMP) - li TMP3, (1 << SCR1_MTIME_CTRL_EN) - not TMP3, TMP3 - and TMP2, TMP2, TMP3 - sw TMP2, 0(TMP) -.endm - - - -#endif // #ifndef __TIMER__H
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/Makefile b/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/Makefile deleted file mode 100644 index 0558434..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/Makefile +++ /dev/null
@@ -1,202 +0,0 @@ -## @file -## Syntacore SCR* tests -## -## @copyright 2015-2018 Syntacore. All rights reserved. -## RISCV-Compliance -## - -ARCH ?=im -override ARCH:=rv32$(ARCH) - -src_dir := $(CURDIR) -RISCV_COMPLIANCE_TESTS := $(src_dir)/../../../dependencies/riscv-compliance/ - -#I IM IMC IC -#EM EMC EC - -ifeq (rv32e,$(findstring rv32e,$(ARCH))) - $(info >>> RV32E - no compliance tests) -else ## ifdef SCR_BASE_RVE_EXT - #ifeq (rv32i,$(findstring rv32i,$(ARCH))) - ifeq ($(ARCH),$(filter $(ARCH),rv32i rv32im rv32imc rv32ic)) - $(info >>> I32 TESTS) - included_i += $(filter %.S,\ - $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32i/src/*)) - included_i += $(filter %.S,\ - $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32Zicsr/src/*)) - included_i += $(filter %.S,\ - $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32Zifencei/src/*)) - compliance_set += $(included_i) - endif - - #$(if or ifeq(rv32im,$(findstring rv32im,$(ARCH))), (rv32imc,$(findstring rv32imc,$(ARCH)))) - ifeq ($(ARCH),$(filter $(ARCH), rv32im rv32imc)) - $(info >>> IM32 TESTS) - included_im += $(filter %.S,\ - $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32im/src/*)) - compliance_set += $(included_im) - endif ## - - ifeq (rv32imc,$(findstring rv32imc,$(ARCH))) - $(info >>> IMC32 TESTS) - included_imc += $(filter %.S,\ - $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32imc/src/*)) - compliance_set += $(included_imc) - endif ## ifeq (rv32imc,$(findstring rv32imc,$(ARCH))) - ifeq (rv32ic,$(findstring rv32ic,$(ARCH))) - endif -endif ## - - -$(info >>>$(ARCH) set included) - -ifeq ($(compliance_set),) -$(info >>> No compliance tests included) -endif - -$(info >>>>> compliance set: $(compliance_set)) - -dst_dir := $(bld_dir) -test_name := riscv_compliance -bld_dir := $(addprefix $(dst_dir)/, $(test_name)) -obj_dir := $(bld_dir)/riscv_compliance_objs - -#cut_list += scall csr shamt simple -cut_list += I-MISALIGN_JMP-01 I-MISALIGN_LDST-01 I-EBREAK-01 I-ECALL-01 -reference_src += $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32i*/*/*.reference_output) -reference_src += $(wildcard $(RISCV_COMPLIANCE_TESTS)/riscv-test-suite/rv32Zi*/*/*.reference_output) -testnames := $(basename $(notdir $(compliance_set))) -filtered := $(filter-out $(cut_list),$(testnames)) -objs := $(addprefix $(bld_dir)/,$(filtered:%=%.o)) -test_elf := $(addprefix $(dst_dir)/compliance_,$(filtered:%=%.elf)) -test_hex := $(addprefix $(dst_dir)/compliance_,$(filtered:%=%.hex)) -test_dump := $(addprefix $(bld_dir)/compliance_,$(filtered:%=%.dump)) - -compliance_macros_file := $(root_dir)/tests/riscv_compliance/compliance_io.h -compliance_output ?= true - -testnames_i := $(basename $(notdir $(included_i))) -testnames_im := $(basename $(notdir $(included_im))) -testnames_imc := $(basename $(notdir $(included_imc))) -filtered_i := $(filter-out $(cut_list),$(testnames_i)) -filtered_im := $(filter-out $(cut_list),$(testnames_im)) -filtered_imc := $(filter-out $(cut_list),$(testnames_imc)) - -# ARCH_FLAGS := -Wa,-march=rv32im -march=rv32im -# ARCH_FLAGS_C := -Wa,-march=rv32imc -march=rv32imc -CFLAGS := -I$(inc_dir) -I$(src_dir) -DASM -mabi=ilp32 -D__riscv_xlen=32 -w -LDFLAGS := -static -fvisibility=hidden -nostdlib -nostartfiles -T$(inc_dir)/link.ld -march=$(ARCH) -mabi=ilp32 -GCCVERSIONGT7 := $(shell expr `$(RISCV_GCC) -dumpfullversion | cut -f1 -d'.'` \> 7) -ifeq "$(GCCVERSIONGT7)" "1" - LDFLAGS += -mno-relax -endif -VPATH += $(src_dir) $(bld_dir) $(obj_dir) $(asm_path) $(ref_path) $(RISCV_COMPLIANCE_TESTS) - -ifeq ($(compliance_output), true) -CFLAGS += -D_COMPLIANCE_OUTPUT -endif - -default: clean log_requested_tgt check_version cp_asm ref_data $(test_elf) $(test_hex) $(test_dump) - -define compile_template -$(obj_dir)/$(1).o: $(obj_dir) cp_asm - $(RISCV_GCC) -c $$(bld_dir)/compliance_asm/$(1).S $$(CFLAGS) -Wa,$(2) $(2) -o $$@ -endef - -define preprocessing -for test_asm in $(1); do \ -march_tmp=$$test_asm ; \ -march_tmp=$${march_tmp%/src*} ; \ -march_tmp=$$(basename $$march_tmp) ; \ -file_name="$$(basename $${test_asm})" ; \ -$(RISCV_GCC) $(CFLAGS) -Wa,$(2) $(2) -E $$test_asm \ --o $(bld_dir)/compliance_asm/$$file_name ; \ -done -endef - -$(foreach SRC,$(filtered_i),$(eval $(call compile_template,$(SRC),-march=rv32i))) -$(foreach SRC,$(filtered_im),$(eval $(call compile_template,$(SRC),-march=rv32im))) -$(foreach SRC,$(filtered_imc),$(eval $(call compile_template,$(SRC),-march=rv32imc))) - - -log_requested_tgt: $(bld_dir) - $(foreach test_name, $(filtered), $(eval $(shell echo compliance_$(test_name).hex >> $(bld_dir)/../test_info))) - -$(bld_dir) : - mkdir -p $(bld_dir) - -$(obj_dir) : | ref_data - mkdir -p $(obj_dir) - -$(dst_dir)/compliance_%.elf: $(obj_dir)/%.o | $(dep_files) - $(RISCV_GCC) $^ $(LDFLAGS) -o $@ -g - -$(dst_dir)/compliance_%.hex: $(dst_dir)/compliance_%.elf - $(RISCV_ROM_OBJCOPY) $^ $@ - $(RISCV_RAM_OBJCOPY) $^ $@.ram - #assign 0x0048_0xxx to 0x0000_0xxx to map to TCM Memory - sed -i 's/@00480/@00000/g' $@.ram - -$(bld_dir)/compliance_%.dump: $(dst_dir)/compliance_%.elf - $(RISCV_OBJDUMP) -D -w -x -S $^ > $@ - -ref_data: - mkdir -p $(bld_dir)/ref_data - for files in $(reference_src) ; do \ - sed_input=$$files ; \ - sed_output=$$(basename $${files%.*}) ; \ - sed "s/\r$$//; \ - s/\(........\)/\1,/g; \ - s/.$$//; s/\(.*\),\(.*\),\(.*\),\(.*\)/\4,\3,\2,\1/; \ - s/\(.........\)/\10x/g; s/^/0x/; s/$$/,/; $$ s/.$$//" $$sed_input > $(bld_dir)/ref_data/$$sed_output; \ - done - -cp_asm: - mkdir -p $(bld_dir)/compliance_asm - $(call preprocessing,$(included_i),-march=rv32i) - $(call preprocessing,$(included_im),-march=rv32im) - $(call preprocessing,$(included_imc),-march=rv32imc) - - -riscv_compliance_tests_dir := $(if $(RISCV_COMPLIANCE_TESTS), $(RISCV_COMPLIANCE_TESTS), ./undefined) -riscv_tests_commit := d51259b2a949be3af02e776c39e135402675ac9b -## commit hash readed from local copy of https://github.com/riscv/riscv-compliance -tmp_commit = $(shell cd $(riscv_compliance_tests_dir) 2>/dev/null && git log -1 | grep "commit" | cut -f2 -d ' ') -is_commit_good = $(if $(subst $(riscv_tests_commit),,$(tmp_commit)),false,true) - -# Color -RED=\033[0;31m -NC=\033[0m - -check_version : $(riscv_compliance_tests_dir) - @if [ ! -d $(riscv_compliance_tests_dir) ]; then \ - echo -e "$(RED)==========================================================================" &&\ - echo " Error! Environment variable RISCV_COMPLIANCE_TESTS='$(riscv_compliance_tests_dir)' " &&\ - echo " directory not exist!" && \ - echo "==========================================================================$(NC)" ; \ - fi -ifneq ($(is_commit_good),true) - @echo -e "$(RED)==========================================================================" - @echo " Warning! Execution of test code is not guaranteed " - @echo " while using the current commit of repository located at : $(riscv_compliance_tests_dir) ." - @echo " " - @echo " riscv_compliance repository must point to commit $(riscv_tests_commit)!" - @echo -e "==========================================================================$(NC)" -endif - -$(riscv_compliance_tests_dir) :. -ifndef RISCV_COMPLIANCE_TESTS - @echo -e "$(RED)==========================================================================" - @echo " Error! Environment variable RISCV_COMPLIANCE_TESTS not set!" - @echo " You must set the environment variable RISCV_COMPLIANCE_TESTS" - @echo " The variable should point to the local copy of the" - @echo " repository https://github.com/riscv/riscv-compliance" - @echo " with the commit $(riscv_tests_commit)" - @echo -e "==========================================================================$(NC)" - exit 1 -endif - -clean: - $(RM) -R $(test_elf) $(test_hex) $(bld_dir) - -.PHONY: check_version clean ref_data cp_asm default
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/aw_test_macros.h b/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/aw_test_macros.h deleted file mode 100644 index 3e052a1..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/aw_test_macros.h +++ /dev/null
@@ -1,683 +0,0 @@ -/* - COPY OF /riscv-compliance/riscv-test-env/aw_test_macros.h - */ - -// See LICENSE for license details. - -#ifndef __TEST_MACROS_SCALAR_H -#define __TEST_MACROS_SCALAR_H - - -#----------------------------------------------------------------------- -# Helper macros -#----------------------------------------------------------------------- - -#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1)) - -#define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: srli a0, a0, 31; la t0, begin_signature; sw a0, 0(t0) - -#define TESTNUM gp - -#define SWSIG( testnum, testreg ) \ - la x28, test_res; \ - sw testreg, (testnum<<2)(x28); \ - -# -# Address = base+(testnum<<2) -# sw testreg, (testnum<<2)(basereg) -# -#define TEST_CASE( testnum, testreg, correctval, code... ) \ -test_ ## testnum: \ - code; \ - li x29, MASK_XLEN(correctval); \ - li TESTNUM, testnum; \ - SWSIG(testnum,testreg); \ - bne testreg, x29, fail; - -# We use a macro hack to simpify code generation for various numbers -# of bubble cycles. - -#define TEST_INSERT_NOPS_0 -#define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0 -#define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1 -#define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2 -#define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3 -#define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4 -#define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5 -#define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6 -#define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7 -#define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8 -#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9 - - -#----------------------------------------------------------------------- -# RV64UI MACROS -#----------------------------------------------------------------------- - -#----------------------------------------------------------------------- -# Tests for instructions with immediate operand -#----------------------------------------------------------------------- - -#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) - -#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \ - TEST_CASE( testnum, x30, result, \ - li x1, MASK_XLEN(val1); \ - inst x30, x1, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \ - TEST_CASE( testnum, x1, result, \ - li x1, MASK_XLEN(val1); \ - inst x1, x1, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ - TEST_CASE( testnum, x6, result, \ - li x4, 0; \ -1: li x1, MASK_XLEN(val1); \ - inst x30, x1, SEXT_IMM(imm); \ - TEST_INSERT_NOPS_ ## nop_cycles \ - addi x6, x30, 0; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ - TEST_CASE( testnum, x30, result, \ - li x4, 0; \ -1: li x1, MASK_XLEN(val1); \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x30, x1, SEXT_IMM(imm); \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \ - TEST_CASE( testnum, x1, result, \ - inst x1, x0, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \ - TEST_CASE( testnum, x0, 0, \ - li x1, MASK_XLEN(val1); \ - inst x0, x1, SEXT_IMM(imm); \ - ) - -#----------------------------------------------------------------------- -# Tests for an instruction with register operands -#----------------------------------------------------------------------- - -#define TEST_R_OP( testnum, inst, result, val1 ) \ - TEST_CASE( testnum, x30, result, \ - li x1, val1; \ - inst x30, x1; \ - ) - -#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \ - TEST_CASE( testnum, x1, result, \ - li x1, val1; \ - inst x1, x1; \ - ) - -#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \ - TEST_CASE( testnum, x6, result, \ - li x4, 0; \ -1: li x1, val1; \ - inst x30, x1; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - addi x6, x30, 0; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#----------------------------------------------------------------------- -# Tests for an instruction with register-register operands -#----------------------------------------------------------------------- - -#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x30, result, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x30, x1, x2; \ - ) - -#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x1, result, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x1, x1, x2; \ - ) - -#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x2, result, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x2, x1, x2; \ - ) - -#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \ - TEST_CASE( testnum, x1, result, \ - li x1, MASK_XLEN(val1); \ - inst x1, x1, x1; \ - ) - -#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x6, result, \ - li x4, 0; \ -1: li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x30, x1, x2; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - addi x6, x30, 0; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x30, result, \ - li x4, 0; \ -1: li x1, MASK_XLEN(val1); \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x2, MASK_XLEN(val2); \ - TEST_INSERT_NOPS_ ## src2_nops \ - inst x30, x1, x2; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ - TEST_CASE( testnum, x30, result, \ - li x4, 0; \ -1: li x2, MASK_XLEN(val2); \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x1, MASK_XLEN(val1); \ - TEST_INSERT_NOPS_ ## src2_nops \ - inst x30, x1, x2; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - ) - -#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \ - TEST_CASE( testnum, x2, result, \ - li x1, MASK_XLEN(val); \ - inst x2, x0, x1; \ - ) - -#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \ - TEST_CASE( testnum, x2, result, \ - li x1, MASK_XLEN(val); \ - inst x2, x1, x0; \ - ) - -#define TEST_RR_ZEROSRC12( testnum, inst, result ) \ - TEST_CASE( testnum, x1, result, \ - inst x1, x0, x0; \ - ) - -#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \ - TEST_CASE( testnum, x0, 0, \ - li x1, MASK_XLEN(val1); \ - li x2, MASK_XLEN(val2); \ - inst x0, x1, x2; \ - ) - -#----------------------------------------------------------------------- -# Test memory instructions -#----------------------------------------------------------------------- - -#define TEST_LD_OP( testnum, inst, result, offset, base ) \ - TEST_CASE( testnum, x30, result, \ - la x1, base; \ - inst x30, offset(x1); \ - ) - -#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \ - TEST_CASE( testnum, x30, result, \ - la x1, base; \ - li x2, result; \ - store_inst x2, offset(x1); \ - load_inst x30, offset(x1); \ - ) - -#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - li x4, 0; \ -1: la x1, base; \ - inst x30, offset(x1); \ - TEST_INSERT_NOPS_ ## nop_cycles \ - addi x6, x30, 0; \ - li x29, result; \ - bne x6, x29, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b; \ - -#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - li x4, 0; \ -1: la x1, base; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x30, offset(x1); \ - li x29, result; \ - bne x30, x29, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - li x4, 0; \ -1: li x1, result; \ - TEST_INSERT_NOPS_ ## src1_nops \ - la x2, base; \ - TEST_INSERT_NOPS_ ## src2_nops \ - store_inst x1, offset(x2); \ - load_inst x30, offset(x2); \ - li x29, result; \ - bne x30, x29, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - li x4, 0; \ -1: la x2, base; \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x1, result; \ - TEST_INSERT_NOPS_ ## src2_nops \ - store_inst x1, offset(x2); \ - load_inst x30, offset(x2); \ - li x29, result; \ - bne x30, x29, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - li x1, val1; \ - li x2, val2; \ - inst x1, x2, 2f; \ - bne x0, TESTNUM, fail; \ -1: bne x0, TESTNUM, 3f; \ -2: inst x1, x2, 1b; \ - bne x0, TESTNUM, fail; \ -3: - -#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - li x1, val1; \ - li x2, val2; \ - inst x1, x2, 1f; \ - bne x0, TESTNUM, 2f; \ -1: bne x0, TESTNUM, fail; \ -2: inst x1, x2, 1b; \ -3: - -#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - li x4, 0; \ -1: li x1, val1; \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x2, val2; \ - TEST_INSERT_NOPS_ ## src2_nops \ - inst x1, x2, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - li x4, 0; \ -1: li x2, val2; \ - TEST_INSERT_NOPS_ ## src1_nops \ - li x1, val1; \ - TEST_INSERT_NOPS_ ## src2_nops \ - inst x1, x2, fail; \ - addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#----------------------------------------------------------------------- -# Test jump instructions -#----------------------------------------------------------------------- - -#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - li x4, 0; \ -1: la x6, 2f; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x6; \ - bne x0, TESTNUM, fail; \ -2: addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - -#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - li x4, 0; \ -1: la x6, 2f; \ - TEST_INSERT_NOPS_ ## nop_cycles \ - inst x19, x6, 0; \ - bne x0, TESTNUM, fail; \ -2: addi x4, x4, 1; \ - li x5, 2; \ - bne x4, x5, 1b \ - - -#----------------------------------------------------------------------- -# RV64UF MACROS -#----------------------------------------------------------------------- - -#----------------------------------------------------------------------- -# Tests floating-point instructions -#----------------------------------------------------------------------- - -#define qNaNf 0f:7fc00000 -#define sNaNf 0f:7f800001 -#define qNaN 0d:7ff8000000000000 -#define sNaN 0d:7ff0000000000001 - -#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - la a0, test_ ## testnum ## _data ;\ - flw f0, 0(a0); \ - flw f1, 4(a0); \ - flw f2, 8(a0); \ - lw a3, 12(a0); \ - code; \ - fsflags a1, x0; \ - li a2, flags; \ - bne a0, a3, fail; \ - bne a1, a2, fail; \ - .pushsection .data; \ - .align 2; \ - test_ ## testnum ## _data: \ - .float val1; \ - .float val2; \ - .float val3; \ - .result; \ - .popsection - -#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - la a0, test_ ## testnum ## _data ;\ - fld f0, 0(a0); \ - fld f1, 8(a0); \ - fld f2, 16(a0); \ - ld a3, 24(a0); \ - code; \ - fsflags a1, x0; \ - li a2, flags; \ - bne a0, a3, fail; \ - bne a1, a2, fail; \ - .pushsection .data; \ - .align 3; \ - test_ ## testnum ## _data: \ - .double val1; \ - .double val2; \ - .double val3; \ - .result; \ - .popsection - -// TODO: assign a separate mem location for the comparison address? -#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - la a0, test_ ## testnum ## _data ;\ - fld f0, 0(a0); \ - fld f1, 8(a0); \ - fld f2, 16(a0); \ - lw a3, 24(a0); \ - lw t1, 28(a0); \ - code; \ - fsflags a1, x0; \ - li a2, flags; \ - bne a0, a3, fail; \ - bne t1, t2, fail; \ - bne a1, a2, fail; \ - .pushsection .data; \ - .align 3; \ - test_ ## testnum ## _data: \ - .double val1; \ - .double val2; \ - .double val3; \ - .result; \ - .popsection - -#define TEST_FCVT_S_D32( testnum, result, val1 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ - fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) - -#define TEST_FCVT_S_D( testnum, result, val1 ) \ - TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ - fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3) - -#define TEST_FCVT_D_S( testnum, result, val1 ) \ - TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \ - fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3) - -#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.s a0, f3) - -#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ - inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) -// ^: store computation result in address from a0, load high-word into t2 - -#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.d a0, f3) - -#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.s a0, f3) - -#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) -// ^: store computation result in address from a0, load high-word into t2 - -#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst f3, f0; fmv.x.d a0, f3) - -#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \ - inst f3, f0, f1; fmv.x.s a0, f3) - -#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ - inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) -// ^: store computation result in address from a0, load high-word into t2 - -#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ - inst f3, f0, f1; fmv.x.d a0, f3) - -#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \ - inst f3, f0, f1, f2; fmv.x.s a0, f3) - -#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \ - inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) -// ^: store computation result in address from a0, load high-word into t2 - -#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \ - inst f3, f0, f1, f2; fmv.x.d a0, f3) - -#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ - inst a0, f0, rm) - -#define TEST_FP_INT_OP_D32( testnum, inst, flags, result, val1, rm ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst a0, f0, f1; li t2, 0) - -#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst a0, f0, rm) - -#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \ - inst a0, f0, f1) - -#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ - inst a0, f0, f1; li t2, 0) - -#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ - inst a0, f0, f1) - -#define TEST_FCLASS_S(testnum, correct, input) \ - TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \ - fclass.s a0, fa0) - -#define TEST_FCLASS_D32(testnum, correct, input) \ - TEST_CASE(testnum, a0, correct, \ - la a0, test_ ## testnum ## _data ;\ - fld fa0, 0(a0); \ - fclass.d a0, fa0) \ - .pushsection .data; \ - .align 3; \ - test_ ## testnum ## _data: \ - .dword input; \ - .popsection - -#define TEST_FCLASS_D(testnum, correct, input) \ - TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \ - fclass.d a0, fa0) - -#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - la a0, test_ ## testnum ## _data ;\ - lw a3, 0(a0); \ - li a0, val1; \ - inst f0, a0; \ - fsflags x0; \ - fmv.x.s a0, f0; \ - bne a0, a3, fail; \ - .pushsection .data; \ - .align 2; \ - test_ ## testnum ## _data: \ - .float result; \ - .popsection - -#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - la a0, test_ ## testnum ## _data ;\ - lw a3, 0(a0); \ - lw a4, 4(a0); \ - li a1, val1; \ - inst f0, a1; \ - \ - fsd f0, 0(a0); \ - lw a1, 4(a0); \ - lw a0, 0(a0); \ - \ - fsflags x0; \ - bne a0, a3, fail; \ - bne a1, a4, fail; \ - .pushsection .data; \ - .align 3; \ - test_ ## testnum ## _data: \ - .double result; \ - .popsection - -#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - la a0, test_ ## testnum ## _data ;\ - ld a3, 0(a0); \ - li a0, val1; \ - inst f0, a0; \ - fsflags x0; \ - fmv.x.d a0, f0; \ - bne a0, a3, fail; \ - .pushsection .data; \ - .align 3; \ - test_ ## testnum ## _data: \ - .double result; \ - .popsection - -// We need some special handling here to allow 64-bit comparison in 32-bit arch -// TODO: find a better name and clean up when intended for general usage? -#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \ -test_ ## testnum: \ - code; \ - la x31, test_ ## testnum ## _data ; \ - lw x29, 0(x31); \ - lw x31, 4(x31); \ - li TESTNUM, testnum; \ - SWSIG (testnum, TESTNUM);\ - bne testreg1, x29, fail;\ - bne testreg2, x31, fail;\ - .pushsection .data; \ - .align 3; \ - test_ ## testnum ## _data: \ - .dword correctval; \ - .popsection - -// ^ x30 is used in some other macros, to avoid issues we use x31 for upper word - -#----------------------------------------------------------------------- -# Pass and fail code (assumes test num is in TESTNUM) -#----------------------------------------------------------------------- - -#define TEST_PASSFAIL \ - bne x0, TESTNUM, pass; \ -fail: \ - RVTEST_FAIL; \ -pass: \ - RVTEST_PASS \ - - -#----------------------------------------------------------------------- -# Test data section -#----------------------------------------------------------------------- - -#define TEST_DATA - -#endif
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/compliance_io.h b/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/compliance_io.h deleted file mode 100644 index 5b7ca54..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/compliance_io.h +++ /dev/null
@@ -1,70 +0,0 @@ -// RISC-V Compliance IO Test Header File - -/* - * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, - * either express or implied. - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -#ifndef _COMPLIANCE_IO_H -#define _COMPLIANCE_IO_H - -//----------------------------------------------------------------------- -// RV IO Macros (Non functional) -//----------------------------------------------------------------------- -#ifdef _COMPLIANCE_OUTPUT - -#define RVTEST_IO_PUSH(_SP) \ -la _SP, begin_regstate; \ -sw x3, 0(_SP); \ -sw x4, 4(_SP); \ -sw x5, 8(_SP); - -#define RVTEST_IO_POP(_SP) \ -la _SP, begin_regstate; \ -lw x3, 0(_SP); \ -lw x4, 4(_SP); \ -lw x5, 8(_SP); - -#define RVTEST_IO_WRITE_STR(_SP, _STR) \ - .section .data.string; \ -20001: \ - .string _STR; \ - .section .text; \ - RVTEST_IO_PUSH(_SP) \ - li x3, 0xF0000000; \ - la x4, 20001b; \ -2: lb x5, 0(x4); \ - sb x5, 0(x3); \ - beq x5, zero, 1f; \ - add x4, x4, 1; \ - j 2b; \ -1: RVTEST_IO_POP(_SP) - -#else // #ifdef _COMPLIANCE_OUTPUT - -#define RVTEST_IO_WRITE_STR(_SP, _STR) - -#endif // #end #ifdef _COMPLIANCE_OUTPUT - -#define RVTEST_IO_INIT -#define RVTEST_IO_CHECK() -#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I) -#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I) -#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I) -#define RVTEST_IO_ASSERT_EQ(_R, _I) - -#endif // _COMPLIANCE_IO_H
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/compliance_test.h b/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/compliance_test.h deleted file mode 100644 index 0c7e7f9..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/compliance_test.h +++ /dev/null
@@ -1,31 +0,0 @@ -// RISC-V Compliance Test Header File -// Copyright (c) 2017, Codasip Ltd. All Rights Reserved. -// See LICENSE for license details. -// -// Description: Common header file for RV32I tests - -#ifndef _COMPLIANCE_TEST_H -#define _COMPLIANCE_TEST_H - -//----------------------------------------------------------------------- -// RV Compliance Macros -//----------------------------------------------------------------------- - -#define RV_COMPLIANCE_HALT \ - -#define RV_COMPLIANCE_RV32M \ - RVTEST_RV32M \ - -#define RV_COMPLIANCE_CODE_BEGIN \ - RVTEST_CODE_BEGIN \ - -#define RV_COMPLIANCE_CODE_END \ - RVTEST_CODE_END \ - -#define RV_COMPLIANCE_DATA_BEGIN \ - RVTEST_DATA_BEGIN \ - -#define RV_COMPLIANCE_DATA_END \ - RVTEST_DATA_END \ - -#endif \ No newline at end of file
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/riscv_test.h b/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/riscv_test.h deleted file mode 100644 index fdc6156..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/riscv_test.h +++ /dev/null
@@ -1,7 +0,0 @@ - -#ifndef _RISCV_TEST_H -#define _RISCV_TEST_H - -#include "test_macros.h" - -#endif \ No newline at end of file
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/riscv_test_macros.h b/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/riscv_test_macros.h deleted file mode 100644 index 6717bd4..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/riscv_test_macros.h +++ /dev/null
@@ -1,463 +0,0 @@ -// RISC-V Compliance IO Test Header File - -/* - * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, - * either express or implied. - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -#include "riscv_macros.h" - -// -// In general the following registers are reserved -// ra, a0, t0, t1 -// Additionally on an assertion violation, t1, t2 are overwritten -// x1, x10, x5, x6, x7 respectively -// Floating registers reserved -// f5 -// - -#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1)) - -#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) - -// Base function for integer operations -#define TEST_CASE(testreg, destreg, correctval, swreg, offset, code... ) \ - code; \ - sw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) \ - -// Base functions for single precision floating point operations -#define TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - flw reg1, 0(a0); \ - flw reg2, 4(a0); \ - lw t1, 8(a0); \ - code; \ - fsw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \ - .pushsection .data; \ - .align 3; \ - test_ ## test_num ## _data: \ - .float val1; \ - .float val2; \ - .word correctval; \ - .popsection - -#define TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - lw t1, 0(a0); \ - code; \ - fsw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \ - .pushsection .data; \ - .align 1; \ - test_ ## test_num ## _data: \ - .word correctval; \ - .popsection - -#define TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - flw reg, 0(a0); \ - lw t1, 4(a0); \ - code; \ - sw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \ - .pushsection .data; \ - .align 2; \ - test_ ## test_num ## _data: \ - .float val; \ - .word correctval; \ - .popsection - -#define TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - flw reg1, 0(a0); \ - flw reg2, 4(a0); \ - flw reg3, 8(a0); \ - lw t1, 12(a0); \ - code; \ - fsw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \ - .pushsection .data; \ - .align 4; \ - test_ ## test_num ## _data: \ - .float val1; \ - .float val2; \ - .float val3; \ - .word correctval; \ - .popsection - -#define TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - flw reg, 0(a0); \ - code; \ - sw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \ - .pushsection .data; \ - .align 1; \ - test_ ## test_num ## _data: \ - .float val; \ - .popsection - -#define TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, code...) \ - la a0, test_ ## test_num ## _data; \ - li reg, val; \ - code; \ - fsw destreg, offset(swreg); \ - lw a1, 0(a0); \ - RVTEST_IO_ASSERT_SFPR_EQ(destreg, a1, correctval) \ - .pushsection .data; \ - .align 1; \ - test_ ## test_num ## _data: \ - .word correctval; \ - .popsection - -// Base functions for double precision floating point operations - rv32d -#define TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - fld reg1, 0(a0); \ - fld reg2, 8(a0); \ - code; \ - fsd destreg, offset(swreg); \ - lw t1, 16(a0); \ - lw t2, 20(a0); \ - la a0, store_ ## test_num ## _data; \ - fsd destreg, 0(a0); \ - lw a1, 0(a0); \ - lw a2, 4(a0); \ - RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \ - .pushsection .data; \ - .align 3; \ - test_ ## test_num ## _data: \ - .double val1; \ - .double val2; \ - .dword correctval; \ - .popsection; \ - .pushsection .data; \ - store_ ## test_num ## _data: \ - .fill 1, 8, -1; \ - .popsection - -#define TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - code; \ - fsd destreg, offset(swreg); \ - lw t1, 0(a0); \ - lw t2, 4(a0); \ - la a0, store_ ## test_num ## _data; \ - fsd destreg, 0(a0); \ - lw a1, 0(a0); \ - lw a2, 4(a0); \ - RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \ - .pushsection .data; \ - .align 1; \ - test_ ## test_num ## _data: \ - .dword correctval; \ - .popsection; \ - store_ ## test_num ## _data: \ - .fill 1, 8, -1; \ - .popsection - -#define TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - fld reg, 0(a0); \ - lw t1, 8(a0); \ - code; \ - sw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \ - .pushsection .data; \ - .align 2; \ - test_ ## test_num ## _data: \ - .double val; \ - .word correctval; \ - .popsection - -#define TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - fld reg1, 0(a0); \ - fld reg2, 8(a0); \ - fld reg3, 16(a0); \ - code; \ - fsd destreg, offset(swreg); \ - lw t1, 24(a0); \ - lw t2, 28(a0); \ - la a0, store_ ## test_num ## _data; \ - fsd destreg, 0(a0); \ - lw a1, 0(a0); \ - lw a2, 4(a0); \ - RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \ - .pushsection .data; \ - .align 4; \ - test_ ## test_num ## _data: \ - .double val1; \ - .double val2; \ - .double val3; \ - .dword correctval; \ - .popsection; \ - .pushsection .data; \ - store_ ## test_num ## _data: \ - .fill 1, 8, -1; \ - .popsection - -//Tests for a instructions with register-register operand -#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - li reg1, MASK_XLEN(val1); \ - li reg2, MASK_XLEN(val2); \ - inst destreg, reg1, reg2; \ - ) - -#define TEST_RR_SRC1( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - li destreg, MASK_XLEN(val1); \ - li reg, MASK_XLEN(val2); \ - inst destreg, destreg, reg; \ - ) - -#define TEST_RR_SRC2( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - li reg, MASK_XLEN(val1); \ - li destreg, MASK_XLEN(val2); \ - inst destreg, reg, destreg; \ - ) - -#define TEST_RR_SRC12( inst, destreg, correctval, val, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - li destreg, MASK_XLEN(val1); \ - inst destreg, destreg, destreg; \ - ) - -#define TEST_RR_ZERO1( inst, destreg, reg, correctval, val, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - li reg, MASK_XLEN(val); \ - inst destreg, x0, reg; \ - ) - -#define TEST_RR_ZERO2( inst, destreg, reg, correctval, val, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - li reg, MASK_XLEN(val); \ - inst destreg, reg, x0; \ - ) - -#define TEST_RR_ZERO12( inst, destreg, correctval, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - inst destreg, x0, x0; \ - ) - -#define TEST_RR_ZERODEST( inst, reg1, reg2, val1, val2, swreg, offset, testreg) \ - TEST_CASE(testreg, x0, 0, swreg, offset, \ - li reg1, MASK_XLEN(val1); \ - li reg2, MASK_XLEN(val2); \ - inst x0, reg1, reg2; \ - ) - -//Tests for a instructions with register-immediate operand -#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - li reg, MASK_XLEN(val); \ - inst destreg, reg, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_SRC( inst, destreg, correctval, val, imm, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - li destreg, MASK_XLEN(val); \ - inst destreg, destreg, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_ZEROSRC( inst, destreg, correctval, imm, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - inst destreg, x0, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_ZERODEST( inst, reg, val, imm, swreg, offset, testreg) \ - TEST_CASE(testreg, x0, 0, swreg, offset, \ - li reg, MASK_XLEN(val); \ - inst x0, reg, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_ONEREG( inst, destreg, correctval, imm, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - inst destreg, SEXT_IMM(imm); \ - ) - -#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - 1: \ - inst destreg, imm; \ - la swreg, 1b; \ - sub destreg, destreg, swreg; \ - ) - -//Tests for a compressed instruction -#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - li reg, MASK_XLEN(val1); \ - li destreg, MASK_XLEN(val2); \ - inst destreg, reg; \ - ) - -#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset, testreg) \ - TEST_CASE(testreg, destreg, correctval, swreg, offset, \ - li destreg, MASK_XLEN(val); \ - inst destreg, imm; \ - ) - -#define TEST_CI_OP_NOREG(inst, correctval, imm, swreg, offset, testreg) \ - TEST_CASE(testreg,x0, correctval, swreg, offset, \ - inst imm; \ - ) - -//Tests for floating point instructions - single precision -#define TEST_FP_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \ - TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \ - inst destreg, reg1, reg2; \ - ) - -#define TEST_FP_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FP(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \ - inst destreg, reg; \ - ) - -#define TEST_FP_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \ - TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \ - inst destreg, reg1, reg2, reg3; \ - ) - -#define TEST_FP_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, \ - li reg, MASK_XLEN(val); \ - inst destreg, reg; \ - ) - -#define TEST_FP_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, \ - inst destreg, reg; \ - ) - -//Tests for floating point instructions - double precision -#define TEST_FPD_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \ - TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \ - inst destreg, reg1, reg2; \ - ) - -#define TEST_FPD_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FPD(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \ - inst destreg, reg; \ - ) - -#define TEST_FPD_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \ - TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \ - inst destreg, reg1, reg2, reg3; \ - ) - -#define TEST_FPD_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, \ - li reg, MASK_XLEN(val); \ - inst destreg, reg; \ - ) - -#define TEST_FPD_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, \ - inst destreg, reg; \ - ) - -#define TEST_CADDI16SP(correctval, imm, swreg, offset, testreg) \ - TEST_CASE(testreg,x2, correctval, swreg, offset, \ - c.addi16sp x2, imm; \ - ) - -#define TEST_CADDI4SPN(destreg, correctval, imm, swreg, offset, testreg) \ - TEST_CASE(testreg,destreg, correctval, swreg, offset, \ - c.addi4spn destreg, x2, SEXT_IMM(imm); \ - ) - -#define TEST_CJL(inst, reg, val, swreg, offset) \ - li x10, val; \ - la reg, 1f; \ - inst reg; \ - li x10, 0x123ab; \ -1: \ - sw x10, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, x10, val); \ - -#define ABS(x) ((x >> 11) ^ x) - (x >> 11) - -#define TEST_CJ(inst, reg, val, swreg, offset) \ - li reg, val; \ - inst 1f; \ - li reg, 0x123ab; \ -1: \ - sw reg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \ - -#define TEST_CL(inst, reg, imm, swreg, offset) \ - la reg, test_data; \ - inst reg, imm(reg); \ - sw reg, offset(swreg); \ - -// lw reg, imm(x2) -// c.lwsp reg, imm(x2) -#define TEST_CLWSP(reg, imm, swreg, offset) \ - la x2, test_data; \ - c.lwsp reg, imm(x2); \ - sw reg, offset(swreg); \ - -#define TEST_CSW(test_data, inst, reg1, reg2, val, imm, swreg, offset) \ - li reg1, val; \ - la reg2, test_data; \ - inst reg1, imm(reg2); \ - lw reg1, imm(reg2); \ - sw reg1, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, reg1, val); \ - -#define TEST_CSWSP(test_data, reg, val, imm, swreg, offset) \ - la x2, test_data; \ - li reg, val; \ - c.swsp reg, imm(x2); \ - lw reg, imm(x2); \ - sw reg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \ - -#define TEST_CBEQZ(reg, val, swreg, offset) \ - li reg, val; \ - c.sub reg, reg; \ - c.beqz reg, 3f; \ - li reg, 0x123ab; \ -3: \ - sw reg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, reg, 0x0); \ - -#define TEST_CBNEZ(reg, val, swreg, offset) \ - li reg, val; \ - c.bnez reg, 4f; \ - li reg, 0x0; \ -4: \ - sw reg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \ - -#define TEST_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, \ - fmv.x.s destreg, reg; \ - ) - -#define TEST_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, \ - fmv.s.x destreg, reg; \ - ) - -#define SWSIG(a,b) -
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/test_macros.h b/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/test_macros.h deleted file mode 100644 index b2c610e..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/riscv_compliance/test_macros.h +++ /dev/null
@@ -1,593 +0,0 @@ - -// RISC-V Compliance Test Header File -// Copyright (c) 2017, Codasip Ltd. All Rights Reserved. -// See LICENSE for license details. -// -// Description: Common header file for RV32I tests - -#ifndef _TEST_MACROS_H -#define _TEST_MACROS_H - -#include "riscv_macros.h" - -// RISC-V Compliance IO Test Header File - -/* - * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, - * either express or implied. - * - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - - -// -// In general the following registers are reserved -// ra, a0, t0, t1 -// Additionally on an assertion violation, t1, t2 are overwritten -// x1, x10, x5, x6, x7 respectively -// Floating registers reserved -// f5 -// - -#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1)) - -#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) - -// Base function for integer operations -#define TEST_CASE(destreg, correctval, swreg, offset, code... ) \ - code; \ - sw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \ - -// Base functions for single precision floating point operations -#define TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - flw reg1, 0(a0); \ - flw reg2, 4(a0); \ - lw t1, 8(a0); \ - code; \ - fsw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \ - .pushsection .data; \ - .balign 8; \ - test_ ## test_num ## _data: \ - .float val1; \ - .float val2; \ - .word correctval; \ - .popsection - -#define TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - lw t1, 0(a0); \ - code; \ - fsw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \ - .pushsection .data; \ - .balign 2; \ - test_ ## test_num ## _data: \ - .word correctval; \ - .popsection - -#define TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - flw reg, 0(a0); \ - lw t1, 4(a0); \ - code; \ - sw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \ - .pushsection .data; \ - .balign 4; \ - test_ ## test_num ## _data: \ - .float val; \ - .word correctval; \ - .popsection - -#define TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - flw reg1, 0(a0); \ - flw reg2, 4(a0); \ - flw reg3, 8(a0); \ - lw t1, 12(a0); \ - code; \ - fsw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_SFPR_EQ(destreg, t1, correctval) \ - .pushsection .data; \ - .balign 16; \ - test_ ## test_num ## _data: \ - .float val1; \ - .float val2; \ - .float val3; \ - .word correctval; \ - .popsection - -#define TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - flw reg, 0(a0); \ - code; \ - sw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \ - .pushsection .data; \ - .balign 2; \ - test_ ## test_num ## _data: \ - .float val; \ - .popsection - -#define TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, code...) \ - la a0, test_ ## test_num ## _data; \ - li reg, val; \ - code; \ - fsw destreg, offset(swreg); \ - lw a1, 0(a0); \ - RVTEST_IO_ASSERT_SFPR_EQ(destreg, a1, correctval) \ - .pushsection .data; \ - .balign 2; \ - test_ ## test_num ## _data: \ - .word correctval; \ - .popsection - -// Base functions for double precision floating point operations - rv32d -#define TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - fld reg1, 0(a0); \ - fld reg2, 8(a0); \ - code; \ - fsd destreg, offset(swreg); \ - lw t1, 16(a0); \ - lw t2, 20(a0); \ - la a0, store_ ## test_num ## _data; \ - fsd destreg, 0(a0); \ - lw a1, 0(a0); \ - lw a2, 4(a0); \ - RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \ - .pushsection .data; \ - .balign 8; \ - test_ ## test_num ## _data: \ - .double val1; \ - .double val2; \ - .dword correctval; \ - .popsection; \ - .pushsection .data; \ - store_ ## test_num ## _data: \ - .fill 1, 8, -1; \ - .popsection - -#define TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - code; \ - fsd destreg, offset(swreg); \ - lw t1, 0(a0); \ - lw t2, 4(a0); \ - la a0, store_ ## test_num ## _data; \ - fsd destreg, 0(a0); \ - lw a1, 0(a0); \ - lw a2, 4(a0); \ - RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \ - .pushsection .data; \ - .balign 2; \ - test_ ## test_num ## _data: \ - .dword correctval; \ - .popsection; \ - store_ ## test_num ## _data: \ - .fill 1, 8, -1; \ - .popsection - -#define TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - fld reg, 0(a0); \ - lw t1, 8(a0); \ - code; \ - sw destreg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, destreg, correctval) \ - .pushsection .data; \ - .balign 4; \ - test_ ## test_num ## _data: \ - .double val; \ - .word correctval; \ - .popsection - -#define TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, code... ) \ - la a0, test_ ## test_num ## _data; \ - fld reg1, 0(a0); \ - fld reg2, 8(a0); \ - fld reg3, 16(a0); \ - code; \ - fsd destreg, offset(swreg); \ - lw t1, 24(a0); \ - lw t2, 28(a0); \ - la a0, store_ ## test_num ## _data; \ - fsd destreg, 0(a0); \ - lw a1, 0(a0); \ - lw a2, 4(a0); \ - RVTEST_IO_ASSERT_DFPR_EQ(destreg, t2, t1, a2, a1, correctval) \ - .pushsection .data; \ - .balign 16; \ - test_ ## test_num ## _data: \ - .double val1; \ - .double val2; \ - .double val3; \ - .dword correctval; \ - .popsection; \ - .pushsection .data; \ - store_ ## test_num ## _data: \ - .fill 1, 8, -1; \ - .popsection - -//Tests for a instructions with register-register operand -#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \ - TEST_CASE( destreg, correctval, swreg, offset, \ - li reg1, MASK_XLEN(val1); \ - li reg2, MASK_XLEN(val2); \ - inst destreg, reg1, reg2; \ - ) - -#define TEST_RR_SRC1( inst, destreg, reg, correctval, val1, val2, swreg, offset) \ - TEST_CASE( destreg, correctval, swreg, offset, \ - li destreg, MASK_XLEN(val1); \ - li reg, MASK_XLEN(val2); \ - inst destreg, destreg, reg; \ - ) - -#define TEST_RR_SRC2( inst, destreg, reg, correctval, val1, val2, swreg, offset) \ - TEST_CASE( destreg, correctval, swreg, offset, \ - li reg, MASK_XLEN(val1); \ - li destreg, MASK_XLEN(val2); \ - inst destreg, reg, destreg; \ - ) - -#define TEST_RR_SRC12( inst, destreg, correctval, val, swreg, offset) \ - TEST_CASE( destreg, correctval, swreg, offset, \ - li destreg, MASK_XLEN(val1); \ - inst destreg, destreg, destreg; \ - ) - -#define TEST_RR_ZERO1( inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE( destreg, correctval, swreg, offset, \ - li reg, MASK_XLEN(val); \ - inst destreg, x0, reg; \ - ) - -#define TEST_RR_ZERO2( inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE( destreg, correctval, swreg, offset, \ - li reg, MASK_XLEN(val); \ - inst destreg, reg, x0; \ - ) - -#define TEST_RR_ZERO12( inst, destreg, correctval, swreg, offset) \ - TEST_CASE( destreg, correctval, swreg, offset, \ - inst destreg, x0, x0; \ - ) - -#define TEST_RR_ZERODEST( inst, reg1, reg2, val1, val2, swreg, offset) \ - TEST_CASE( x0, 0, swreg, offset, \ - li reg1, MASK_XLEN(val1); \ - li reg2, MASK_XLEN(val2); \ - inst x0, reg1, reg2; \ - ) - -//Tests for a instructions with register-immediate operand -#define TEST_IMM_OP( inst, destreg, reg, correctval, val, imm, swreg, offset) \ - TEST_CASE ( destreg, correctval, swreg, offset, \ - li reg, MASK_XLEN(val); \ - inst destreg, reg, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_SRC( inst, destreg, correctval, val, imm, swreg, offset) \ - TEST_CASE ( destreg, correctval, swreg, offset, \ - li destreg, MASK_XLEN(val); \ - inst destreg, destreg, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_ZEROSRC( inst, destreg, correctval, imm, swreg, offset) \ - TEST_CASE ( destreg, correctval, swreg, offset, \ - inst destreg, x0, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_ZERODEST( inst, reg, val, imm, swreg, offset) \ - TEST_CASE ( x0, 0, swreg, offset, \ - li reg, MASK_XLEN(val); \ - inst x0, reg, SEXT_IMM(imm); \ - ) - -#define TEST_IMM_ONEREG( inst, destreg, correctval, imm, swreg, offset) \ - TEST_CASE ( destreg, correctval, swreg, offset, \ - inst destreg, SEXT_IMM(imm); \ - ) - -#define TEST_AUIPC(inst, destreg, correctval, imm, swreg, offset) \ - TEST_CASE ( destreg, correctval, swreg, offset, \ - 1: \ - inst destreg, SEXT_IMM(imm); \ - la swreg, 1b; \ - sub destreg, destreg, swreg; \ - ) - -//Tests for a compressed instruction -#define TEST_CR_OP( inst, destreg, reg, correctval, val1, val2, swreg, offset) \ - TEST_CASE ( destreg, correctval, swreg, offset, \ - li reg, MASK_XLEN(val1); \ - li destreg, MASK_XLEN(val2); \ - inst destreg, reg; \ - ) - -#define TEST_CI_OP( inst, destreg, correctval, val, imm, swreg, offset) \ - TEST_CASE( destreg, correctval, swreg, offset, \ - li destreg, MASK_XLEN(val); \ - inst destreg, imm; \ - ) - -#define TEST_CI_OP_NOREG(inst, correctval, imm, swreg, offset) \ - TEST_CASE (x0, correctval, swreg, offset, \ - inst imm; \ - ) - -//Tests for floating point instructions - single precision -#define TEST_FP_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \ - TEST_CASE_FP(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \ - inst destreg, reg1, reg2; \ - ) - -#define TEST_FP_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FP(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \ - inst destreg, reg; \ - ) - -#define TEST_FP_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \ - TEST_CASE_FP_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \ - inst destreg, reg1, reg2, reg3; \ - ) - -#define TEST_FP_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FP_I(test_num, destreg, reg, correctval, val, swreg, offset, \ - li reg, MASK_XLEN(val); \ - inst destreg, reg; \ - ) - -#define TEST_FP_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FP_I2(test_num, destreg, reg, correctval, val, swreg, offset, \ - inst destreg, reg; \ - ) - -//Tests for floating point instructions - double precision -#define TEST_FPD_OP(test_num, inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset) \ - TEST_CASE_FPD(test_num, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, \ - inst destreg, reg1, reg2; \ - ) - -#define TEST_FPD_ONEREG(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FPD(test_num, destreg, reg, reg, correctval, val, val, swreg, offset, \ - inst destreg, reg; \ - ) - -#define TEST_FPD_4REG(test_num, inst, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset) \ - TEST_CASE_FPD_4REG(test_num, destreg, reg1, reg2, reg3, correctval, val1, val2, val3, swreg, offset, \ - inst destreg, reg1, reg2, reg3; \ - ) - -#define TEST_FPD_I(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FPD_I(test_num, destreg, reg, correctval, val, swreg, offset, \ - li reg, MASK_XLEN(val); \ - inst destreg, reg; \ - ) - -#define TEST_FPD_I2(test_num, inst, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FPD_I2(test_num, destreg, reg, correctval, val, swreg, offset, \ - inst destreg, reg; \ - ) - -#define TEST_CADDI16SP(correctval, imm, swreg, offset) \ - TEST_CASE(x2, correctval, swreg, offset, \ - c.addi16sp x2, imm; \ - ) - -#define TEST_CADDI4SPN(destreg, correctval, imm, swreg, offset) \ - TEST_CASE(destreg, correctval, swreg, offset, \ - c.addi4spn destreg, x2, SEXT_IMM(imm); \ - ) - -#define TEST_CJL(inst, reg, val, swreg, offset) \ - li x10, val; \ - la reg, 1f; \ - inst reg; \ - li x10, 0x123ab; \ -1: \ - sw x10, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, x10, val); \ - -#define ABS(x) ((x >> 11) ^ x) - (x >> 11) - -#define TEST_CJ(inst, reg, val, swreg, offset) \ - li reg, val; \ - inst 1f; \ - li reg, 0x123ab; \ -1: \ - sw reg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \ - -#define TEST_CL(inst, reg, imm, swreg, offset) \ - la reg, test_data; \ - inst reg, imm(reg); \ - sw reg, offset(swreg); \ - -// lw reg, imm(x2) -// c.lwsp reg, imm(x2) -#define TEST_CLWSP(reg, imm, swreg, offset) \ - la x2, test_data; \ - c.lwsp reg, imm(x2); \ - sw reg, offset(swreg); \ - -#define TEST_CSW(test_data, inst, reg1, reg2, val, imm, swreg, offset) \ - li reg1, val; \ - la reg2, test_data; \ - inst reg1, imm(reg2); \ - lw reg1, imm(reg2); \ - sw reg1, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, reg1, val); \ - -#define TEST_CSWSP(test_data, reg, val, imm, swreg, offset) \ - la x2, test_data; \ - li reg, val; \ - c.swsp reg, imm(x2); \ - lw reg, imm(x2); \ - sw reg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \ - -#define TEST_CBEQZ(reg, val, swreg, offset) \ - li reg, val; \ - c.sub reg, reg; \ - c.beqz reg, 3f; \ - li reg, 0x123ab; \ -3: \ - sw reg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, reg, 0x0); \ - -#define TEST_CBNEZ(reg, val, swreg, offset) \ - li reg, val; \ - c.bnez reg, 4f; \ - li reg, 0x0; \ -4: \ - sw reg, offset(swreg); \ - RVTEST_IO_ASSERT_GPR_EQ(x31, reg, val); \ - -#define TEST_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FP_FMVXS(test_num, destreg, reg, correctval, val, swreg, offset, \ - fmv.x.s destreg, reg; \ - ) - -#define TEST_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset) \ - TEST_CASE_FP_FMVSX(test_num, destreg, reg, correctval, val, swreg, offset, \ - fmv.s.x destreg, reg; \ - ) - -#define SWSIG(a,b) - - -#if __riscv_xlen == 64 -#define SATP_MODE SATP64_MODE -#else -#define SATP_MODE SATP32_MODE -#endif - -#define SATP32_MODE 0x80000000 -#define SATP32_ASID 0x7FC00000 -#define SATP32_PPN 0x003FFFFF -#define SATP64_MODE 0xF000000000000000 -#define SATP64_ASID 0x0FFFF00000000000 -#define SATP64_PPN 0x00000FFFFFFFFFFF - -#define SATP_MODE_OFF 0 -#define SATP_MODE_SV32 1 -#define SATP_MODE_SV39 8 -#define SATP_MODE_SV48 9 -#define SATP_MODE_SV57 10 -#define SATP_MODE_SV64 11 - -#define TEST_FP_OP2_D32( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ - inst f3, f0, f1; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) - -#define TEST_CASE_D32( testnum, testreg1, testreg2, correctval, code... ) \ -test_ ## testnum: \ - code; \ - la x31, test_ ## testnum ## _data ; \ - lw x29, 0(x31); \ - lw x31, 4(x31); \ - li TESTNUM, testnum; \ - bne testreg1, x29, fail;\ - bne testreg2, x31, fail;\ - .pushsection .data; \ - .balign 8; \ - test_ ## testnum ## _data: \ - .dword correctval; \ - .popsection - -#define TEST_FP_OP_D32_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - fld f0, 0(a0); \ - fld f1, 8(a0); \ - fld f2, 16(a0); \ - lw a3, 24(a0); \ - lw t1, 28(a0); \ - code; \ - fsflags a1, x0; \ - li a2, flags; \ - bne a0, a3, fail; \ - bne t1, t2, fail; \ - bne a1, a2, fail; \ - .pushsection .data; \ - .balign 8; \ - test_ ## testnum ## _data: \ - .double val1; \ - .double val2; \ - .double val3; \ - .result; \ - .popsection - -#define TEST_FP_OP1_D32( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ - inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) - -#define TEST_FCLASS_D32(testnum, correct, input) \ - TEST_CASE(testnum, a0, correct, \ - la a0, test_ ## testnum ## _data ;\ - fld fa0, 0(a0); \ - fclass.d a0, fa0) \ - .pushsection .data; \ - .balign 8; \ - test_ ## testnum ## _data: \ - .dword input; \ - .popsection - -#define TEST_FP_CMP_OP_D32( testnum, inst, flags, result, val1, val2 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ - inst a0, f0, f1; li t2, 0) - -#define TEST_INT_FP_OP_D32( testnum, inst, result, val1 ) \ -test_ ## testnum: \ - li TESTNUM, testnum; \ - la a0, test_ ## testnum ## _data ;\ - lw a3, 0(a0); \ - lw a4, 4(a0); \ - li a1, val1; \ - inst f0, a1; \ - \ - fsd f0, 0(a0); \ - lw a1, 4(a0); \ - lw a0, 0(a0); \ - \ - fsflags x0; \ - bne a0, a3, fail; \ - bne a1, a4, fail; \ - .pushsection .data; \ - .balign 8; \ - test_ ## testnum ## _data: \ - .double result; \ - .popsection - -#define TEST_FCVT_S_D32( testnum, result, val1 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ - fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) - -#define TEST_FP_OP3_D32( testnum, inst, flags, result, val1, val2, val3 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, double result, val1, val2, val3, \ - inst f3, f0, f1, f2; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) - -#define TEST_FP_OP1_D32_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ - TEST_FP_OP_D32_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ - inst f3, f0; fsd f3, 0(a0); lw t2, 4(a0); lw a0, 0(a0)) - - -#endif
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/Makefile b/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/Makefile deleted file mode 100644 index b953642..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/Makefile +++ /dev/null
@@ -1,96 +0,0 @@ - -include rv32_tests.inc - -ARCH_tmp := imf - -ifneq (,$(findstring c,$(ARCH_lowercase))) - ARCH_tmp := $(ARCH_tmp)c -endif - -override ARCH := $(ARCH_tmp) - -src_dir := $(CURDIR) -obj_dir := $(bld_dir)/riscv_objs -test_list := $(patsubst %.S, %, $(notdir $(rv32_isa_tests))) -objs := $(addprefix $(obj_dir)/,$(test_list:%=%.o)) -test_elf := $(addprefix $(bld_dir)/,$(test_list:%=%.elf)) -test_hex := $(addprefix $(bld_dir)/,$(test_list:%=%.hex)) -test_dump := $(addprefix $(bld_dir)/,$(test_list:%=%.dump)) - -CFLAGS := -I$(inc_dir) -I$(src_dir) -DASM -Wa,-march=rv32$(ARCH) -march=rv32$(ARCH) -mabi=ilp32f -D__riscv_xlen=32 -LDFLAGS := -static -fvisibility=hidden -nostdlib -nostartfiles -T$(inc_dir)/link.ld -march=rv32$(ARCH) -mabi=ilp32f -RISCV_TESTS := $(src_dir)/../../../dependencies/riscv-tests/ - -VPATH += $(src_dir) $(bld_dir) $(obj_dir) $(RISCV_TESTS) - -default: log_requested_tgt check_riscv_tests $(test_elf) $(test_hex) $(test_dump) - -define compile_template -$(obj_dir)/$$(basename $(notdir $(SRC))).o: $$(SRC) | $(obj_dir) - $(RISCV_GCC) -c $$< $(CFLAGS) -o $$@ - endef - -$(foreach SRC,$(rv32_isa_tests), $(eval $(compile_template))) - -log_requested_tgt: - $(foreach test_name, $(test_list), $(eval $(shell echo $(test_name).hex >> $(bld_dir)/test_info))) - -$(obj_dir) : - mkdir -p $(obj_dir) - -$(bld_dir)/%.elf: $(obj_dir)/%.o | $(obj_dir) - $(RISCV_GCC) $^ $(LDFLAGS) -o $@ - -$(bld_dir)/%.hex: $(bld_dir)/%.elf - $(RISCV_ROM_OBJCOPY) $^ $@ - $(RISCV_RAM_OBJCOPY) $^ $@.ram - #assign 0x0048_0xxx to 0x0000_0xxx to map to TCM Memory - sed -i 's/@00480/@00000/g' $@.ram - -$(bld_dir)/%.dump: $(bld_dir)/%.elf - $(RISCV_OBJDUMP) $^ > $@ - -clean: - $(RM) $(test_elf) $(test_hex) $(test_dump) $(objs) - $(RM) -R $(obj_dir) - - -.PHONY: check_riscv_tests - -riscv_tests_dir := $(if $(RISCV_TESTS), $(RISCV_TESTS), ./undefined) -riscv_tests_commit := 5f8a4918c6482e65c67a2b7decd5c2af3e3fe0e5 -## commit hash readed from local copy of https://github.com/riscv/riscv-tests -tmp_commit = $(shell cd $(riscv_tests_dir) 2>/dev/null && git log -1 | grep "commit" | cut -f2 -d ' ') -is_commit_good = $(if $(subst $(riscv_tests_commit),,$(tmp_commit)),false,true) - -# Color -RED=\033[0;31m -NC=\033[0m - -check_riscv_tests : $(riscv_tests_dir) - @if [ ! -d $(riscv_tests_dir) ]; then \ - echo -e "$(RED)==========================================================================" &&\ - echo " Error! Environment variable RISCV_TESTS='$(riscv_tests_dir)' " &&\ - echo " directory not exist!" && \ - echo "==========================================================================$(NC)" ; \ - fi -ifneq ($(is_commit_good),true) - @echo -e "$(RED)==========================================================================" - @echo " Warning! Execution of test code is not guaranteed " - @echo " while using the current commit of repositorylocated at : $(riscv_tests_dir) ." - @echo " " - @echo " Riscv-tests repository must point to commit $(riscv_tests_commit)!" - @echo -e "==========================================================================$(NC)" -endif - -$(riscv_tests_dir) :. -ifndef RISCV_TESTS - @echo -e "$(RED)==========================================================================" - @echo " Error! Environment variable RISCV_TESTS not set!" - @echo " You must set the environment variable RISCV_TESTS" - @echo " The variable should point to the local copy of the" - @echo " repository https://github.com/riscv/riscv-tests" - @echo " with the commit $(riscv_tests_commit)" - @echo -e "==========================================================================$(NC)" - exit 1 -endif
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/riscv_test.h b/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/riscv_test.h deleted file mode 100644 index 2b9ce0d..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/riscv_test.h +++ /dev/null
@@ -1,6 +0,0 @@ -#ifndef __RISCV__TEST__H -#define __RISCV__TEST__H - -#include "riscv_macros.h" - -#endif // #ifndef __RISCV__TEST__H
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/rv32_tests.inc b/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/rv32_tests.inc deleted file mode 100644 index 62e5012..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/rv32_tests.inc +++ /dev/null
@@ -1,66 +0,0 @@ - -ARCH_lowercase = $(shell echo $(ARCH) | tr A-Z a-z) - - -rv32_isa_tests += isa/rv32ui/add.S \ - isa/rv32ui/addi.S \ - isa/rv32ui/and.S \ - isa/rv32ui/andi.S \ - isa/rv32ui/auipc.S \ - isa/rv32ui/beq.S \ - isa/rv32ui/bge.S \ - isa/rv32ui/bgeu.S \ - isa/rv32ui/blt.S \ - isa/rv32ui/bltu.S \ - isa/rv32ui/bne.S \ - isa/rv32mi/csr.S \ - isa/rv32ui/fence_i.S \ - isa/rv32mi/illegal.S \ - isa/rv32ui/jal.S \ - isa/rv32ui/jalr.S \ - isa/rv32ui/lb.S \ - isa/rv32ui/lbu.S \ - isa/rv32ui/lh.S \ - isa/rv32ui/lhu.S \ - isa/rv32ui/lui.S \ - isa/rv32ui/lw.S \ - isa/rv32mi/ma_addr.S \ - isa/rv32mi/ma_fetch.S \ - isa/rv32mi/mcsr.S \ - isa/rv32ui/or.S \ - isa/rv32ui/ori.S \ - isa/rv32ui/sb.S \ - isa/rv32mi/sbreak.S \ - isa/rv32mi/scall.S \ - isa/rv32ui/sh.S \ - isa/rv32mi/shamt.S \ - isa/rv32ui/simple.S \ - isa/rv32ui/sll.S \ - isa/rv32ui/slli.S \ - isa/rv32ui/slt.S \ - isa/rv32ui/slti.S \ - isa/rv32ui/sltiu.S \ - isa/rv32ui/sltu.S \ - isa/rv32ui/sra.S \ - isa/rv32ui/srai.S \ - isa/rv32ui/srl.S \ - isa/rv32ui/srli.S \ - isa/rv32ui/sub.S \ - isa/rv32ui/sw.S \ - isa/rv32ui/xor.S \ - isa/rv32ui/xori.S - -ifneq (,$(findstring m,$(ARCH_lowercase))) -rv32_isa_tests += isa/rv32um/div.S \ - isa/rv32um/divu.S \ - isa/rv32um/mul.S \ - isa/rv32um/mulh.S \ - isa/rv32um/mulhsu.S \ - isa/rv32um/mulhu.S \ - isa/rv32um/rem.S \ - isa/rv32um/remu.S -endif ## ifeq (m,$(findstring m,$(ARCH_lowercase))) - -ifneq (,$(findstring c,$(ARCH_lowercase))) -rv32_isa_tests += isa/rv32uc/rvc.S -endif ## ifeq (m,$(findstring c,$(ARCH_lowercase))) \ No newline at end of file
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/test_macros.h b/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/test_macros.h deleted file mode 100644 index 743918d..0000000 --- a/verilog/rtl/syntacore/scr1/sim/tests/riscv_isa/test_macros.h +++ /dev/null
@@ -1,5 +0,0 @@ -#ifndef __TEST__MACROS__H -#define __TEST__MACROS__H - - -#endif
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v deleted file mode 100644 index b33e032..0000000 --- a/verilog/rtl/user_proj_example.v +++ /dev/null
@@ -1,171 +0,0 @@ -// SPDX-FileCopyrightText: 2020 Efabless Corporation -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 - -`default_nettype none -/* - *------------------------------------------------------------- - * - * user_proj_example - * - * This is an example of a (trivially simple) user project, - * showing how the user project can connect to the logic - * analyzer, the wishbone bus, and the I/O pads. - * - * This project generates an integer count, which is output - * on the user area GPIO pads (digital output only). The - * wishbone connection allows the project to be controlled - * (start and stop) from the management SoC program. - * - * See the testbenches in directory "mprj_counter" for the - * example programs that drive this user project. The three - * testbenches are "io_ports", "la_test1", and "la_test2". - * - *------------------------------------------------------------- - */ - -module user_proj_example #( - parameter BITS = 32 -)( -`ifdef USE_POWER_PINS - inout vdda1, // User area 1 3.3V supply - inout vdda2, // User area 2 3.3V supply - inout vssa1, // User area 1 analog ground - inout vssa2, // User area 2 analog ground - inout vccd1, // User area 1 1.8V supply - inout vccd2, // User area 2 1.8v supply - inout vssd1, // User area 1 digital ground - inout vssd2, // User area 2 digital ground -`endif - - // Wishbone Slave ports (WB MI A) - input wb_clk_i, - input wb_rst_i, - input wbs_stb_i, - input wbs_cyc_i, - input wbs_we_i, - input [3:0] wbs_sel_i, - input [31:0] wbs_dat_i, - input [31:0] wbs_adr_i, - output wbs_ack_o, - output [31:0] wbs_dat_o, - - // Logic Analyzer Signals - input [127:0] la_data_in, - output [127:0] la_data_out, - input [127:0] la_oenb, - - // IOs - input [`MPRJ_IO_PADS-1:0] io_in, - output [`MPRJ_IO_PADS-1:0] io_out, - output [`MPRJ_IO_PADS-1:0] io_oeb, - - // IRQ - output [2:0] irq -); - wire clk; - wire rst; - - wire [`MPRJ_IO_PADS-1:0] io_in; - wire [`MPRJ_IO_PADS-1:0] io_out; - wire [`MPRJ_IO_PADS-1:0] io_oeb; - - wire [31:0] rdata; - wire [31:0] wdata; - wire [BITS-1:0] count; - - wire valid; - wire [3:0] wstrb; - wire [31:0] la_write; - - // WB MI A - assign valid = wbs_cyc_i && wbs_stb_i; - assign wstrb = wbs_sel_i & {4{wbs_we_i}}; - assign wbs_dat_o = rdata; - assign wdata = wbs_dat_i; - - // IO - assign io_out = count; - assign io_oeb = {(`MPRJ_IO_PADS-1){rst}}; - - // IRQ - assign irq = 3'b000; // Unused - - // LA - assign la_data_out = {{(127-BITS){1'b0}}, count}; - // Assuming LA probes [63:32] are for controlling the count register - assign la_write = ~la_oenb[63:32] & ~{BITS{valid}}; - // Assuming LA probes [65:64] are for controlling the count clk & reset - assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i; - assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i; - - counter #( - .BITS(BITS) - ) counter( - .clk(clk), - .reset(rst), - .ready(wbs_ack_o), - .valid(valid), - .rdata(rdata), - .wdata(wbs_dat_i), - .wstrb(wstrb), - .la_write(la_write), - .la_input(la_data_in[63:32]), - .count(count) - ); - -endmodule - -module counter #( - parameter BITS = 32 -)( - input clk, - input reset, - input valid, - input [3:0] wstrb, - input [BITS-1:0] wdata, - input [BITS-1:0] la_write, - input [BITS-1:0] la_input, - output ready, - output [BITS-1:0] rdata, - output [BITS-1:0] count -); - reg ready; - reg [BITS-1:0] count; - reg [BITS-1:0] rdata; - - always @(posedge clk) begin - if (reset) begin - count <= 0; - ready <= 0; - end else begin - ready <= 1'b0; - if (~|la_write) begin - count <= count + 1; - end - if (valid && !ready) begin - ready <= 1'b1; - rdata <= count; - if (wstrb[0]) count[7:0] <= wdata[7:0]; - if (wstrb[1]) count[15:8] <= wdata[15:8]; - if (wstrb[2]) count[23:16] <= wdata[23:16]; - if (wstrb[3]) count[31:24] <= wdata[31:24]; - end else if (|la_write) begin - count <= la_write & la_input; - end - end - end - -endmodule -`default_nettype wire