wbhost reset bug fix and clocking cleanup
diff --git a/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib b/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib new file mode 100644 index 0000000..f1e226c --- /dev/null +++ b/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
@@ -0,0 +1,538 @@ +library (sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C_lib){ + delay_model : "table_lookup"; + time_unit : "1ns" ; + voltage_unit : "1V" ; + current_unit : "1mA" ; + resistance_unit : "1kohm" ; + capacitive_load_unit(1, pF) ; + leakage_power_unit : "1mW" ; + pulling_resistance_unit :"1kohm" ; + operating_conditions(OC){ + process : 1.0 ; + voltage : 1.8 ; + temperature : 25; + } + + input_threshold_pct_fall : 50.0 ; + output_threshold_pct_fall : 50.0 ; + input_threshold_pct_rise : 50.0 ; + output_threshold_pct_rise : 50.0 ; + slew_lower_threshold_pct_fall : 10.0 ; + slew_upper_threshold_pct_fall : 90.0 ; + slew_lower_threshold_pct_rise : 10.0 ; + slew_upper_threshold_pct_rise : 90.0 ; + + nom_voltage : 1.8; + nom_temperature : 25; + nom_process : 1.0; + default_cell_leakage_power : 0.0 ; + default_leakage_power_density : 0.0 ; + default_input_pin_cap : 1.0 ; + default_inout_pin_cap : 1.0 ; + default_output_pin_cap : 0.0 ; + default_max_transition : 0.5 ; + default_fanout_load : 1.0 ; + default_max_fanout : 4.0 ; + default_connection_class : universal ; + + voltage_map ( VCCD1, 1.8 ); + voltage_map ( VSSD1, 0 ); + + lu_table_template(CELL_TABLE){ + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1("0.00125, 0.005, 0.04"); + index_2("0.0017224999999999999, 0.006889999999999999, 0.027559999999999998"); + } + + lu_table_template(CONSTRAINT_TABLE){ + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1("0.00125, 0.005, 0.04"); + index_2("0.00125, 0.005, 0.04"); + } + + default_operating_conditions : OC; + + + type (data){ + base_type : array; + data_type : bit; + bit_width : 32; + bit_from : 31; + bit_to : 0; + } + + type (addr){ + base_type : array; + data_type : bit; + bit_width : 9; + bit_from : 8; + bit_to : 0; + } + + type (wmask){ + base_type : array; + data_type : bit; + bit_width : 4; + bit_from : 3; + bit_to : 0; + } + +cell (sky130_sram_2kbyte_1rw1r_32x512_8){ + memory(){ + type : ram; + address_width : 9; + word_width : 32; + } + interface_timing : true; + dont_use : true; + map_only : true; + dont_touch : true; + area : 284538.474; + + pg_pin(vccd1) { + voltage_name : VCCD1; + pg_type : primary_power; + } + + pg_pin(vssd1) { + voltage_name : VSSD1; + pg_type : primary_ground; + } + + leakage_power () { + value : 0.017726; + } + cell_leakage_power : 0.017726; + bus(din0){ + bus_type : data; + direction : input; + capacitance : 0.006889999999999999; + memory_write(){ + address : addr0; + clocked_on : clk0; + } + pin(din0[31:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + } + } + } + bus(dout0){ + bus_type : data; + direction : output; + max_capacitance : 0.027559999999999998; + min_capacitance : 0.0017224999999999999; + memory_read(){ + address : addr0; + } + pin(dout0[31:0]){ + timing(){ + timing_sense : non_unate; + related_pin : "clk0"; + timing_type : falling_edge; + cell_rise(CELL_TABLE) { + values("0.383, 0.412, 0.529",\ + "0.383, 0.412, 0.529",\ + "0.383, 0.412, 0.529"); + } + cell_fall(CELL_TABLE) { + values("0.383, 0.412, 0.529",\ + "0.383, 0.412, 0.529",\ + "0.383, 0.412, 0.529"); + } + rise_transition(CELL_TABLE) { + values("0.002, 0.005, 0.016",\ + "0.002, 0.005, 0.016",\ + "0.002, 0.005, 0.016"); + } + fall_transition(CELL_TABLE) { + values("0.002, 0.005, 0.016",\ + "0.002, 0.005, 0.016",\ + "0.002, 0.005, 0.016"); + } + } + } + } + + bus(addr0){ + bus_type : addr; + direction : input; + capacitance : 0.006889999999999999; + max_transition : 0.04; + pin(addr0[8:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + } + } + } + + bus(wmask0){ + bus_type : wmask; + direction : input; + capacitance : 0.006889999999999999; + max_transition : 0.04; + pin(wmask0[3:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + } + } + } + + pin(csb0){ + direction : input; + capacitance : 0.006889999999999999; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + } + } + + pin(web0){ + direction : input; + capacitance : 0.006889999999999999; + timing(){ + timing_type : setup_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk0"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + } + } + + pin(clk0){ + clock : true; + direction : input; + capacitance : 0.006889999999999999; + internal_power(){ + when : "!csb0 & !web0"; + rise_power(scalar){ + values("1.380840e+01"); + } + fall_power(scalar){ + values("1.380840e+01"); + } + } + internal_power(){ + when : "csb0 & !web0"; + rise_power(scalar){ + values("1.380840e+01"); + } + fall_power(scalar){ + values("1.380840e+01"); + } + } + internal_power(){ + when : "!csb0 & web0"; + rise_power(scalar){ + values("1.380840e+01"); + } + fall_power(scalar){ + values("1.380840e+01"); + } + } + internal_power(){ + when : "csb0 & web0"; + rise_power(scalar){ + values("1.380840e+01"); + } + fall_power(scalar){ + values("1.380840e+01"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk0; + rise_constraint(scalar) { + values("0.978"); + } + fall_constraint(scalar) { + values("0.978"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk0; + rise_constraint(scalar) { + values("1.956"); + } + fall_constraint(scalar) { + values("1.956"); + } + } + } + + bus(dout1){ + bus_type : data; + direction : output; + max_capacitance : 0.027559999999999998; + min_capacitance : 0.0017224999999999999; + memory_read(){ + address : addr1; + } + pin(dout1[31:0]){ + timing(){ + timing_sense : non_unate; + related_pin : "clk1"; + timing_type : falling_edge; + cell_rise(CELL_TABLE) { + values("0.383, 0.412, 0.529",\ + "0.383, 0.412, 0.529",\ + "0.383, 0.412, 0.529"); + } + cell_fall(CELL_TABLE) { + values("0.383, 0.412, 0.529",\ + "0.383, 0.412, 0.529",\ + "0.383, 0.412, 0.529"); + } + rise_transition(CELL_TABLE) { + values("0.002, 0.005, 0.016",\ + "0.002, 0.005, 0.016",\ + "0.002, 0.005, 0.016"); + } + fall_transition(CELL_TABLE) { + values("0.002, 0.005, 0.016",\ + "0.002, 0.005, 0.016",\ + "0.002, 0.005, 0.016"); + } + } + } + } + + bus(addr1){ + bus_type : addr; + direction : input; + capacitance : 0.006889999999999999; + max_transition : 0.04; + pin(addr1[8:0]){ + timing(){ + timing_type : setup_rising; + related_pin : "clk1"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk1"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + } + } + } + + pin(csb1){ + direction : input; + capacitance : 0.006889999999999999; + timing(){ + timing_type : setup_rising; + related_pin : "clk1"; + rise_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103",\ + "0.103, 0.103, 0.103"); + } + } + timing(){ + timing_type : hold_rising; + related_pin : "clk1"; + rise_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + fall_constraint(CONSTRAINT_TABLE) { + values("-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056",\ + "-0.056, -0.056, -0.056"); + } + } + } + + pin(clk1){ + clock : true; + direction : input; + capacitance : 0.006889999999999999; + internal_power(){ + when : "!csb1"; + rise_power(scalar){ + values("1.380840e+01"); + } + fall_power(scalar){ + values("1.380840e+01"); + } + } + internal_power(){ + when : "csb1"; + rise_power(scalar){ + values("1.380840e+01"); + } + fall_power(scalar){ + values("1.380840e+01"); + } + } + timing(){ + timing_type :"min_pulse_width"; + related_pin : clk1; + rise_constraint(scalar) { + values("0.978"); + } + fall_constraint(scalar) { + values("0.978"); + } + } + timing(){ + timing_type :"minimum_period"; + related_pin : clk1; + rise_constraint(scalar) { + values("1.956"); + } + fall_constraint(scalar) { + values("1.956"); + } + } + } + + } +}
diff --git a/openlane/qspim/base.sdc b/openlane/qspim/base.sdc index 5cd8013..263206d 100644 --- a/openlane/qspim/base.sdc +++ b/openlane/qspim/base.sdc
@@ -9,6 +9,18 @@ create_clock -name mclk -period 10.0000 [get_ports {mclk}] set_propagated_clock [get_clocks {mclk}] create_generated_clock -name spiclk -add -source [get_ports {mclk}] -master_clock [get_clocks {mclk}] -divide_by 2 -comment {SPI Clock Out} [get_ports {spi_clk}] +#Keep in transparent zero delay path +set_case_analysis 0 [get_ports {cfg_cska_spi[3]}] +set_case_analysis 0 [get_ports {cfg_cska_spi[2]}] +set_case_analysis 0 [get_ports {cfg_cska_spi[1]}] +set_case_analysis 0 [get_ports {cfg_cska_spi[0]}] + +#Keep the Clock Skew in center of the Mux +set_case_analysis 0 [get_ports {cfg_cska_sp_co[3]}] +set_case_analysis 1 [get_ports {cfg_cska_sp_co[2]}] +set_case_analysis 0 [get_ports {cfg_cska_sp_co[1]}] +set_case_analysis 0 [get_ports {cfg_cska_sp_co[0]}] + set_propagated_clock [get_clocks {spiclk}] set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -hold 0.1000 set_clock_uncertainty -rise_from [get_clocks {mclk}] -rise_to [get_clocks {mclk}] -setup 0.2000 @@ -36,29 +48,35 @@ set_false_path -from [get_ports {cfg_cska_spi[2]}] set_false_path -from [get_ports {cfg_cska_spi[1]}] set_false_path -from [get_ports {cfg_cska_spi[0]}] -set_max_delay 2 -to [get_ports {wbd_clk_spi}] -set_max_delay 2 -from [get_ports {wbd_clk_int}] +set_max_delay 3 -to [get_ports {wbd_clk_spi}] +set_max_delay 3 -from [get_ports {wbd_clk_int}] -set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {rst_n}] +set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {rst_n}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {rst_n}] -set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[0]}] -set_input_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[0]}] -set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[1]}] -set_input_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[1]}] -set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[2]}] -set_input_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[2]}] -set_input_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdi[3]}] -set_input_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdi[3]}] -set_output_delay 0.0000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_csn0}] -set_output_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_csn0}] -set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[0]}] -set_output_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[0]}] -set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[1]}] -set_output_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[1]}] -set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[2]}] -set_output_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[2]}] -set_output_delay -0.5000 -clock [get_clocks {spiclk}] -min -add_delay [get_ports {spi_sdo[3]}] -set_output_delay 6.0000 -clock [get_clocks {spiclk}] -max -add_delay [get_ports {spi_sdo[3]}] +set_input_delay -max 5.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[0]}] +set_input_delay -max 5.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[1]}] +set_input_delay -max 5.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[2]}] +set_input_delay -max 5.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[3]}] + + +set_input_delay -min 0.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[0]}] +set_input_delay -min 0.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[1]}] +set_input_delay -min 0.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[2]}] +set_input_delay -min 0.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdi[3]}] + + +set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn0}] +set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[0]}] +set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[1]}] +set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[2]}] +set_output_delay -max 4.0000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[3]}] + +set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_csn0}] +set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[0]}] +set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[1]}] +set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[2]}] +set_output_delay -min -0.5000 -clock [get_clocks {spiclk}] -add_delay [get_ports {spi_sdo[3]}] set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[0]}] set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[10]}] @@ -131,109 +149,110 @@ set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_stb_i}] set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_we_i}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_stb_i}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_we_i}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[0]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[10]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[11]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[12]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[13]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[14]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[15]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[16]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[17]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[18]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[19]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[1]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[20]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[21]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[22]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[23]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[24]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[25]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[26]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[27]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[28]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[29]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[2]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[30]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[31]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[3]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[4]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[5]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[6]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[7]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[8]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_adr_i[9]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[0]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[10]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[11]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[12]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[13]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[14]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[15]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[16]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[17]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[18]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[19]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[1]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[20]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[21]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[22]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[23]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[24]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[25]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[26]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[27]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[28]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[29]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[2]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[30]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[31]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[3]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[4]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[5]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[6]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[7]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[8]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_i[9]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[0]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[1]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[2]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_sel_i[3]}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_stb_i}] +set_input_delay -min 3.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_we_i}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[0]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[10]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[11]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[12]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[13]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[14]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[15]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[16]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[17]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[18]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[19]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[1]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[20]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[21]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[22]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[23]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[24]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[25]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[26]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[27]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[28]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[29]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[2]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[30]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[31]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[3]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[4]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[5]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[6]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[7]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[8]}] -set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[9]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[0]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[10]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[11]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[12]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[13]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[14]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[15]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[16]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[17]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[18]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[19]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[1]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[20]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[21]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[22]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[23]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[24]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[25]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[26]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[27]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[28]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[29]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[2]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[30]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[31]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[3]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[4]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[5]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[6]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[7]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[8]}] +set_max_delay 10.0000 -to [get_ports {spi_debug[9]}] + set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}] set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[0]}] set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[10]}] @@ -269,38 +288,6 @@ set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[9]}] set_output_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_err_o}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[10]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[11]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[12]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[13]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[14]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[15]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[16]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[17]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[18]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[19]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[20]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[21]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[22]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[23]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[24]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[25]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[26]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[27]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[28]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[29]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[30]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[31]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[4]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[5]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[6]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[7]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[8]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {spi_debug[9]}] set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_ack_o}] set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[0]}] set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {wbd_dat_o[10]}]
diff --git a/openlane/qspim/config.tcl b/openlane/qspim/config.tcl index 57a2226..192d47c 100755 --- a/openlane/qspim/config.tcl +++ b/openlane/qspim/config.tcl
@@ -37,6 +37,7 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ + $script_dir/../../verilog/rtl/lib/reset_sync.sv \ $script_dir/../../verilog/rtl/qspim/src/qspim_top.sv \ $script_dir/../../verilog/rtl/qspim/src/qspim_if.sv \ $script_dir/../../verilog/rtl/qspim/src/qspim_regs.sv \ @@ -68,15 +69,12 @@ set ::env(PL_TIME_DRIVEN) 1 set ::env(PL_TARGET_DENSITY) "0.40" - # If you're going to use multiple power domains, then keep this disabled. set ::env(RUN_CVC) 0 #set ::env(PDN_CFG) $script_dir/pdn.tcl -set ::env(PL_ROUTABILITY_DRIVEN) 1 - # helps in anteena fix set ::env(USE_ARC_ANTENNA_CHECK) "0"
diff --git a/openlane/user_project_wrapper/base.sdc b/openlane/user_project_wrapper/base.sdc index df41652..ead8841 100644 --- a/openlane/user_project_wrapper/base.sdc +++ b/openlane/user_project_wrapper/base.sdc
@@ -133,112 +133,112 @@ set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_i}] set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_i}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_i}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_i}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_i}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[0]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[10]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[11]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[12]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[13]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[14]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[15]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[16]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[17]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[18]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[19]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[1]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[20]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[21]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[22]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[23]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[24]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[25]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[26]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[27]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[28]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[29]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[2]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[30]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[31]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[3]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[4]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[5]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[6]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[7]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[8]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_i[9]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_i}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_i[0]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_i[1]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_i[2]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_i[3]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_i}] +set_input_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_i}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_ack_o}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}] -set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_ack_o}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}] +set_output_delay -max 4.5000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}] set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_ack_o}] set_output_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}]
diff --git a/openlane/user_project_wrapper/sta.tcl b/openlane/user_project_wrapper/sta.tcl index 987d612..7d1086a 100644 --- a/openlane/user_project_wrapper/sta.tcl +++ b/openlane/user_project_wrapper/sta.tcl
@@ -54,7 +54,7 @@ read_spef -path u_uart_i2c_usb_spi ../../spef/uart_i2c_usb_spi_top.spef read_spef -path u_wb_host ../../spef/wb_host.spef read_spef -path u_intercon ../../spef/wb_interconnect.spef -read_spef ../..//spef/user_project_wrapper.spef +read_spef ../../spef/user_project_wrapper.spef read_sdc -echo $::env(BASE_SDC_FILE)
diff --git a/openlane/wb_host/base.sdc b/openlane/wb_host/base.sdc index 54dfe00..3a3e386 100644 --- a/openlane/wb_host/base.sdc +++ b/openlane/wb_host/base.sdc
@@ -102,78 +102,78 @@ set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_stb_i}] set_input_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_we_i}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_cyc_i}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_rst_i}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_stb_i}] -set_input_delay -min 1.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_we_i}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[0]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[10]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[11]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[12]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[13]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[14]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[15]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[16]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[17]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[18]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[19]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[1]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[20]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[21]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[22]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[23]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[24]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[25]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[26]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[27]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[28]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[29]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[2]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[30]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[31]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[3]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[4]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[5]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[6]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[7]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[8]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_adr_i[9]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_cyc_i}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[0]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[10]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[11]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[12]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[13]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[14]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[15]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[16]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[17]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[18]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[19]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[1]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[20]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[21]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[22]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[23]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[24]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[25]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[26]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[27]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[28]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[29]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[2]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[30]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[31]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[3]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[4]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[5]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[6]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[7]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[8]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_i[9]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_rst_i}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[0]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[1]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[2]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_sel_i[3]}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_stb_i}] +set_input_delay -min 0.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_we_i}] set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_ack_o}] set_output_delay -max 6.0000 -clock [get_clocks {wbm_clk_i}] -add_delay [get_ports {wbm_dat_o[0]}] @@ -279,39 +279,39 @@ set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}] set_input_delay -max 6.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_ack_i}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[0]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[10]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[11]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[12]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[13]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[14]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[15]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[16]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[17]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[18]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[19]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[1]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[20]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[21]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[22]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[23]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[24]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[25]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[26]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[27]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[28]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[29]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[2]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[30]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[31]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[3]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[4]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[5]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[6]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[7]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[8]}] +set_input_delay -min 2.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_i[9]}] set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[0]}] set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[10]}] @@ -385,77 +385,77 @@ set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}] set_output_delay -max 4.5000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[0]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[10]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[11]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[12]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[13]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[14]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[15]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[16]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[17]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[18]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[19]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[1]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[20]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[21]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[22]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[23]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[24]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[25]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[26]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[27]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[28]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[29]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[2]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[30]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[31]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[3]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[4]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[5]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[6]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[7]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[8]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[9]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[0]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[1]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[2]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[3]}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}] -set_output_delay -min 0.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[0]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[10]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[11]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[12]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[13]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[14]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[15]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[16]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[17]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[18]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[19]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[1]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[20]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[21]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[22]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[23]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[24]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[25]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[26]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[27]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[28]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[29]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[2]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[30]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[31]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[3]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[4]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[5]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[6]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[7]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[8]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_adr_o[9]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_cyc_o}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[0]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[10]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[11]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[12]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[13]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[14]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[15]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[16]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[17]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[18]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[19]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[1]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[20]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[21]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[22]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[23]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[24]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[25]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[26]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[27]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[28]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[29]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[2]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[30]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[31]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[3]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[4]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[5]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[6]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[7]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[8]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_dat_o[9]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[0]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[1]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[2]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_sel_o[3]}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_stb_o}] +set_output_delay -min 1.0000 -clock [get_clocks {wbs_clk_i}] -add_delay [get_ports {wbs_we_o}] ############################################################################### # Environment
diff --git a/signoff/qspim/final_summary_report.csv b/signoff/qspim/final_summary_report.csv index c15070c..fad139a 100644 --- a/signoff/qspim/final_summary_report.csv +++ b/signoff/qspim/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h14m26s,-1,54792.30769230769,0.26,27396.153846153844,31.72,706.7,7123,0,0,0,0,0,0,0,1,0,-1,-1,379934,68845,-1.97,-4.68,-1,-3.71,-1,-23.17,-106.34,-1,-38.77,-1,232014592.0,13.2,31.17,35.82,3.36,2.58,-1,5828,8780,488,3439,0,0,0,6883,0,0,0,0,0,0,0,4,1765,2184,20,460,3480,0,3940,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h10m36s,-1,54838.46153846153,0.26,27419.230769230766,31.76,683.73,7129,0,0,0,0,0,0,0,1,0,-1,-1,322453,64409,0.0,-2.76,-1,0.0,-1,0.0,-754.97,-1,0.0,-1,222393243.0,6.51,27.06,31.81,0.72,1.25,-1,5836,8788,495,3446,0,0,0,6886,0,0,0,0,0,0,0,4,1766,2187,21,460,3480,0,3940,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index bfcdec4..0c5c3c7 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h18m0s,-1,1.5566625155666252,10.2784,0.7783312577833126,-1,513.07,8,0,0,0,0,0,0,-1,0,0,-1,-1,1262493,5472,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,1.83,5.13,0.91,0.89,-1,166,1800,166,1800,0,0,0,8,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h17m45s,-1,1.5566625155666252,10.2784,0.7783312577833126,-1,514.47,8,0,0,0,0,0,0,-1,0,0,-1,-1,1262458,5462,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40141.04,1.83,5.13,0.91,0.89,-1,166,1800,166,1800,0,0,0,8,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,180,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv index b3644ca..1c22120 100644 --- a/signoff/wb_host/final_summary_report.csv +++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h6m1s,-1,31826.66666666667,0.15,15913.333333333336,19.7,592.62,2387,0,0,0,0,0,0,-1,4,0,0,-1,178981,26092,-3.95,-4.14,-1,-3.91,-1,-133.05,-138.26,-1,-130.87,-1,120849453.0,0.0,27.81,25.26,5.11,2.03,-1,1227,2833,700,2304,0,0,0,1248,0,0,0,0,0,0,0,4,721,808,13,204,1924,0,2128,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h7m26s,-1,34600.0,0.15,17300.0,21.07,602.71,2595,0,0,0,0,0,0,-1,4,0,0,-1,182887,27544,-4.26,-4.87,-1,-4.46,-1,-133.15,-138.34,-1,-147.66,-1,122772438.0,0.0,28.22,26.16,5.59,1.46,-1,1331,2937,696,2300,0,0,0,1379,0,0,0,0,0,0,0,4,762,894,13,204,1924,0,2128,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/verilog/rtl/qspim/src/qspim_top.sv b/verilog/rtl/qspim/src/qspim_top.sv index d1b5823..d4aede1 100644 --- a/verilog/rtl/qspim/src/qspim_top.sv +++ b/verilog/rtl/qspim/src/qspim_top.sv
@@ -231,6 +231,7 @@ logic spi_sdo1_dl; logic spi_sdo2_dl; logic spi_sdo3_dl; +logic rst_ss_n; @@ -280,9 +281,18 @@ .sel (cfg_cska_sp_co ), .clk_out (spi_clk ) ); +//################################### +// Application Reset Synchronization +//################################### +reset_sync u_app_rst ( + .scan_mode (1'b0 ), + .dclk (mclk ), // Destination clock domain + .arst_n (rst_n ), // active low async reset + .srst_n (rst_ss_n ) + ); qspim_if #( .WB_WIDTH(WB_WIDTH)) u_wb_if( .mclk (mclk ), - .rst_n (rst_n ), + .rst_n (rst_ss_n ), .wbd_stb_i (wbd_stb_i ), // strobe/request .wbd_adr_i (wbd_adr_i ), // address @@ -335,7 +345,7 @@ u_spim_regs ( .mclk (mclk ), - .rst_n (rst_n ), + .rst_n (rst_ss_n ), .fast_sim_mode (1'b0 ), .spi_clk_div (spi_clk_div ), @@ -389,7 +399,7 @@ // Master 0 Command FIFO qspim_fifo #(.W(34), .DP(2)) u_m0_cmd_fifo ( .clk (mclk ), - .reset_n (rst_n ), + .reset_n (rst_ss_n ), .flush (1'b0 ), .wr_en (m0_cmd_fifo_wr ), .wr_data (m0_cmd_fifo_wdata ), @@ -404,7 +414,7 @@ // Master 0 Response FIFO qspim_fifo #(.W(32), .DP(8)) u_m0_res_fifo ( .clk (mclk ), - .reset_n (rst_n ), + .reset_n (rst_ss_n ), .flush (m0_res_fifo_flush ), .wr_en (m0_res_fifo_wr ), .wr_data (m0_res_fifo_wdata ), @@ -419,7 +429,7 @@ // Master 1 Command FIFO qspim_fifo #(.W(34), .DP(4)) u_m1_cmd_fifo ( .clk (mclk ), - .reset_n (rst_n ), + .reset_n (rst_ss_n ), .flush (1'b0 ), .wr_en (m1_cmd_fifo_wr ), .wr_data (m1_cmd_fifo_wdata ), @@ -433,7 +443,7 @@ // Master 1 Response FIFO qspim_fifo #(.W(32), .DP(8)) u_m1_res_fifo ( .clk (mclk ), - .reset_n (rst_n ), + .reset_n (rst_ss_n ), .flush (m1_res_fifo_flush ), .wr_en (m1_res_fifo_wr ), .wr_data (m1_res_fifo_wdata ), @@ -449,7 +459,7 @@ qspim_ctrl u_spictrl ( .clk (mclk ), - .rstn (rst_n ), + .rstn (rst_ss_n ), .spi_clk_div (spi_clk_div ), .spi_status (spi_ctrl_status ),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 3e347ae..9bd8900 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -117,6 +117,9 @@ //// 1.5 - 6th Nov 2021, Dinesh A //// //// Clock Skew block moved inside respective block due //// // to top-level power hook-up challenges for small IP //// +//// 1.6 Nov 14, 2021, Dinesh A //// +//// Major bug, clock divider inside the wb_host reset //// +//// connectivity open is fixed //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG ////
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv index 6867253..f5f2d4f 100644 --- a/verilog/rtl/wb_host/src/wb_host.sv +++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -36,6 +36,9 @@ //// Revision : //// //// 0.1 - 25th Feb 2021, Dinesh A //// //// initial version //// +//// 0.2 - Nov 14 2021, Dinesh A //// +//// Reset connectivity bug fix clk_ctl in u_sdramclk //// +//// u_cpuclk,u_rtcclk,u_usbclk ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -398,7 +401,7 @@ .clk_o (cpu_clk_div ), // Inputs .mclk (cpu_ref_clk ), - .reset_n (reset_n ), + .reset_n (wbm_rst_n ), .clk_div_ratio (cfg_cpu_clk_ratio) ); @@ -416,7 +419,7 @@ .clk_o (rtc_clk_div ), // Inputs .mclk (user_clock2 ), - .reset_n (reset_n ), + .reset_n (wbm_rst_n ), .clk_div_ratio (cfg_rtc_clk_ratio) ); @@ -443,7 +446,7 @@ .clk_o (usb_clk_div ), // Inputs .mclk (usb_ref_clk ), - .reset_n (reset_n ), + .reset_n (wbm_rst_n ), .clk_div_ratio (cfg_usb_clk_ratio) );