sspi bug fixes
diff --git a/openlane/Makefile b/openlane/Makefile index ecdee61..c782204 100644 --- a/openlane/Makefile +++ b/openlane/Makefile
@@ -19,7 +19,7 @@ CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl) CLEAN = $(foreach block,$(BLOCKS), clean-$(block)) -OPENLANE_TAG = mpw5 +OPENLANE_TAG = mpw4 OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG) OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite" OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index c721d0f..836d0cd 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = wb_port risc_boot user_risc_boot user_uart user_spi user_i2cm riscv_regress user_basic user_uart_master uart_master +PATTERNS = wb_port risc_boot user_risc_boot user_uart user_qspi user_i2cm riscv_regress user_basic user_uart_master uart_master all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c index 48e54f0..3e42aaa 100644 --- a/verilog/dv/risc_boot/risc_boot.c +++ b/verilog/dv/risc_boot/risc_boot.c
@@ -178,7 +178,7 @@ // Remove All Reset - reg_mprj_wbhost_reg0 = 0x1F; + reg_mprj_globl_reg2 = 0x11F; // Enable UART Multi Functional Ports
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v index 2d0d7d5..766e403 100644 --- a/verilog/dv/risc_boot/risc_boot_tb.v +++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -314,7 +314,7 @@ //----------------------------------------- wire user_flash_clk = mprj_io[24]; - wire user_flash_csb = mprj_io[28]; + wire user_flash_csb = mprj_io[25]; //tri user_flash_io0 = mprj_io[26]; //tri user_flash_io1 = mprj_io[27]; //tri user_flash_io2 = mprj_io[28];
diff --git a/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S b/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S index d7b3d63..19f8703 100644 --- a/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S +++ b/verilog/dv/riscv_regress/tests/isr_sample/isr_sample.S
@@ -11,9 +11,9 @@ #define MCAUSE_TMR_IRQ (1 << 31 | IRQ_M_TIMER) // IPIC -#define IRQ_LINES_ADDR 0x10020018 // simulation -#define TRIG_EXT_IRQ_ADDR 0x10020018 // external irq is triggered when tb memory is set to non-zero // Bit [15:0] -#define TRIG_SW_IRQ_ADDR 0x10020018 // software irq is triggered when tb memory is set to non-zero // Bit [16] +#define IRQ_LINES_ADDR 0x10020020 // simulation +#define TRIG_EXT_IRQ_ADDR 0x10020020 // external irq is triggered when tb memory is set to non-zero // Bit [15:0] +#define TRIG_SW_IRQ_ADDR 0x10020020 // software irq is triggered when tb memory is set to non-zero // Bit [16] #define IPIC_EOI 0xBF4 // end of interrupt #define IPIC_SOI 0xBF5 // start of interrupt
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v index 826774d..f0bed30 100644 --- a/verilog/dv/user_i2cm/user_i2cm_tb.v +++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -127,7 +127,7 @@ `ifdef WFDUMP initial begin - $dumpfile("tb_top.vcd"); + $dumpfile("simx.vcd"); $dumpvars(0, tb_top); end `endif @@ -151,11 +151,14 @@ repeat (10) @(posedge clock); #1; // Enable I2M Block & WB Reset and Enable I2CM Mux Select - wb_user_core_write('h3080_0000,'hA1); + wb_user_core_write('h3080_0000,'h01); // Enable I2C Multi Functional Ports wb_user_core_write(`ADDR_SPACE_PINMUX+'h0038,'h200); + // Remove i2m reset + wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h010); + repeat (100) @(posedge clock); @(posedge clock); @@ -355,7 +358,7 @@ // ---------------------------------------------------- wire flash_clk = io_out[24]; - wire flash_csb = io_out[28]; + wire flash_csb = io_out[25]; // Creating Pad Delay wire #1 io_oeb_29 = io_oeb[29]; wire #1 io_oeb_30 = io_oeb[30];
diff --git a/verilog/dv/user_spi/Makefile b/verilog/dv/user_qspi/Makefile similarity index 99% rename from verilog/dv/user_spi/Makefile rename to verilog/dv/user_qspi/Makefile index e0934e1..2192cb7 100644 --- a/verilog/dv/user_spi/Makefile +++ b/verilog/dv/user_qspi/Makefile
@@ -50,7 +50,7 @@ .SUFFIXES: -PATTERN = user_spi +PATTERN = user_qspi all: ${PATTERN:=.vcd}
diff --git a/verilog/dv/user_spi/flash0.hex b/verilog/dv/user_qspi/flash0.hex similarity index 100% rename from verilog/dv/user_spi/flash0.hex rename to verilog/dv/user_qspi/flash0.hex
diff --git a/verilog/dv/user_spi/flash1.hex b/verilog/dv/user_qspi/flash1.hex similarity index 100% rename from verilog/dv/user_spi/flash1.hex rename to verilog/dv/user_qspi/flash1.hex
diff --git a/verilog/dv/user_spi/run_iverilog b/verilog/dv/user_qspi/run_iverilog similarity index 100% rename from verilog/dv/user_spi/run_iverilog rename to verilog/dv/user_qspi/run_iverilog
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v similarity index 99% rename from verilog/dv/user_spi/user_spi_tb.v rename to verilog/dv/user_qspi/user_qspi_tb.v index cb37454..4a35096 100644 --- a/verilog/dv/user_spi/user_spi_tb.v +++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -101,7 +101,9 @@ `define QSPIM_IMEM_RDATA 32'h1000002C `define QSPIM_SPI_STATUS 32'h10000030 -module user_spi_tb; + `define ADDR_SPACE_PINMUX 32'h3002_0000 + +module user_qspi_tb; reg clock; reg wb_rst_i; reg power1, power2; @@ -205,7 +207,7 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(5, user_spi_tb); + $dumpvars(5, user_qspi_tb); end `endif @@ -221,8 +223,8 @@ repeat (2) @(posedge clock); #1; - // Remove WB and SPI Reset, Keep SDARM and CORE under Reset - wb_user_core_write('h3080_0000,'h5); + // Remove only WB and SPI Reset + wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h2); wb_user_core_write('h3080_0004,'h0); // Change the Bank Sel 0 @@ -1227,7 +1229,7 @@ // ---------------------------------------------------- wire flash_clk = io_out[24]; - wire flash_csb = io_out[28]; + wire flash_csb = io_out[25]; // Creating Pad Delay wire #1 io_oeb_29 = io_oeb[29]; wire #1 io_oeb_30 = io_oeb[30]; @@ -1261,7 +1263,7 @@ ); - wire spiram_csb = io_out[26]; + wire spiram_csb = io_out[27]; is62wvs1288 #(.mem_file_name("flash1.hex")) u_sfram ( @@ -1356,7 +1358,7 @@ wbd_ext_sel_i ='h0; // byte enable if(data !== cmp_data) begin $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); - user_spi_tb.test_fail = 1; + user_qspi_tb.test_fail = 1; end else begin $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); end
diff --git a/verilog/dv/user_spi/user_risc_boot.c b/verilog/dv/user_qspi/user_risc_boot.c similarity index 100% rename from verilog/dv/user_spi/user_risc_boot.c rename to verilog/dv/user_qspi/user_risc_boot.c
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v index fff2408..97b8ae9 100644 --- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v +++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -78,6 +78,7 @@ `include "uprj_netlists.v" `include "mt48lc8m8a2.v" +`define ADDR_SPACE_PINMUX 32'h3002_0000 module user_risc_boot_tb; reg clock; reg wb_rst_i; @@ -143,7 +144,7 @@ repeat (2) @(posedge clock); #1; // Remove all the reset - wb_user_core_write('h3080_0000,'hF); + wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F); // Repeat cycles of 1000 clock edges as needed to complete testbench @@ -257,7 +258,7 @@ // ---------------------------------------------------- wire flash_clk = io_out[24]; - wire flash_csb = io_out[28]; + wire flash_csb = io_out[25]; // Creating Pad Delay wire #1 io_oeb_29 = io_oeb[29]; wire #1 io_oeb_30 = io_oeb[30];
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index dba2b77..f60c07a 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -80,6 +80,8 @@ `include "uart_agent.v" +// Note in caravel, 0x30XX_XXXX only come to user interface +// So, using wb_host bank select we have changing MSB address [31:24] = 0x10 `define ADDR_SPACE_UART 32'h3001_0000 `define ADDR_SPACE_PINMUX 32'h3002_0000 @@ -184,7 +186,7 @@ repeat (2) @(posedge clock); #1; // Remove all the reset - wb_user_core_write('h3080_0000,'h1F); + wb_user_core_write(`ADDR_SPACE_PINMUX+8'h8,'h11F); repeat (100) @(posedge clock); // wait for Processor Get Ready @@ -303,7 +305,7 @@ // ---------------------------------------------------- wire flash_clk = io_out[24]; - wire flash_csb = io_out[28]; + wire flash_csb = io_out[25]; // Creating Pad Delay wire #1 io_oeb_29 = io_oeb[29]; wire #1 io_oeb_30 = io_oeb[30];
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c index 2649c67..a4da212 100644 --- a/verilog/dv/wb_port/wb_port.c +++ b/verilog/dv/wb_port/wb_port.c
@@ -120,7 +120,10 @@ // Remove Wishbone Reset reg_mprj_wbhost_reg0 = 0x1; - if (reg_mprj_globl_reg0 != 0x89490201) bFail = 1; + // Remove Reset + reg_mprj_globl_reg2 = 0x01F; + + if (reg_mprj_globl_reg0 != 0x82681301) bFail = 1; if (reg_mprj_globl_reg1 != 0xA55AA55A) bFail = 1; // Write software Write & Read Register
diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v index 1d8eec5..99caccc 100644 --- a/verilog/dv/wb_port/wb_port_tb.v +++ b/verilog/dv/wb_port/wb_port_tb.v
@@ -51,9 +51,9 @@ `ifdef WFDUMP initial begin - $dumpfile("wb_port.vcd"); + $dumpfile("simx.vcd"); $dumpvars(1, wb_port_tb); - $dumpvars(2, wb_port_tb.uut); + $dumpvars(0, wb_port_tb.uut.soc); //$dumpvars(1, wb_port_tb.uut.mprj); $dumpvars(1, wb_port_tb.uut.mprj.u_wb_host); $dumpvars(2, wb_port_tb.uut.mprj.u_pinmux);
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index 5015bb6..4446c89 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -50,6 +50,17 @@ input logic mclk, input logic h_reset_n, + // Global Reset control + output logic [1:0] cpu_core_rst_n , + output logic cpu_intf_rst_n , + output logic qspim_rst_n , + output logic sspim_rst_n , + output logic uart_rst_n , + output logic i2cm_rst_n , + output logic usb_rst_n , + + output logic [1:0] cfg_riscv_debug_sel, + // Reg Bus Interface Signal input logic reg_cs, input logic reg_wr, @@ -264,6 +275,16 @@ .mclk (mclk ), .h_reset_n (h_reset_n ), + .cpu_core_rst_n (cpu_core_rst_n ), + .cpu_intf_rst_n (cpu_intf_rst_n ), + .qspim_rst_n (qspim_rst_n ), + .sspim_rst_n (sspim_rst_n ), + .uart_rst_n (uart_rst_n ), + .i2cm_rst_n (i2cm_rst_n ), + .usb_rst_n (usb_rst_n ), + + .cfg_riscv_debug_sel (cfg_riscv_debug_sel ), + // Reg read/write Interface Inputs .reg_cs (reg_cs ), @@ -430,10 +451,10 @@ * * Additional Pad used for Externam ROM/RAM * sflash_sck digital_io[24] -* sflash_ss[3] digital_io[25] -* sflash_ss[2] digital_io[26] -* sflash_ss[1] digital_io[27] -* sflash_ss[0] digital_io[28] +* sflash_ss[0] digital_io[25] +* sflash_ss[1] digital_io[26] +* sflash_ss[2] digital_io[27] +* sflash_ss[3] digital_io[28] * sflash_io0 digital_io[29] * sflash_io1 digital_io[30] * sflash_io2 digital_io[31] @@ -648,10 +669,10 @@ // Serial Flash digital_io_out[24] = sflash_sck ; - digital_io_out[25] = sflash_ss[3] ; - digital_io_out[26] = sflash_ss[2] ; - digital_io_out[27] = sflash_ss[1] ; - digital_io_out[28] = sflash_ss[0] ; + digital_io_out[25] = sflash_ss[0] ; + digital_io_out[26] = sflash_ss[1] ; + digital_io_out[27] = sflash_ss[2] ; + digital_io_out[28] = sflash_ss[3] ; digital_io_out[29] = sflash_do[0] ; digital_io_out[30] = sflash_do[1] ; digital_io_out[31] = sflash_do[2] ;
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv index 31b3ea7..da87d24 100644 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -42,6 +42,15 @@ input logic mclk, input logic h_reset_n, + // Global Reset control + output logic [1:0] cpu_core_rst_n , + output logic cpu_intf_rst_n , + output logic qspim_rst_n , + output logic sspim_rst_n , + output logic uart_rst_n , + output logic i2cm_rst_n , + output logic usb_rst_n , + // Reg Bus Interface Signal input logic reg_cs, input logic reg_wr, @@ -64,6 +73,7 @@ input logic i2cm_intr, output logic [9:0] cfg_pulse_1us, + output logic [1:0] cfg_riscv_debug_sel, //--------------------------------------------------- // 6 PWM Configuration @@ -134,13 +144,13 @@ logic [31:0] reg_out; logic [31:0] reg_0; // Chip ID logic [31:0] reg_1; // Risc Fuse Id -logic [31:0] reg_2; // GPIO Read Data -logic [31:0] reg_3; // GPIO Output Data -logic [31:0] reg_4; // GPIO Dir Sel -logic [31:0] reg_5; // GPIO Type -logic [31:0] reg_6; // Interrupt -logic [31:0] reg_7; // -logic [31:0] reg_8; // +logic [31:0] reg_2; // Global config-1 +logic [31:0] reg_3; // Global config-2 +logic [31:0] reg_4; // GPIO Read Data +logic [31:0] reg_5; // GPIO Output Data +logic [31:0] reg_6; // GPIO Dir Sel +logic [31:0] reg_7; // GPIO Type +logic [31:0] reg_8; // Interrupt logic [31:0] reg_9; // GPIO Interrupt Status logic [31:0] reg_10; // GPIO Interrupt Status logic [31:0] reg_11; // GPIO Interrupt Mask @@ -269,11 +279,12 @@ //----------------------------------------------------------------------- // Chip ID -wire [15:0] manu_id = 16'h8949; // Asci value of YI -wire [7:0] chip_id = 8'h02; -wire [7:0] chip_rev = 8'h01; +wire [15:0] manu_id = 16'h8268; // Asci value of RD +wire [3:0] total_core = 4'h1; +wire [3:0] chip_id = 4'h3; +wire [7:0] chip_rev = 8'h01; -assign reg_0 = {manu_id,chip_id,chip_rev}; +assign reg_0 = {manu_id,total_core,chip_id,chip_rev}; //----------------------------------------------------------------------- @@ -294,34 +305,36 @@ assign fuse_mhartid = reg_1; -//----------------------------------------------------------------------- -// Logic for gpio_data_in -//----------------------------------------------------------------------- -logic [31:0] gpio_in_data_s; -logic [31:0] gpio_in_data_ss; -// Double Sync the gpio pin data for edge detection -always @ (posedge mclk or negedge h_reset_n) -begin - if (h_reset_n == 1'b0) begin - reg_2 <= 'h0 ; - gpio_in_data_s <= 32'd0; - gpio_in_data_ss <= 32'd0; - end - else begin - gpio_in_data_s <= gpio_in_data; - gpio_in_data_ss <= gpio_in_data_s; - reg_2 <= gpio_in_data_ss; - end -end +//------------------------------------------ +// reg-2: GLBL_CFG_1 +//------------------------------------------ +wire [31:0] cfg_glb_ctrl = reg_2; +ctech_buf u_buf_cpu_intf_rst (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n)); +ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n)); +ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n)); +ctech_buf u_buf_uart_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n)); +ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n)); +ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[5]),.X(usb_rst_n)); -assign cfg_gpio_data_in = reg_2[31:0]; // to be used for edge interrupt detect -assign gpio_prev_indata = gpio_in_data_ss; +ctech_buf u_buf_cpu0_rst (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0])); +ctech_buf u_buf_cpu1_rst (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1])); -//----------------------------------------------------------------------- -// Logic for cfg_gpio_out_data -//----------------------------------------------------------------------- -assign cfg_gpio_out_data = reg_3[31:0]; // data to the GPIO control blk +gen_32b_reg #(32'h0) u_reg_2 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_2 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_2 ) + ); + +//---------------------------------------------- +// reg-3: GLBL_CFG_1 +//------------------------------------------ gen_32b_reg #(32'h0) u_reg_3 ( //List of Inputs @@ -334,26 +347,37 @@ //List of Outs .data_out (reg_3 ) ); -//----------------------------------------------------------------------- -// Logic for cfg_gpio_dir_sel -//----------------------------------------------------------------------- -assign cfg_gpio_dir_sel = reg_4[31:0]; // data to the GPIO O/P pins -gen_32b_reg #(32'h0) u_reg_4 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_4 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_4 ) - ); +assign cfg_pulse_1us = reg_3[9:0]; +assign cfg_riscv_debug_sel = reg_3[31:30]; //----------------------------------------------------------------------- -// Logic for cfg_gpio_out_type +// Logic for gpio_data_in //----------------------------------------------------------------------- -assign cfg_gpio_out_type = reg_5[31:0]; // to be used for read +logic [31:0] gpio_in_data_s; +logic [31:0] gpio_in_data_ss; +// Double Sync the gpio pin data for edge detection +always @ (posedge mclk or negedge h_reset_n) +begin + if (h_reset_n == 1'b0) begin + reg_4 <= 'h0 ; + gpio_in_data_s <= 32'd0; + gpio_in_data_ss <= 32'd0; + end + else begin + gpio_in_data_s <= gpio_in_data; + gpio_in_data_ss <= gpio_in_data_s; + reg_4 <= gpio_in_data_ss; + end +end + + +assign cfg_gpio_data_in = reg_4[31:0]; // to be used for edge interrupt detect +assign gpio_prev_indata = gpio_in_data_ss; + +//----------------------------------------------------------------------- +// Logic for cfg_gpio_out_data +//----------------------------------------------------------------------- +assign cfg_gpio_out_data = reg_5[31:0]; // data to the GPIO control blk gen_32b_reg #(32'h0) u_reg_5 ( //List of Inputs @@ -366,69 +390,87 @@ //List of Outs .data_out (reg_5 ) ); +//----------------------------------------------------------------------- +// Logic for cfg_gpio_dir_sel +//----------------------------------------------------------------------- +assign cfg_gpio_dir_sel = reg_6[31:0]; // data to the GPIO O/P pins + +gen_32b_reg #(32'h0) u_reg_6 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_6 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_6 ) + ); +//----------------------------------------------------------------------- +// Logic for cfg_gpio_out_type +//----------------------------------------------------------------------- +assign cfg_gpio_out_type = reg_7[31:0]; // to be used for read + +gen_32b_reg #(32'h0) u_reg_7 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_7 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_7 ) + ); //----------------------------------------------------------------------- -// reg-6 +// reg-8 //----------------------------------------------------------------- -assign irq_lines = reg_6[15:0]; -assign soft_irq = reg_6[16]; -assign user_irq = reg_6[19:17]; +assign irq_lines = reg_8[15:0]; +assign soft_irq = reg_8[16]; +assign user_irq = reg_8[19:17]; -generic_register #(8,0 ) u_reg6_be0 ( - .we ({8{sw_wr_en_6 & +generic_register #(8,0 ) u_reg8_be0 ( + .we ({8{sw_wr_en_8 & wr_be[0] }} ), .data_in (sw_reg_wdata[7:0] ), .reset_n (h_reset_n ), .clk (mclk ), //List of Outs - .data_out (reg_6[7:0] ) + .data_out (reg_8[7:0] ) ); -generic_register #(3,0 ) u_reg6_be1_1 ( - .we ({3{sw_wr_en_6 & +generic_register #(3,0 ) u_reg8_be1_1 ( + .we ({3{sw_wr_en_8 & wr_be[1] }} ), .data_in (sw_reg_wdata[10:8] ), .reset_n (h_reset_n ), .clk (mclk ), //List of Outs - .data_out (reg_6[10:8] ) + .data_out (reg_8[10:8] ) ); -assign reg_6[15:11] = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr}; +assign reg_8[15:11] = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr}; -generic_register #(4,0 ) u_reg6_be2 ( - .we ({4{sw_wr_en_6 & +generic_register #(4,0 ) u_reg8_be2 ( + .we ({4{sw_wr_en_8 & wr_be[2] }} ), .data_in (sw_reg_wdata[19:16]), .reset_n (h_reset_n ), .clk (mclk ), //List of Outs - .data_out (reg_6[19:16] ) + .data_out (reg_8[19:16] ) ); -assign reg_6[31:20] = '0; +assign reg_8[31:20] = '0; -// Register-7 -gen_32b_reg #(32'h0) u_reg_7 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_7 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_7 ) - ); - -assign cfg_pulse_1us = reg_7[9:0]; //----------------------------------------------------------------------- // Logic for cfg_int_status
diff --git a/verilog/rtl/qspim b/verilog/rtl/qspim index f83d4c0..efa1519 160000 --- a/verilog/rtl/qspim +++ b/verilog/rtl/qspim
@@ -1 +1 @@ -Subproject commit f83d4c0182dfd50f867f7cb49ec1bebc833e0a58 +Subproject commit efa151915f9d00cb329388845356c5b734601571
diff --git a/verilog/rtl/sspim/src/sspim_cfg.sv b/verilog/rtl/sspim/src/sspim_cfg.sv index cd39e1f..e849f81 100755 --- a/verilog/rtl/sspim/src/sspim_cfg.sv +++ b/verilog/rtl/sspim/src/sspim_cfg.sv
@@ -56,6 +56,7 @@ output logic [1:0] cfg_tgt_sel , output logic cfg_op_req , // SPI operation request + output logic cfg_endian , // Endian selection output logic [1:0] cfg_op_type , // SPI operation type output logic [1:0] cfg_transfer_size , // SPI transfer size output logic [5:0] cfg_sck_period , // sck clock period @@ -89,7 +90,6 @@ logic sw_rd_en ; logic sw_wr_en; logic [1:0] sw_addr; // addressing 16 registers -logic [31:0] sw_reg_wdata; logic [3:0] wr_be ; logic reg_cs_l; logic reg_cs_2l; @@ -104,29 +104,12 @@ //----------------------------------------------------------------------- //----------------------------------------------------------------------- -// To avoid interface timing, all the content are registered +// Internal Logic Starts here //----------------------------------------------------------------------- -always @ (posedge mclk or negedge reset_n) -begin - if (reset_n == 1'b0) - begin - sw_addr <= '0; - sw_rd_en <= '0; - sw_wr_en <= '0; - sw_reg_wdata <= '0; - wr_be <= '0; - reg_cs_l <= '0; - reg_cs_2l <= '0; - end else begin - sw_addr <= reg_addr [3:2]; - sw_rd_en <= reg_cs & !reg_wr; - sw_wr_en <= reg_cs & reg_wr; - sw_reg_wdata <= reg_wdata; - wr_be <= reg_be; - reg_cs_l <= reg_cs; - reg_cs_2l <= reg_cs_l; - end -end + assign sw_addr = reg_addr [3:2]; + assign sw_rd_en = reg_cs & !reg_wr; + assign sw_wr_en = reg_cs & reg_wr; + assign wr_be = reg_be; //----------------------------------------------------------------------- // Read path mux @@ -134,18 +117,24 @@ always @ (posedge mclk or negedge reset_n) begin : preg_out_Seq - if (reset_n == 1'b0) begin - reg_rdata [31:0] <= 32'h0000_0000; - reg_ack <= 1'b0; - end else if (sw_rd_en && !reg_ack && !reg_cs_2l) begin - reg_rdata [31:0] <= reg_out [31:0]; - reg_ack <= 1'b1; - end else if (sw_wr_en && !reg_ack && !reg_cs_2l) begin - reg_ack <= 1'b1; - end else begin - reg_ack <= 1'b0; + if (reset_n == 1'b0) + begin + reg_rdata <= 'h0; + reg_ack <= 1'b0; + end + else if (sw_rd_en && !reg_ack) + begin + reg_rdata <= reg_out; + reg_ack <= 1'b1; + end + else if (sw_wr_en && !reg_ack) + reg_ack <= 1'b1; + else + begin + reg_ack <= 1'b0; end end + //----------------------------------------------------------------------- // register read enable and write enable decoding logic //----------------------------------------------------------------------- @@ -164,10 +153,10 @@ reg_out [31:0] = 32'd0; - case (sw_addr [3:0]) - 4'b0000 : reg_out [31:0] = reg_0 [31:0]; - 4'b0001 : reg_out [31:0] = reg_1 [31:0]; - 4'b0010 : reg_out [31:0] = reg_2 [31:0]; + case (sw_addr [1:0]) + 2'b00 : reg_out [31:0] = reg_0 [31:0]; + 2'b01 : reg_out [31:0] = reg_1 [31:0]; + 2'b10 : reg_out [31:0] = reg_2 [31:0]; default : reg_out [31:0] = 32'h0; endcase end @@ -180,6 +169,7 @@ // Logic for Register 0 : SPI Control Register //----------------------------------------------------------------------- assign cfg_op_req = reg_0[31]; // cpu request +assign cfg_endian = reg_0[25]; // Endian, 0 - little, 1 - Big assign cfg_tgt_sel = reg_0[24:23]; // target chip select assign cfg_op_type = reg_0[22:21]; // SPI operation type assign cfg_transfer_size = reg_0[20:19]; // SPI transfer size @@ -190,7 +180,7 @@ generic_register #(8,0 ) u_spi_ctrl_be0 ( .we ({8{sw_wr_en_0 & wr_be[0] }} ), - .data_in (sw_reg_wdata[7:0] ), + .data_in (reg_wdata[7:0] ), .reset_n (reset_n ), .clk (mclk ), @@ -201,7 +191,7 @@ generic_register #(8,0 ) u_spi_ctrl_be1 ( .we ({8{sw_wr_en_0 & wr_be[1] }} ), - .data_in (sw_reg_wdata[15:8] ), + .data_in (reg_wdata[15:8] ), .reset_n (reset_n ), .clk (mclk ), @@ -212,7 +202,7 @@ generic_register #(8,0 ) u_spi_ctrl_be2 ( .we ({8{sw_wr_en_0 & wr_be[2] }} ), - .data_in (sw_reg_wdata[23:16] ), + .data_in (reg_wdata[23:16] ), .reset_n (reset_n ), .clk (mclk ), @@ -220,12 +210,23 @@ .data_out (reg_0[23:16] ) ); -assign reg_0[30:24] = 7'h0; +generic_register #(2,0 ) u_spi_ctrl_be3 ( + .we ({2{sw_wr_en_0 & + wr_be[3] }} ), + .data_in (reg_wdata[25:24] ), + .reset_n (reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_0[25:24] ) + ); + +assign reg_0[30:26] = 5'h0; req_register #(0 ) u_spi_ctrl_req ( .cpu_we ({sw_wr_en_0 & wr_be[3] } ), - .cpu_req (sw_reg_wdata[31] ), + .cpu_req (reg_wdata[31] ), .hware_ack (hware_op_done ), .reset_n (reset_n ), .clk (mclk ), @@ -245,7 +246,7 @@ generic_register #(8,0 ) u_spi_din_be0 ( .we ({8{sw_wr_en_1 & wr_be[0] }} ), - .data_in (sw_reg_wdata[7:0] ), + .data_in (reg_wdata[7:0] ), .reset_n (reset_n ), .clk (mclk ), @@ -256,7 +257,7 @@ generic_register #(8,0 ) u_spi_din_be1 ( .we ({8{sw_wr_en_1 & wr_be[1] }} ), - .data_in (sw_reg_wdata[15:8] ), + .data_in (reg_wdata[15:8] ), .reset_n (reset_n ), .clk (mclk ), @@ -267,7 +268,7 @@ generic_register #(8,0 ) u_spi_din_be2 ( .we ({8{sw_wr_en_1 & wr_be[2] }} ), - .data_in (sw_reg_wdata[23:16] ), + .data_in (reg_wdata[23:16] ), .reset_n (reset_n ), .clk (mclk ), @@ -279,7 +280,7 @@ generic_register #(8,0 ) u_spi_din_be3 ( .we ({8{sw_wr_en_1 & wr_be[3] }} ), - .data_in (sw_reg_wdata[31:24] ), + .data_in (reg_wdata[31:24] ), .reset_n (reset_n ), .clk (mclk ),
diff --git a/verilog/rtl/sspim/src/sspim_ctl.sv b/verilog/rtl/sspim/src/sspim_ctl.sv index f65c0c2..ea6aa1f 100755 --- a/verilog/rtl/sspim/src/sspim_ctl.sv +++ b/verilog/rtl/sspim/src/sspim_ctl.sv
@@ -53,6 +53,7 @@ input logic clk, input logic reset_n, input logic cfg_op_req, + input logic cfg_endian, input logic [1:0] cfg_op_type, input logic [1:0] cfg_transfer_size, @@ -77,6 +78,8 @@ //************************************************************************* + parameter LITTLE_ENDIAN = 1'b0; + parameter BIG_ENDIAN = 1'b1; logic [5:0] clk_cnt; logic [5:0] sck_cnt; @@ -150,9 +153,14 @@ (byte_cnt == 2'b01) ? cfg_cs_byte[5:4] : (byte_cnt == 2'b10) ? cfg_cs_byte[3:2] : cfg_cs_byte[1:0] ; -assign byte_out = (byte_cnt == 2'b00) ? cfg_datain[31:24] : - (byte_cnt == 2'b01) ? cfg_datain[23:16] : - (byte_cnt == 2'b10) ? cfg_datain[15:8] : cfg_datain[7:0] ; +assign byte_out = (cfg_endian == LITTLE_ENDIAN) ? + ((byte_cnt == 2'b00) ? cfg_datain[7:0] : + (byte_cnt == 2'b01) ? cfg_datain[15:8] : + (byte_cnt == 2'b10) ? cfg_datain[23:16] : cfg_datain[31:24]) : + ((byte_cnt == 2'b00) ? cfg_datain[31:24] : + (byte_cnt == 2'b01) ? cfg_datain[23:16] : + (byte_cnt == 2'b10) ? cfg_datain[15:8] : cfg_datain[7:0]) ; + assign shift_out = shift_enb && sck_ne; @@ -252,13 +260,15 @@ cs_int_n <= cs_data[0]; if(sck_cnt == cfg_sck_cs_period) begin if(cfg_op_type == 1) begin // Read Mode - cfg_dataout <= (byte_cnt[1:0] == 2'b00) ? { byte_in, cfg_dataout[23:0] } : - (byte_cnt[1:0] == 2'b01) ? { cfg_dataout[31:24] , - byte_in, cfg_dataout[15:0] } : - (byte_cnt[1:0] == 2'b10) ? { cfg_dataout[31:16] , - byte_in, cfg_dataout[7:0] } : - { cfg_dataout[31:8] , - byte_in } ; + cfg_dataout <= (cfg_endian == LITTLE_ENDIAN) ? + ((byte_cnt[1:0] == 2'b00) ? { cfg_dataout[31:8],byte_in } : + (byte_cnt[1:0] == 2'b01) ? { cfg_dataout[31:16], byte_in, cfg_dataout[7:0] } : + (byte_cnt[1:0] == 2'b10) ? { cfg_dataout[31:24], byte_in, cfg_dataout[15:0] } : + { byte_in,cfg_dataout[23:0]}) : + ((byte_cnt[1:0] == 2'b00) ? { byte_in,cfg_dataout[23:0] } : + (byte_cnt[1:0] == 2'b01) ? { cfg_dataout[31:24], byte_in, cfg_dataout[15:0] } : + (byte_cnt[1:0] == 2'b10) ? { cfg_dataout[31:16], byte_in, cfg_dataout[7:0] } : + { cfg_dataout[31:8],byte_in}) ; end clr_sck_cnt <= 1'b1; if(byte_cnt == cfg_transfer_size) begin
diff --git a/verilog/rtl/sspim/src/sspim_top.sv b/verilog/rtl/sspim/src/sspim_top.sv index 0c740d6..8a632a0 100755 --- a/verilog/rtl/sspim/src/sspim_top.sv +++ b/verilog/rtl/sspim/src/sspim_top.sv
@@ -38,6 +38,12 @@ //// 0.1 - 03 Oct 2021, Dinesh A //// //// Initial SpI Module picked from //// //// http://www.opencores.org/cores/turbo8051/ //// +//// 0.2 - Mar 2, 2022, Dinesh A //// +//// 1. Reg Bus changes to match with wishbone format //// +//// 2. SPI tx and rx change to little endian format //// +//// i.e byte transfer [7:0],[15:8] ...[31:24] //// +//// Note: As per SPI transfer still first bit sent //// +//// out is big endian, i.e bit[7],[6] ..[0] //// //// //// ////////////////////////////////////////////////////////////////////// //// //// @@ -108,6 +114,7 @@ logic [1:0] cfg_tgt_sel ; logic cfg_op_req ; // SPI operation request +logic cfg_endian ; // Endian selection logic [1:0] cfg_op_type ; // SPI operation type logic [1:0] cfg_transfer_size ; // SPI transfer size logic [5:0] cfg_sck_period ; // sck clock period @@ -150,6 +157,7 @@ . reset_n (reset_n ), . cfg_op_req (cfg_op_req ), + . cfg_endian (cfg_endian ), . cfg_op_type (cfg_op_type ), . cfg_transfer_size (cfg_transfer_size ), . cfg_sck_period (cfg_sck_period ), @@ -194,6 +202,7 @@ // configuration signal . cfg_tgt_sel (cfg_tgt_sel ), . cfg_op_req (cfg_op_req ), // SPI operation request + . cfg_endian (cfg_endian ), . cfg_op_type (cfg_op_type ), // SPI operation type . cfg_transfer_size (cfg_transfer_size ), // SPI transfer size . cfg_sck_period (cfg_sck_period ), // sck clock period
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index bfda0c9..1ca7c78 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -187,6 +187,9 @@ //// spi clock config = 0x2 //// //// 2. spi_oen generation fix for different spi mode //// //// 3. spi_csn de-assertion fix for different spi clk div //// +//// 3.7 Mar 2, Dinesh A //// +//// 1. qspi cs# port mapping changed from io 28:25 to 25:28//// +//// 2. sspi, bug fix in reg access and endian support added//// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -415,7 +418,8 @@ //---------------------------------------------------- // CPU Configuration //---------------------------------------------------- -wire cpu_rst_n ; +wire cpu_intf_rst_n ; +wire [1:0] cpu_core_rst_n ; wire qspim_rst_n ; wire sspim_rst_n ; wire uart_rst_n ; // uart reset @@ -592,13 +596,6 @@ .usb_clk (usb_clk ), .wbd_int_rst_n (wbd_int_rst_n ), - .cpu_rst_n (cpu_rst_n ), - .qspim_rst_n (qspim_rst_n ), - .sspim_rst_n (sspim_rst_n ), // spi reset - .uart_rst_n (uart_rst_n ), // uart reset - .i2cm_rst_n (i2c_rst_n ), // i2c reset - .usb_rst_n (usb_rst_n ), // usb reset - .bist_rst_n (bist_rst_n ), // BIST Reset // Master Port .wbm_rst_i (wb_rst_i ), @@ -660,7 +657,7 @@ // Reset .pwrup_rst_n (wbd_int_rst_n ), .rst_n (wbd_int_rst_n ), - .cpu_rst_n (cpu_rst_n ), + .cpu_rst_n (cpu_core_rst_n[0] ), .riscv_debug (riscv_debug ), // Clock @@ -854,13 +851,13 @@ /********************************************************* * SPI Master -* This is of an SPI master that is controlled via an AXI bus . +* This is implementation of an SPI master that is controlled via an AXI bus . * It has FIFOs for transmitting and receiving data. * It supports both the normal SPI mode and QPI mode with 4 data lines. * *******************************************************/ qspim_top -# ( +#( `ifndef SYNTHESIS .WB_WIDTH (WB_WIDTH ) `endif @@ -1119,6 +1116,17 @@ .mclk (wbd_clk_pinmux_skew ), .h_reset_n (wbd_int_rst_n ), + // Reset Control + .cpu_core_rst_n (cpu_core_rst_n ), + .cpu_intf_rst_n (cpu_intf_rst_n ), + .qspim_rst_n (qspim_rst_n ), + .sspim_rst_n (sspim_rst_n ), + .uart_rst_n (uart_rst_n ), + .i2cm_rst_n (i2c_rst_n ), + .usb_rst_n (usb_rst_n ), + + .cfg_riscv_debug_sel ( ), + // Reg Bus Interface Signal .reg_cs (wbd_glbl_stb_o ), .reg_wr (wbd_glbl_we_o ),