riscv compliance test cleanup
diff --git a/verilog/dv/riscv_regress/riscv_runtests.sv b/verilog/dv/riscv_regress/riscv_runtests.sv index bfbb3bb..ee1aeca 100644 --- a/verilog/dv/riscv_regress/riscv_runtests.sv +++ b/verilog/dv/riscv_regress/riscv_runtests.sv
@@ -53,7 +53,7 @@ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.dmem2core_rdata_i,`RISC_CORE.dmem2core_resp_i); end **/ -/** +/*** logic [31:0] test_count; `define RISC_CORE u_top.u_riscv_top.i_core_top `define RISC_EXU u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu @@ -162,18 +162,15 @@ while (!$feof(fd) && (start != stop)) begin $fscanf(fd, "0x%h,\n", ref_data); //---------------------------------------------------- - // Note: 32'h2xxx_xxxx address mapped to SDRAM // Assumed all signaure are with-in first 512 location of memory, // other-wise need to switch bank // -------------------------------------------------- - test_data[31:24] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+3]; - test_data[23:16] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+2]; - test_data[15:8] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+1]; - test_data[7:0] = u_top.u_tsram0_2kb.mem[(start & 32'h1FFF)+0]; + //$writememh("sram0_out.hex",u_top.u_tsram0_2kb.mem,0,511); + test_data = u_top.u_tsram0_2kb.mem[((start >> 2) & 32'h1FFF)]; //$display("Compare Addr: %x ref_data : %x, test_data: %x",start,ref_data,test_data); test_pass &= (ref_data == test_data); if(ref_data != test_data) - $display("ERROR: Compare Addr: %x ref_data : %x, test_data: %x",start,ref_data,test_data); + $display("ERROR: Compare Addr: %x Mem Addr: %x ref_data : %x, test_data: %x",start,start & 32'h1FFF,ref_data,test_data); start += 4; end $fclose(fd);
diff --git a/verilog/dv/riscv_regress/run_iverilog b/verilog/dv/riscv_regress/run_iverilog index 7e1401b..8200d99 100755 --- a/verilog/dv/riscv_regress/run_iverilog +++ b/verilog/dv/riscv_regress/run_iverilog
@@ -10,17 +10,10 @@ rm /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/sc_print.o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/crt_tcm.o /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/hello.o cd /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0 -iverilog -g2005-sv -DFUNCTIONAL -DWFDUMP -DSIM -I /opt/pdk/sky130A \ --I /home/dinesha/workarea/efabless/MPW-4/caravel/verilog/dv/caravel -I /home/dinesha/workarea/efabless/MPW-4/caravel/verilog/rtl \ --I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../model -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog \ --I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../agents \ --I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/syntacore/scr1/src/includes -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/sdram_ctrl/src/defs -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/i2cm/src/includes \ --I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/usb1_host/src/includes -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/mbist/include -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress \ -../../user_risc_regress_tb.v \ --o user_risc_regress_tb.vvp + +iverilog -g2005-sv -DFUNCTIONAL -DWFDUMP -DSIM -I /opt/pdk/sky130A -I /home/dinesha/workarea/efabless/MPW-4/caravel/verilog/dv/caravel -I /home/dinesha/workarea/efabless/MPW-4/caravel/verilog/rtl -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../model -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../agents -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/syntacore/scr1/src/includes -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/sdram_ctrl/src/defs -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/i2cm/src/includes -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/usb1_host/src/includes -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/../../../verilog/rtl/mbist/include -I /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress ../../user_risc_regress_tb.v -o user_risc_regress_tb.vvp iverilog-vpi ../../../vpi/system/system.c -vvp -M. -msystem user_risc_regress_tb.vvp \ -+test_info=/home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/test_info \ -+test_results=/home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/test_results.txt \ -| tee /home/dinesha/workarea/opencore/git/riscduino/verilog/dv/riscv_regress/build/iverilog_WB_MAX_imc_IPIC_1_TCM_1_VIRQ_1_TRACE_0/sim_results.txt + +vvp -M. -msystem user_risc_regress_tb.vvp +test_info=./test_info +test_results=./test_results.txt | tee sim_results.txt +
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index 894ffb3..5b06160 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -133,7 +133,7 @@ int unsigned tests_passed; int unsigned tests_total; - logic [7:0] tem_mem[0:2047]; + logic [31:0] tem_mem[0:1047]; //----------------------------------------------------------------- @@ -199,8 +199,18 @@ // some of the RISCV test need SRAM area for specific // instruction execution like fence $sformat(test_ram_file, "%s.ram",test_file); - $write("\033[0;34m---Initializing the u_tsram0_2kb Memory with Hexfile: %s\033[0m\n", test_ram_file); - $readmemh(test_ram_file,u_top.u_tsram0_2kb.mem); + // Load the RAM content to local temp memory + $readmemh(test_ram_file,tem_mem); + // Split the Temp memory content to two sram file + $readmemh(test_ram_file,tem_mem); + $writememh("sram0.hex",tem_mem,0,511); + $writememh("sram1.hex",tem_mem,512,1023); + // Load the SRAM0/SRAM1 with 2KB data + $write("\033[0;34m---Initializing the u_tsram0_2kb Memory with Hexfile: sram0.hex\033[0m\n"); + $readmemh("sram0.hex",u_top.u_tsram0_2kb.mem); + $write("\033[0;34m---Initializing the u_tsram1_2kb Memory with Hexfile: sram1.hex\033[0m\n"); + $readmemh("sram1.hex",u_top.u_tsram1_2kb.mem); + //for(i =32'h00; i < 32'h100; i = i+1) // $display("Location: %x, Data: %x", i, u_top.u_tsram0_2kb.mem[i]);