syntacore interface change to wishbone
diff --git a/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv b/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv
index f5f82df..d53127b 100644
--- a/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv
+++ b/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv
@@ -100,7 +100,6 @@
function automatic type_scr1_search_one_16_s scr1_search_one_16(
input logic [15:0] din
);
-begin
logic [7:0] stage1_vd;
logic [3:0] stage2_vd;
logic [1:0] stage3_vd;
@@ -109,7 +108,9 @@
logic [1:0] stage2_idx [3:0];
logic [2:0] stage3_idx [1:0];
type_scr1_search_one_16_s result;
+ type_scr1_search_one_2_s tmp;
integer i; // cp.17
+begin
// Stage 1
for (i=0; i<8; i=i+1) begin
tmp = scr1_search_one_2(din[(i+1)*2-1-:2]);
diff --git a/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv b/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv
index f638a1a..ca96215 100644
--- a/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv
+++ b/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv
@@ -78,7 +78,7 @@
input logic exu2csr_take_exc_i, // Take exception trap
input logic exu2csr_mret_update_i, // MRET update CSR
input logic exu2csr_mret_instr_i, // MRET instruction
- input type_scr1_exc_code_e exu2csr_exc_code_i, // Exception code (see scr1_arch_types.svh)
+ input logic [SCR1_EXC_CODE_WIDTH_E-1:0] exu2csr_exc_code_i, // Exception code (see scr1_arch_types.svh) - cp.7
input logic [`SCR1_XLEN-1:0] exu2csr_trap_val_i, // Trap value
output logic csr2exu_irq_o, // IRQ request
output logic csr2exu_ip_ie_o, // Some IRQ pending and locally enabled
@@ -181,9 +181,9 @@
logic csr_mcause_upd; // MCAUSE update enable
logic csr_mcause_i_ff; // MCAUSE: Interrupt
logic csr_mcause_i_next; // MCAUSE: Interrupt next value
-type_scr1_exc_code_e csr_mcause_ec_ff; // MCAUSE: Exception code
-type_scr1_exc_code_e csr_mcause_ec_next; // MCAUSE: Exception code next value
-type_scr1_exc_code_e csr_mcause_ec_new; // MCAUSE: Exception code new value (IRQs)
+logic [SCR1_EXC_CODE_WIDTH_E-1:0] csr_mcause_ec_ff; // MCAUSE: Exception code - cp.7
+logic [SCR1_EXC_CODE_WIDTH_E-1:0] csr_mcause_ec_next; // MCAUSE: Exception code next value - cp.7
+logic [SCR1_EXC_CODE_WIDTH_E-1:0] csr_mcause_ec_new; // MCAUSE: Exception code new value (IRQs) - cp.7
// MTVAL register
logic csr_mtval_upd; // MTVAL update enable
diff --git a/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_exu.sv b/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_exu.sv
index f518a84..b587fa0 100644
--- a/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_exu.sv
+++ b/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_exu.sv
@@ -94,7 +94,7 @@
output logic exu2csr_take_exc_o, // Take exception trap
output logic exu2csr_mret_update_o, // MRET update CSR
output logic exu2csr_mret_instr_o, // MRET instruction
- output type_scr1_exc_code_e exu2csr_exc_code_o, // Exception code (see scr1_arch_types.svh)
+ output logic [SCR1_EXC_CODE_WIDTH_E-1:0] exu2csr_exc_code_o, // Exception code (see scr1_arch_types.svh) - cp.7
output logic [`SCR1_XLEN-1:0] exu2csr_trap_val_o, // Trap value
input logic [`SCR1_XLEN-1:0] csr2exu_new_pc_i, // Exception/IRQ/MRET new PC
input logic csr2exu_irq_i, // IRQ request
@@ -103,13 +103,13 @@
// EXU <-> DMEM interface
output logic exu2dmem_req_o, // Data memory request
- output type_scr1_mem_cmd_e exu2dmem_cmd_o, // Data memory command
+ output logic exu2dmem_cmd_o, // Data memory command - cp.7
output type_scr1_mem_width_e exu2dmem_width_o, // Data memory width
output logic [`SCR1_DMEM_AWIDTH-1:0] exu2dmem_addr_o, // Data memory address
output logic [`SCR1_DMEM_DWIDTH-1:0] exu2dmem_wdata_o, // Data memory write data
input logic dmem2exu_req_ack_i, // Data memory request acknowledge
input logic [`SCR1_DMEM_DWIDTH-1:0] dmem2exu_rdata_i, // Data memory read data
- input type_scr1_mem_resp_e dmem2exu_resp_i, // Data memory response
+ input logic [1:0] dmem2exu_resp_i, // Data memory response - cp.7
// EXU control
output logic exu2pipe_exc_req_o, // Exception on last instruction
@@ -219,7 +219,7 @@
logic exu_exc_req_ff;
logic exu_exc_req_next;
`endif // SCR1_DBG_EN
-type_scr1_exc_code_e exc_code;
+logic [SCR1_EXC_CODE_WIDTH_E-1:0] exc_code; // cp.7
logic [`SCR1_XLEN-1:0] exc_trap_val;
logic instr_fault_rvi_hi;
@@ -263,7 +263,7 @@
logic lsu_rdy;
logic [`SCR1_XLEN-1:0] lsu_l_data;
logic lsu_exc_req;
-type_scr1_exc_code_e lsu_exc_code;
+logic [SCR1_EXC_CODE_WIDTH_E-1:0] lsu_exc_code; // cp.7
// EXU status signals
//------------------------------------------------------------------------------
diff --git a/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv b/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv
index d18629c..86b4d41 100644
--- a/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv
+++ b/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv
@@ -80,10 +80,19 @@
assign instr = ifu2idu_instr_i;
// RVI / RVC
-assign instr_type = instr[1:0];
+`ifdef YOSYS
+assign instr_type = 2'(instr[1:0]);
+`else
+
+assign instr_type = type_scr1_instr_type_e'(instr[1:0]);
+`endif
// RVI / RVC fields
-assign rvi_opcode = instr[6:2]; // RVI
+`ifdef YOSYS
+assign rvi_opcode = 5'(instr[6:2]); // RVI
+`else
+assign rvi_opcode = type_scr1_rvi_opcode_e'(instr[6:2]); // RVI
+`endif
assign funct3 = (instr_type == SCR1_INSTR_RVI) ? instr[14:12] : instr[15:13]; // RVI / RVC
assign funct7 = instr[31:25]; // RVI
assign funct12 = instr[31:20]; // RVI (SYSTEM)
diff --git a/verilog/rtl/syntacore_scr1/src/includes/scr1_wb.svh b/verilog/rtl/syntacore_scr1/src/includes/scr1_wb.svh
new file mode 100644
index 0000000..58f99d6
--- /dev/null
+++ b/verilog/rtl/syntacore_scr1/src/includes/scr1_wb.svh
@@ -0,0 +1,66 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// yifive Wishbone define for syntacore ////
+//// ////
+//// This file is part of the yifive cores project ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description: ////
+//// integrated wishbone i/f to Syntacore,scr1 core ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// v0: June 7, 2021, Dinesh A ////
+//// wishbone define added ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+// Orginal owner Details ////
+//////////////////////////////////////////////////////////////////////
+/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details///
+/// @file <scr1_ahb.svh> ///
+/// @brief WB header file ///
+/////////////////////////////////////////////////////////////////////
+
+`ifndef SCR1_WB_SVH
+`define SCR1_WB_SVH
+
+`include "scr1_arch_description.svh"
+
+parameter SCR1_WB_WIDTH = 32;
+
+// Encoding for DATA SIZE
+parameter logic [2:0] SCR1_DSIZE_8B = 3'b000;
+parameter logic [2:0] SCR1_DSIZE_16B = 3'b001;
+parameter logic [2:0] SCR1_DSIZE_32B = 3'b010;
+
+`endif // SCR1_WB_SVH
diff --git a/verilog/rtl/syntacore_scr1/src/run_modemsim b/verilog/rtl/syntacore_scr1/src/run_modemsim
new file mode 100755
index 0000000..ae5f764
--- /dev/null
+++ b/verilog/rtl/syntacore_scr1/src/run_modemsim
@@ -0,0 +1,2 @@
+vlib work
+vlog -f wb_top.files -f core.files +incdir+includes -sv
diff --git a/verilog/rtl/syntacore_scr1/src/top/scr1_dmem_wb.sv b/verilog/rtl/syntacore_scr1/src/top/scr1_dmem_wb.sv
new file mode 100644
index 0000000..9aa0b4d
--- /dev/null
+++ b/verilog/rtl/syntacore_scr1/src/top/scr1_dmem_wb.sv
@@ -0,0 +1,448 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// yifive Wishbone interface for Data memory ////
+//// ////
+//// This file is part of the yifive cores project ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description: ////
+//// integrated wishbone i/f to data memory ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// v0: June 7, 2021, Dinesh A ////
+//// wishbone integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+// Orginal owner Details ////
+//////////////////////////////////////////////////////////////////////
+/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details///
+/// @file <scr1_dmem_wb.sv> ///
+/// @brief Data memory WB bridge ///
+/////////////////////////////////////////////////////////////////////
+
+`include "scr1_wb.svh"
+`include "scr1_memif.svh"
+
+module scr1_dmem_wb (
+ // Control Signals
+ input logic rst_n,
+ input logic clk,
+
+ // Core Interface
+ output logic dmem_req_ack,
+ input logic dmem_req,
+ input type_scr1_mem_cmd_e dmem_cmd,
+ input type_scr1_mem_width_e dmem_width,
+ input logic [SCR1_WB_WIDTH-1:0] dmem_addr,
+ input logic [SCR1_WB_WIDTH-1:0] dmem_wdata,
+ output logic [SCR1_WB_WIDTH-1:0] dmem_rdata,
+ output type_scr1_mem_resp_e dmem_resp,
+
+ // WB Interface
+ output logic wbd_stb_o, // strobe/request
+ output logic [SCR1_WB_WIDTH-1:0] wbd_adr_o, // address
+ output logic wbd_we_o, // write
+ output logic [SCR1_WB_WIDTH-1:0] wbd_dat_o, // data output
+ output logic [3:0] wbd_sel_o, // byte enable
+ input logic [SCR1_WB_WIDTH-1:0] wbd_dat_i, // data input
+ input logic wbd_ack_i, // acknowlegement
+ input logic wbd_err_i // error
+
+);
+
+//-------------------------------------------------------------------------------
+// Local Parameters
+//-------------------------------------------------------------------------------
+`ifndef SCR1_DMEM_WB_OUT_BP
+localparam SCR1_FIFO_WIDTH = 2;
+localparam SCR1_FIFO_CNT_WIDTH = 2;
+`endif // SCR1_DMEM_WB_OUT_BP
+
+//-------------------------------------------------------------------------------
+// Local type declaration
+//-------------------------------------------------------------------------------
+typedef enum logic {
+ SCR1_FSM_ADDR = 1'b0,
+ SCR1_FSM_DATA = 1'b1,
+ SCR1_FSM_ERR = 1'bx
+} type_scr1_fsm_e;
+
+typedef struct packed {
+ logic hwrite;
+ logic [2:0] hwidth;
+ logic [SCR1_WB_WIDTH-1:0] haddr;
+ logic [SCR1_WB_WIDTH-1:0] hwdata;
+} type_scr1_req_fifo_s;
+
+typedef struct packed {
+ logic hwrite;
+ logic [2:0] hwidth;
+ logic [1:0] haddr;
+} type_scr1_data_fifo_s;
+
+typedef struct packed {
+ logic hresp;
+ logic [2:0] hwidth;
+ logic [1:0] haddr;
+ logic [SCR1_WB_WIDTH-1:0] hrdata;
+} type_scr1_resp_fifo_s;
+
+//-------------------------------------------------------------------------------
+// Local functions
+//-------------------------------------------------------------------------------
+function automatic logic [2:0] scr1_conv_mem2wb_width (
+ input type_scr1_mem_width_e dmem_width
+);
+ logic [2:0] tmp;
+begin
+ case (dmem_width)
+ SCR1_MEM_WIDTH_BYTE : begin
+ tmp = SCR1_DSIZE_8B;
+ end
+ SCR1_MEM_WIDTH_HWORD : begin
+ tmp = SCR1_DSIZE_16B;
+ end
+ SCR1_MEM_WIDTH_WORD : begin
+ tmp = SCR1_DSIZE_32B;
+ end
+ default : begin
+ tmp = SCR1_DSIZE_32B;
+ end
+ endcase
+ scr1_conv_mem2wb_width = tmp; // cp.11
+end
+endfunction
+
+function automatic logic[SCR1_WB_WIDTH-1:0] scr1_conv_mem2wb_wdata (
+ input logic [1:0] dmem_addr,
+ input type_scr1_mem_width_e dmem_width,
+ input logic [SCR1_WB_WIDTH-1:0] dmem_wdata
+);
+ logic [SCR1_WB_WIDTH-1:0] tmp;
+begin
+ tmp = 'x;
+ case (dmem_width)
+ SCR1_MEM_WIDTH_BYTE : begin
+ case (dmem_addr)
+ 2'b00 : begin
+ tmp[7:0] = dmem_wdata[7:0];
+ end
+ 2'b01 : begin
+ tmp[15:8] = dmem_wdata[7:0];
+ end
+ 2'b10 : begin
+ tmp[23:16] = dmem_wdata[7:0];
+ end
+ 2'b11 : begin
+ tmp[31:24] = dmem_wdata[7:0];
+ end
+ default : begin
+ end
+ endcase
+ end
+ SCR1_MEM_WIDTH_HWORD : begin
+ case (dmem_addr[1])
+ 1'b0 : begin
+ tmp[15:0] = dmem_wdata[15:0];
+ end
+ 1'b1 : begin
+ tmp[31:16] = dmem_wdata[15:0];
+ end
+ default : begin
+ end
+ endcase
+ end
+ SCR1_MEM_WIDTH_WORD : begin
+ tmp = dmem_wdata;
+ end
+ default : begin
+ end
+ endcase
+ scr1_conv_mem2wb_wdata = tmp;
+end
+endfunction
+
+function automatic logic[SCR1_WB_WIDTH-1:0] scr1_conv_wb2mem_rdata (
+ input logic [2:0] hwidth,
+ input logic [1:0] haddr,
+ input logic [SCR1_WB_WIDTH-1:0] hrdata
+);
+ logic [SCR1_WB_WIDTH-1:0] tmp;
+begin
+ tmp = 'x;
+ case (hwidth)
+ SCR1_DSIZE_8B : begin
+ case (haddr)
+ 2'b00 : tmp[7:0] = hrdata[7:0];
+ 2'b01 : tmp[7:0] = hrdata[15:8];
+ 2'b10 : tmp[7:0] = hrdata[23:16];
+ 2'b11 : tmp[7:0] = hrdata[31:24];
+ default : begin
+ end
+ endcase
+ end
+ SCR1_DSIZE_16B : begin
+ case (haddr[1])
+ 1'b0 : tmp[15:0] = hrdata[15:0];
+ 1'b1 : tmp[15:0] = hrdata[31:16];
+ default : begin
+ end
+ endcase
+ end
+ SCR1_DSIZE_32B : begin
+ tmp = hrdata;
+ end
+ default : begin
+ end
+ endcase
+ scr1_conv_wb2mem_rdata = tmp;
+end
+endfunction
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+logic req_fifo_rd;
+logic req_fifo_wr;
+logic req_fifo_up;
+`ifdef SCR1_DMEM_WB_OUT_BP
+type_scr1_req_fifo_s req_fifo_new;
+type_scr1_req_fifo_s req_fifo_r;
+type_scr1_req_fifo_s [0:0] req_fifo;
+`else // SCR1_DMEM_WB_OUT_BP
+type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo;
+type_scr1_req_fifo_s [0:SCR1_FIFO_WIDTH-1] req_fifo_new;
+logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt;
+logic [SCR1_FIFO_CNT_WIDTH-1:0] req_fifo_cnt_new;
+`endif // SCR1_DMEM_WB_OUT_BP
+logic req_fifo_empty;
+logic req_fifo_full;
+
+type_scr1_data_fifo_s data_fifo;
+type_scr1_resp_fifo_s resp_fifo;
+logic resp_fifo_hready;
+
+//-------------------------------------------------------------------------------
+// Interface to Core
+//-------------------------------------------------------------------------------
+assign dmem_req_ack = ~req_fifo_full;
+assign req_fifo_wr = ~req_fifo_full & dmem_req;
+
+assign dmem_rdata = scr1_conv_wb2mem_rdata(resp_fifo.hwidth, resp_fifo.haddr, resp_fifo.hrdata);
+
+assign dmem_resp = (resp_fifo_hready)
+ ? (resp_fifo.hresp == 1'b1)
+ ? SCR1_MEM_RESP_RDY_OK
+ : SCR1_MEM_RESP_RDY_ER
+ : SCR1_MEM_RESP_NOTRDY ;
+
+//-------------------------------------------------------------------------------
+// REQ_FIFO
+//-------------------------------------------------------------------------------
+`ifdef SCR1_DMEM_WB_OUT_BP
+always_ff @(negedge rst_n, posedge clk) begin
+ if (~rst_n) begin
+ req_fifo_full <= 1'b0;
+ end else begin
+ if (~req_fifo_full) begin
+ req_fifo_full <= dmem_req & ~req_fifo_rd;
+ end else begin
+ req_fifo_full <= ~req_fifo_rd;
+ end
+ end
+end
+assign req_fifo_empty = ~(req_fifo_full | dmem_req);
+
+assign req_fifo_up = ~req_fifo_rd & req_fifo_wr;
+always_ff @(posedge clk) begin
+ if (req_fifo_up) begin
+ req_fifo_r <= req_fifo_new;
+ end
+end
+
+assign req_fifo_new.hwrite = dmem_req ? (dmem_cmd == SCR1_MEM_CMD_WR) : 1'b0;
+assign req_fifo_new.hwidth = dmem_req ? scr1_conv_mem2wb_width(dmem_width) : '0;
+assign req_fifo_new.haddr = dmem_req ? dmem_addr : '0;
+assign req_fifo_new.hwdata = (dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR))
+ ? scr1_conv_mem2wb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata)
+ : '0;
+assign req_fifo[0] = (req_fifo_full) ? req_fifo_r: req_fifo_new;
+
+//-------------------------------------------------------------------------------
+// Register Data from response path - Used by Read path logic
+//-------------------------------------------------------------------------------
+always_ff @(posedge clk) begin
+ if (wbd_ack_i) begin
+ if (~req_fifo_empty) begin
+ data_fifo.hwidth <= req_fifo[0].hwidth;
+ data_fifo.haddr <= req_fifo[0].haddr[1:0];
+ end
+ end
+end
+
+`else // SCR1_DMEM_WB_OUT_BP
+
+
+wire hwrite_in = (dmem_cmd == SCR1_MEM_CMD_WR);
+wire [2:0] hwidth_in = scr1_conv_mem2wb_width(dmem_width);
+wire [SCR1_WB_WIDTH-1:0] haddr_in = dmem_addr;
+wire [SCR1_WB_WIDTH-1:0] hwdata_in = scr1_conv_mem2wb_wdata(dmem_addr[1:0], dmem_width, dmem_wdata);
+
+reg [3:0] hbel_in; // byte select
+always_comb begin
+ hbel_in = 0;
+ case (hwidth_in)
+ SCR1_DSIZE_8B : begin
+ hbel_in = 4'b0001 << haddr_in[1:0];
+ end
+ SCR1_DSIZE_16B : begin
+ hbel_in = 4'b0011 << haddr_in[1:0];
+ end
+ SCR1_DSIZE_32B : begin
+ hbel_in = 4'b1111;
+ end
+ endcase
+end
+
+
+wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_din = {hbel_in,hwrite_in,hwidth_in,haddr_in,hwdata_in};
+
+ sync_fifo #(
+ .DATA_WIDTH(SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+1+4), // Data Width
+ .ADDR_WIDTH(1), // Address Width
+ .FIFO_DEPTH(2) // FIFO DEPTH
+ ) u_req_fifo(
+
+ .dout (req_fifo_dout ),
+
+ .rstn (rst_n ),
+ .clk (clk ),
+ .wr_en (req_fifo_wr ), // Write
+ .rd_en (req_fifo_rd ), // Read
+ .din (req_fifo_din ),
+ .full (req_fifo_full ),
+ .empty (req_fifo_empty )
+);
+
+//-------------------------------------------------------------------------------
+// Register Data from response path - Used by Read path logic
+//-------------------------------------------------------------------------------
+wire hwrite_out;
+wire [2:0] hwidth_out;
+wire [SCR1_WB_WIDTH-1:0] haddr_out;
+wire [SCR1_WB_WIDTH-1:0] hwdata_out;
+wire [3:0] hbel_out;
+
+assign {hbel_out,hwrite_out,hwidth_out,haddr_out,hwdata_out} = req_fifo_dout;
+
+always_ff @(posedge clk) begin
+ if (wbd_ack_i) begin
+ if (~req_fifo_empty) begin
+ data_fifo.hwidth <= hwidth_out;
+ data_fifo.haddr <= haddr_out[1:0];
+ end
+ end
+end
+
+`endif // SCR1_DMEM_WB_OUT_BP
+
+
+always_comb begin
+ req_fifo_rd = 1'b0;
+ if (wbd_ack_i) begin
+ req_fifo_rd = ~req_fifo_empty;
+ end
+end
+
+
+//-------------------------------------------------------------------------------
+// FIFO response
+//-------------------------------------------------------------------------------
+`ifdef SCR1_DMEM_WB_IN_BP
+
+assign resp_fifo_hready = wbd_ack_i;
+assign resp_fifo.hresp = (wbd_err_i) ? 1'b0 : 1'b1;
+assign resp_fifo.hwidth = data_fifo.hwidth;
+assign resp_fifo.haddr = data_fifo.haddr;
+assign resp_fifo.hrdata = wbd_dat_i;
+
+assign wbd_stb_o = ~req_fifo_empty;
+assign wbd_adr_o = req_fifo[0].haddr;
+assign wbd_we_o = req_fifo[0].hwrite;
+assign wbd_dat_o = req_fifo[0].hwdata;
+
+always_comb begin
+ wbd_sel_o = 0;
+ case (req_fifo[0].hwidth)
+ SCR1_DSIZE_8B : begin
+ wbd_sel_o = 4'b0001 << req_fifo[0].haddr[1:0];
+ end
+ SCR1_DSIZE_16B : begin
+ wbd_sel_o = 4'b0011 << req_fifo[0].haddr[1:0];
+ end
+ SCR1_DSIZE_32B : begin
+ wbd_sel_o = 4'b1111;
+ end
+ endcase
+end
+`else // SCR1_DMEM_WB_IN_BP
+always_ff @(negedge rst_n, posedge clk) begin
+ if (~rst_n) begin
+ resp_fifo_hready <= 1'b0;
+ end else begin
+ resp_fifo_hready <= wbd_ack_i ;
+ end
+end
+
+always_ff @(posedge clk) begin
+ if (wbd_ack_i) begin
+ resp_fifo.hresp <= (wbd_err_i) ? 1'b0 : 1'b1;
+ resp_fifo.hwidth <= data_fifo.hwidth;
+ resp_fifo.haddr <= data_fifo.haddr;
+ resp_fifo.hrdata <= wbd_dat_i;
+ end
+end
+
+
+assign wbd_stb_o = ~req_fifo_empty;
+assign wbd_adr_o = haddr_out;
+assign wbd_we_o = hwrite_out;
+assign wbd_dat_o = hwdata_out;
+assign wbd_sel_o = hbel_out;
+
+`endif // SCR1_DMEM_WB_IN_BP
+
+
+
+endmodule : scr1_dmem_wb
diff --git a/verilog/rtl/syntacore_scr1/src/top/scr1_imem_wb.sv b/verilog/rtl/syntacore_scr1/src/top/scr1_imem_wb.sv
new file mode 100644
index 0000000..1346b59
--- /dev/null
+++ b/verilog/rtl/syntacore_scr1/src/top/scr1_imem_wb.sv
@@ -0,0 +1,273 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// yifive Wishbone interface for Instruction memory ////
+//// ////
+//// This file is part of the yifive cores project ////
+//// http://www.opencores.org/cores/yifive/ ////
+//// ////
+//// Description: ////
+//// integrated wishbone i/f to instruction memory ////
+//// ////
+//// To Do: ////
+//// nothing ////
+//// ////
+//// Author(s): ////
+//// - Dinesh Annayya, dinesha@opencores.org ////
+//// ////
+//// Revision : ////
+//// v0: June 7, 2021, Dinesh A ////
+//// wishbone integration ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+// Orginal owner Details ////
+//////////////////////////////////////////////////////////////////////
+/// Copyright by Syntacore LLC © 2016-2021. See LICENSE for details///
+/// @file <scr1_imem_wb.sv> ///
+/// @brief Instruction memory AHB bridge ///
+//////////////////////////////////////////////////////////////////////
+
+`include "scr1_wb.svh"
+`include "scr1_memif.svh"
+
+module scr1_imem_wb (
+ // Control Signals
+ input logic rst_n,
+ input logic clk,
+
+ // Core Interface
+ output logic imem_req_ack,
+ input logic imem_req,
+ input logic [SCR1_WB_WIDTH-1:0] imem_addr,
+ output logic [SCR1_WB_WIDTH-1:0] imem_rdata,
+ output type_scr1_mem_resp_e imem_resp,
+
+ // WB Interface
+ output logic wbd_stb_o, // strobe/request
+ output logic [SCR1_WB_WIDTH-1:0] wbd_adr_o, // address
+ output logic wbd_we_o, // write
+ output logic [SCR1_WB_WIDTH-1:0] wbd_dat_o, // data output
+ output logic [3:0] wbd_sel_o, // byte enable
+ input logic [SCR1_WB_WIDTH-1:0] wbd_dat_i, // data input
+ input logic wbd_ack_i, // acknowlegement
+ input logic wbd_err_i // error
+
+);
+
+//-------------------------------------------------------------------------------
+// Local parameters declaration
+//-------------------------------------------------------------------------------
+`ifndef SCR1_IMEM_WB_OUT_BP
+localparam SCR1_FIFO_WIDTH = 2;
+localparam SCR1_FIFO_CNT_WIDTH = $clog2(SCR1_FIFO_WIDTH+1);
+`endif // SCR1_IMEM_WB_OUT_BP
+
+//-------------------------------------------------------------------------------
+// Local types declaration
+//-------------------------------------------------------------------------------
+typedef enum logic {
+ SCR1_FSM_ADDR = 1'b0,
+ SCR1_FSM_DATA = 1'b1,
+ SCR1_FSM_ERR = 1'bx
+} type_scr1_fsm_e;
+
+typedef struct packed {
+ logic [SCR1_WB_WIDTH-1:0] haddr;
+} type_scr1_req_fifo_s;
+
+typedef struct packed {
+ logic hresp;
+ logic [SCR1_WB_WIDTH-1:0] hrdata;
+} type_scr1_resp_fifo_s;
+
+//-------------------------------------------------------------------------------
+// Local signal declaration
+//-------------------------------------------------------------------------------
+type_scr1_fsm_e fsm;
+logic req_fifo_rd;
+logic req_fifo_wr;
+logic req_fifo_up;
+`ifdef SCR1_IMEM_WB_OUT_BP
+type_scr1_req_fifo_s req_fifo_r;
+type_scr1_req_fifo_s [0:0] req_fifo;
+`else // SCR1_IMEM_WB_OUT_BP
+logic [SCR1_WB_WIDTH-1:0] req_fifo_dout;
+`endif // SCR1_IMEM_WB_OUT_BP
+
+logic req_fifo_empty;
+logic req_fifo_full;
+
+type_scr1_resp_fifo_s resp_fifo;
+logic resp_fifo_hready;
+
+//-------------------------------------------------------------------------------
+// Interface to Core
+//-------------------------------------------------------------------------------
+assign imem_req_ack = ~req_fifo_full;
+assign req_fifo_wr = ~req_fifo_full & imem_req;
+
+assign imem_rdata = resp_fifo.hrdata;
+
+assign imem_resp = (resp_fifo_hready)
+ ? (resp_fifo.hresp == 1'b1)
+ ? SCR1_MEM_RESP_RDY_OK
+ : SCR1_MEM_RESP_RDY_ER
+ : SCR1_MEM_RESP_NOTRDY;
+
+//-------------------------------------------------------------------------------
+// REQ_FIFO
+//-------------------------------------------------------------------------------
+`ifdef SCR1_IMEM_WB_OUT_BP
+always_ff @(negedge rst_n, posedge clk) begin
+ if (~rst_n) begin
+ req_fifo_full <= 1'b0;
+ end else begin
+ if (~req_fifo_full) begin
+ req_fifo_full <= imem_req & ~req_fifo_rd;
+ end else begin
+ req_fifo_full <= ~req_fifo_rd;
+ end
+ end
+end
+assign req_fifo_empty = ~(req_fifo_full | imem_req);
+
+assign req_fifo_up = ~req_fifo_rd & req_fifo_wr;
+always_ff @(posedge clk) begin
+ if (req_fifo_up) begin
+ req_fifo_r.haddr <= imem_addr;
+ end
+end
+
+assign req_fifo[0] = (req_fifo_full) ? req_fifo_r : imem_addr;
+
+`else // SCR1_IMEM_WB_OUT_BP
+
+
+ sync_fifo #(
+ .DATA_WIDTH(SCR1_WB_WIDTH), // Data Width
+ .ADDR_WIDTH(1), // Address Width
+ .FIFO_DEPTH(2) // FIFO DEPTH
+ ) u_req_fifo(
+
+ .dout (req_fifo_dout ),
+
+ .rstn (rst_n ),
+ .clk (clk ),
+ .wr_en (req_fifo_wr ), // Write
+ .rd_en (req_fifo_rd ), // Read
+ .din (imem_addr ),
+ .full (req_fifo_full ),
+ .empty (req_fifo_empty )
+);
+
+
+
+
+`endif // SCR1_IMEM_WB_OUT_BP
+
+
+always_comb begin
+ req_fifo_rd = 1'b0;
+ if (wbd_ack_i) begin
+ req_fifo_rd = ~req_fifo_empty;
+ end
+end
+
+//-------------------------------------------------------------------------------
+// FIFO response
+//-------------------------------------------------------------------------------
+`ifdef SCR1_IMEM_WB_IN_BP
+assign resp_fifo_hready = wbd_ack_i;
+assign resp_fifo.hresp = (wbd_err_i) ? 1'b0 : 1'b1;
+assign resp_fifo.hrdata = wbd_dat_i;
+assign wbd_stb_o = ~req_fifo_empty;
+assign wbd_adr_o = req_fifo[0];
+assign wbd_we_o = 0; // Only Read supported
+assign wbd_dat_o = 32'h0; // No Write
+assign wbd_sel_o = 4'b1111; // Only Read allowed in imem i/f
+
+
+`else // SCR1_IMEM_WB_IN_BP
+always_ff @(negedge rst_n, posedge clk) begin
+ if (~rst_n) begin
+ resp_fifo_hready <= 1'b0;
+ end else begin
+ resp_fifo_hready <= wbd_ack_i ;
+ end
+end
+
+always_ff @(posedge clk) begin
+ if (wbd_ack_i) begin
+ resp_fifo.hresp <= (wbd_err_i) ? 1'b0 : 1'b1;
+ resp_fifo.hrdata <= wbd_dat_i;
+ end
+end
+
+assign wbd_stb_o = ~req_fifo_empty;
+assign wbd_adr_o = req_fifo_dout;
+assign wbd_we_o = 0; // Only Read supported
+assign wbd_dat_o = 32'h0; // No Write
+assign wbd_sel_o = 4'b1111; // Only Read allowed in imem i/f
+`endif // SCR1_IMEM_WB_IN_BP
+
+
+
+`ifdef SCR1_TRGT_SIMULATION
+//-------------------------------------------------------------------------------
+// Assertion
+//-------------------------------------------------------------------------------
+
+// Check Core interface
+SCR1_SVA_IMEM_WB_BRIDGE_REQ_XCHECK : assert property (
+ @(negedge clk) disable iff (~rst_n)
+ !$isunknown(imem_req)
+ ) else $error("IMEM WB bridge Error: imem_req has unknown values");
+
+SCR1_IMEM_WB_BRIDGE_ADDR_XCHECK : assert property (
+ @(negedge clk) disable iff (~rst_n)
+ imem_req |-> !$isunknown(imem_addr)
+ ) else $error("IMEM WB bridge Error: imem_addr has unknown values");
+
+SCR1_IMEM_WB_BRIDGE_ADDR_ALLIGN : assert property (
+ @(negedge clk) disable iff (~rst_n)
+ imem_req |-> (imem_addr[1:0] == '0)
+ ) else $error("IMEM WB bridge Error: imem_addr has unalign values");
+
+// Check WB interface
+SCR1_IMEM_WB_BRIDGE_HREADY_XCHECK : assert property (
+ @(negedge clk) disable iff (~rst_n)
+ !$isunknown(hready)
+ ) else $error("IMEM WB bridge Error: hready has unknown values");
+
+SCR1_IMEM_WB_BRIDGE_HRESP_XCHECK : assert property (
+ @(negedge clk) disable iff (~rst_n)
+ !$isunknown(hresp)
+ ) else $error("IMEM WB bridge Error: hresp has unknown values");
+
+`endif // SCR1_TRGT_SIMULATION
+
+endmodule : scr1_imem_wb
diff --git a/verilog/rtl/syntacore_scr1/src/top/scr1_top_wb.sv b/verilog/rtl/syntacore_scr1/src/top/scr1_top_wb.sv
index 0cf1c09..87e6607 100644
--- a/verilog/rtl/syntacore_scr1/src/top/scr1_top_wb.sv
+++ b/verilog/rtl/syntacore_scr1/src/top/scr1_top_wb.sv
@@ -1,28 +1,23 @@
//////////////////////////////////////////////////////////////////////
//// ////
-//// Syntacore SCR1 interface map to westbone ////
+//// yifive Wishbone interface for syntacore ////
//// ////
-//// This file is part of the yifive project ////
+//// This file is part of the yifive cores project ////
//// http://www.opencores.org/cores/yifive/ ////
//// ////
-//// Description ////
-//// This module does the westbone interface to syntacore/scr1 ////
+//// Description: ////
+//// integrated wishbone i/f to instruction/data memory ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Dinesh Annayya, dinesha@opencores.org ////
-//// Initial Author: syntacore
-//// - https://github.com/syntacore/scr1
//// ////
-//////////////////////////////////////////////////////////////////////
-//// Revision : 06-June- 2021 ////
-//// v-0.0 - Dinesh.A, June 06, 2021 ////
-//// 1. Initial Version picked from ////
-//// https://github.com/syntacore/scr1 ////
-//// 2. Added westone i/f towards instruction ////
-//// and data memory ////
+//// Revision : ////
+//// v0: June 7, 2021, Dinesh A ////
+//// wishbone integration ////
+//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
@@ -49,11 +44,16 @@
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
-
+// Orginal owner Details ////
+//////////////////////////////////////////////////////////////////////
+/// Copyright by Syntacore LLC © 2016-2020. See LICENSE for details///
+/// @file <scr1_top_wb.sv> ///
+/// @brief SCR1 AHB top ///
+//////////////////////////////////////////////////////////////////////
`include "scr1_arch_description.svh"
`include "scr1_memif.svh"
-`include "scr1_ahb.svh"
+`include "scr1_wb.svh"
`ifdef SCR1_IPIC_EN
`include "scr1_ipic.svh"
`endif // SCR1_IPIC_EN
@@ -104,28 +104,24 @@
`endif // SCR1_DBG_EN
// Instruction Memory Interface
- output logic [3:0] imem_hprot,
- output logic [2:0] imem_hburst,
- output logic [2:0] imem_hsize,
- output logic [1:0] imem_htrans,
- output logic imem_hmastlock,
- output logic [SCR1_AHB_WIDTH-1:0] imem_haddr,
- input logic imem_hready,
- input logic [SCR1_AHB_WIDTH-1:0] imem_hrdata,
- input logic imem_hresp,
+ output logic wbd_imem_stb_o, // strobe/request
+ output logic [SCR1_WB_WIDTH-1:0] wbd_imem_adr_o, // address
+ output logic wbd_imem_we_o, // write
+ output logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_o, // data output
+ output logic [3:0] wbd_imem_sel_o, // byte enable
+ input logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_i, // data input
+ input logic wbd_imem_ack_i, // acknowlegement
+ input logic wbd_imem_err_i, // error
// Data Memory Interface
- output logic [3:0] dmem_hprot,
- output logic [2:0] dmem_hburst,
- output logic [2:0] dmem_hsize,
- output logic [1:0] dmem_htrans,
- output logic dmem_hmastlock,
- output logic [SCR1_AHB_WIDTH-1:0] dmem_haddr,
- output logic dmem_hwrite,
- output logic [SCR1_AHB_WIDTH-1:0] dmem_hwdata,
- input logic dmem_hready,
- input logic [SCR1_AHB_WIDTH-1:0] dmem_hrdata,
- input logic dmem_hresp
+ output logic wbd_dmem_stb_o, // strobe/request
+ output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_adr_o, // address
+ output logic wbd_dmem_we_o, // write
+ output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_o, // data output
+ output logic [3:0] wbd_dmem_sel_o, // byte enable
+ input logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_i, // data input
+ input logic wbd_dmem_ack_i, // acknowlegement
+ input logic wbd_dmem_err_i // error
);
//-------------------------------------------------------------------------------
@@ -163,23 +159,23 @@
logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata;
type_scr1_mem_resp_e core_dmem_resp;
-// Instruction memory interface from router to AHB bridge
-logic ahb_imem_req_ack;
-logic ahb_imem_req;
-type_scr1_mem_cmd_e ahb_imem_cmd;
-logic [`SCR1_IMEM_AWIDTH-1:0] ahb_imem_addr;
-logic [`SCR1_IMEM_DWIDTH-1:0] ahb_imem_rdata;
-type_scr1_mem_resp_e ahb_imem_resp;
+// Instruction memory interface from router to WB bridge
+logic wb_imem_req_ack;
+logic wb_imem_req;
+type_scr1_mem_cmd_e wb_imem_cmd;
+logic [`SCR1_IMEM_AWIDTH-1:0] wb_imem_addr;
+logic [`SCR1_IMEM_DWIDTH-1:0] wb_imem_rdata;
+type_scr1_mem_resp_e wb_imem_resp;
-// Data memory interface from router to AHB bridge
-logic ahb_dmem_req_ack;
-logic ahb_dmem_req;
-type_scr1_mem_cmd_e ahb_dmem_cmd;
-type_scr1_mem_width_e ahb_dmem_width;
-logic [`SCR1_DMEM_AWIDTH-1:0] ahb_dmem_addr;
-logic [`SCR1_DMEM_DWIDTH-1:0] ahb_dmem_wdata;
-logic [`SCR1_DMEM_DWIDTH-1:0] ahb_dmem_rdata;
-type_scr1_mem_resp_e ahb_dmem_resp;
+// Data memory interface from router to WB bridge
+logic wb_dmem_req_ack;
+logic wb_dmem_req;
+type_scr1_mem_cmd_e wb_dmem_cmd;
+type_scr1_mem_width_e wb_dmem_width;
+logic [`SCR1_DMEM_AWIDTH-1:0] wb_dmem_addr;
+logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_wdata;
+logic [`SCR1_DMEM_DWIDTH-1:0] wb_dmem_rdata;
+type_scr1_mem_resp_e wb_dmem_resp;
`ifdef SCR1_TCM_EN
// Instruction memory interface from router to TCM
@@ -404,13 +400,13 @@
.imem_addr (core_imem_addr ),
.imem_rdata (core_imem_rdata ),
.imem_resp (core_imem_resp ),
- // Interface to AHB bridge
- .port0_req_ack (ahb_imem_req_ack ),
- .port0_req (ahb_imem_req ),
- .port0_cmd (ahb_imem_cmd ),
- .port0_addr (ahb_imem_addr ),
- .port0_rdata (ahb_imem_rdata ),
- .port0_resp (ahb_imem_resp ),
+ // Interface to WB bridge
+ .port0_req_ack (wb_imem_req_ack ),
+ .port0_req (wb_imem_req ),
+ .port0_cmd (wb_imem_cmd ),
+ .port0_addr (wb_imem_addr ),
+ .port0_rdata (wb_imem_rdata ),
+ .port0_resp (wb_imem_resp ),
`ifdef SCR1_TCM_EN
// Interface to TCM
.port1_req_ack (tcm_imem_req_ack ),
@@ -424,12 +420,12 @@
`else // SCR1_IMEM_ROUTER_EN
-assign ahb_imem_req = core_imem_req;
-assign ahb_imem_cmd = core_imem_cmd;
-assign ahb_imem_addr = core_imem_addr;
-assign core_imem_req_ack = ahb_imem_req_ack;
-assign core_imem_resp = ahb_imem_resp;
-assign core_imem_rdata = ahb_imem_rdata;
+assign wb_imem_req = core_imem_req;
+assign wb_imem_cmd = core_imem_cmd;
+assign wb_imem_addr = core_imem_addr;
+assign core_imem_req_ack = wb_imem_req_ack;
+assign core_imem_resp = wb_imem_resp;
+assign core_imem_rdata = wb_imem_rdata;
`endif // SCR1_IMEM_ROUTER_EN
@@ -490,72 +486,68 @@
.port2_wdata (timer_dmem_wdata ),
.port2_rdata (timer_dmem_rdata ),
.port2_resp (timer_dmem_resp ),
- // Interface to AHB bridge
- .port0_req_ack (ahb_dmem_req_ack ),
- .port0_req (ahb_dmem_req ),
- .port0_cmd (ahb_dmem_cmd ),
- .port0_width (ahb_dmem_width ),
- .port0_addr (ahb_dmem_addr ),
- .port0_wdata (ahb_dmem_wdata ),
- .port0_rdata (ahb_dmem_rdata ),
- .port0_resp (ahb_dmem_resp )
+ // Interface to WB bridge
+ .port0_req_ack (wb_dmem_req_ack ),
+ .port0_req (wb_dmem_req ),
+ .port0_cmd (wb_dmem_cmd ),
+ .port0_width (wb_dmem_width ),
+ .port0_addr (wb_dmem_addr ),
+ .port0_wdata (wb_dmem_wdata ),
+ .port0_rdata (wb_dmem_rdata ),
+ .port0_resp (wb_dmem_resp )
);
//-------------------------------------------------------------------------------
-// Instruction memory AHB bridge
+// Instruction memory WB bridge
//-------------------------------------------------------------------------------
-scr1_imem_ahb i_imem_ahb (
+scr1_imem_wb i_imem_wb (
.rst_n (core_rst_n_local ),
.clk (clk ),
// Interface to imem router
- .imem_req_ack (ahb_imem_req_ack ),
- .imem_req (ahb_imem_req ),
- .imem_addr (ahb_imem_addr ),
- .imem_rdata (ahb_imem_rdata ),
- .imem_resp (ahb_imem_resp ),
- // AHB interface
- .hprot (imem_hprot ),
- .hburst (imem_hburst ),
- .hsize (imem_hsize ),
- .htrans (imem_htrans ),
- .hmastlock (imem_hmastlock ),
- .haddr (imem_haddr ),
- .hready (imem_hready ),
- .hrdata (imem_hrdata ),
- .hresp (imem_hresp )
+ .imem_req_ack (wb_imem_req_ack ),
+ .imem_req (wb_imem_req ),
+ .imem_addr (wb_imem_addr ),
+ .imem_rdata (wb_imem_rdata ),
+ .imem_resp (wb_imem_resp ),
+ // WB interface
+ .wbd_stb_o (wbd_imem_stb_o ),
+ .wbd_adr_o (wbd_imem_adr_o ),
+ .wbd_we_o (wbd_imem_we_o ),
+ .wbd_dat_o (wbd_imem_dat_o ),
+ .wbd_sel_o (wbd_imem_sel_o ),
+ .wbd_dat_i (wbd_imem_dat_i ),
+ .wbd_ack_i (wbd_imem_ack_i ),
+ .wbd_err_i (wbd_imem_err_i )
);
//-------------------------------------------------------------------------------
-// Data memory AHB bridge
+// Data memory WB bridge
//-------------------------------------------------------------------------------
-scr1_dmem_ahb i_dmem_ahb (
+scr1_dmem_wb i_dmem_wb (
.rst_n (core_rst_n_local ),
.clk (clk ),
// Interface to dmem router
- .dmem_req_ack (ahb_dmem_req_ack ),
- .dmem_req (ahb_dmem_req ),
- .dmem_cmd (ahb_dmem_cmd ),
- .dmem_width (ahb_dmem_width ),
- .dmem_addr (ahb_dmem_addr ),
- .dmem_wdata (ahb_dmem_wdata ),
- .dmem_rdata (ahb_dmem_rdata ),
- .dmem_resp (ahb_dmem_resp ),
- // AHB interface
- .hprot (dmem_hprot ),
- .hburst (dmem_hburst ),
- .hsize (dmem_hsize ),
- .htrans (dmem_htrans ),
- .hmastlock (dmem_hmastlock ),
- .haddr (dmem_haddr ),
- .hwrite (dmem_hwrite ),
- .hwdata (dmem_hwdata ),
- .hready (dmem_hready ),
- .hrdata (dmem_hrdata ),
- .hresp (dmem_hresp )
+ .dmem_req_ack (wb_dmem_req_ack ),
+ .dmem_req (wb_dmem_req ),
+ .dmem_cmd (wb_dmem_cmd ),
+ .dmem_width (wb_dmem_width ),
+ .dmem_addr (wb_dmem_addr ),
+ .dmem_wdata (wb_dmem_wdata ),
+ .dmem_rdata (wb_dmem_rdata ),
+ .dmem_resp (wb_dmem_resp ),
+ // WB interface
+ .wbd_stb_o (wbd_dmem_stb_o ),
+ .wbd_adr_o (wbd_dmem_adr_o ),
+ .wbd_we_o (wbd_dmem_we_o ),
+ .wbd_dat_o (wbd_dmem_dat_o ),
+ .wbd_sel_o (wbd_dmem_sel_o ),
+ .wbd_dat_i (wbd_dmem_dat_i ),
+ .wbd_ack_i (wbd_dmem_ack_i ),
+ .wbd_err_i (wbd_dmem_err_i )
);
-endmodule : scr1_top_ahb
+endmodule : scr1_top_wb
diff --git a/verilog/rtl/syntacore_scr1/src/wb_top.files b/verilog/rtl/syntacore_scr1/src/wb_top.files
new file mode 100644
index 0000000..87dd341
--- /dev/null
+++ b/verilog/rtl/syntacore_scr1/src/wb_top.files
@@ -0,0 +1,9 @@
+top/scr1_dmem_router.sv
+top/scr1_imem_router.sv
+top/scr1_dp_memory.sv
+top/scr1_tcm.sv
+top/scr1_timer.sv
+top/scr1_dmem_wb.sv
+top/scr1_imem_wb.sv
+top/scr1_top_wb.sv
+../../lib/sync_fifo.sv
