precheck cleanup for power verilog
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl index fde4083..61f45ea 100644 --- a/openlane/user_project_wrapper/interactive.tcl +++ b/openlane/user_project_wrapper/interactive.tcl
@@ -62,6 +62,21 @@ } +proc run_power_pins_insertion_step {args} { + # set_def $::env(tritonRoute_result_file_tag).def + if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } { + set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF) + } + if { $::env(LVS_INSERT_POWER_PINS) } { + write_powered_verilog + set_netlist $::env(lvs_result_file_tag).powered.v + } + +} + + proc run_lvs_step {{ lvs_enabled 1 }} { if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } { set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF) @@ -123,8 +138,9 @@ "floorplan" {run_floorplan ""} \ "placement" {run_placement_step ""} \ "cts" {run_cts_step ""} \ - "routing" {run_routing_step ""}\ + "routing" {run_routing_step ""} \ "diode_insertion" {run_diode_insertion_2_5_step ""} \ + "power_pins_insertion" {run_power_pins_insertion_step ""} \ "gds_magic" {run_magic ""} \ "gds_drc_klayout" {run_klayout ""} \ "gds_xor_klayout" {run_klayout_gds_xor ""} \
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index a82158b..cdbf6b0 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h49m1s,-1,2.724159402241594,10.2784,1.362079701120797,-1,538.05,14,0,0,0,0,0,0,-1,0,0,-1,-1,1480871,10235,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,64380.84,4.37,5.34,0.99,0.77,-1,313,2874,313,2874,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,100,90,0.55,0.0,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h49m16s,-1,2.724159402241594,10.2784,1.362079701120797,-1,536.59,14,0,0,0,0,0,0,-1,0,0,-1,-1,1480871,10235,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,64380.84,4.37,5.34,0.99,0.77,-1,313,2874,313,2874,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,100,90,0.55,0.0,sky130_fd_sc_hd,4,0