replaced sram with dffram
diff --git a/.gitmodules b/.gitmodules index 7c54d50..e422cb9 100644 --- a/.gitmodules +++ b/.gitmodules
@@ -1,6 +1,6 @@ -[submodule "verilog/rtl/yifive/ycr1c"] - path = verilog/rtl/yifive/ycr1c - url = https://github.com/dineshannayya/ycr1c.git [submodule "verilog/rtl/qspim"] path = verilog/rtl/qspim url = https://github.com/dineshannayya/qspim.git +[submodule "verilog/rtl/yifive/ycr1cr"] + path = verilog/rtl/yifive/ycr1c + url = https://github.com/dineshannayya/ycr1cr.git
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg index ffdf50f..512813f 100644 --- a/openlane/pinmux/pin_order.cfg +++ b/openlane/pinmux/pin_order.cfg
@@ -63,40 +63,6 @@ pinmux_debug\[31\] #W -bist_error_cnt3\[3\] 000 0 2 -bist_error_cnt3\[2\] -bist_error_cnt3\[1\] -bist_error_cnt3\[0\] -bist_correct\[3\] -bist_error\[3\] - -bist_error_cnt2\[3\] -bist_error_cnt2\[2\] -bist_error_cnt2\[1\] -bist_error_cnt2\[0\] -bist_correct\[2\] -bist_error\[2\] - -bist_error_cnt1\[3\] -bist_error_cnt1\[2\] -bist_error_cnt1\[1\] -bist_error_cnt1\[0\] -bist_correct\[1\] -bist_error\[1\] - -bist_error_cnt0\[3\] -bist_error_cnt0\[2\] -bist_error_cnt0\[1\] -bist_error_cnt0\[0\] -bist_correct\[0\] -bist_error\[0\] -bist_done -bist_sdo -bist_shift -bist_sdi -bist_load -bist_run -bist_en soft_irq irq_lines\[15\]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 2895ec4..1a720a6 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -69,11 +69,10 @@ $proj_dir/../../verilog/gl/qspim.v \ $proj_dir/../../verilog/gl/wb_interconnect.v \ $proj_dir/../../verilog/gl/pinmux.v \ - $proj_dir/../../verilog/gl/mbist_wrapper.v \ $proj_dir/../../verilog/gl/uart_i2cm_usb_spi.v \ $proj_dir/../../verilog/gl/wb_host.v \ $proj_dir/../../verilog/gl/yifive.v \ - $proj_dir/../../verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v \ + $proj_dir/../../verilog/gl/DFFRAM.v \ " set ::env(EXTRA_LEFS) "\ @@ -82,9 +81,8 @@ $lef_root/wb_interconnect.lef \ $lef_root/uart_i2cm_usb_spi.lef \ $lef_root/wb_host.lef \ - $lef_root/mbist_wrapper.lef \ $lef_root/yifive.lef \ - $lef_root/sky130_sram_2kbyte_1rw1r_32x512_8.lef \ + $lef_root/DFFRAM.lef \ " set ::env(EXTRA_GDS_FILES) "\ @@ -93,9 +91,8 @@ $gds_root/wb_interconnect.gds \ $gds_root/uart_i2cm_usb_spi.gds \ $gds_root/wb_host.gds \ - $gds_root/mbist_wrapper.gds \ $gds_root/yifive.gds \ - $gds_root/sky130_sram_2kbyte_1rw1r_32x512_8.gds \ + $gds_root/DFFRAM.gds \ " set ::env(SYNTH_DEFINES) [list SYNTHESIS ] @@ -118,53 +115,32 @@ set ::env(VDD_PIN) "vccd1" set ::env(GND_PIN) "vssd1" -set ::env(GLB_RT_OBS) " li1 150 2100 833.1 2516.54,\ - met1 150 2100 833.1 2516.54,\ - met2 150 2100 833.1 2516.54,\ - met3 150 2100 833.1 2516.54,\ - li1 950 2100 1633.1 2516.54,\ - met1 950 2100 1633.1 2516.54,\ - met2 950 2100 1633.1 2516.54,\ - met3 950 2100 1633.1 2516.54,\ - li1 150 3000 833.1 3416.54,\ - met1 150 3000 833.1 3416.54,\ - met2 150 3000 833.1 3416.54,\ - met3 150 3000 833.1 3416.54,\ - li1 950 3000 1633.1 3416.54,\ - met1 950 3000 1633.1 3416.54,\ - met2 950 3000 1633.1 3416.54,\ - met3 950 3000 1633.1 3416.54,\ - li1 150 1400 833.1 1816.54,\ - met1 150 1400 833.1 1816.54,\ - met2 150 1400 833.1 1816.54,\ - met3 150 1400 833.1 1816.54,\ - li1 150 800 833.1 1216.54,\ - met1 150 800 833.1 1216.54,\ - met2 150 800 833.1 1216.54,\ - met3 150 800 833.1 1216.54,\ - li1 150 200 833.1 616.54,\ - met1 150 200 833.1 616.54,\ - met2 150 200 833.1 616.54,\ - met3 150 200 833.1 616.54,\ - met5 0 0 2920 3520" - +set ::env(GLB_RT_OBS) " met5 0 0 2920 3520, \ + met4 125 950 675 1640, \ + met4 125 1800 675 2540, \ + met4 125 100 675 840, \ + met4 850 100 1400 840, \ + met4 325 2650 875 3400, \ + met4 1050 2650 1600 3400 \ + " + set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0" -set ::env(FP_PDN_MACRO_HOOKS) " \ - u_intercon vccd1 vssd1 \ - u_pinmux vccd1 vssd1 \ - u_qspi_master vccd1 vssd1 \ - u_riscv_top vccd1 vssd1 \ - u_tsram0_2kb vccd1 vssd1 \ - u_icache_2kb vccd1 vssd1 \ - u_dcache_2kb vccd1 vssd1 \ - u_mbist vccd1 vssd1 \ - u_sram0_2kb vccd1 vssd1 \ - u_sram1_2kb vccd1 vssd1 \ - u_sram2_2kb vccd1 vssd1 \ - u_sram3_2kb vccd1 vssd1 \ - u_uart_i2c_usb_spi vccd1 vssd1 \ - u_wb_host vccd1 vssd1 " +#set ::env(FP_PDN_MACRO_HOOKS) " \ +# u_intercon vccd1 vssd1 \ +# u_pinmux vccd1 vssd1 \ +# u_qspi_master vccd1 vssd1 \ +# u_riscv_top vccd1 vssd1 \ +# u_tsram0_2kb vccd1 vssd1 \ +# u_icache_2kb vccd1 vssd1 \ +# u_dcache_2kb vccd1 vssd1 \ +# u_mbist vccd1 vssd1 \ +# u_sram0_2kb vccd1 vssd1 \ +# u_sram1_2kb vccd1 vssd1 \ +# u_sram2_2kb vccd1 vssd1 \ +# u_sram3_2kb vccd1 vssd1 \ +# u_uart_i2c_usb_spi vccd1 vssd1 \ +# u_wb_host vccd1 vssd1 " # The following is because there are no std cells in the example wrapper project. @@ -184,13 +160,13 @@ set ::env(CLOCK_TREE_SYNTH) 0 set ::env(QUIT_ON_LVS_ERROR) "0" -set ::env(QUIT_ON_MAGIC_DRC) "0" +set ::env(QUIT_ON_MAGIC_DRC) "1" set ::env(QUIT_ON_NEGATIVE_WNS) "0" set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" set ::env(QUIT_ON_TR_DRC) "0" -set ::env(FP_PDN_IRDROP) "1" +set ::env(FP_PDN_IRDROP) "0" set ::env(FP_PDN_HORIZONTAL_HALO) "10" set ::env(FP_PDN_VERTICAL_HALO) "10" @@ -199,10 +175,8 @@ set ::env(FP_PDN_VSPACING) "15.5" set ::env(FP_PDN_VWIDTH) "3.1" -set ::env(FP_PDN_HOFFSET) "10" -set ::env(FP_PDN_HPITCH) "120" -set ::env(FP_PDN_HSPACING) "10" -set ::env(FP_PDN_HWIDTH) "3.1" +set ::env(FP_PDN_HOFFSET) "16.65" +set ::env(FP_PDN_HPITCH) "130"
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl index 45668cd..2842c9f 100644 --- a/openlane/user_project_wrapper/interactive.tcl +++ b/openlane/user_project_wrapper/interactive.tcl
@@ -223,7 +223,7 @@ set ground [lindex $hooks 1] if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } { set ::env(FP_PDN_ENABLE_MACROS_GRID) 1 - set ::env(FP_PDN_IRDROP) "1" + set ::env(FP_PDN_IRDROP) "0" puts_info "Connecting $instance_name to $power and $ground nets." lappend ::env(FP_PDN_MACROS) $instance_name } @@ -344,7 +344,7 @@ } set LVS_ENABLED 1 - set DRC_ENABLED 0 + set DRC_ENABLED 1 set ANTENNACHECK_ENABLED 1 set steps [dict create \
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index 729781f..6f35c2f 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,18 +1,15 @@ u_qspi_master 2225 700 N u_uart_i2c_usb_spi 2225 1400 N u_pinmux 2225 2300 N -u_sram2_2kb 150 3000 N -u_sram3_2kb 950 3000 N -u_mbist 150 2650 N -u_sram0_2kb 150 2100 N -u_sram1_2kb 950 2100 N +u_tcm_1KB_mem0 125 945 N +u_tcm_1KB_mem1 125 1790 N +u_riscv_top 850 945 N +u_icache_1KB_mem0 125 100 N +u_icache_1KB_mem1 850 100 N -u_riscv_top 950 450 N -u_dcache_2kb 150 1400 N -u_icache_2kb 150 800 N -u_tsram0_2kb 150 200 N - +u_dcache_1KB_mem0 325 2635 N +u_dcache_1KB_mem1 1050 2635 N u_intercon 1850 700 N -u_wb_host 1450 100 N +u_wb_host 1650 200 N
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl index fcd1da4..ff38b49 100755 --- a/openlane/wb_host/config.tcl +++ b/openlane/wb_host/config.tcl
@@ -75,7 +75,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 800 200" +set ::env(DIE_AREA) "0 0 350 400" # If you're going to use multiple power domains, then keep this disabled. @@ -85,7 +85,7 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.35" +set ::env(PL_TARGET_DENSITY) "0.38"
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg index a29f24b..540187b 100644 --- a/openlane/wb_host/pin_order.cfg +++ b/openlane/wb_host/pin_order.cfg
@@ -146,7 +146,7 @@ wbm_dat_o\[31\] wbm_err_o -la_data_in\[0\] 300 0 2 +la_data_in\[0\] 250 0 2 la_data_in\[1\] la_data_in\[2\] la_data_in\[3\] @@ -172,7 +172,7 @@ #N -wbd_int_rst_n 0400 0 2 +wbd_int_rst_n 0100 0 2 cfg_clk_ctrl2\[31\] cfg_clk_ctrl2\[30\] cfg_clk_ctrl2\[29\] @@ -232,7 +232,7 @@ -wbs_stb_o 460 0 2 +wbs_stb_o 160 0 2 wbs_we_o wbs_adr_o\[31\] wbs_adr_o\[30\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index 85fe0e5..bc25fd0 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -23,7 +23,6 @@ set ::env(DESIGN_IS_CORE) "0" -set ::env(FP_PDN_CORE_RING) "0" # Timing configuration set ::env(CLOCK_PERIOD) "10" @@ -50,8 +49,8 @@ set ::env(SYNTH_DEFINES) [list SYNTHESIS ] -set ::env(SYNTH_PARAMS) "CH_CLK_WD 8,\ - CH_DATA_WD 116 \ +set ::env(SYNTH_PARAMS) "CH_CLK_WD 4,\ + CH_DATA_WD 69 \ " set ::env(SYNTH_READ_BLACKBOX_LIB) 1 @@ -78,6 +77,14 @@ #set ::env(PDN_CFG) $script_dir/pdn.tcl +## PDN +set ::env(FP_PDN_CORE_RING) 0 +set ::env(FP_PDN_VPITCH) 120 +set ::env(FP_PDN_HPITCH) 120 + +set ::env(FP_PDN_VWIDTH) 1.6 +set ::env(FP_PDN_CORE_RING_VWIDTH) 1.6 + set ::env(PL_TIME_DRIVEN) 1 set ::env(PL_TARGET_DENSITY) "0.30"
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index 9f2007f..ae3e4b5 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -4,30 +4,6 @@ #S rst_n 000 0 2 -dcache_remap\[3\] -dcache_remap\[2\] -dcache_remap\[1\] -dcache_remap\[0\] -boot_remap\[3\] -boot_remap\[2\] -boot_remap\[1\] -boot_remap\[0\] -ch_data_in\[35\] -ch_data_in\[34\] -ch_data_in\[33\] -ch_data_in\[32\] -ch_data_in\[31\] -ch_data_in\[30\] -ch_data_in\[29\] -ch_data_in\[28\] -ch_data_in\[27\] -ch_data_in\[26\] -ch_data_in\[25\] -ch_data_in\[24\] -ch_data_in\[23\] -ch_data_in\[22\] -ch_data_in\[21\] -ch_data_in\[20\] ch_data_in\[19\] ch_data_in\[18\] ch_data_in\[17\] @@ -52,10 +28,6 @@ cfg_cska_wi\[2\] cfg_cska_wi\[1\] cfg_cska_wi\[0\] -ch_clk_in\[7\] -ch_clk_in\[6\] -ch_clk_in\[5\] -ch_clk_in\[4\] ch_clk_in\[3\] ch_clk_in\[2\] ch_clk_in\[1\] @@ -175,55 +147,55 @@ #W -ch_data_out\[84\] 0250 0 2 -ch_data_out\[83\] -ch_data_out\[82\] -ch_data_out\[81\] -ch_data_out\[80\] -ch_data_out\[79\] -ch_data_out\[78\] -ch_data_out\[77\] -ch_data_out\[76\] -ch_data_out\[75\] -ch_data_out\[74\] -ch_data_out\[73\] -ch_data_out\[72\] -ch_data_out\[71\] -ch_data_out\[70\] -ch_data_out\[69\] -ch_data_out\[68\] -ch_data_out\[67\] -ch_data_out\[66\] -ch_data_out\[65\] -ch_data_out\[64\] -ch_data_out\[63\] -ch_data_out\[62\] -ch_data_out\[61\] -ch_data_out\[60\] -ch_data_out\[59\] -ch_data_out\[58\] -ch_data_out\[57\] -ch_data_out\[56\] -ch_data_out\[55\] -ch_data_out\[54\] -ch_data_out\[53\] -ch_data_out\[52\] -ch_data_out\[51\] -ch_data_out\[50\] -ch_data_out\[49\] -ch_data_out\[48\] -ch_data_out\[47\] -ch_data_out\[46\] -ch_data_out\[45\] -ch_data_out\[44\] -ch_data_out\[43\] -ch_data_out\[42\] -ch_data_out\[41\] -ch_data_out\[40\] -ch_data_out\[39\] -ch_data_out\[38\] -ch_data_out\[37\] -ch_data_out\[36\] +ch_data_out\[68\] 0750 0 2 +ch_data_out\[67\] +ch_data_out\[66\] +ch_data_out\[65\] +ch_data_out\[64\] +ch_data_out\[63\] +ch_data_out\[62\] +ch_data_out\[61\] +ch_data_out\[60\] +ch_data_out\[59\] +ch_data_out\[58\] +ch_data_out\[57\] +ch_data_out\[56\] +ch_data_out\[55\] +ch_data_out\[54\] +ch_data_out\[53\] +ch_data_out\[52\] +ch_data_out\[51\] +ch_data_out\[50\] +ch_data_out\[49\] +ch_data_out\[48\] +ch_data_out\[47\] +ch_data_out\[46\] +ch_data_out\[45\] +ch_data_out\[44\] +ch_data_out\[43\] +ch_data_out\[42\] +ch_data_out\[41\] +ch_data_out\[40\] +ch_data_out\[39\] +ch_data_out\[38\] +ch_data_out\[37\] +ch_data_out\[36\] +ch_data_out\[35\] +ch_data_out\[34\] +ch_data_out\[33\] +ch_data_out\[32\] +ch_data_out\[31\] +ch_data_out\[30\] +ch_data_out\[29\] +ch_data_out\[28\] +ch_data_out\[27\] +ch_data_out\[26\] +ch_data_out\[25\] +ch_data_out\[24\] +ch_data_out\[23\] +ch_data_out\[22\] +ch_data_out\[21\] +ch_data_out\[20\] ch_data_out\[3\] ch_data_out\[2\] @@ -232,7 +204,7 @@ ch_clk_out\[0\] -m1_wbd_stb_i 0450 0 2 +m1_wbd_stb_i 0950 0 2 m1_wbd_we_i m1_wbd_adr_i\[31\] m1_wbd_adr_i\[30\] @@ -339,7 +311,7 @@ m1_wbd_err_o m1_wbd_cyc_i -m2_wbd_stb_i 0650 0 2 +m2_wbd_stb_i 1150 0 2 m2_wbd_we_i m2_wbd_adr_i\[31\] m2_wbd_adr_i\[30\] @@ -457,7 +429,7 @@ m2_wbd_err_o m2_wbd_cyc_i -m3_wbd_stb_i 0850 0 2 +m3_wbd_stb_i 1350 0 2 m3_wbd_we_i m3_wbd_adr_i\[31\] m3_wbd_adr_i\[30\] @@ -543,159 +515,6 @@ m3_wbd_err_o m3_wbd_cyc_i -ch_data_out\[23\] 1950 0 2 -ch_data_out\[22\] -ch_data_out\[21\] -ch_data_out\[20\] -ch_clk_out\[4\] - -s3_wbd_cyc_o 1975 0 2 -s3_wbd_stb_o -s3_wbd_we_o -s3_wbd_adr_o\[12\] -s3_wbd_adr_o\[11\] -s3_wbd_adr_o\[10\] -s3_wbd_adr_o\[9\] -s3_wbd_adr_o\[8\] -s3_wbd_adr_o\[7\] -s3_wbd_adr_o\[6\] -s3_wbd_adr_o\[5\] -s3_wbd_adr_o\[4\] -s3_wbd_adr_o\[3\] -s3_wbd_adr_o\[2\] -s3_wbd_adr_o\[1\] -s3_wbd_adr_o\[0\] -s3_wbd_dat_o\[31\] -s3_wbd_dat_o\[30\] -s3_wbd_dat_o\[29\] -s3_wbd_dat_o\[28\] -s3_wbd_dat_o\[27\] -s3_wbd_dat_o\[26\] -s3_wbd_dat_o\[25\] -s3_wbd_dat_o\[24\] -s3_wbd_dat_o\[23\] -s3_wbd_dat_o\[22\] -s3_wbd_dat_o\[21\] -s3_wbd_dat_o\[20\] -s3_wbd_dat_o\[19\] -s3_wbd_dat_o\[18\] -s3_wbd_dat_o\[17\] -s3_wbd_dat_o\[16\] -s3_wbd_dat_o\[15\] -s3_wbd_dat_o\[14\] -s3_wbd_dat_o\[13\] -s3_wbd_dat_o\[12\] -s3_wbd_dat_o\[11\] -s3_wbd_dat_o\[10\] -s3_wbd_dat_o\[9\] -s3_wbd_dat_o\[8\] -s3_wbd_dat_o\[7\] -s3_wbd_dat_o\[6\] -s3_wbd_dat_o\[5\] -s3_wbd_dat_o\[4\] -s3_wbd_dat_o\[3\] -s3_wbd_dat_o\[2\] -s3_wbd_dat_o\[1\] -s3_wbd_dat_o\[0\] -s3_wbd_sel_o\[3\] -s3_wbd_sel_o\[2\] -s3_wbd_sel_o\[1\] -s3_wbd_sel_o\[0\] -s3_wbd_bl_o\[9\] -s3_wbd_bl_o\[8\] -s3_wbd_bl_o\[7\] -s3_wbd_bl_o\[6\] -s3_wbd_bl_o\[5\] -s3_wbd_bl_o\[4\] -s3_wbd_bl_o\[3\] -s3_wbd_bl_o\[2\] -s3_wbd_bl_o\[1\] -s3_wbd_bl_o\[0\] -s3_wbd_bry_o -s3_wbd_dat_i\[31\] -s3_wbd_dat_i\[30\] -s3_wbd_dat_i\[29\] -s3_wbd_dat_i\[28\] -s3_wbd_dat_i\[27\] -s3_wbd_dat_i\[26\] -s3_wbd_dat_i\[25\] -s3_wbd_dat_i\[24\] -s3_wbd_dat_i\[23\] -s3_wbd_dat_i\[22\] -s3_wbd_dat_i\[21\] -s3_wbd_dat_i\[20\] -s3_wbd_dat_i\[19\] -s3_wbd_dat_i\[18\] -s3_wbd_dat_i\[17\] -s3_wbd_dat_i\[16\] -s3_wbd_dat_i\[15\] -s3_wbd_dat_i\[14\] -s3_wbd_dat_i\[13\] -s3_wbd_dat_i\[12\] -s3_wbd_dat_i\[11\] -s3_wbd_dat_i\[10\] -s3_wbd_dat_i\[9\] -s3_wbd_dat_i\[8\] -s3_wbd_dat_i\[7\] -s3_wbd_dat_i\[6\] -s3_wbd_dat_i\[5\] -s3_wbd_dat_i\[4\] -s3_wbd_dat_i\[3\] -s3_wbd_dat_i\[2\] -s3_wbd_dat_i\[1\] -s3_wbd_dat_i\[0\] -s3_wbd_ack_i -s3_wbd_lack_i - -ch_data_in\[115\] 2110 0 2 -ch_data_in\[114\] -ch_data_in\[113\] -ch_data_in\[112\] -ch_data_in\[111\] -ch_data_in\[110\] -ch_data_in\[109\] -ch_data_in\[108\] -ch_data_in\[107\] -ch_data_in\[106\] -ch_data_in\[105\] -ch_data_in\[104\] -ch_data_in\[103\] -ch_data_in\[102\] -ch_data_in\[101\] -ch_data_in\[100\] -ch_data_in\[99\] -ch_data_in\[98\] -ch_data_in\[97\] -ch_data_in\[96\] -ch_data_in\[95\] -ch_data_in\[94\] -ch_data_in\[93\] -ch_data_in\[92\] -ch_data_in\[91\] -ch_data_in\[90\] -ch_data_out\[89\] -ch_data_out\[88\] -ch_data_out\[87\] -ch_data_out\[86\] -ch_data_out\[85\] - - - -ch_clk_out\[5\] 2200 0 2 -ch_clk_out\[6\] -ch_clk_out\[7\] -ch_data_out\[24\] -ch_data_out\[25\] -ch_data_out\[26\] -ch_data_out\[27\] -ch_data_out\[28\] -ch_data_out\[29\] -ch_data_out\[30\] -ch_data_out\[31\] -ch_data_out\[32\] -ch_data_out\[33\] -ch_data_out\[34\] -ch_data_out\[35\] #E ch_data_out\[19\] 0000 0 2 @@ -913,55 +732,7 @@ s1_wbd_ack_i s1_wbd_cyc_o -ch_data_out\[115\] 1600 0 2 -ch_data_out\[114\] -ch_data_out\[113\] -ch_data_out\[112\] -ch_data_out\[111\] -ch_data_out\[110\] -ch_data_out\[109\] -ch_data_out\[108\] -ch_data_out\[107\] -ch_data_out\[106\] -ch_data_out\[105\] -ch_data_out\[104\] -ch_data_out\[103\] -ch_data_out\[102\] -ch_data_out\[101\] -ch_data_out\[100\] -ch_data_out\[99\] -ch_data_out\[98\] -ch_data_out\[97\] -ch_data_out\[96\] -ch_data_out\[95\] -ch_data_out\[94\] -ch_data_out\[93\] -ch_data_out\[92\] -ch_data_out\[91\] -ch_data_out\[90\] -ch_data_in\[89\] -ch_data_in\[88\] -ch_data_in\[87\] -ch_data_in\[86\] -ch_data_in\[85\] - -ch_data_in\[84\] -ch_data_in\[83\] -ch_data_in\[82\] -ch_data_in\[81\] -ch_data_in\[80\] -ch_data_in\[79\] -ch_data_in\[78\] -ch_data_in\[77\] -ch_data_in\[76\] -ch_data_in\[75\] -ch_data_in\[74\] -ch_data_in\[73\] -ch_data_in\[72\] -ch_data_in\[71\] -ch_data_in\[70\] -ch_data_in\[69\] -ch_data_in\[68\] +ch_data_in\[68\] 1600 0 2 ch_data_in\[67\] ch_data_in\[66\] ch_data_in\[65\] @@ -994,6 +765,22 @@ ch_data_in\[38\] ch_data_in\[37\] ch_data_in\[36\] +ch_data_in\[35\] +ch_data_in\[34\] +ch_data_in\[33\] +ch_data_in\[32\] +ch_data_in\[31\] +ch_data_in\[30\] +ch_data_in\[29\] +ch_data_in\[28\] +ch_data_in\[27\] +ch_data_in\[26\] +ch_data_in\[25\] +ch_data_in\[24\] +ch_data_in\[23\] +ch_data_in\[22\] +ch_data_in\[21\] +ch_data_in\[20\] ch_data_out\[15\] ch_data_out\[14\]
diff --git a/openlane/yifive/base.sdc b/openlane/yifive/base.sdc index 375538d..d2293b6 100644 --- a/openlane/yifive/base.sdc +++ b/openlane/yifive/base.sdc
@@ -2,17 +2,18 @@ # Timing Constraints ############################################################################### create_clock -name core_clk -period 20.0000 [get_ports {core_clk}] +create_clock -name core_clk_mclk -period 20.0000 [get_ports {core_clk_mclk}] create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}] create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}] -create_generated_clock -name sram0_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {tcm sram clock0} [get_ports sram0_clk0] -create_generated_clock -name sram0_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {tcm sram clock1} [get_ports sram0_clk1] +create_generated_clock -name tcm_dffram_clk0 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {tcm clock0} [get_ports tcm_dffram_clk0] +create_generated_clock -name tcm_dffram_clk1 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {tcm clock1} [get_ports tcm_dffram_clk1] -create_generated_clock -name icache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache clock0} [get_ports icache_mem_clk0] -create_generated_clock -name icache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache clock1} [get_ports icache_mem_clk1] +create_generated_clock -name icache_dffram_clk0 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {icache clock0} [get_ports icache_dffram_clk0] +create_generated_clock -name icache_dffram_clk1 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {icache clock1} [get_ports icache_dffram_clk1] -create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache clock0} [get_ports dcache_mem_clk0] -create_generated_clock -name dcache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache clock1} [get_ports dcache_mem_clk1] +create_generated_clock -name dcache_dffram_clk0 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {dcache clock0} [get_ports dcache_dffram_clk0] +create_generated_clock -name dcache_dffram_clk1 -add -source [get_ports {core_clk_mclk}] -master_clock [get_clocks core_clk_mclk] -divide_by 1 -comment {dcache clock1} [get_ports dcache_dffram_clk1] set_clock_transition 0.1500 [all_clocks] set_clock_uncertainty -setup 0.2500 [all_clocks] @@ -27,7 +28,7 @@ set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] set_clock_groups -name async_clock -asynchronous \ - -group [get_clocks {core_clk sram0_clk0 sram0_clk1 icache_mem_clk0 icache_mem_clk1 dcache_mem_clk0 dcache_mem_clk1} ]\ + -group [get_clocks {core_clk core_clk_mclk tcm_dffram_clk0 tcm_dffram_clk1 icache_dffram_clk0 icache_dffram_clk1 dcache_dffram_clk0 dcache_dffram_clk1} ]\ -group [get_clocks {rtc_clk}]\ -group [get_clocks {wb_clk}] -comment {Async Clock group} @@ -43,76 +44,92 @@ set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_riscv #TCM Memory -set_input_delay -max 6.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_dout0[*]}] -set_input_delay -min 3.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_dout0[*]}] +set_input_delay -max 6.0000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_dout0[*]}] +set_input_delay -min 3.0000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_dout0[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_dout1[*]}] -set_input_delay -min 3.0000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_dout1[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_cs0}] +set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_addr0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_wmask0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_din0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_addr1[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_csb1}] +set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_cs0}] +set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_addr0[*]}] +set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_wmask0[*]}] +set_output_delay -min -3.5000 -clock [get_clocks {tcm_dffram_clk0}] -add_delay [get_ports {tcm_dffram_din0[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_addr1[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_csb1}] +# mem1 +set_input_delay -max 6.0000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_dout1[*]}] +set_input_delay -min 3.0000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_dout1[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_addr0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_csb0}] -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_din0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_web0}] -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_wmask0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_cs1}] +set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_addr1[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_wmask1[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_din1[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_addr0[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_csb0}] -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_din0[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_web0}] -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_wmask0[*]}] +set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_cs1}] +set_output_delay -min -0.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_addr1[*]}] +set_output_delay -min -1.0000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_wmask1[*]}] +set_output_delay -min -3.5000 -clock [get_clocks {tcm_dffram_clk1}] -add_delay [get_ports {tcm_dffram_din1[*]}] #icache memory -set_input_delay -max 6.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_dout1[*]}] -set_input_delay -min 3.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_dout1[*]}] +set_input_delay -max 6.0000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_dout0[*]}] +set_input_delay -min 3.0000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_dout0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_addr1[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_csb1}] +set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_cs0}] +set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_addr0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_wmask0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_din0[*]}] -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_addr1[*]}] -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_csb1}] +set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_cs0}] +set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_addr0[*]}] +set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_wmask0[*]}] +set_output_delay -min -3.5000 -clock [get_clocks {icache_dffram_clk0}] -add_delay [get_ports {icache_dffram_din0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}] -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}] -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}] +# mem1 +set_input_delay -max 6.0000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_dout1[*]}] +set_input_delay -min 3.0000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_dout1[*]}] -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}] -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}] -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}] -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}] -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_cs1}] +set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_addr1[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_wmask1[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_din1[*]}] + +set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_cs1}] +set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_addr1[*]}] +set_output_delay -min -0.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_wmask1[*]}] +set_output_delay -min -3.5000 -clock [get_clocks {icache_dffram_clk1}] -add_delay [get_ports {icache_dffram_din1[*]}] #dcache memory -set_input_delay -max 6.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_dout0[*]}] -set_input_delay -min 3.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_dout0[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_dout1[*]}] -set_input_delay -min 3.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_dout1[*]}] +set_input_delay -max 6.0000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_dout0[*]}] +set_input_delay -min 3.0000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_dout0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}] +set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_cs0}] +set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_addr0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_wmask0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_din0[*]}] -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}] -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}] +set_output_delay -min -0.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_cs0}] +set_output_delay -min -0.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_addr0[*]}] +set_output_delay -min -2.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_wmask0[*]}] +set_output_delay -min -3.5000 -clock [get_clocks {dcache_dffram_clk0}] -add_delay [get_ports {dcache_dffram_din0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}] -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}] -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}] +# mem1 +set_input_delay -max 6.0000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_dout1[*]}] +set_input_delay -min 3.0000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_dout1[*]}] -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}] -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}] -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}] -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}] -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_cs1}] +set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_addr1[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_wmask1[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_din1[*]}] + +set_output_delay -min -0.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_cs1}] +set_output_delay -min -0.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_addr1[*]}] +set_output_delay -min -2.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_wmask1[*]}] +set_output_delay -min -3.5000 -clock [get_clocks {dcache_dffram_clk1}] -add_delay [get_ports {dcache_dffram_din1[*]}] + + + set_input_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_rst_n}] @@ -138,56 +155,56 @@ set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}] #Wishbone icache -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_lack_i}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_ack_i}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_dat_i[*]}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_err_i}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_lack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_ack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_dat_i[*]}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_err_i}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_lack_i}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_ack_i}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_dat_i[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_dat_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_lack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_dat_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_dat_i[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_adr_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_sel_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_bl_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_bry_o}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_stb_o}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_we_o}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_adr_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_sel_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bl_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bry_o}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_stb_o}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_we_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_adr_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_sel_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_bl_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_bry_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_stb_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_we_o}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_adr_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_sel_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bl_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bry_o}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_stb_o}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_we_o}] #Wishbone dcache -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_lack_i}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_ack_i}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_i[*]}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_err_i}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}] +set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_err_i}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_lack_i}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_ack_i}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_i[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_adr_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_sel_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_bl_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_bry_o}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_stb_o}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_we_o}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_adr_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_sel_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bl_o[*]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bry_o}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_stb_o}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_we_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_adr_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_sel_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_bl_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_bry_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_stb_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_we_o}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_adr_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_sel_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bl_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bry_o}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_stb_o}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_we_o}] set_false_path\ -from [get_ports {soft_irq}]
diff --git a/openlane/yifive/config.tcl b/openlane/yifive/config.tcl index 1f117a8..c0a0db0 100755 --- a/openlane/yifive/config.tcl +++ b/openlane/yifive/config.tcl
@@ -67,7 +67,7 @@ $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_imem_router.sv \ $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_icache_router.sv \ $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_dcache_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_tcm.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_tcm_router.sv \ $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_timer.sv \ $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_top_wb.sv \ $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_dmem_wb.sv \ @@ -106,7 +106,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) [list 0.0 0.0 725.0 1550.0] +set ::env(DIE_AREA) [list 0.0 0.0 825.0 1550.0] # If you're going to use multiple power domains, then keep this disabled. @@ -116,21 +116,15 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.35" +set ::env(PL_TARGET_DENSITY) "0.34" set ::env(FP_CORE_UTIL) "50" -# helps in anteena fix -set ::env(USE_ARC_ANTENNA_CHECK) "0" -set ::env(FP_IO_VEXTEND) 4 -set ::env(FP_IO_HEXTEND) 4 -set ::env(FP_PDN_VPITCH) 100 -set ::env(FP_PDN_HPITCH) 100 -set ::env(FP_PDN_VWIDTH) 3 -set ::env(FP_PDN_HWIDTH) 3 +## Routing -set ::env(GLB_RT_MAXLAYER) 6 + +set ::env(GLB_RT_MAXLAYER) 5 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/yifive/pin_order.cfg b/openlane/yifive/pin_order.cfg index e168c5f..8a9b2a8 100644 --- a/openlane/yifive/pin_order.cfg +++ b/openlane/yifive/pin_order.cfg
@@ -371,358 +371,486 @@ wb_icache_err_i #W -sram0_clk1 0000 0 2 -sram0_csb1 -sram0_addr1\[8\] -sram0_addr1\[7\] -sram0_addr1\[6\] -sram0_addr1\[5\] -sram0_addr1\[4\] -sram0_addr1\[3\] -sram0_addr1\[2\] -sram0_addr1\[1\] -sram0_addr1\[0\] -sram0_dout1\[0\] 0200 0 2 -sram0_dout1\[1\] -sram0_dout1\[2\] -sram0_dout1\[3\] -sram0_dout1\[4\] -sram0_dout1\[5\] -sram0_dout1\[6\] -sram0_dout1\[7\] -sram0_dout1\[8\] -sram0_dout1\[9\] -sram0_dout1\[10\] -sram0_dout1\[11\] -sram0_dout1\[12\] -sram0_dout1\[13\] -sram0_dout1\[14\] -sram0_dout1\[15\] -sram0_dout1\[16\] -sram0_dout1\[17\] -sram0_dout1\[18\] -sram0_dout1\[19\] -sram0_dout1\[20\] -sram0_dout1\[21\] -sram0_dout1\[22\] -sram0_dout1\[23\] -sram0_dout1\[24\] -sram0_dout1\[25\] -sram0_dout1\[26\] -sram0_dout1\[27\] -sram0_dout1\[28\] -sram0_dout1\[29\] -sram0_dout1\[30\] -sram0_dout1\[31\] +tcm_dffram_clk0 0000 0 2 +tcm_dffram_cs0 +tcm_dffram_addr0\[7\] +tcm_dffram_addr0\[6\] +tcm_dffram_addr0\[5\] +tcm_dffram_addr0\[4\] +tcm_dffram_addr0\[3\] +tcm_dffram_addr0\[2\] +tcm_dffram_addr0\[1\] +tcm_dffram_addr0\[0\] +tcm_dffram_wmask0\[3\] +tcm_dffram_wmask0\[2\] +tcm_dffram_wmask0\[1\] +tcm_dffram_wmask0\[0\] +tcm_dffram_din0\[31\] +tcm_dffram_din0\[30\] +tcm_dffram_din0\[29\] +tcm_dffram_din0\[28\] +tcm_dffram_din0\[27\] +tcm_dffram_din0\[26\] +tcm_dffram_din0\[25\] +tcm_dffram_din0\[24\] +tcm_dffram_din0\[23\] +tcm_dffram_din0\[22\] +tcm_dffram_din0\[21\] +tcm_dffram_din0\[20\] +tcm_dffram_din0\[19\] +tcm_dffram_din0\[18\] +tcm_dffram_din0\[17\] +tcm_dffram_din0\[16\] +tcm_dffram_din0\[15\] +tcm_dffram_din0\[14\] +tcm_dffram_din0\[13\] +tcm_dffram_din0\[12\] +tcm_dffram_din0\[11\] +tcm_dffram_din0\[10\] +tcm_dffram_din0\[9\] +tcm_dffram_din0\[8\] +tcm_dffram_din0\[7\] +tcm_dffram_din0\[6\] +tcm_dffram_din0\[5\] +tcm_dffram_din0\[4\] +tcm_dffram_din0\[3\] +tcm_dffram_din0\[2\] +tcm_dffram_din0\[1\] +tcm_dffram_din0\[0\] -icache_mem_clk0 300 0 2 -icache_mem_csb0 -icache_mem_web0 -icache_mem_addr0\[0\] -icache_mem_addr0\[1\] -icache_mem_addr0\[2\] -icache_mem_addr0\[3\] -icache_mem_addr0\[4\] -icache_mem_addr0\[5\] -icache_mem_addr0\[6\] -icache_mem_addr0\[7\] -icache_mem_addr0\[8\] -icache_mem_wmask0\[0\] -icache_mem_wmask0\[1\] -icache_mem_wmask0\[2\] -icache_mem_wmask0\[3\] -icache_mem_din0\[0\] -icache_mem_din0\[1\] -icache_mem_din0\[2\] -icache_mem_din0\[3\] -icache_mem_din0\[4\] -icache_mem_din0\[5\] -icache_mem_din0\[6\] -icache_mem_din0\[7\] -icache_mem_din0\[8\] -icache_mem_din0\[9\] -icache_mem_din0\[10\] -icache_mem_din0\[11\] -icache_mem_din0\[12\] -icache_mem_din0\[13\] -icache_mem_din0\[14\] -icache_mem_din0\[15\] -icache_mem_din0\[16\] -icache_mem_din0\[17\] -icache_mem_din0\[18\] -icache_mem_din0\[19\] -icache_mem_din0\[20\] -icache_mem_din0\[21\] -icache_mem_din0\[22\] -icache_mem_din0\[23\] -icache_mem_din0\[24\] -icache_mem_din0\[25\] -icache_mem_din0\[26\] -icache_mem_din0\[27\] -icache_mem_din0\[28\] -icache_mem_din0\[29\] -icache_mem_din0\[30\] -icache_mem_din0\[31\] +tcm_dffram_dout0\[31\] 750 0 2 +tcm_dffram_dout0\[30\] +tcm_dffram_dout0\[29\] +tcm_dffram_dout0\[28\] +tcm_dffram_dout0\[27\] +tcm_dffram_dout0\[26\] +tcm_dffram_dout0\[25\] +tcm_dffram_dout0\[24\] +tcm_dffram_dout0\[23\] +tcm_dffram_dout0\[22\] +tcm_dffram_dout0\[21\] +tcm_dffram_dout0\[20\] +tcm_dffram_dout0\[19\] +tcm_dffram_dout0\[18\] +tcm_dffram_dout0\[17\] +tcm_dffram_dout0\[16\] +tcm_dffram_dout0\[15\] +tcm_dffram_dout0\[14\] +tcm_dffram_dout0\[13\] +tcm_dffram_dout0\[12\] +tcm_dffram_dout0\[11\] +tcm_dffram_dout0\[10\] +tcm_dffram_dout0\[9\] +tcm_dffram_dout0\[8\] +tcm_dffram_dout0\[7\] +tcm_dffram_dout0\[6\] +tcm_dffram_dout0\[5\] +tcm_dffram_dout0\[4\] +tcm_dffram_dout0\[3\] +tcm_dffram_dout0\[2\] +tcm_dffram_dout0\[1\] +tcm_dffram_dout0\[0\] -icache_mem_clk1 0400 0 2 -icache_mem_csb1 -icache_mem_addr1\[8\] -icache_mem_addr1\[7\] -icache_mem_addr1\[6\] -icache_mem_addr1\[5\] -icache_mem_addr1\[4\] -icache_mem_addr1\[3\] -icache_mem_addr1\[2\] -icache_mem_addr1\[1\] -icache_mem_addr1\[0\] +tcm_dffram_clk1 0800 0 2 +tcm_dffram_cs1 +tcm_dffram_addr1\[0\] +tcm_dffram_addr1\[1\] +tcm_dffram_addr1\[2\] +tcm_dffram_addr1\[3\] +tcm_dffram_addr1\[4\] +tcm_dffram_addr1\[5\] +tcm_dffram_addr1\[6\] +tcm_dffram_addr1\[7\] +tcm_dffram_wmask1\[0\] +tcm_dffram_wmask1\[1\] +tcm_dffram_wmask1\[2\] +tcm_dffram_wmask1\[3\] +tcm_dffram_din1\[0\] +tcm_dffram_din1\[1\] +tcm_dffram_din1\[2\] +tcm_dffram_din1\[3\] +tcm_dffram_din1\[4\] +tcm_dffram_din1\[5\] +tcm_dffram_din1\[6\] +tcm_dffram_din1\[7\] +tcm_dffram_din1\[8\] +tcm_dffram_din1\[9\] +tcm_dffram_din1\[10\] +tcm_dffram_din1\[11\] +tcm_dffram_din1\[12\] +tcm_dffram_din1\[13\] +tcm_dffram_din1\[14\] +tcm_dffram_din1\[15\] +tcm_dffram_din1\[16\] +tcm_dffram_din1\[17\] +tcm_dffram_din1\[18\] +tcm_dffram_din1\[19\] +tcm_dffram_din1\[20\] +tcm_dffram_din1\[21\] +tcm_dffram_din1\[22\] +tcm_dffram_din1\[23\] +tcm_dffram_din1\[24\] +tcm_dffram_din1\[25\] +tcm_dffram_din1\[26\] +tcm_dffram_din1\[27\] +tcm_dffram_din1\[28\] +tcm_dffram_din1\[29\] +tcm_dffram_din1\[30\] +tcm_dffram_din1\[31\] -icache_mem_dout1\[0\] 0450 0 2 -icache_mem_dout1\[1\] -icache_mem_dout1\[2\] -icache_mem_dout1\[3\] -icache_mem_dout1\[4\] -icache_mem_dout1\[5\] -icache_mem_dout1\[6\] -icache_mem_dout1\[7\] -icache_mem_dout1\[8\] -icache_mem_dout1\[9\] -icache_mem_dout1\[10\] -icache_mem_dout1\[11\] -icache_mem_dout1\[12\] -icache_mem_dout1\[13\] -icache_mem_dout1\[14\] -icache_mem_dout1\[15\] -icache_mem_dout1\[16\] -icache_mem_dout1\[17\] -icache_mem_dout1\[18\] -icache_mem_dout1\[19\] -icache_mem_dout1\[20\] -icache_mem_dout1\[21\] -icache_mem_dout1\[22\] -icache_mem_dout1\[23\] -icache_mem_dout1\[24\] -icache_mem_dout1\[25\] -icache_mem_dout1\[26\] -icache_mem_dout1\[27\] -icache_mem_dout1\[28\] -icache_mem_dout1\[29\] -icache_mem_dout1\[30\] -icache_mem_dout1\[31\] +tcm_dffram_dout1\[31\] 1450 0 2 +tcm_dffram_dout1\[30\] +tcm_dffram_dout1\[29\] +tcm_dffram_dout1\[28\] +tcm_dffram_dout1\[27\] +tcm_dffram_dout1\[26\] +tcm_dffram_dout1\[25\] +tcm_dffram_dout1\[24\] +tcm_dffram_dout1\[23\] +tcm_dffram_dout1\[22\] +tcm_dffram_dout1\[21\] +tcm_dffram_dout1\[20\] +tcm_dffram_dout1\[19\] +tcm_dffram_dout1\[18\] +tcm_dffram_dout1\[17\] +tcm_dffram_dout1\[16\] +tcm_dffram_dout1\[15\] +tcm_dffram_dout1\[14\] +tcm_dffram_dout1\[13\] +tcm_dffram_dout1\[12\] +tcm_dffram_dout1\[11\] +tcm_dffram_dout1\[10\] +tcm_dffram_dout1\[9\] +tcm_dffram_dout1\[8\] +tcm_dffram_dout1\[7\] +tcm_dffram_dout1\[6\] +tcm_dffram_dout1\[5\] +tcm_dffram_dout1\[4\] +tcm_dffram_dout1\[3\] +tcm_dffram_dout1\[2\] +tcm_dffram_dout1\[1\] +tcm_dffram_dout1\[0\] -dcache_mem_clk0 850 0 2 -dcache_mem_csb0 -dcache_mem_web0 -dcache_mem_addr0\[0\] -dcache_mem_addr0\[1\] -dcache_mem_addr0\[2\] -dcache_mem_addr0\[3\] -dcache_mem_addr0\[4\] -dcache_mem_addr0\[5\] -dcache_mem_addr0\[6\] -dcache_mem_addr0\[7\] -dcache_mem_addr0\[8\] -dcache_mem_wmask0\[0\] -dcache_mem_wmask0\[1\] -dcache_mem_wmask0\[2\] -dcache_mem_wmask0\[3\] -dcache_mem_din0\[0\] -dcache_mem_din0\[1\] -dcache_mem_din0\[2\] -dcache_mem_din0\[3\] -dcache_mem_din0\[4\] -dcache_mem_din0\[5\] -dcache_mem_din0\[6\] -dcache_mem_din0\[7\] -dcache_mem_din0\[8\] -dcache_mem_din0\[9\] -dcache_mem_din0\[10\] -dcache_mem_din0\[11\] -dcache_mem_din0\[12\] -dcache_mem_din0\[13\] -dcache_mem_din0\[14\] -dcache_mem_din0\[15\] -dcache_mem_din0\[16\] -dcache_mem_din0\[17\] -dcache_mem_din0\[18\] -dcache_mem_din0\[19\] -dcache_mem_din0\[20\] -dcache_mem_din0\[21\] -dcache_mem_din0\[22\] -dcache_mem_din0\[23\] -dcache_mem_din0\[24\] -dcache_mem_din0\[25\] -dcache_mem_din0\[26\] -dcache_mem_din0\[27\] -dcache_mem_din0\[28\] -dcache_mem_din0\[29\] -dcache_mem_din0\[30\] -dcache_mem_din0\[31\] +#N +dcache_dffram_clk0 0000 0 2 +dcache_dffram_din0\[0\] +dcache_dffram_din0\[1\] +dcache_dffram_din0\[2\] +dcache_dffram_din0\[3\] +dcache_dffram_din0\[4\] +dcache_dffram_din0\[5\] +dcache_dffram_din0\[6\] +dcache_dffram_din0\[7\] +dcache_dffram_din0\[8\] +dcache_dffram_din0\[9\] +dcache_dffram_din0\[10\] +dcache_dffram_din0\[11\] +dcache_dffram_din0\[12\] +dcache_dffram_din0\[13\] +dcache_dffram_din0\[14\] +dcache_dffram_din0\[15\] +dcache_dffram_din0\[16\] +dcache_dffram_din0\[17\] +dcache_dffram_din0\[18\] +dcache_dffram_din0\[19\] +dcache_dffram_din0\[20\] +dcache_dffram_din0\[21\] +dcache_dffram_din0\[22\] +dcache_dffram_din0\[23\] +dcache_dffram_din0\[24\] +dcache_dffram_din0\[25\] +dcache_dffram_din0\[26\] +dcache_dffram_din0\[27\] +dcache_dffram_din0\[28\] +dcache_dffram_din0\[29\] +dcache_dffram_din0\[30\] +dcache_dffram_din0\[31\] +dcache_dffram_cs0 +dcache_dffram_addr0\[7\] +dcache_dffram_addr0\[6\] +dcache_dffram_addr0\[5\] +dcache_dffram_addr0\[4\] +dcache_dffram_addr0\[3\] +dcache_dffram_addr0\[2\] +dcache_dffram_addr0\[1\] +dcache_dffram_addr0\[0\] +dcache_dffram_wmask0\[3\] +dcache_dffram_wmask0\[2\] +dcache_dffram_wmask0\[1\] +dcache_dffram_wmask0\[0\] +dcache_dffram_dout0\[0\] +dcache_dffram_dout0\[1\] +dcache_dffram_dout0\[2\] +dcache_dffram_dout0\[3\] +dcache_dffram_dout0\[4\] +dcache_dffram_dout0\[5\] +dcache_dffram_dout0\[6\] +dcache_dffram_dout0\[7\] +dcache_dffram_dout0\[8\] +dcache_dffram_dout0\[9\] +dcache_dffram_dout0\[10\] +dcache_dffram_dout0\[11\] +dcache_dffram_dout0\[12\] +dcache_dffram_dout0\[13\] +dcache_dffram_dout0\[14\] +dcache_dffram_dout0\[15\] +dcache_dffram_dout0\[16\] +dcache_dffram_dout0\[17\] +dcache_dffram_dout0\[18\] +dcache_dffram_dout0\[19\] +dcache_dffram_dout0\[20\] +dcache_dffram_dout0\[21\] +dcache_dffram_dout0\[22\] +dcache_dffram_dout0\[23\] +dcache_dffram_dout0\[24\] +dcache_dffram_dout0\[25\] +dcache_dffram_dout0\[26\] +dcache_dffram_dout0\[27\] +dcache_dffram_dout0\[28\] +dcache_dffram_dout0\[29\] +dcache_dffram_dout0\[30\] +dcache_dffram_dout0\[31\] - -dcache_mem_dout0\[0\] 950 0 2 -dcache_mem_dout0\[1\] -dcache_mem_dout0\[2\] -dcache_mem_dout0\[3\] -dcache_mem_dout0\[4\] -dcache_mem_dout0\[5\] -dcache_mem_dout0\[6\] -dcache_mem_dout0\[7\] -dcache_mem_dout0\[8\] -dcache_mem_dout0\[9\] -dcache_mem_dout0\[10\] -dcache_mem_dout0\[11\] -dcache_mem_dout0\[12\] -dcache_mem_dout0\[13\] -dcache_mem_dout0\[14\] -dcache_mem_dout0\[15\] -dcache_mem_dout0\[16\] -dcache_mem_dout0\[17\] -dcache_mem_dout0\[18\] -dcache_mem_dout0\[19\] -dcache_mem_dout0\[20\] -dcache_mem_dout0\[21\] -dcache_mem_dout0\[22\] -dcache_mem_dout0\[23\] -dcache_mem_dout0\[24\] -dcache_mem_dout0\[25\] -dcache_mem_dout0\[26\] -dcache_mem_dout0\[27\] -dcache_mem_dout0\[28\] -dcache_mem_dout0\[29\] -dcache_mem_dout0\[30\] -dcache_mem_dout0\[31\] - -dcache_mem_clk1 1000 0 2 -dcache_mem_csb1 -dcache_mem_addr1\[8\] -dcache_mem_addr1\[7\] -dcache_mem_addr1\[6\] -dcache_mem_addr1\[5\] -dcache_mem_addr1\[4\] -dcache_mem_addr1\[3\] -dcache_mem_addr1\[2\] -dcache_mem_addr1\[1\] -dcache_mem_addr1\[0\] - -dcache_mem_dout1\[0\] 1050 0 2 -dcache_mem_dout1\[1\] -dcache_mem_dout1\[2\] -dcache_mem_dout1\[3\] -dcache_mem_dout1\[4\] -dcache_mem_dout1\[5\] -dcache_mem_dout1\[6\] -dcache_mem_dout1\[7\] -dcache_mem_dout1\[8\] -dcache_mem_dout1\[9\] -dcache_mem_dout1\[10\] -dcache_mem_dout1\[11\] -dcache_mem_dout1\[12\] -dcache_mem_dout1\[13\] -dcache_mem_dout1\[14\] -dcache_mem_dout1\[15\] -dcache_mem_dout1\[16\] -dcache_mem_dout1\[17\] -dcache_mem_dout1\[18\] -dcache_mem_dout1\[19\] -dcache_mem_dout1\[20\] -dcache_mem_dout1\[21\] -dcache_mem_dout1\[22\] -dcache_mem_dout1\[23\] -dcache_mem_dout1\[24\] -dcache_mem_dout1\[25\] -dcache_mem_dout1\[26\] -dcache_mem_dout1\[27\] -dcache_mem_dout1\[28\] -dcache_mem_dout1\[29\] -dcache_mem_dout1\[30\] -dcache_mem_dout1\[31\] +dcache_dffram_clk1 0300 0 2 +dcache_dffram_din1\[0\] +dcache_dffram_din1\[1\] +dcache_dffram_din1\[2\] +dcache_dffram_din1\[3\] +dcache_dffram_din1\[4\] +dcache_dffram_din1\[5\] +dcache_dffram_din1\[6\] +dcache_dffram_din1\[7\] +dcache_dffram_din1\[8\] +dcache_dffram_din1\[9\] +dcache_dffram_din1\[10\] +dcache_dffram_din1\[11\] +dcache_dffram_din1\[12\] +dcache_dffram_din1\[13\] +dcache_dffram_din1\[14\] +dcache_dffram_din1\[15\] +dcache_dffram_din1\[16\] +dcache_dffram_din1\[17\] +dcache_dffram_din1\[18\] +dcache_dffram_din1\[19\] +dcache_dffram_din1\[20\] +dcache_dffram_din1\[21\] +dcache_dffram_din1\[22\] +dcache_dffram_din1\[23\] +dcache_dffram_din1\[24\] +dcache_dffram_din1\[25\] +dcache_dffram_din1\[26\] +dcache_dffram_din1\[27\] +dcache_dffram_din1\[28\] +dcache_dffram_din1\[29\] +dcache_dffram_din1\[30\] +dcache_dffram_din1\[31\] +dcache_dffram_cs1 +dcache_dffram_addr1\[7\] +dcache_dffram_addr1\[6\] +dcache_dffram_addr1\[5\] +dcache_dffram_addr1\[4\] +dcache_dffram_addr1\[3\] +dcache_dffram_addr1\[2\] +dcache_dffram_addr1\[1\] +dcache_dffram_addr1\[0\] +dcache_dffram_wmask1\[3\] +dcache_dffram_wmask1\[2\] +dcache_dffram_wmask1\[1\] +dcache_dffram_wmask1\[0\] +dcache_dffram_dout1\[0\] +dcache_dffram_dout1\[1\] +dcache_dffram_dout1\[2\] +dcache_dffram_dout1\[3\] +dcache_dffram_dout1\[4\] +dcache_dffram_dout1\[5\] +dcache_dffram_dout1\[6\] +dcache_dffram_dout1\[7\] +dcache_dffram_dout1\[8\] +dcache_dffram_dout1\[9\] +dcache_dffram_dout1\[10\] +dcache_dffram_dout1\[11\] +dcache_dffram_dout1\[12\] +dcache_dffram_dout1\[13\] +dcache_dffram_dout1\[14\] +dcache_dffram_dout1\[15\] +dcache_dffram_dout1\[16\] +dcache_dffram_dout1\[17\] +dcache_dffram_dout1\[18\] +dcache_dffram_dout1\[19\] +dcache_dffram_dout1\[20\] +dcache_dffram_dout1\[21\] +dcache_dffram_dout1\[22\] +dcache_dffram_dout1\[23\] +dcache_dffram_dout1\[24\] +dcache_dffram_dout1\[25\] +dcache_dffram_dout1\[26\] +dcache_dffram_dout1\[27\] +dcache_dffram_dout1\[28\] +dcache_dffram_dout1\[29\] +dcache_dffram_dout1\[30\] +dcache_dffram_dout1\[31\] #S -sram0_clk0 0 0 2 -sram0_csb0 -sram0_web0 -sram0_addr0\[0\] -sram0_addr0\[1\] -sram0_addr0\[2\] -sram0_addr0\[3\] -sram0_addr0\[4\] -sram0_addr0\[5\] -sram0_addr0\[6\] -sram0_addr0\[7\] -sram0_addr0\[8\] -sram0_wmask0\[0\] -sram0_wmask0\[1\] -sram0_wmask0\[2\] -sram0_wmask0\[3\] -sram0_din0\[0\] -sram0_din0\[1\] -sram0_din0\[2\] -sram0_din0\[3\] -sram0_din0\[4\] -sram0_din0\[5\] -sram0_din0\[6\] -sram0_din0\[7\] -sram0_din0\[8\] -sram0_din0\[9\] -sram0_din0\[10\] -sram0_din0\[11\] -sram0_din0\[12\] -sram0_din0\[13\] -sram0_din0\[14\] -sram0_din0\[15\] -sram0_din0\[16\] -sram0_din0\[17\] -sram0_din0\[18\] -sram0_din0\[19\] -sram0_din0\[20\] -sram0_din0\[21\] -sram0_din0\[22\] -sram0_din0\[23\] -sram0_din0\[24\] -sram0_din0\[25\] -sram0_din0\[26\] -sram0_din0\[27\] -sram0_din0\[28\] -sram0_din0\[29\] -sram0_din0\[30\] -sram0_din0\[31\] +icache_dffram_clk0 0000 0 2 +icache_dffram_dout0\[0\] +icache_dffram_dout0\[1\] +icache_dffram_dout0\[2\] +icache_dffram_dout0\[3\] +icache_dffram_dout0\[4\] +icache_dffram_dout0\[5\] +icache_dffram_dout0\[6\] +icache_dffram_dout0\[7\] +icache_dffram_dout0\[8\] +icache_dffram_dout0\[9\] +icache_dffram_dout0\[10\] +icache_dffram_dout0\[11\] +icache_dffram_dout0\[12\] +icache_dffram_dout0\[13\] +icache_dffram_dout0\[14\] +icache_dffram_dout0\[15\] +icache_dffram_dout0\[16\] +icache_dffram_dout0\[17\] +icache_dffram_dout0\[18\] +icache_dffram_dout0\[19\] +icache_dffram_dout0\[20\] +icache_dffram_dout0\[21\] +icache_dffram_dout0\[22\] +icache_dffram_dout0\[23\] +icache_dffram_dout0\[24\] +icache_dffram_dout0\[25\] +icache_dffram_dout0\[26\] +icache_dffram_dout0\[27\] +icache_dffram_dout0\[28\] +icache_dffram_dout0\[29\] +icache_dffram_dout0\[30\] +icache_dffram_dout0\[31\] +icache_dffram_cs0 +icache_dffram_addr0\[7\] +icache_dffram_addr0\[6\] +icache_dffram_addr0\[5\] +icache_dffram_addr0\[4\] +icache_dffram_addr0\[3\] +icache_dffram_addr0\[2\] +icache_dffram_addr0\[1\] +icache_dffram_addr0\[0\] +icache_dffram_wmask0\[3\] +icache_dffram_wmask0\[2\] +icache_dffram_wmask0\[1\] +icache_dffram_wmask0\[0\] +icache_dffram_din0\[0\] +icache_dffram_din0\[1\] +icache_dffram_din0\[2\] +icache_dffram_din0\[3\] +icache_dffram_din0\[4\] +icache_dffram_din0\[5\] +icache_dffram_din0\[6\] +icache_dffram_din0\[7\] +icache_dffram_din0\[8\] +icache_dffram_din0\[9\] +icache_dffram_din0\[10\] +icache_dffram_din0\[11\] +icache_dffram_din0\[12\] +icache_dffram_din0\[13\] +icache_dffram_din0\[14\] +icache_dffram_din0\[15\] +icache_dffram_din0\[16\] +icache_dffram_din0\[17\] +icache_dffram_din0\[18\] +icache_dffram_din0\[19\] +icache_dffram_din0\[20\] +icache_dffram_din0\[21\] +icache_dffram_din0\[22\] +icache_dffram_din0\[23\] +icache_dffram_din0\[24\] +icache_dffram_din0\[25\] +icache_dffram_din0\[26\] +icache_dffram_din0\[27\] +icache_dffram_din0\[28\] +icache_dffram_din0\[29\] +icache_dffram_din0\[30\] +icache_dffram_din0\[31\] +icache_dffram_clk1 0300 0 2 +icache_dffram_dout1\[0\] +icache_dffram_dout1\[1\] +icache_dffram_dout1\[2\] +icache_dffram_dout1\[3\] +icache_dffram_dout1\[4\] +icache_dffram_dout1\[5\] +icache_dffram_dout1\[6\] +icache_dffram_dout1\[7\] +icache_dffram_dout1\[8\] +icache_dffram_dout1\[9\] +icache_dffram_dout1\[10\] +icache_dffram_dout1\[11\] +icache_dffram_dout1\[12\] +icache_dffram_dout1\[13\] +icache_dffram_dout1\[14\] +icache_dffram_dout1\[15\] +icache_dffram_dout1\[16\] +icache_dffram_dout1\[17\] +icache_dffram_dout1\[18\] +icache_dffram_dout1\[19\] +icache_dffram_dout1\[20\] +icache_dffram_dout1\[21\] +icache_dffram_dout1\[22\] +icache_dffram_dout1\[23\] +icache_dffram_dout1\[24\] +icache_dffram_dout1\[25\] +icache_dffram_dout1\[26\] +icache_dffram_dout1\[27\] +icache_dffram_dout1\[28\] +icache_dffram_dout1\[29\] +icache_dffram_dout1\[30\] +icache_dffram_dout1\[31\] +icache_dffram_cs1 +icache_dffram_addr1\[7\] +icache_dffram_addr1\[6\] +icache_dffram_addr1\[5\] +icache_dffram_addr1\[4\] +icache_dffram_addr1\[3\] +icache_dffram_addr1\[2\] +icache_dffram_addr1\[1\] +icache_dffram_addr1\[0\] +icache_dffram_wmask1\[3\] +icache_dffram_wmask1\[2\] +icache_dffram_wmask1\[1\] +icache_dffram_wmask1\[0\] +icache_dffram_din1\[0\] +icache_dffram_din1\[1\] +icache_dffram_din1\[2\] +icache_dffram_din1\[3\] +icache_dffram_din1\[4\] +icache_dffram_din1\[5\] +icache_dffram_din1\[6\] +icache_dffram_din1\[7\] +icache_dffram_din1\[8\] +icache_dffram_din1\[9\] +icache_dffram_din1\[10\] +icache_dffram_din1\[11\] +icache_dffram_din1\[12\] +icache_dffram_din1\[13\] +icache_dffram_din1\[14\] +icache_dffram_din1\[15\] +icache_dffram_din1\[16\] +icache_dffram_din1\[17\] +icache_dffram_din1\[18\] +icache_dffram_din1\[19\] +icache_dffram_din1\[20\] +icache_dffram_din1\[21\] +icache_dffram_din1\[22\] +icache_dffram_din1\[23\] +icache_dffram_din1\[24\] +icache_dffram_din1\[25\] +icache_dffram_din1\[26\] +icache_dffram_din1\[27\] +icache_dffram_din1\[28\] +icache_dffram_din1\[29\] +icache_dffram_din1\[30\] +icache_dffram_din1\[31\] -sram0_dout0\[0\] 0100 0 2 -sram0_dout0\[1\] -sram0_dout0\[2\] -sram0_dout0\[3\] -sram0_dout0\[4\] -sram0_dout0\[5\] -sram0_dout0\[6\] -sram0_dout0\[7\] -sram0_dout0\[8\] -sram0_dout0\[9\] -sram0_dout0\[10\] -sram0_dout0\[11\] -sram0_dout0\[12\] -sram0_dout0\[13\] -sram0_dout0\[14\] -sram0_dout0\[15\] -sram0_dout0\[16\] -sram0_dout0\[17\] -sram0_dout0\[18\] -sram0_dout0\[19\] -sram0_dout0\[20\] -sram0_dout0\[21\] -sram0_dout0\[22\] -sram0_dout0\[23\] -sram0_dout0\[24\] -sram0_dout0\[25\] -sram0_dout0\[26\] -sram0_dout0\[27\] -sram0_dout0\[28\] -sram0_dout0\[29\] -sram0_dout0\[30\] -sram0_dout0\[31\] - -riscv_debug\[0\] 300 0 2 +riscv_debug\[0\] 600 0 2 riscv_debug\[1\] riscv_debug\[2\] riscv_debug\[3\] @@ -788,9 +916,10 @@ riscv_debug\[63\] -wb_rst_n 500 0 2 +wb_rst_n 700 0 2 pwrup_rst_n rst_n core_clk +core_clk_mclk rtc_clk cpu_rst_n
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv index 7337820..35e8e08 100644 --- a/signoff/pinmux/final_summary_report.csv +++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h16m12s,-1,46109.09090909091,0.2475,23054.545454545456,27.07,714.13,5706,0,0,0,0,0,0,-1,1,0,-1,-1,434666,61807,0.0,-0.01,-1,0.0,-1,0.0,-0.03,-1,0.0,-1,320204079.0,5.99,43.88,33.8,11.89,0.3,-1,3574,8564,543,5532,0,0,0,4202,0,0,0,0,0,0,0,4,1343,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h19m18s,-1,42496.969696969696,0.2475,21248.484848484848,25.12,683.6,5259,0,0,0,0,0,0,-1,1,0,-1,-1,386276,55331,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,284511398.0,1.83,41.67,29.27,8.61,0.36,-1,3370,8310,523,5463,0,0,0,3952,0,0,0,0,0,0,0,4,1188,1209,11,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index a731e6b..5600253 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h49m56s0ms,0h3m54s0ms,-2.0,-1,-1,-1,556.96,14,0,0,0,0,0,0,-1,0,1,-1,-1,1417872,9018,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,6.67,6.71,1.05,1.33,-1,313,2877,313,2877,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,120,0.55,0.3,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h31m29s0ms,0h5m4s0ms,-2.0,-1,-1,-1,542.86,12,0,0,0,0,0,0,0,0,2,-1,-1,1256382,6969,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.83,7.29,0.62,0.23,-1,225,2313,225,2313,0,0,0,12,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,130,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv index 7be1787..d1c2680 100644 --- a/signoff/wb_host/final_summary_report.csv +++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h10m23s,-1,51962.5,0.16,25981.25,34.69,645.3,4157,0,0,0,0,0,0,0,5,0,0,-1,329531,47752,0.0,-0.23,-1,0.0,-1,0.0,-26.36,-1,0.0,-1,265017619.0,4.63,61.49,19.26,29.21,0.09,-1,3490,6163,1024,3553,0,0,0,3793,0,0,0,0,0,0,0,4,1233,1205,17,130,2043,0,2173,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h7m6s,-1,59385.714285714275,0.14,29692.857142857138,37.96,637.61,4157,0,0,0,0,0,0,0,5,0,0,-1,217151,39662,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,160154988.0,8.33,37.43,36.42,1.44,1.04,-1,3490,6163,1024,3553,0,0,0,3793,0,0,0,0,0,0,0,4,1233,1205,17,278,1833,0,2111,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.38,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv index 5f2f6ea..dc04ace 100644 --- a/signoff/wb_interconnect/final_summary_report.csv +++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h18m24s,-1,19852.173913043476,0.46,9926.086956521738,9.27,726.88,4566,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,848196,51567,-0.9,-9.3,-1,-1.34,-1,-99.69,-2508.48,-1,-173.72,-1,745063608.0,0.0,15.97,52.54,2.07,42.24,0.0,1776,5292,252,3767,0,0,0,2682,0,0,0,0,0,0,0,4,1192,1079,18,1674,5873,0,7547,90.9090909090909,11,10,AREA 0,2,50,1,153.6,153.18,0.3,0,sky130_fd_sc_hd,4,4 +0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h8m15s,-1,17786.95652173913,0.46,8893.478260869564,8.68,721.65,4091,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,640876,41064,-0.73,-6.41,-1,-1.56,-1,-52.16,-1603.55,-1,-180.97,-1,557971394.0,0.0,10.49,40.22,1.32,33.74,0.0,1458,4661,237,3439,0,0,0,2319,0,0,0,0,0,0,0,4,1150,1018,18,1674,5873,0,7547,90.9090909090909,11,10,AREA 0,2,50,1,120,120,0.3,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/yifive/final_summary_report.csv b/signoff/yifive/final_summary_report.csv index 1468984..4a26323 100644 --- a/signoff/yifive/final_summary_report.csv +++ b/signoff/yifive/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h15m29s,-1,60431.59065628477,1.12375,30215.795328142383,34.22,1576.42,33955,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,2627806,392238,-14.85,-43.3,-1,-1.42,-1,-32507.17,-16836.69,-1,-10.35,-1,1924632372.0,11.2,42.7,59.54,6.88,11.31,0.0,28631,47773,1744,20479,0,0,0,34029,0,0,0,0,0,0,0,4,8317,8690,56,1122,15482,0,16604,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h0m15s,-1,53775.953079178886,1.27875,26887.976539589443,30.43,1603.14,34383,0,-1,-1,-1,-1,0,-1,-1,0,-1,-1,2656544,381348,-15.47,-42.07,-1,-2.29,-1,-34148.14,-19180.15,-1,-43.72,-1,1952929426.0,10.78,39.67,51.49,5.51,10.2,-1,28691,48378,1777,21057,0,0,0,34243,0,0,0,0,0,0,0,4,8316,8735,54,1122,17734,0,18856,90.9090909090909,11,10,AREA 0,4,50,1,153.6,153.18,0.34,0.0,sky130_fd_sc_hd,4,4
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl index f78d21e..1eb1445 100644 --- a/sta/scripts/caravel_timing.tcl +++ b/sta/scripts/caravel_timing.tcl
@@ -1,7 +1,9 @@ set ::env(USER_ROOT) "/home/dinesha/workarea/opencore/git/riscduino" - set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe" - set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw4" + #set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe" + #set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw4" + set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel" + set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw4" read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib @@ -49,7 +51,6 @@ read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v - read_verilog $::env(USER_ROOT)/verilog/gl/mbist_wrapper.v read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v @@ -144,14 +145,18 @@ read_spef -path gpio_defaults_block_37 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef ## User Project Spef - read_spef -path mprj/u_mbist $::env(USER_ROOT)/spef/mbist_wrapper.spef - read_spef -path mprj/u_riscv_top $::env(USER_ROOT)/spef/ycr1_top_wb.spef read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux.spef read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef read_spef -path mprj/u_intercon $::env(USER_ROOT)/spef/wb_interconnect.spef + read_spef -path mprj/u_tcm_1KB_mem0 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef + read_spef -path mprj/u_tcm_1KB_mem1 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef + read_spef -path mprj/u_icache_1KB_mem0 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef + read_spef -path mprj/u_icache_1KB_mem1 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef + read_spef -path mprj/u_dcache_1KB_mem0 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef + read_spef -path mprj/u_dcache_1KB_mem1 $::env(CARAVEL_ROOT)/mgmt_core_wrapper/spef/DFFRAM.spef read_spef -path mprj $::env(USER_ROOT)/spef/user_project_wrapper.spef @@ -182,4 +187,80 @@ echo "Wishbone Interface Timing for [get_full_name $pin]" >> wb.min.rpt report_checks -path_delay min -fields {slew cap input nets fanout} -through $pin >> wb.min.rpt } + + #Min Delay check around DFFRAM + echo "DFFRAM Interface Min Timing.................." > mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/WE[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/EN >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/Di[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/A[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/Do[*] >> mprj.dffram.min.rpt + + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/WE[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/EN >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/Di[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/A[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/Do[*] >> mprj.dffram.min.rpt + + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/WE[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/EN >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/Di[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/A[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/Do[*] >> mprj.dffram.min.rpt + + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/WE[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/EN >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/Di[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/A[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/Do[*] >> mprj.dffram.min.rpt + + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/WE[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/EN >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/Di[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/A[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/A[*] >> mprj.dffram.min.rpt + + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/WE[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/EN >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/Di[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/A[*] >> mprj.dffram.min.rpt + report_checks -path_delay min -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/Do[*] >> mprj.dffram.min.rpt + + #Max Delay check around DFFRAM + echo "DFFRAM Interface Max Timing.................." > mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/WE[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/EN >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/Di[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/A[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem0/Do[*] >> mprj.dffram.max.rpt + + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/WE[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/EN >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/Di[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/A[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_tcm_1KB_mem1/Do[*] >> mprj.dffram.max.rpt + + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/WE[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/EN >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/Di[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/A[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem0/Do[*] >> mprj.dffram.max.rpt + + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/WE[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/EN >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/Di[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/A[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_icache_1KB_mem1/Do[*] >> mprj.dffram.max.rpt + + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/WE[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/EN >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/Di[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/A[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem0/A[*] >> mprj.dffram.max.rpt + + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/WE[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/EN >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/Di[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/A[*] >> mprj.dffram.max.rpt + report_checks -path_delay max -fields {slew cap input nets fanout} -through mprj/u_dcache_1KB_mem1/Do[*] >> mprj.dffram.max.rpt
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index 711014a..48d5279 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -22,10 +22,6 @@ create_clock -name uarts_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart_core.u_lineclk_buf.u_mux/X}] create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.u_mux/X}] -create_generated_clock -name mem_clk0 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[0].u_mem_sel.u_mem_clk_sel.u_mux/X] -create_generated_clock -name mem_clk1 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[1].u_mem_sel.u_mem_clk_sel.u_mux/X] -create_generated_clock -name mem_clk2 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[2].u_mem_sel.u_mem_clk_sel.u_mux/X] -create_generated_clock -name mem_clk3 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/u_mbist.mem_no[3].u_mem_sel.u_mem_clk_sel.u_mux/X] ## Case analysis @@ -64,10 +60,6 @@ set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}] set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}] -set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[0]}] -set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[1]}] -set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[2]}] -set_case_analysis 1 [get_pins {mprj/u_mbist/cfg_cska_mbist[3]}] #disable clock gating check at static clock select pins
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 4ee38f8..c721d0f 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = wb_port risc_boot user_risc_boot user_uart user_spi user_i2cm riscv_regress user_basic user_mbist_test1 user_risc_soft_boot user_uart_master uart_master +PATTERNS = wb_port risc_boot user_risc_boot user_uart user_spi user_i2cm riscv_regress user_basic user_uart_master uart_master all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/model/spiram.v b/verilog/dv/model/is62wvs1288.v similarity index 99% rename from verilog/dv/model/spiram.v rename to verilog/dv/model/is62wvs1288.v index cd33c11..c938977 100644 --- a/verilog/dv/model/spiram.v +++ b/verilog/dv/model/is62wvs1288.v
@@ -42,7 +42,7 @@ // WRMR 0x01 Write Mode Register // -module spiram #( +module is62wvs1288 #( parameter mem_file_name = "firmware.hex" )( input csb,
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index ca9ee0a..2bc1cfb 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -76,7 +76,7 @@ `include "s25fl256s.sv" `include "uprj_netlists.v" `include "mt48lc8m8a2.v" -`include "spiram.v" +`include "is62wvs1288.v" localparam [31:0] YCR1_SIM_EXIT_ADDR = 32'h0000_00F8; localparam [31:0] YCR1_SIM_PRINT_ADDR = 32'hF000_0000; @@ -418,7 +418,7 @@ wire spiram_csb = io_out[26]; - spiram #(.mem_file_name("none")) + is62wvs1288 #(.mem_file_name("none")) u_sram ( // Data Inputs/Outputs .io0 (flash_io0),
diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile index e1558d4..e9e1108 100644 --- a/verilog/dv/user_basic/Makefile +++ b/verilog/dv/user_basic/Makefile
@@ -61,7 +61,7 @@ %.vvp: %_tb.v ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ -I $(UPRJ_BEHAVIOURAL_AGENTS) \ @@ -69,7 +69,7 @@ -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ $< -o $@ else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ -I $(UPRJ_BEHAVIOURAL_AGENTS) \ @@ -78,7 +78,7 @@ $< -o $@ endif else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ + iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ -I $(UPRJ_BEHAVIOURAL_AGENTS) \
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index 70d9821..8f6d96f 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -242,8 +242,8 @@ wb_user_core_write('h3080_0000,'h1); wb_user_core_read_check(32'h30020058,read_data,32'h8273_8343); - wb_user_core_read_check(32'h3002005C,read_data,32'h1402_2022); - wb_user_core_read_check(32'h30020060,read_data,32'h0003_4000); + wb_user_core_read_check(32'h3002005C,read_data,32'h1602_2022); + wb_user_core_read_check(32'h30020060,read_data,32'h0003_5000); end
diff --git a/verilog/dv/user_mbist_test1/Makefile b/verilog/dv/user_mbist_test1/Makefile deleted file mode 100644 index 685d6ba..0000000 --- a/verilog/dv/user_mbist_test1/Makefile +++ /dev/null
@@ -1,109 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel - - -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include - -## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware -GCC64_PREFIX?=riscv64-unknown-elf - -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A - -## Simulation mode: RTL/GL -SIM?=RTL -DUMP?=OFF - -.SUFFIXES: - -PATTERN = user_mbist_test1 - -all: ${PATTERN:=.vcd} - -vvp: ${PATTERN:=.vvp} - -%.vvp: %_tb.v -ifeq ($(SIM),RTL) - ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ - $< -o $@ - else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ - $< -o $@ - endif -else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - $< -o $@ -endif - -%.vcd: %.vvp - vvp $< | tee sim_result.log - -check-env: -ifndef PDK_ROOT - $(error PDK_ROOT is undefined, please export it before running make) -endif -ifeq (,$(wildcard $(PDK_ROOT)/sky130A)) - $(error $(PDK_ROOT)/sky130A not found, please install pdk before running make) -endif -#ifeq (,$(wildcard $(GCC64_PREFIX)-gcc )) -# $(error $(GCC64_PREFIX)-gcc is not found, please export GCC_PATH and GCC_PREFIX before running make) -#endif -# check for efabless style installation -ifeq (,$(wildcard $(PDK_ROOT)/sky130A/libs.ref/*/verilog)) -SIM_DEFINES := ${SIM_DEFINES} -DEF_STYLE -endif - -# ---- Clean ---- - -clean: - rm -f *.vvp *.vcd *.log - -.PHONY: clean all
diff --git a/verilog/dv/user_mbist_test1/run_iverilog b/verilog/dv/user_mbist_test1/run_iverilog deleted file mode 100755 index e66b863..0000000 --- a/verilog/dv/user_mbist_test1/run_iverilog +++ /dev/null
@@ -1,31 +0,0 @@ -# ////////////////////////////////////////////////////////////////////////////// -# // SPDX-FileCopyrightText: 2021, Dinesh Annayya -# // -# // Licensed under the Apache License, Version 2.0 (the "License"); -# // you may not use this file except in compliance with the License. -# // You may obtain a copy of the License at -# // -# // http://www.apache.org/licenses/LICENSE-2.0 -# // -# // Unless required by applicable law or agreed to in writing, software -# // distributed under the License is distributed on an "AS IS" BASIS, -# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# // See the License for the specific language governing permissions and -# // limitations under the License. -# // SPDX-License-Identifier: Apache-2.0 -# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> -# // ////////////////////////////////////////////////////////////////////////// - -#iverilog without Dump -# -iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I /home/dinesha/workarea/efabless/MPW-3/pdk/sky130A \ --I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/dv/caravel \ --I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/rtl \ --I ../ -I ../../../verilog/rtl \ --I ../../../verilog/rtl/mbist/include \ -user_mbist_test1_tb.v -o user_mbist_test1.vvp - - -vvp user_mbist_test1.vvp | tee test.log - -\rm -rf user_mbist_test1.vvp
diff --git a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v deleted file mode 100644 index c570e18..0000000 --- a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v +++ /dev/null
@@ -1,1139 +0,0 @@ -//////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> -////////////////////////////////////////////////////////////////////// -//// //// -//// Standalone User validation Test bench //// -//// //// -//// //// -//// Description //// -//// This is a standalone test bench to validate the //// -//// Digital core MBIST logic through External WB i/F. //// -//// //// -//// To Do: //// -//// nothing //// -//// //// -//// Author(s): //// -//// - Dinesh Annayya, dinesha@opencores.org //// -//// //// -//// Revision : //// -//// 0.1 - 18 Oct 2021, Dinesh A //// -//// //// -////////////////////////////////////////////////////////////////////// - -`default_nettype wire - -`timescale 1 ns / 1 ns - -`include "uprj_netlists.v" - -`define WB_MAP `30080_0000 -`define GLBL_FUNC_MAP 'h3002_0000 -`define MBIST1_FUNC_MAP 'h3003_0000 // 0x3003_0000 to 0x3003_07FF -`define MBIST2_FUNC_MAP 'h3003_0800 // 0x3003_0800 to 0x3003_0FFF -`define MBIST3_FUNC_MAP 'h3003_1000 // 0x3003_1000 to 0x3003_17FF -`define MBIST4_FUNC_MAP 'h3003_1800 // 0x3003_1800 to 0x3003_1FFF - -`define GLBL_BIST_CTRL1 'h3002_0070 -`define GLBL_BIST_STAT1 'h3002_0074 -`define GLBL_BIST_SWDATA 'h3002_0078 -`define GLBL_BIST_SRDATA 'h3002_007C -`define GLBL_BIST_SPDATA 'h3002_0078 # - -`define WB_GLBL_CTRL 'h3080_0000 - -`define NO_SRAM 4 // 8 - - - -module user_mbist_test1_tb; - reg clock; - reg wb_rst_i; - reg power1, power2; - reg power3, power4; - - reg wbd_ext_cyc_i; // strobe/request - reg wbd_ext_stb_i; // strobe/request - reg [31:0] wbd_ext_adr_i; // address - reg wbd_ext_we_i; // write - reg [31:0] wbd_ext_dat_i; // data output - reg [3:0] wbd_ext_sel_i; // byte enable - - wire [31:0] wbd_ext_dat_o; // data input - wire wbd_ext_ack_o; // acknowlegement - wire wbd_ext_err_o; // error - - // User I/O - wire [37:0] io_oeb; - wire [37:0] io_out; - wire [37:0] io_in; - - wire gpio; - wire [37:0] mprj_io; - wire [7:0] mprj_io_0; - reg test_fail; - reg [31:0] read_data; - reg [31:0] writemem [0:511]; - reg [8:0] faultaddr [0:7]; - integer i; - event error_insert; - - - // External clock is used by default. Make this artificially fast for the - // simulation. Normally this would be a slow clock and the digital PLL - // would be the fast clock. - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - end - - `ifdef WFDUMP - initial begin - $dumpfile("simx.vcd"); - $dumpvars(2, user_mbist_test1_tb); - $dumpvars(0, user_mbist_test1_tb.u_top.u_mbist); - $dumpvars(0, user_mbist_test1_tb.u_top.u_intercon); - $dumpoff; - end - `endif - - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - - #200; // Wait for reset removal - repeat (10) @(posedge clock); - $display("Monitor: Standalone User Test Started"); - - test_fail = 0; - // Remove Wb Reset - wb_user_core_write(`WB_GLBL_CTRL,'h1); - - $dumpoff; - $display("###################################################"); - $display(" MBIST Test with Without Address Failure"); - $display("###################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 0 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h0 - insert_fault(0,0,0,0,0,32'h01010101); - - if(test_fail == 0) begin - $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Failed"); - end - $display("###################################################"); - - $display("#########################################################"); - $display(" MBIST Test with With Single Address Failure for MEM-0"); - $display("#########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(1,0,0,0,0,32'h01010115); - - if(test_fail == 0) begin - $display("Monitor: Step-2.1: BIST Test with Single Address Failure at MEM0 Error insertion test Passed"); - end else begin - $display("Monitor: Step-2.1: BIST Test with Single Address Failure at MEM0 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Single Address Failure for MEM-0/1"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(1,1,0,0,0,32'h01011515); - - if(test_fail == 0) begin - $display("Monitor: Step-2.2: BIST Test with Single Address Failure at MEM0/1 Error insertion test Passed"); - end else begin - $display("Monitor: Step-2.2: BIST Test with Single Address Failure at MEM0/1 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Single Address Failure for MEM-0/1/2"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(1,1,1,0,0,32'h01151515); - - if(test_fail == 0) begin - $display("Monitor: Step-2.3: BIST Test with Single Address Failure at MEM0/1/2 Error insertion test Passed"); - end else begin - $display("Monitor: Step-2.3: BIST Test with Single Address Failure at MEM0/1/2 Error insertion test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Single Address Failure to All Memory"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h1 - //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(1,1,1,1,1,32'h15151515); - - if(test_fail == 0) begin - $display("Monitor: Step-2.4: BIST Test with One Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-2.4: BIST Test with One Memory Error insertion test Failed"); - end - $display("###################################################"); - - $display("#########################################################"); - $display(" MBIST Test with With Two Address Failure for MEM-0"); - $display("#########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h2 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(2,0,0,0,0,32'h01010125); - - if(test_fail == 0) begin - $display("Monitor: Step-3.1: BIST Test with Two Address Failure at MEM0 Error insertion test Passed"); - end else begin - $display("Monitor: Step-3.1: BIST Test with Two Address Failure at MEM0 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Two Address Failure for MEM-0/1"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h2 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(2,2,0,0,0,32'h01012525); - - if(test_fail == 0) begin - $display("Monitor: Step-3.2: BIST Test with Two Address Failure at MEM0/1 Error insertion test Passed"); - end else begin - $display("Monitor: Step-3.2: BIST Test with Two Address Failure at MEM0/1 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Two Address Failure for MEM-0/1/2"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h2 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(2,2,2,0,0,32'h01252525); - - if(test_fail == 0) begin - $display("Monitor: Step-3.3: BIST Test with Two Address Failure at MEM0/1/2 Error insertion test Passed"); - end else begin - $display("Monitor: Step-3.3: BIST Test with Two Address Failure at MEM0/1/2 Error insertion test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Two Address Failure to All Memory"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h2 - //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(2,2,2,2,1,32'h25252525); - - if(test_fail == 0) begin - $display("Monitor: Step-3.4: BIST Test with Two Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-3.4: BIST Test with Two Memory Error insertion test Failed"); - end - $display("###################################################"); - - $display("#########################################################"); - $display(" MBIST Test with With Three Address Failure for MEM-0"); - $display("#########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h3 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(3,0,0,0,0,32'h01010135); - - if(test_fail == 0) begin - $display("Monitor: Step-4.1: BIST Test with Three Address Failure at MEM0 Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.1: BIST Test with Three Address Failure at MEM0 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Three Address Failure for MEM-0/1"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h3 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(3,3,0,0,0,32'h01013535); - - if(test_fail == 0) begin - $display("Monitor: Step-4.2: BIST Test with Three Address Failure at MEM0/1 Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.2: BIST Test with Three Address Failure at MEM0/1 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Three Address Failure for MEM-0/1/2"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h3 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(3,3,3,0,0,32'h01353535); - - if(test_fail == 0) begin - $display("Monitor: Step-4.3: BIST Test with Three Address Failure at MEM0/1/2 Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.3: BIST Test with Three Address Failure at MEM0/1/2 Error insertion test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Three Address Failure to All Memory"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h3 - //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(3,3,3,3,1,32'h35353535); - - if(test_fail == 0) begin - $display("Monitor: Step-4.4: BIST Test with Three Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.4: BIST Test with Three Memory Error insertion test Failed"); - end - $display("###################################################"); - - $display("#########################################################"); - $display(" MBIST Test with With Four Address Failure for MEM-0"); - $display("#########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(4,0,0,0,0,32'h01010145); - - if(test_fail == 0) begin - $display("Monitor: Step-4.1: BIST Test with Four Address Failure at MEM0 Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.1: BIST Test with Four Address Failure at MEM0 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Four Address Failure for MEM-0/1"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(4,4,0,0,0,32'h01014545); - - if(test_fail == 0) begin - $display("Monitor: Step-4.2: BIST Test with Four Address Failure at MEM0/1 Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.2: BIST Test with Four Address Failure at MEM0/1 Error insertion test Failed"); - end - $display("##########################################################"); - $display(" MBIST Test with With Four Address Failure for MEM-0/1/2"); - $display("##########################################################"); - - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h3 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(4,4,4,0,0,32'h01454545); - - if(test_fail == 0) begin - $display("Monitor: Step-4.3: BIST Test with Four Address Failure at MEM0/1/2 Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.3: BIST Test with Four Address Failure at MEM0/1/2 Error insertion test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Four Address Failure to All Memory"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h3 - //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - insert_fault(4,4,4,4,1,32'h45454545); - - if(test_fail == 0) begin - $display("Monitor: Step-4.4: BIST Test with Four Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-4.4: BIST Test with Four Memory Error insertion test Failed"); - end - $display("###################################################"); - - - $display("###################################################"); - $display(" MBIST Test with Fours Address(Continous Starting Addrsess) Failure"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 - faultaddr[0] = 9'h0; - faultaddr[1] = 9'h1; - faultaddr[2] = 9'h2; - faultaddr[3] = 9'h3; - insert_fault(4,4,4,4,0,32'h45454545); - - if(test_fail == 0) begin - $display("Monitor: Step-5.1: BIST Test with Four Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-5.1: BIST Test with Four Memory Error insertion test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Fours Address(Last Addrsess) Failure"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 0 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 - faultaddr[0] = 9'hF0; - faultaddr[1] = 9'hF1; - faultaddr[2] = 9'hF2; - faultaddr[3] = 9'hF3; - insert_fault(4,4,4,4,0,32'h45454545); - - if(test_fail == 0) begin - $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Five Address Failure for MEM0"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 1 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - faultaddr[4] = 9'h50; - insert_fault(5,0,0,0,1,32'h01010147); - - if(test_fail == 0) begin - $display("Monitor: Step-6.1: BIST Test with Five Memory Error insertion for MEM0 test Passed"); - end else begin - $display("Monitor: Step-6.1: BIST Test with Five Memory Error insertion for MEM0 test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Five Address Failure for MEM0/1"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 1 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - faultaddr[4] = 9'h50; - insert_fault(5,5,0,0,1,32'h01014747); - - if(test_fail == 0) begin - $display("Monitor: Step-6.2: BIST Test with Five Memory Error insertion for MEM0/1 test Passed"); - end else begin - $display("Monitor: Step-6.2: BIST Test with Five Memory Error insertion for MEM0/1 test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Five Address Failure for MEM0/1/2"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 1 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - faultaddr[4] = 9'h50; - insert_fault(5,5,5,0,1,32'h01474747); - - if(test_fail == 0) begin - $display("Monitor: Step-6.3: BIST Test with Five Memory Error insertion for MEM0/1/2 test Passed"); - end else begin - $display("Monitor: Step-6.3: BIST Test with Five Memory Error insertion for MEM0/1/2 test Failed"); - end - - $display("###################################################"); - $display(" MBIST Test with Five Address Failure for All Memory"); - $display("###################################################"); - // Check Is there is any BIST Error - // [0] - Bist Done - 1 - // [1] - Bist Error - 1 - // [2] - Bist Correct - 1 - // [3] - Reserved - 0 - // [7:4] - Bist Error Cnt - 4'h4 - //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 - faultaddr[0] = 9'h10; - faultaddr[1] = 9'h20; - faultaddr[2] = 9'h30; - faultaddr[3] = 9'h40; - faultaddr[4] = 9'h50; - insert_fault(5,5,5,5,1,32'h47474747); - - if(test_fail == 0) begin - $display("Monitor: Step-6.4: BIST Test with Five Memory Error insertion test Passed"); - end else begin - $display("Monitor: Step-6.4: BIST Test with Five Memory Error insertion test Failed"); - end - $dumpon; - $display("###################################################"); - $display(" MBIST Test with Functional Access, continuation of previous MBIST Signature"); - $display("###################################################"); - fork - begin - // Remove the Bist Enable and Bist Run - wb_user_core_write(`GLBL_BIST_CTRL1,'h000); - // Remove WB and BIST RESET - wb_user_core_write(`WB_GLBL_CTRL,'h081); - - // Fill Random Data - for (i=0; i< 9'h1FC; i=i+1) begin - writemem[i] = $random; - wb_user_core_write(`MBIST1_FUNC_MAP+(i*4),writemem[i]); - wb_user_core_write(`MBIST2_FUNC_MAP+(i*4),writemem[i]); - wb_user_core_write(`MBIST3_FUNC_MAP+(i*4),writemem[i]); - wb_user_core_write(`MBIST4_FUNC_MAP+(i*4),writemem[i]); - //if(i < 9'h0FC) begin // SRAM5-SRAM8 are 1KB - // wb_user_core_write(`MBIST5_FUNC_MAP+(i*4),writemem[i]); - // wb_user_core_write(`MBIST6_FUNC_MAP+(i*4),writemem[i]); - // wb_user_core_write(`MBIST7_FUNC_MAP+(i*4),writemem[i]); - // wb_user_core_write(`MBIST8_FUNC_MAP+(i*4),writemem[i]); - //end - end - // Read back data - for (i=0; i< 9'h1FC; i=i+1) begin - wb_user_core_read_check(`MBIST1_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST2_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST3_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST4_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - //if(i < 9'h0FC) begin // SRAM5 - SRAM8 are 1KB - // wb_user_core_read_check(`MBIST5_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - // wb_user_core_read_check(`MBIST6_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - // wb_user_core_read_check(`MBIST7_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - // wb_user_core_read_check(`MBIST8_FUNC_MAP+(i*4),read_data,writemem[i],32'hFFFFFFFF); - //end - end - - // Cross-check Reducency address hold the failure address data - // Is last Error inserted address are 0x10,0x20,0x30,0x40 - // So Address 0x1FC = Data[0x10], 0x1FD = Data[0x20] - // Address 0x1FE = Data[0x30], 0x1FF = Data[0x40] - // Check 2kb SRAM1 - wb_user_core_read_check(`MBIST1_FUNC_MAP + (9'h1FC *4),read_data,writemem[9'h10],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST1_FUNC_MAP + (9'h1FD *4),read_data,writemem[9'h20],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST1_FUNC_MAP + (9'h1FE *4),read_data,writemem[9'h30],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST1_FUNC_MAP + (9'h1FF *4),read_data,writemem[9'h40],32'hFFFFFFFF); - - // Check 2kb SRAM2 - wb_user_core_read_check(`MBIST2_FUNC_MAP + (9'h1FC *4),read_data,writemem[9'h11],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST2_FUNC_MAP + (9'h1FD *4),read_data,writemem[9'h21],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST2_FUNC_MAP + (9'h1FE *4),read_data,writemem[9'h31],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST2_FUNC_MAP + (9'h1FF *4),read_data,writemem[9'h41],32'hFFFFFFFF); - - //// Check 2kb SRAM3 - wb_user_core_read_check(`MBIST3_FUNC_MAP + (9'h1FC *4),read_data,writemem[9'h12],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST3_FUNC_MAP + (9'h1FD *4),read_data,writemem[9'h22],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST3_FUNC_MAP + (9'h1FE *4),read_data,writemem[9'h32],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST3_FUNC_MAP + (9'h1FF *4),read_data,writemem[9'h42],32'hFFFFFFFF); - - //// Check 2kb SRAM4 - wb_user_core_read_check(`MBIST4_FUNC_MAP + (9'h1FC *4),read_data,writemem[9'h13],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST4_FUNC_MAP + (9'h1FD *4),read_data,writemem[9'h23],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST4_FUNC_MAP + (9'h1FE *4),read_data,writemem[9'h33],32'hFFFFFFFF); - wb_user_core_read_check(`MBIST4_FUNC_MAP + (9'h1FF *4),read_data,writemem[9'h43],32'hFFFFFFFF); - - //// Check 1kb SRAM5 - //wb_user_core_read_check(`MBIST5_FUNC_MAP + (8'hFC *4),read_data,writemem[9'h14],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST5_FUNC_MAP + (8'hFD *4),read_data,writemem[9'h24],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST5_FUNC_MAP + (8'hFE *4),read_data,writemem[9'h34],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST5_FUNC_MAP + (8'hFF *4),read_data,writemem[9'h44],32'hFFFFFFFF); - - //// Check 1kb SRAM6 - //wb_user_core_read_check(`MBIST6_FUNC_MAP + (8'hFC *4),read_data,writemem[9'h15],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST6_FUNC_MAP + (8'hFD *4),read_data,writemem[9'h25],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST6_FUNC_MAP + (8'hFE *4),read_data,writemem[9'h35],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST6_FUNC_MAP + (8'hFF *4),read_data,writemem[9'h45],32'hFFFFFFFF); - - //// Check 1kb SRAM7 - //wb_user_core_read_check(`MBIST7_FUNC_MAP + (8'hFC *4),read_data,writemem[9'h16],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST7_FUNC_MAP + (8'hFD *4),read_data,writemem[9'h26],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST7_FUNC_MAP + (8'hFE *4),read_data,writemem[9'h36],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST7_FUNC_MAP + (8'hFF *4),read_data,writemem[9'h46],32'hFFFFFFFF); - - //// Check 1kb SRAM8 - //wb_user_core_read_check(`MBIST8_FUNC_MAP + (8'hFC *4),read_data,writemem[9'h17],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST8_FUNC_MAP + (8'hFD *4),read_data,writemem[9'h27],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST8_FUNC_MAP + (8'hFE *4),read_data,writemem[9'h37],32'hFFFFFFFF); - //wb_user_core_read_check(`MBIST8_FUNC_MAP + (8'hFF *4),read_data,writemem[9'h47],32'hFFFFFFFF); - end - begin - // Loop for BIST TimeOut - repeat (200000) @(posedge clock); - // $display("+1000 cycles"); - test_fail = 1; - end - join_any - disable fork; //disable pending fork activity - if(test_fail == 0) begin - $display("Monitor: Step-7: BIST Test with Functional access test Passed"); - end else begin - $display("Monitor: Step-7: BIST Test with Functional access test failed"); - end - - $display("###################################################"); - $finish; - end - -wire USER_VDD1V8 = 1'b1; -wire VSS = 1'b0; - - -user_project_wrapper u_top( -`ifdef USE_POWER_PINS - .vccd1(USER_VDD1V8), // User area 1 1.8V supply - .vssd1(VSS), // User area 1 digital ground -`endif - .wb_clk_i (clock), // System clock - .user_clock2 (1'b1), // Real-time clock - .wb_rst_i (wb_rst_i), // Regular Reset signal - - .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request - .wbs_stb_i (wbd_ext_stb_i), // strobe/request - .wbs_adr_i (wbd_ext_adr_i), // address - .wbs_we_i (wbd_ext_we_i), // write - .wbs_dat_i (wbd_ext_dat_i), // data output - .wbs_sel_i (wbd_ext_sel_i), // byte enable - - .wbs_dat_o (wbd_ext_dat_o), // data input - .wbs_ack_o (wbd_ext_ack_o), // acknowlegement - - - // Logic Analyzer Signals - .la_data_in ('1) , - .la_data_out (), - .la_oenb ('0), - - - // IOs - .io_in (io_in) , - .io_out (io_out) , - .io_oeb (io_oeb) , - - .user_irq () - -); - -`ifndef GL // Drive Power for Hold Fix Buf - // All standard cell need power hook-up for functionality work - initial begin - - - end -`endif - - -//------------------------------------- -// Insert user defined number of fault -// ----------------------------------- - -task insert_fault; -input [3:0] num0_fault; -input [3:0] num1_fault; -input [3:0] num2_fault; -input [3:0] num3_fault; -input fault_type; // 0 -> struck at 0 and 1 -> struck at 1 -input [31:0] mbist_signature; -reg [31:0] datain; -reg [8:0] fail_addr1; -reg [8:0] fail_addr2; -reg [8:0] fail_addr3; -reg [8:0] fail_addr4; -reg [3:0] num_fault[0:3]; -integer j; -begin - num_fault[0] = num0_fault; - num_fault[1] = num1_fault; - num_fault[2] = num2_fault; - num_fault[3] = num3_fault; - repeat (2) @(posedge clock); - fork - begin - // Remove the Bist Enable and Bist Run - wb_user_core_write(`GLBL_BIST_CTRL1,'h000); - // Remove WB and BIST RESET - wb_user_core_write(`WB_GLBL_CTRL,'h001); - // Set the Bist Enable and Bist Run - wb_user_core_write(`GLBL_BIST_CTRL1,'h00000003); - // Remove WB and BIST RESET - wb_user_core_write(`WB_GLBL_CTRL,'h081); - // Check for MBIST Done - read_data = 'h0; - while (read_data[0] != 1'b1) begin - wb_user_core_read(`GLBL_BIST_STAT1,read_data); - end - // wait for some time for all the BIST to complete - repeat (1000) @(posedge clock); - // Toggle the Bist Load for update the shift data - wb_user_core_write(`GLBL_BIST_CTRL1,'h00000004); - wb_user_core_write(`GLBL_BIST_CTRL1,'h00000000); - // Check Is there is any BIST Error - // [0] - Bist Done - // [1] - Bist Error - // [2] - Bist Correct - // [3] - Reserved - // [7:4] - Bist Error Cnt - wb_user_core_read_check(`GLBL_BIST_STAT1,read_data,mbist_signature[31:0],32'hFFFFFFFF); - //wb_user_core_read_check(`GLBL_BIST_STAT2,read_data,mbist_signature[63:32],32'hFFFFFFFF); - end - // Insert Error Insertion - begin - while(1) begin - repeat (1) @(posedge clock); - #1; - - if(u_top.u_sram0_2kb.web0 == 1'b0 && - ((num_fault[0] > 0 && u_top.u_sram0_2kb.addr0 == faultaddr[0]) || - (num_fault[0] > 1 && u_top.u_sram0_2kb.addr0 == faultaddr[1]) || - (num_fault[0] > 2 && u_top.u_sram0_2kb.addr0 == faultaddr[2]) || - (num_fault[0] > 3 && u_top.u_sram0_2kb.addr0 == faultaddr[3]) || - (num_fault[0] > 4 && u_top.u_sram0_2kb.addr0 == faultaddr[4]) || - (num_fault[0] > 5 && u_top.u_sram0_2kb.addr0 == faultaddr[5]) || - (num_fault[0] > 6 && u_top.u_sram0_2kb.addr0 == faultaddr[6]) || - (num_fault[0] > 7 && u_top.u_sram0_2kb.addr0 == faultaddr[7]))) - begin - if(fault_type == 0) // Struck at 0 - force u_top.u_sram0_2kb.din0 = u_top.mem0_din_a & 32'hFFFF_FFFE; - else - force u_top.u_sram0_2kb.din0 = u_top.mem0_din_a | 32'h1; - -> error_insert; - end else begin - release u_top.u_sram0_2kb.din0; - end - - if(u_top.u_sram1_2kb.web0 == 1'b0 && - ((num_fault[1] > 0 && u_top.u_sram1_2kb.addr0 == faultaddr[0]+1) || - (num_fault[1] > 1 && u_top.u_sram1_2kb.addr0 == faultaddr[1]+1) || - (num_fault[1] > 2 && u_top.u_sram1_2kb.addr0 == faultaddr[2]+1) || - (num_fault[1] > 3 && u_top.u_sram1_2kb.addr0 == faultaddr[3]+1) || - (num_fault[1] > 4 && u_top.u_sram1_2kb.addr0 == faultaddr[4]+1) || - (num_fault[1] > 5 && u_top.u_sram1_2kb.addr0 == faultaddr[5]+1) || - (num_fault[1] > 6 && u_top.u_sram1_2kb.addr0 == faultaddr[6]+1) || - (num_fault[1] > 7 && u_top.u_sram1_2kb.addr0 == faultaddr[7]+1))) - begin - if(fault_type == 0) // Struck at 0 - force u_top.u_sram1_2kb.din0 = u_top.mem1_din_a & 32'hFFFF_FFFE; - else - force u_top.u_sram1_2kb.din0 = u_top.mem1_din_a | 32'h1; - -> error_insert; - end else begin - release u_top.u_sram1_2kb.din0; - end - - if(u_top.u_sram2_2kb.web0 == 1'b0 && - ((num_fault[2] > 0 && u_top.u_sram2_2kb.addr0 == faultaddr[0]+2) || - (num_fault[2] > 1 && u_top.u_sram2_2kb.addr0 == faultaddr[1]+2) || - (num_fault[2] > 2 && u_top.u_sram2_2kb.addr0 == faultaddr[2]+2) || - (num_fault[2] > 3 && u_top.u_sram2_2kb.addr0 == faultaddr[3]+2) || - (num_fault[2] > 4 && u_top.u_sram2_2kb.addr0 == faultaddr[4]+2) || - (num_fault[2] > 5 && u_top.u_sram2_2kb.addr0 == faultaddr[5]+2) || - (num_fault[2] > 6 && u_top.u_sram2_2kb.addr0 == faultaddr[6]+2) || - (num_fault[2] > 7 && u_top.u_sram2_2kb.addr0 == faultaddr[7]+2))) - begin - if(fault_type == 0) // Struck at 0 - force u_top.u_sram2_2kb.din0 = u_top.mem2_din_a & 32'hFFFF_FFFE; - else - force u_top.u_sram2_2kb.din0 = u_top.mem2_din_a | 32'h1; - -> error_insert; - end else begin - release u_top.u_sram2_2kb.din0; - end - - if(u_top.u_sram3_2kb.web0 == 1'b0 && - ((num_fault[3] > 0 && u_top.u_sram3_2kb.addr0 == faultaddr[0]+3) || - (num_fault[3] > 1 && u_top.u_sram3_2kb.addr0 == faultaddr[1]+3) || - (num_fault[3] > 2 && u_top.u_sram3_2kb.addr0 == faultaddr[2]+3) || - (num_fault[3] > 3 && u_top.u_sram3_2kb.addr0 == faultaddr[3]+3) || - (num_fault[3] > 4 && u_top.u_sram3_2kb.addr0 == faultaddr[4]+3) || - (num_fault[3] > 5 && u_top.u_sram3_2kb.addr0 == faultaddr[5]+3) || - (num_fault[3] > 6 && u_top.u_sram3_2kb.addr0 == faultaddr[6]+3) || - (num_fault[3] > 7 && u_top.u_sram3_2kb.addr0 == faultaddr[7]+3))) - begin - if(fault_type == 0) // Struck at 0 - force u_top.u_sram3_2kb.din0 = u_top.mem3_din_a & 32'hFFFF_FFFE; - else - force u_top.u_sram3_2kb.din0 = u_top.mem3_din_a | 32'h1; - -> error_insert; - end else begin - release u_top.u_sram3_2kb.din0; - end - - //if(u_top.u_sram5_1kb.web0 == 1'b0 && - // ((num_fault > 0 && u_top.u_sram5_1kb.addr0 == faultaddr[0]+4) || - // (num_fault > 1 && u_top.u_sram5_1kb.addr0 == faultaddr[1]+4) || - // (num_fault > 2 && u_top.u_sram5_1kb.addr0 == faultaddr[2]+4) || - // (num_fault > 3 && u_top.u_sram5_1kb.addr0 == faultaddr[3]+4) || - // (num_fault > 4 && u_top.u_sram5_1kb.addr0 == faultaddr[4]+4) || - // (num_fault > 5 && u_top.u_sram5_1kb.addr0 == faultaddr[5]+4) || - // (num_fault > 6 && u_top.u_sram5_1kb.addr0 == faultaddr[6]+4) || - // (num_fault > 7 && u_top.u_sram5_1kb.addr0 == faultaddr[7]+4))) - // begin - // if(fault_type == 0) // Struck at 0 - // force u_top.u_sram5_1kb.din0 = u_top.mem5_din_b & 32'hFFFF_FFFE; - // else - // force u_top.u_sram5_1kb.din0 = u_top.mem5_din_b | 32'h1; - // -> error_insert; - //end else begin - // release u_top.u_sram5_1kb.din0; - //end - - //if(u_top.u_sram6_1kb.web0 == 1'b0 && - // ((num_fault > 0 && u_top.u_sram6_1kb.addr0 == faultaddr[0]+5) || - // (num_fault > 1 && u_top.u_sram6_1kb.addr0 == faultaddr[1]+5) || - // (num_fault > 2 && u_top.u_sram6_1kb.addr0 == faultaddr[2]+5) || - // (num_fault > 3 && u_top.u_sram6_1kb.addr0 == faultaddr[3]+5) || - // (num_fault > 4 && u_top.u_sram6_1kb.addr0 == faultaddr[4]+5) || - // (num_fault > 5 && u_top.u_sram6_1kb.addr0 == faultaddr[5]+5) || - // (num_fault > 6 && u_top.u_sram6_1kb.addr0 == faultaddr[6]+5) || - // (num_fault > 7 && u_top.u_sram6_1kb.addr0 == faultaddr[7]+5))) - // begin - // if(fault_type == 0) // Struck at 0 - // force u_top.u_sram6_1kb.din0 = u_top.mem6_din_b & 32'hFFFF_FFFE; - // else - // force u_top.u_sram6_1kb.din0 = u_top.mem6_din_b | 32'h1; - // -> error_insert; - //end else begin - // release u_top.u_sram6_1kb.din0; - //end - - //if(u_top.u_sram7_1kb.web0 == 1'b0 && - // ((num_fault > 0 && u_top.u_sram7_1kb.addr0 == faultaddr[0]+6) || - // (num_fault > 1 && u_top.u_sram7_1kb.addr0 == faultaddr[1]+6) || - // (num_fault > 2 && u_top.u_sram7_1kb.addr0 == faultaddr[2]+6) || - // (num_fault > 3 && u_top.u_sram7_1kb.addr0 == faultaddr[3]+6) || - // (num_fault > 4 && u_top.u_sram7_1kb.addr0 == faultaddr[4]+6) || - // (num_fault > 5 && u_top.u_sram7_1kb.addr0 == faultaddr[5]+6) || - // (num_fault > 6 && u_top.u_sram7_1kb.addr0 == faultaddr[6]+6) || - // (num_fault > 7 && u_top.u_sram7_1kb.addr0 == faultaddr[7]+6))) - // begin - // if(fault_type == 0) // Struck at 0 - // force u_top.u_sram7_1kb.din0 = u_top.mem7_din_b & 32'hFFFF_FFFE; - // else - // force u_top.u_sram7_1kb.din0 = u_top.mem7_din_b | 32'h1; - // -> error_insert; - //end else begin - // release u_top.u_sram7_1kb.din0; - //end - - //if(u_top.u_sram8_1kb.web0 == 1'b0 && - // ((num_fault > 0 && u_top.u_sram8_1kb.addr0 == faultaddr[0]+7) || - // (num_fault > 1 && u_top.u_sram8_1kb.addr0 == faultaddr[1]+7) || - // (num_fault > 2 && u_top.u_sram8_1kb.addr0 == faultaddr[2]+7) || - // (num_fault > 3 && u_top.u_sram8_1kb.addr0 == faultaddr[3]+7) || - // (num_fault > 4 && u_top.u_sram8_1kb.addr0 == faultaddr[4]+7) || - // (num_fault > 5 && u_top.u_sram8_1kb.addr0 == faultaddr[5]+7) || - // (num_fault > 6 && u_top.u_sram8_1kb.addr0 == faultaddr[6]+7) || - // (num_fault > 7 && u_top.u_sram8_1kb.addr0 == faultaddr[7]+7))) - // begin - // if(fault_type == 0) // Struck at 0 - // force u_top.u_sram8_1kb.din0 = u_top.mem8_din_b & 32'hFFFF_FFFE; - // else - // force u_top.u_sram8_1kb.din0 = u_top.mem8_din_b | 32'h1; - // -> error_insert; - //end else begin - // release u_top.u_sram8_1kb.din0; - //end - - end - end - begin - // Loop for BIST TimeOut - repeat (200000) @(posedge clock); - // $display("+1000 cycles"); - test_fail = 1; - end - join_any - disable fork; //disable pending fork activity - - // Read Back the Failure Address and cross-check all the 8 MBIST - // Read Signature is comming is reverse order, MBIST4 => MBIST3 => MBIST2 - for(j=`NO_SRAM; j > 0; j=j-1) begin - fail_addr1 = faultaddr[0]+j-1; - fail_addr2 = faultaddr[1]+j-1; - fail_addr3 = faultaddr[2]+j-1; - fail_addr4 = faultaddr[3]+j-1; - - if(num_fault[j-1] == 1) begin - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{32'h0},32'hFFFF_FFFF); - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr1,16'h0},32'hFFFF_FFFF); - end else if(num_fault[j-1] == 2) begin - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{32'h0},32'hFFFF_FFFF); - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr1,7'h0,fail_addr2},32'hFFFF_FFFF); - end else if(num_fault[j-1] == 3) begin - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr3,16'h0},32'hFFFF_FFFF); - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr1,7'h0,fail_addr2},32'hFFFF_FFFF); - end else if(num_fault[j-1] >= 4) begin - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr3,7'h0,fail_addr4},32'hFFFF_FFFF); - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr1,7'h0,fail_addr2},32'hFFFF_FFFF); - end else begin - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,32'h0,32'hFFFF_FFFF); - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,32'h0,32'hFFFF_FFFF); - end - end -end -endtask - - -task wb_user_core_write; -input [31:0] address; -input [31:0] data; -begin - repeat (1) @(posedge clock); - #1; - wbd_ext_adr_i =address; // address - wbd_ext_we_i ='h1; // write - wbd_ext_dat_i =data; // data output - wbd_ext_sel_i ='hF; // byte enable - wbd_ext_cyc_i ='h1; // strobe/request - wbd_ext_stb_i ='h1; // strobe/request - wait(wbd_ext_ack_o == 1); - repeat (1) @(posedge clock); - #1; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data); - repeat (2) @(posedge clock); -end -endtask - -task wb_user_core_read; -input [31:0] address; -output [31:0] data; -reg [31:0] data; -begin - repeat (1) @(posedge clock); - #1; - wbd_ext_adr_i =address; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='0; // data output - wbd_ext_sel_i ='hF; // byte enable - wbd_ext_cyc_i ='h1; // strobe/request - wbd_ext_stb_i ='h1; // strobe/request - wait(wbd_ext_ack_o == 1); - #1; - data = wbd_ext_dat_o; - repeat (1) @(posedge clock); - #1; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - //$display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); - repeat (2) @(posedge clock); -end -endtask - -task wb_user_core_read_check; -input [31:0] address; -output [31:0] data; -input [31:0] cmp_data; -input [31:0] cmp_mask; -reg [31:0] data; -begin - repeat (1) @(posedge clock); - #1; - wbd_ext_adr_i =address; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='0; // data output - wbd_ext_sel_i ='hF; // byte enable - wbd_ext_cyc_i ='h1; // strobe/request - wbd_ext_stb_i ='h1; // strobe/request - wait(wbd_ext_ack_o == 1); - #1; - data = wbd_ext_dat_o; - repeat (1) @(posedge clock); - #1; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - if((data & cmp_mask) !== (cmp_data & cmp_mask) ) begin - $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,(cmp_data & cmp_mask),(data & cmp_mask)); - test_fail = 1; - end else begin - $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,(data & cmp_mask)); - end - repeat (2) @(posedge clock); -end -endtask - - -endmodule -`default_nettype wire
diff --git a/verilog/dv/user_risc_soft_boot/Makefile b/verilog/dv/user_risc_soft_boot/Makefile deleted file mode 100644 index 12f65be..0000000 --- a/verilog/dv/user_risc_soft_boot/Makefile +++ /dev/null
@@ -1,111 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# SPDX-License-Identifier: Apache-2.0 - -## Caravel Pointers -CARAVEL_ROOT ?= ../../../caravel -CARAVEL_PATH ?= $(CARAVEL_ROOT) -CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel -CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog -CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl -CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel - - -## User Project Pointers -UPRJ_VERILOG_PATH ?= ../../../verilog -UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl -UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl -UPRJ_BEHAVIOURAL_MODELS = ../model -UPRJ_BEHAVIOURAL_AGENTS = ../agents -UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes -UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs -UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes -UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes -UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include - -## YIFIVE FIRMWARE -YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware -GCC64_PREFIX?=riscv64-unknown-elf - -## RISCV GCC -GCC_PATH?=/ef/apps/bin -GCC32_PREFIX?=riscv32-unknown-elf -PDK_PATH?=/ef/tech/SW/sky130A - -## Simulation mode: RTL/GL -SIM?=RTL -DUMP?=OFF - -.SUFFIXES: - -PATTERN = user_risc_soft_boot - -all: ${PATTERN:=.vcd} - -hex: ${PATTERN:=.hex} - -vvp: ${PATTERN:=.vvp} - -%.vvp: %_tb.v - ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I$(YIFIVE_FIRMWARE_PATH) user_risc_boot.c -o user_risc_boot.o - ${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH) $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o - ${GCC64_PREFIX}-gcc -o user_risc_boot.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_risc_boot.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N - ${GCC64_PREFIX}-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex - ${GCC64_PREFIX}-objdump -D user_risc_boot.elf > user_risc_boot.dump - rm crt.o user_risc_boot.o -ifeq ($(SIM),RTL) - ifeq ($(DUMP),OFF) - iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ - $< -o $@ - else - iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - -I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \ - -I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \ - $< -o $@ - endif -else - iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \ - -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_AGENTS) \ - $< -o $@ -endif - -%.vcd: %.vvp - vvp $< - -%.elf: %.c $(CARAVEL_FIRMWARE_PATH)/sections.lds $(CARAVEL_FIRMWARE_PATH)/start.s - ${GCC64_PREFIX}-gcc -I $(CARAVEL_PATH) -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(CARAVEL_FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(CARAVEL_FIRMWARE_PATH)/start.s $< - -%.hex: - echo @"This is user boot test, noting to compile the mangment core code" - -%.bin: %.elf - ${GCC64_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ - -# ---- Clean ---- - -clean: - rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump - -.PHONY: clean hex all
diff --git a/verilog/dv/user_risc_soft_boot/run_iverilog b/verilog/dv/user_risc_soft_boot/run_iverilog deleted file mode 100755 index 56414f8..0000000 --- a/verilog/dv/user_risc_soft_boot/run_iverilog +++ /dev/null
@@ -1,49 +0,0 @@ -# ////////////////////////////////////////////////////////////////////////////// -# // SPDX-FileCopyrightText: 2021, Dinesh Annayya -# // -# // Licensed under the Apache License, Version 2.0 (the "License"); -# // you may not use this file except in compliance with the License. -# // You may obtain a copy of the License at -# // -# // http://www.apache.org/licenses/LICENSE-2.0 -# // -# // Unless required by applicable law or agreed to in writing, software -# // distributed under the License is distributed on an "AS IS" BASIS, -# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# // See the License for the specific language governing permissions and -# // limitations under the License. -# // SPDX-License-Identifier: Apache-2.0 -# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> -# // ////////////////////////////////////////////////////////////////////////// - -riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_risc_boot.c -o user_risc_boot.o - -riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o - -riscv64-unknown-elf-gcc -o user_risc_boot.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_risc_boot.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 - -riscv64-unknown-elf-objcopy -O verilog user_risc_boot.elf user_risc_boot.hex - -riscv64-unknown-elf-objdump -D user_risc_boot.elf > user_risc_boot.dump - -rm crt_tcm.o user_risc_boot.o - -#iverilog with waveform dump - -iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH \ --I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/dv/caravel -I /home/dinesha/workarea/opencore/git/riscduino/caravel/verilog/rtl \ --I ../model -I ../../../verilog/rtl -I ../../../verilog \ --I ../agents \ --I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I ../../../verilog/rtl/i2cm/src/includes \ --I ../../../verilog/rtl/usb1_host/src/includes -I ../../../verilog/rtl/mbist/include \ -user_risc_soft_boot_tb.v -o user_risc_soft_boot.vvp - - -#iverilog -g2005-sv -I $PDK_PATH -DFUNCTIONAL -DSIM -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_risc_boot_tb.v -o user_risc_boot_tb.vvp - -# GLS -#iverilog -g2005-sv -DGL -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_risc_boot_tb.vvp - -vvp user_risc_soft_boot.vvp | tee test.log - -\rm -rf user_risc_soft_boot.vvp
diff --git a/verilog/dv/user_risc_soft_boot/user_risc_boot.c b/verilog/dv/user_risc_soft_boot/user_risc_boot.c deleted file mode 100644 index 37e424b..0000000 --- a/verilog/dv/user_risc_soft_boot/user_risc_boot.c +++ /dev/null
@@ -1,73 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021, Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> -// ////////////////////////////////////////////////////////////////////////// -#define SC_SIM_OUTPORT (0xf0000000) -#define uint32_t long - -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) -#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018) -#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C) -#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020) -#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024) -#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028) -#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C) -#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030) -#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034) -#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038) -#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C) -#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040) -#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044) -#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048) -#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C) -#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050) -#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054) -#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058) -#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C) -#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060) -#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064) -#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068) -#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C) - -int main() -{ - - //volatile long *out_ptr = (volatile long*)SC_SIM_OUTPORT; - //*out_ptr = 0xAABBCCDD; - //*out_ptr = 0xBBCCDDEE; - //*out_ptr = 0xCCDDEEFF; - //*out_ptr = 0xDDEEFF00; - - // Write software Write & Read Register - reg_mprj_globl_reg22 = 0x11223344; - reg_mprj_globl_reg23 = 0x22334455; - reg_mprj_globl_reg24 = 0x33445566; - reg_mprj_globl_reg25 = 0x44556677; - reg_mprj_globl_reg26 = 0x55667788; - reg_mprj_globl_reg27 = 0x66778899; - //reg_mprj_globl_reg12 = 0x778899AA; - //reg_mprj_globl_reg13 = 0x8899AABB; - //reg_mprj_globl_reg14 = 0x99AABBCC; - //reg_mprj_globl_reg15 = 0xAABBCCDD; - - while(1) {} - return 0; -}
diff --git a/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v b/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v deleted file mode 100644 index 32a28b8..0000000 --- a/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v +++ /dev/null
@@ -1,407 +0,0 @@ -//////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> -////////////////////////////////////////////////////////////////////// -//// //// -//// Standalone User validation Test bench //// -//// //// -//// This file is part of the YIFive cores project //// -//// https://github.com/dineshannayya/yifive_r0.git //// -//// http://www.opencores.org/cores/yifive/ //// -//// //// -//// Description //// -//// This is a standalone test bench to validate the //// -//// Digital core. //// -//// 1. User Risc core is booted using compiled code of //// -//// user_risc_boot.c //// -//// 2. User Risc core uses Serial Flash and SDRAM to boot //// -//// 3. After successful boot, Risc core will write signature //// -//// in to user register from 0x1003_0058 to 0x1003_006C //// -//// 4. Through the External Wishbone Interface we read back //// -//// from 0x3003_0058 to 0x3003_006C //// -//// and validate the user register to declared pass fail //// -//// //// -//// To Do: //// -//// nothing //// -//// //// -//// Author(s): //// -//// - Dinesh Annayya, dinesha@opencores.org //// -//// //// -//// Revision : //// -//// 0.1 - 16th Feb 2021, Dinesh A //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2000 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// - -`default_nettype wire - -`timescale 1 ns / 1 ns - -`include "uprj_netlists.v" - -module user_risc_soft_boot_tb; - reg clock; - reg wb_rst_i; - reg power1, power2; - reg power3, power4; - - reg wbd_ext_cyc_i; // strobe/request - reg wbd_ext_stb_i; // strobe/request - reg [31:0] wbd_ext_adr_i; // address - reg wbd_ext_we_i; // write - reg [31:0] wbd_ext_dat_i; // data output - reg [3:0] wbd_ext_sel_i; // byte enable - - wire [31:0] wbd_ext_dat_o; // data input - wire wbd_ext_ack_o; // acknowlegement - wire wbd_ext_err_o; // error - - // User I/O - wire [37:0] io_oeb; - wire [37:0] io_out; - wire [37:0] io_in; - - wire gpio; - wire [37:0] mprj_io; - wire [7:0] mprj_io_0; - reg test_fail; - reg [31:0] read_data; - logic [7:0] tem_mem[0:4095]; - logic [31:0] tem_mem_32b[0:511]; - - `ifdef VERILATOR - logic [255:0] test_ram_file; - `else // VERILATOR - - string test_ram_file; - - `endif // VERILATOR - - integer i; - - - // External clock is used by default. Make this artificially fast for the - // simulation. Normally this would be a slow clock and the digital PLL - // would be the fast clock. - - always #12.5 clock <= (clock === 1'b0); - - initial begin - clock = 0; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - end - - `ifdef WFDUMP - initial begin - $dumpfile("simx.vcd"); - $dumpvars(4, user_risc_soft_boot_tb.u_top); - //$dumpvars(3, user_risc_soft_boot_tb.u_top.u_riscv_top); - end - `endif - - initial begin - - #200; // Wait for reset removal - repeat (10) @(posedge clock); - $display("Monitor: Standalone User Risc Boot Test Started"); - - // Remove Wb Reset - wb_user_core_write('h3080_0000,'h1); - - $readmemh("user_risc_boot.hex",tem_mem); - // convert 8 bit 32 mem format - for(i =0; i < 511; i = i+1) - tem_mem_32b[i] = {tem_mem[(i*4)+3],tem_mem[(i*4)+2],tem_mem[(i*4)+1],tem_mem[(i*4)]}; - - $writememh("sram_bank0.hex",tem_mem_32b,0,511); - $readmemh("sram_bank0.hex",u_top.u_sram0_2kb.mem,0,511); - - for(i =512; i < 1023; i = i+1) - tem_mem_32b[i-512] = {tem_mem[(i*4)+3],tem_mem[(i*4)+2],tem_mem[(i*4)+1],tem_mem[(i*4)]}; - - $writememh("sram_bank1.hex",tem_mem_32b,0,511); - $readmemh("sram_bank1.hex",u_top.u_sram1_2kb.mem,0,511); - - // Enable the SRAM Remap to boot region - wb_user_core_write('h3080_000C,{4'b1111,28'h0}); - repeat (2) @(posedge clock); - #1; - // Remove the reset, mbist, wishbone, riscv - wb_user_core_write('h3080_0000,'h8F); - - - // Repeat cycles of 1000 clock edges as needed to complete testbench - repeat (24) begin - repeat (500) @(posedge clock); - //$display("+500 cycles"); - end - - - $display("Monitor: Reading Back the expected value"); - // User RISC core expect to write these value in global - // register, read back and decide on pass fail - // 0x30000018 = 0x11223344; - // 0x3000001C = 0x22334455; - // 0x30000020 = 0x33445566; - // 0x30000024 = 0x44556677; - // 0x30000028 = 0x55667788; - // 0x3000002C = 0x66778899; - - test_fail = 0; - wb_user_core_read_check(32'h30020058,read_data,32'h11223344); - wb_user_core_read_check(32'h3002005C,read_data,32'h22334455); - wb_user_core_read_check(32'h30020060,read_data,32'h33445566); - wb_user_core_read_check(32'h30020064,read_data,32'h44556677); - wb_user_core_read_check(32'h30020068,read_data,32'h55667788); - wb_user_core_read_check(32'h3002006C,read_data,32'h66778899) ; - - - $display("###################################################"); - if(test_fail == 0) begin - `ifdef GL - $display("Monitor: Standalone User Risc Boot (GL) Passed"); - `else - $display("Monitor: Standalone User Risc Boot (RTL) Passed"); - `endif - end else begin - `ifdef GL - $display("Monitor: Standalone User Risc Boot (GL) Failed"); - `else - $display("Monitor: Standalone User Risc Boot (RTL) Failed"); - `endif - end - $display("###################################################"); - $finish; - end - - initial begin - wb_rst_i <= 1'b1; - #100; - wb_rst_i <= 1'b0; // Release reset - end -wire USER_VDD1V8 = 1'b1; -wire VSS = 1'b0; - -user_project_wrapper u_top( -`ifdef USE_POWER_PINS - .vccd1(USER_VDD1V8), // User area 1 1.8V supply - .vssd1(VSS), // User area 1 digital ground -`endif - .wb_clk_i (clock), // System clock - .user_clock2 (1'b1), // Real-time clock - .wb_rst_i (wb_rst_i), // Regular Reset signal - - .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request - .wbs_stb_i (wbd_ext_stb_i), // strobe/request - .wbs_adr_i (wbd_ext_adr_i), // address - .wbs_we_i (wbd_ext_we_i), // write - .wbs_dat_i (wbd_ext_dat_i), // data output - .wbs_sel_i (wbd_ext_sel_i), // byte enable - - .wbs_dat_o (wbd_ext_dat_o), // data input - .wbs_ack_o (wbd_ext_ack_o), // acknowlegement - - - // Logic Analyzer Signals - .la_data_in ('1) , - .la_data_out (), - .la_oenb ('0), - - - // IOs - .io_in (io_in) , - .io_out (io_out) , - .io_oeb (io_oeb) , - - .user_irq () - -); - -`ifndef GL // Drive Power for Hold Fix Buf - // All standard cell need power hook-up for functionality work - initial begin - - end -`endif - - - -task wb_user_core_write; -input [31:0] address; -input [31:0] data; -begin - repeat (1) @(posedge clock); - #1; - wbd_ext_adr_i =address; // address - wbd_ext_we_i ='h1; // write - wbd_ext_dat_i =data; // data output - wbd_ext_sel_i ='hF; // byte enable - wbd_ext_cyc_i ='h1; // strobe/request - wbd_ext_stb_i ='h1; // strobe/request - wait(wbd_ext_ack_o == 1); - repeat (1) @(posedge clock); - #1; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data); - repeat (2) @(posedge clock); -end -endtask - -task wb_user_core_read; -input [31:0] address; -output [31:0] data; -reg [31:0] data; -begin - repeat (1) @(posedge clock); - #1; - wbd_ext_adr_i =address; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='0; // data output - wbd_ext_sel_i ='hF; // byte enable - wbd_ext_cyc_i ='h1; // strobe/request - wbd_ext_stb_i ='h1; // strobe/request - wait(wbd_ext_ack_o == 1); - data = wbd_ext_dat_o; - repeat (1) @(posedge clock); - #1; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); - repeat (2) @(posedge clock); -end -endtask - -task wb_user_core_read_check; -input [31:0] address; -output [31:0] data; -input [31:0] cmp_data; -reg [31:0] data; -begin - repeat (1) @(posedge clock); - #1; - wbd_ext_adr_i =address; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='0; // data output - wbd_ext_sel_i ='hF; // byte enable - wbd_ext_cyc_i ='h1; // strobe/request - wbd_ext_stb_i ='h1; // strobe/request - wait(wbd_ext_ack_o == 1); - data = wbd_ext_dat_o; - repeat (1) @(posedge clock); - #1; - wbd_ext_cyc_i ='h0; // strobe/request - wbd_ext_stb_i ='h0; // strobe/request - wbd_ext_adr_i ='h0; // address - wbd_ext_we_i ='h0; // write - wbd_ext_dat_i ='h0; // data output - wbd_ext_sel_i ='h0; // byte enable - if(data !== cmp_data) begin - $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); - test_fail = 1; - end else begin - $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); - end - repeat (2) @(posedge clock); -end -endtask - -`ifdef GL - -wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i; -wire wbd_spi_ack_o = u_top.u_spi_master.wbd_ack_o; -wire wbd_spi_we_i = u_top.u_spi_master.wbd_we_i; -wire [31:0] wbd_spi_adr_i = u_top.u_spi_master.wbd_adr_i; -wire [31:0] wbd_spi_dat_i = u_top.u_spi_master.wbd_dat_i; -wire [31:0] wbd_spi_dat_o = u_top.u_spi_master.wbd_dat_o; -wire [3:0] wbd_spi_sel_i = u_top.u_spi_master.wbd_sel_i; - -wire wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i; -wire wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o; -wire wbd_sdram_we_i = u_top.u_sdram_ctrl.wb_we_i; -wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i; -wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i; -wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o; -wire [3:0] wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i; - -wire wbd_uart_stb_i = u_top.u_uart_i2c_usb.reg_cs; -wire wbd_uart_ack_o = u_top.u_uart_i2c_usb.reg_ack; -wire wbd_uart_we_i = u_top.u_uart_i2c_usb.reg_wr; -wire [7:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb.reg_addr; -wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb.reg_wdata; -wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb.reg_rdata; -wire wbd_uart_sel_i = u_top.u_uart_i2c_usb.reg_be; - -`endif - -/** -`ifdef GL -//----------------------------------------------------------------------------- -// RISC IMEM amd DMEM Monitoring TASK -//----------------------------------------------------------------------------- - -`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top - -always@(posedge `RISC_CORE.wb_clk) begin - if(`RISC_CORE.wbd_imem_ack_i) - $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i); - if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o) - $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o); - if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o) - $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i); -end - -`endif -**/ -endmodule -`default_nettype wire
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v index d16bfa8..cb37454 100644 --- a/verilog/dv/user_spi/user_spi_tb.v +++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -82,7 +82,7 @@ `include "s25fl256s.sv" `include "uprj_netlists.v" `include "mt48lc8m8a2.v" -`include "spiram.v" +`include "is62wvs1288.v" // REGISTER MAP `define QSPIM_GLBL_CTRL 32'h10000000 @@ -1263,7 +1263,7 @@ wire spiram_csb = io_out[26]; - spiram #(.mem_file_name("flash1.hex")) + is62wvs1288 #(.mem_file_name("flash1.hex")) u_sfram ( // Data Inputs/Outputs .io0 (flash_io0),
diff --git a/verilog/rtl/DFFRAM/DFFRAM.v b/verilog/rtl/DFFRAM/DFFRAM.v new file mode 100644 index 0000000..939fe2c --- /dev/null +++ b/verilog/rtl/DFFRAM/DFFRAM.v
@@ -0,0 +1,45 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none + + +module DFFRAM ( +`ifdef USE_POWER_PINS + input VPWR, + input VGND, +`endif + input CLK, + input [3:0] WE, + input EN, + input [31:0] Di, + output reg [31:0] Do, + input [7:0] A +); + + +reg [31:0] mem [0:`MEM_WORDS-1]; + +always @(posedge CLK) begin + if (EN == 1'b1) begin + Do <= mem[A]; + if (WE[0]) mem[A][ 7: 0] <= Di[ 7: 0]; + if (WE[1]) mem[A][15: 8] <= Di[15: 8]; + if (WE[2]) mem[A][23:16] <= Di[23:16]; + if (WE[3]) mem[A][31:24] <= Di[31:24]; + end +end +endmodule +
diff --git a/verilog/rtl/DFFRAM/DFFRAMBB.v b/verilog/rtl/DFFRAM/DFFRAMBB.v new file mode 100644 index 0000000..15fa627 --- /dev/null +++ b/verilog/rtl/DFFRAM/DFFRAMBB.v
@@ -0,0 +1,772 @@ +/* + Copyright ©2020-2021 The American University in Cairo and the Cloud V Project. + + This file is part of the DFFRAM Memory Compiler. + See https://github.com/Cloud-V/DFFRAM for further info. + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +// Add 1x2 binary decoder +`default_nettype none + +module DEC1x2 ( +`ifdef USE_POWER_PINS + input wire VPWR, + input wire VGND, +`endif + input wire EN, + input wire A, + output wire [1:0] SEL +); + + sky130_fd_sc_hd__and2b_2 AND0 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + + .X(SEL[0]), + .A_N(A), + .B(EN) + ); + + sky130_fd_sc_hd__and2_2 AND1 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + + .X(SEL[1]), + .A(A) , + .B(EN) + ); + +endmodule + +module DEC2x4 ( +`ifdef USE_POWER_PINS + input wire VPWR, + input wire VGND, +`endif + input EN, + input [1:0] A, + output [3:0] SEL +); + sky130_fd_sc_hd__nor3b_4 AND0 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .Y(SEL[0]), .A(A[0]), .B(A[1]), .C_N(EN) ); + sky130_fd_sc_hd__and3b_4 AND1 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[1]), .A_N(A[1]), .B(A[0]), .C(EN) ); + sky130_fd_sc_hd__and3b_4 AND2 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[2]), .A_N(A[0]), .B(A[1]), .C(EN) ); + sky130_fd_sc_hd__and3_4 AND3 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[3]), .A(A[1]), .B(A[0]), .C(EN) ); + +endmodule + +module DEC3x8 ( +`ifdef USE_POWER_PINS + input wire VPWR, + input wire VGND, +`endif + input EN, + input [2:0] A, + output [7:0] SEL +); + + wire [2:0] A_buf; + wire EN_buf; + + sky130_fd_sc_hd__clkbuf_2 ABUF[2:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(A_buf), .A(A)); + sky130_fd_sc_hd__clkbuf_2 ENBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(EN_buf), .A(EN)); + + sky130_fd_sc_hd__nor4b_2 AND0 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .Y(SEL[0]) , .A(A_buf[0]), .B(A_buf[1]) , .C(A_buf[2]), .D_N(EN_buf) ); // 000 + sky130_fd_sc_hd__and4bb_2 AND1 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[1]) , .A_N(A_buf[2]), .B_N(A_buf[1]), .C(A_buf[0]) , .D(EN_buf) ); // 001 + sky130_fd_sc_hd__and4bb_2 AND2 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[2]) , .A_N(A_buf[2]), .B_N(A_buf[0]), .C(A_buf[1]) , .D(EN_buf) ); // 010 + sky130_fd_sc_hd__and4b_2 AND3 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[3]) , .A_N(A_buf[2]), .B(A_buf[1]), .C(A_buf[0]) , .D(EN_buf) ); // 011 + sky130_fd_sc_hd__and4bb_2 AND4 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[4]) , .A_N(A_buf[0]), .B_N(A_buf[1]), .C(A_buf[2]) , .D(EN_buf) ); // 100 + sky130_fd_sc_hd__and4b_2 AND5 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[5]) , .A_N(A_buf[1]), .B(A_buf[0]), .C(A_buf[2]) , .D(EN_buf) ); // 101 + sky130_fd_sc_hd__and4b_2 AND6 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[6]) , .A_N(A_buf[0]), .B(A_buf[1]), .C(A_buf[2]) , .D(EN_buf) ); // 110 + sky130_fd_sc_hd__and4_2 AND7 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL[7]) , .A(A_buf[0]), .B(A_buf[1]), .C(A_buf[2]) , .D(EN_buf) ); // 111 +endmodule + +module MUX4x1 #(parameter WIDTH=32) +( +`ifdef USE_POWER_PINS + input wire VPWR, + input wire VGND, +`endif + input wire [WIDTH-1:0] A0, A1, A2, A3, + input wire [1:0] S, + output wire [WIDTH-1:0] X +); + localparam SIZE = WIDTH/8; + wire [SIZE-1:0] SEL0, SEL1; + sky130_fd_sc_hd__clkbuf_2 SEL0BUF[SIZE-1:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL0), .A(S[0])); + + sky130_fd_sc_hd__clkbuf_2 SEL1BUF[SIZE-1:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL1), .A(S[1])); + + generate + genvar i; + for(i=0; i<SIZE; i=i+1) begin : M + sky130_fd_sc_hd__mux4_1 MUX[7:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A0(A0[(i+1)*8-1:i*8]), + .A1(A1[(i+1)*8-1:i*8]), + .A2(A2[(i+1)*8-1:i*8]), + .A3(A3[(i+1)*8-1:i*8]), + .S0(SEL0[i]), + .S1(SEL1[i]), + .X(X[(i+1)*8-1:i*8]) ); + end + endgenerate +endmodule + +module MUX2x1 #(parameter WIDTH=32) +( +`ifdef USE_POWER_PINS + input wire VPWR, + input wire VGND, +`endif + input wire [WIDTH-1:0] A0, A1, A2, A3, + input wire S, + output wire [WIDTH-1:0] X +); + localparam SIZE = WIDTH/8; + wire [SIZE-1:0] SEL; + sky130_fd_sc_hd__clkbuf_2 SELBUF[SIZE-1:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL), .A(S)); + generate + genvar i; + for(i=0; i<SIZE; i=i+1) begin : M + sky130_fd_sc_hd__mux2_1 MUX[7:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A0(A0[(i+1)*8-1:i*8]), .A1(A1[(i+1)*8-1:i*8]), .S(SEL[i]), .X(X[(i+1)*8-1:i*8]) ); + end + endgenerate +endmodule + +module BYTE #( parameter USE_LATCH=`DFFRAM_USE_LATCH)( +`ifdef USE_POWER_PINS + input wire VPWR, + input wire VGND, +`endif + input wire CLK, // FO: 1 + input wire WE, // FO: 1 + input wire SEL, // FO: 2 + input wire [7:0] Di, // FO: 1 + output wire [7:0] Do +); + + wire [7:0] q_wire; + wire we_wire; + wire SEL_B; + wire GCLK; + wire CLK_B; + + generate + genvar i; + + if(USE_LATCH == 1) begin + sky130_fd_sc_hd__inv_1 CLKINV( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .Y(CLK_B), .A(CLK)); + sky130_fd_sc_hd__dlclkp_1 CG( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .CLK(CLK_B), .GCLK(GCLK), .GATE(we_wire) ); + end else + sky130_fd_sc_hd__dlclkp_1 CG( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .CLK(CLK), .GCLK(GCLK), .GATE(we_wire) ); + + sky130_fd_sc_hd__inv_1 SELINV( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .Y(SEL_B), .A(SEL)); + sky130_fd_sc_hd__and2_1 CGAND( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A(SEL), .B(WE), .X(we_wire) ); + + for(i=0; i<8; i=i+1) begin : BIT + if(USE_LATCH == 0) + sky130_fd_sc_hd__dfxtp_1 FF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .D(Di[i]), .Q(q_wire[i]), .CLK(GCLK) ); + else + sky130_fd_sc_hd__dlxtp_1 LATCH ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .Q(q_wire[i]), .D(Di[i]), .GATE(GCLK) ); + sky130_fd_sc_hd__ebufn_2 OBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A(q_wire[i]), .Z(Do[i]), .TE_B(SEL_B) ); + end + endgenerate + +endmodule + + +module WORD #( parameter USE_LATCH=`DFFRAM_USE_LATCH, + WSIZE=`DFFRAM_WSIZE ) ( +`ifdef USE_POWER_PINS + input wire VPWR, + input wire VGND, +`endif + input wire CLK, // FO: 1 + input wire [WSIZE-1:0] WE, // FO: 1 + input wire SEL, // FO: 1 + input wire [(WSIZE*8-1):0] Di, // FO: 1 + output wire [(WSIZE*8-1):0] Do +); + + wire SEL_buf; + wire CLK_buf; + sky130_fd_sc_hd__clkbuf_2 SELBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(SEL_buf), .A(SEL)); + sky130_fd_sc_hd__clkbuf_1 CLKBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(CLK_buf), .A(CLK)); + generate + genvar i; + for(i=0; i<WSIZE; i=i+1) begin : BYTE + BYTE #(.USE_LATCH(USE_LATCH)) B ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK_buf), .WE(WE[i]), .SEL(SEL_buf), .Di(Di[(i+1)*8-1:i*8]), .Do(Do[(i+1)*8-1:i*8]) ); + end + endgenerate + +endmodule + + +module RAM8 #( parameter USE_LATCH=`DFFRAM_USE_LATCH, + WSIZE=`DFFRAM_WSIZE ) ( +`ifdef USE_POWER_PINS + input wire VPWR, + input wire VGND, +`endif + input wire CLK, // FO: 1 + input wire [WSIZE-1:0] WE, // FO: 1 + input EN, // EN: 1 + input wire [2:0] A, // A: 1 + input wire [(WSIZE*8-1):0] Di, // FO: 1 + output wire [(WSIZE*8-1):0] Do +); + + wire [7:0] SEL; + wire [WSIZE-1:0] WE_buf; + wire CLK_buf; + + DEC3x8 DEC ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .EN(EN), .A(A), .SEL(SEL)); + sky130_fd_sc_hd__clkbuf_2 WEBUF[WSIZE-1:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(WE_buf), .A(WE)); + sky130_fd_sc_hd__clkbuf_2 CLKBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(CLK_buf), .A(CLK)); + + generate + genvar i; + for (i=0; i< 8; i=i+1) begin : WORD + WORD #(.USE_LATCH(USE_LATCH), .WSIZE(WSIZE)) W ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK_buf), .WE(WE_buf), .SEL(SEL[i]), .Di(Di), .Do(Do) ); + end + endgenerate + +endmodule + + +// 4 x RAM8 slices (128 bytes) with registered outout +module RAM32 #( parameter USE_LATCH=`DFFRAM_USE_LATCH, + WSIZE=`DFFRAM_WSIZE ) +( +`ifdef USE_POWER_PINS + input wire VPWR, + input wire VGND, +`endif + input wire CLK, // FO: 1 + input wire [WSIZE-1:0] WE, // FO: 1 + input EN, // FO: 1 + input wire [4:0] A, // FO: 1 + input wire [(WSIZE*8-1):0] Di, // FO: 1 + output wire [(WSIZE*8-1):0] Do + +); + wire [3:0] SEL; + wire [4:0] A_buf; + wire CLK_buf; + wire [WSIZE-1:0] WE_buf; + wire EN_buf; + + wire [(WSIZE*8-1):0] Do_pre; + wire [(WSIZE*8-1):0] Di_buf; + + // Buffers + // Di Buffers + sky130_fd_sc_hd__clkbuf_16 DIBUF[(WSIZE*8-1):0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(Di_buf), .A(Di)); + // Control signals buffers + sky130_fd_sc_hd__clkbuf_2 CLKBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(CLK_buf), .A(CLK)); + sky130_fd_sc_hd__clkbuf_2 WEBUF[(WSIZE-1):0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(WE_buf), .A(WE)); + sky130_fd_sc_hd__clkbuf_2 ABUF[4:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(A_buf), .A(A[4:0])); + sky130_fd_sc_hd__clkbuf_2 ENBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(EN_buf), .A(EN)); + + DEC2x4 DEC ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .EN(EN_buf), .A(A_buf[4:3]), .SEL(SEL)); + + generate + genvar i; + for (i=0; i< 4; i=i+1) begin : SLICE + RAM8 #(.USE_LATCH(USE_LATCH), .WSIZE(WSIZE)) RAM8 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK_buf), .WE(WE_buf),.EN(SEL[i]), .Di(Di_buf), .Do(Do_pre), .A(A_buf[2:0]) ); + end + endgenerate + + // Ensure that the Do_pre lines are not floating when EN = 0 + wire [WSIZE-1:0] lo; + wire [WSIZE-1:0] float_buf_en; + sky130_fd_sc_hd__clkbuf_2 FBUFENBUF[WSIZE-1:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(float_buf_en), .A(EN) ); + sky130_fd_sc_hd__conb_1 TIE[WSIZE-1:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .LO(lo), .HI()); + + // Following split by group because each is done by one TIE CELL and ONE CLKINV_4 + // Provides default values for floating lines (lo) + generate + for (i=0; i< WSIZE; i=i+1) begin : BYTE + sky130_fd_sc_hd__ebufn_2 FLOATBUF[(8*(i+1))-1:8*i] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .A( lo[i] ), .Z(Do_pre[(8*(i+1))-1:8*i]), .TE_B(float_buf_en[i]) ); + end + endgenerate + + sky130_fd_sc_hd__dfxtp_1 Do_FF[WSIZE*8-1:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .D(Do_pre), .Q(Do), .CLK(CLK) ); + +endmodule + + +/* + 4 x RAM32 Blocks +*/ + +module RAM128 #(parameter USE_LATCH=`DFFRAM_USE_LATCH, + WSIZE=`DFFRAM_WSIZE ) +( +`ifdef USE_POWER_PINS + input wire VPWR, + input wire VGND, +`endif + input wire CLK, // FO: 1 + input wire [WSIZE-1:0] WE, // FO: 1 + input EN, // FO: 1 + input wire [6:0] A, // FO: 1 + input wire [(WSIZE*8-1):0] Di, // FO: 1 + output wire [(WSIZE*8-1):0] Do + +); + + wire CLK_buf; + wire [WSIZE-1:0] WE_buf; + wire EN_buf; + wire [6:0] A_buf; + wire [(WSIZE*8-1):0] Di_buf; + wire [3:0] SEL; + + wire [(WSIZE*8-1):0] Do_pre[3:0]; + + // Buffers + sky130_fd_sc_hd__clkbuf_16 DIBUF[(WSIZE*8-1):0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(Di_buf), .A(Di)); + sky130_fd_sc_hd__clkbuf_4 CLKBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(CLK_buf), .A(CLK)); + sky130_fd_sc_hd__clkbuf_2 WEBUF[WSIZE-1:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(WE_buf), .A(WE)); + sky130_fd_sc_hd__clkbuf_2 ENBUF ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(EN_buf), .A(EN)); + sky130_fd_sc_hd__clkbuf_2 ABUF[6:0] ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .X(A_buf), .A(A)); + + DEC2x4 DEC ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .EN(EN_buf), .A(A_buf[6:5]), .SEL(SEL)); + + generate + genvar i; + for (i=0; i< 4; i=i+1) begin : BLOCK + RAM32 #(.USE_LATCH(USE_LATCH), .WSIZE(WSIZE)) RAM32 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK_buf), .EN(SEL[i]), .WE(WE_buf), .Di(Di_buf), .Do(Do_pre[i]), .A(A_buf[4:0]) ); + end + endgenerate + + // Output MUX + MUX4x1 #(.WIDTH(WSIZE*8)) DoMUX ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .A0(Do_pre[0]), .A1(Do_pre[1]), .A2(Do_pre[2]), .A3(Do_pre[3]), .S(A_buf[6:5]), .X(Do) ); + +endmodule + +module RAM256 #(parameter USE_LATCH=`DFFRAM_USE_LATCH, + WSIZE=`DFFRAM_WSIZE ) +( +`ifdef USE_POWER_PINS + input wire VPWR, + input wire VGND, +`endif + input wire CLK, // FO: 2 + input wire [WSIZE-1:0] WE, // FO: 2 + input EN, // FO: 2 + input wire [7:0] A, // FO: 5 + input wire [(WSIZE*8-1):0] Di, // FO: 2 + output wire [(WSIZE*8-1):0] Do + +); + + wire [1:0] SEL; + wire [(WSIZE*8-1):0] Do_pre[1:0]; + + // 1x2 DEC + sky130_fd_sc_hd__inv_2 DEC ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), + `endif + .Y(SEL[0]), .A(A[7])); + assign SEL[1] = A[7]; + + generate + genvar i; + for (i=0; i< 2; i=i+1) begin : BLOCK + RAM128 #(.USE_LATCH(USE_LATCH), .WSIZE(WSIZE)) RAM128 ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .CLK(CLK), .EN(SEL[i]), .WE(WE), .Di(Di), .Do(Do_pre[i]), .A(A[6:0]) ); + end + endgenerate + + // Output MUX + MUX2x1 #(.WIDTH(WSIZE*8)) DoMUX ( + `ifdef USE_POWER_PINS + .VPWR(VPWR), + .VGND(VGND), + `endif + .A0(Do_pre[0]), .A1(Do_pre[1]), .S(A[7]), .X(Do) ); + +endmodule
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index 46a69a4..5015bb6 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -118,24 +118,8 @@ input logic uartm_txd , output logic pulse1m_mclk, - output logic [31:0] pinmux_debug, + output logic [31:0] pinmux_debug - // BIST I/F - output logic bist_en, - output logic bist_run, - output logic bist_load, - - output logic bist_sdi, - output logic bist_shift, - input logic bist_sdo, - - input logic bist_done, - input logic [3:0] bist_error, - input logic [3:0] bist_correct, - input logic [3:0] bist_error_cnt0, - input logic [3:0] bist_error_cnt1, - input logic [3:0] bist_error_cnt2, - input logic [3:0] bist_error_cnt3 ); @@ -334,21 +318,21 @@ .gpio_prev_indata (gpio_prev_indata ) , // BIST I/F - .bist_en (bist_en ), - .bist_run (bist_run ), - .bist_load (bist_load ), + .bist_en ( ), + .bist_run ( ), + .bist_load ( ), - .bist_sdi (bist_sdi ), - .bist_shift (bist_shift ), - .bist_sdo (bist_sdo ), + .bist_sdi ( ), + .bist_shift ( ), + .bist_sdo ('b0 ), - .bist_done (bist_done ), - .bist_error (bist_error ), - .bist_correct (bist_correct ), - .bist_error_cnt0 (bist_error_cnt0 ), - .bist_error_cnt1 (bist_error_cnt1 ), - .bist_error_cnt2 (bist_error_cnt2 ), - .bist_error_cnt3 (bist_error_cnt3 ) + .bist_done ('b0 ), + .bist_error ('h0 ), + .bist_correct ('h0 ), + .bist_error_cnt0 ('h0 ), + .bist_error_cnt1 ('h0 ), + .bist_error_cnt2 ('h0 ), + .bist_error_cnt3 ('h0 ) );
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv index 211bd40..b09e18c 100644 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -721,7 +721,7 @@ //----------------------------------------- // Software Reg-2, Release date: <DAY><MONTH><YEAR> // ---------------------------------------- -gen_32b_reg #(32'h1402_2022) u_reg_23 ( +gen_32b_reg #(32'h1602_2022) u_reg_23 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -734,9 +734,9 @@ ); //----------------------------------------- -// Software Reg-3: Poject Revison 3.3 = 0003400 +// Software Reg-3: Poject Revison 3.3 = 0003500 // ---------------------------------------- -gen_32b_reg #(32'h0003_4000) u_reg_24 ( +gen_32b_reg #(32'h0003_5000) u_reg_24 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ),
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index b81ad7e..0652188 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -41,14 +41,7 @@ `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v" `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v" - `include"sar_adc/SAR.sv" - `include"sar_adc/ACMP.sv" - `include"sar_adc/sar_adc.sv" - `include"sar_adc/adc_reg.sv" - `include"sar_adc/DAC_8BIT.v" - - `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" `include "pinmux/src/pinmux.sv" `include "pinmux/src/pinmux_reg.sv" `include "pinmux/src/gpio_intr.sv" @@ -137,7 +130,7 @@ `include "yifive/ycr1c/src/top/ycr1_imem_router.sv" `include "yifive/ycr1c/src/top/ycr1_dmem_router.sv" `include "yifive/ycr1c/src/top/ycr1_dp_memory.sv" - `include "yifive/ycr1c/src/top/ycr1_tcm.sv" + `include "yifive/ycr1c/src/top/ycr1_tcm_router.sv" `include "yifive/ycr1c/src/top/ycr1_timer.sv" `include "yifive/ycr1c/src/top/ycr1_dmem_wb.sv" `include "yifive/ycr1c/src/top/ycr1_imem_wb.sv" @@ -155,20 +148,7 @@ `include "lib/sync_fifo.sv" - `include "mbist/src/core/mbist_addr_gen.sv" - `include "mbist/src/core/mbist_fsm.sv" - `include "mbist/src/core/mbist_op_sel.sv" - `include "mbist/src/core/mbist_repair_addr.sv" - `include "mbist/src/core/mbist_sti_sel.sv" - `include "mbist/src/core/mbist_pat_sel.sv" - `include "mbist/src/core/mbist_mux.sv" - `include "mbist/src/core/mbist_data_cmp.sv" - `include "mbist/src/core/mbist_mem_wrapper.sv" - - `include "mbist/src/top/mbist_top.sv" - `include "mbist_wrapper/src/mbist_wb.sv" - `include "mbist_wrapper/src/mbist_wrapper.sv" - + `include "DFFRAM/DFFRAM.v" `include "uart2wb/src/uart2wb.sv" `include "uart2wb/src/uart2_core.sv" @@ -178,6 +158,6 @@ `include "user_project_wrapper.v" // we are using netlist file for clk_skew_adjust as it has // standard cell + power pin - `include "clk_skew_adjust/src/clk_skew_adjust.v" + `include "lib/clk_skew_adjust.gv" `include "lib/ctech_cells.sv" `endif
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index c39bf3b..525d578 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -169,6 +169,14 @@ //// dineshannayya/riscduino_sram.git //// //// This repo will remove mbist + SRAM and RISC SRAM will be //// //// replaced with DFRAM //// +//// 3.5 Feb 16, Dinesh A //// +//// As SRAM from sky130A is not yet qualified, //// +//// Following changes are done //// +//// A. riscv core cache and tcm interface changed to dffram//// +//// B. removed the mbist controller + 4 SRAM //// +//// C. mbist controller slave port in wb_intern removed //// +//// D. Pinmux mbist port are removed //// +//// E. mbist related buffering are removed at wb_inter //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -268,20 +276,22 @@ wire wbd_riscv_dcache_lack_o ; // last burst acknowlegement wire wbd_riscv_dcache_err_o ; // error -// CACHE SRAM Memory I/F -wire dcache_mem_clk0 ; // CLK -wire dcache_mem_csb0 ; // CS# -wire dcache_mem_web0 ; // WE# -wire [8:0] dcache_mem_addr0 ; // Address -wire [3:0] dcache_mem_wmask0 ; // WMASK# -wire [31:0] dcache_mem_din0 ; // Write Data -wire [31:0] dcache_mem_dout0 ; // Read Data - -// SRAM-0 PORT-1, IMEM I/F -wire dcache_mem_clk1 ; // CLK -wire dcache_mem_csb1 ; // CS# -wire [8:0] dcache_mem_addr1 ; // Address -wire [31:0] dcache_mem_dout1 ; // Read Data +// DFFRAM I/F + +wire dcache_dffram_clk0 ; // CLK +wire dcache_dffram_cs0 ; // Chip Select +wire [7:0] dcache_dffram_addr0 ; // Address +wire [3:0] dcache_dffram_wmask0 ; // Write Mask +wire [31:0] dcache_dffram_din0 ; // Write Data +wire [31:0] dcache_dffram_dout0 ; // Read Data + +wire dcache_dffram_clk1 ; // CLK +wire dcache_dffram_cs1 ; // Chip Select +wire [7:0] dcache_dffram_addr1 ; // Address +wire [3:0] dcache_dffram_wmask1 ; // Write Mask +wire [31:0] dcache_dffram_din1 ; // Write Data +wire [31:0] dcache_dffram_dout1 ; // Read Data + //--------------------------------------------------------------------- // Wishbone Risc V Icache Memory Interface //--------------------------------------------------------------------- @@ -296,20 +306,21 @@ wire wbd_riscv_icache_lack_o ; // last burst acknowlegement wire wbd_riscv_icache_err_o ; // error -// CACHE SRAM Memory I/F -wire icache_mem_clk0 ; // CLK -wire icache_mem_csb0 ; // CS# -wire icache_mem_web0 ; // WE# -wire [8:0] icache_mem_addr0 ; // Address -wire [3:0] icache_mem_wmask0 ; // WMASK# -wire [31:0] icache_mem_din0 ; // Write Data -// wire [31:0] icache_mem_dout0 ; // Read Data - -// SRAM-0 PORT-1, IMEM I/F -wire icache_mem_clk1 ; // CLK -wire icache_mem_csb1 ; // CS# -wire [8:0] icache_mem_addr1 ; // Address -wire [31:0] icache_mem_dout1 ; // Read Data +// DFFRAM I/F + +wire icache_dffram_clk0 ; // CLK +wire icache_dffram_cs0 ; // Chip Select +wire [7:0] icache_dffram_addr0 ; // Address +wire [3:0] icache_dffram_wmask0 ; // Write Mask +wire [31:0] icache_dffram_din0 ; // Write Data +wire [31:0] icache_dffram_dout0 ; // Read Data + +wire icache_dffram_clk1 ; // CLK +wire icache_dffram_cs1 ; // Chip Select +wire [7:0] icache_dffram_addr1 ; // Address +wire [3:0] icache_dffram_wmask1 ; // Write Mask +wire [31:0] icache_dffram_din1 ; // Write Data +wire [31:0] icache_dffram_dout1 ; // Read Data //--------------------------------------------------------------------- // RISC V Wishbone Data Memory Interface @@ -390,21 +401,6 @@ wire wbd_uart_ack_i ; // acknowlegement wire wbd_uart_err_i ; // error -//--------------------------------------------------------------------- -// MBIST1 -//--------------------------------------------------------------------- -wire wbd_mbist_stb_o ; // strobe/request -wire [12:0] wbd_mbist_adr_o ; // address -wire wbd_mbist_we_o ; // write -wire [WB_WIDTH-1:0] wbd_mbist_dat_o ; // data output -wire [3:0] wbd_mbist_sel_o ; // byte enable -wire [9:0] wbd_mbist_bl_o ; // byte enable -wire wbd_mbist_bry_o ; // byte enable -wire wbd_mbist_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist_dat_i ; // data input -wire wbd_mbist_ack_i ; // acknowlegement -wire wbd_mbist_lack_i ; // acknowlegement -wire wbd_mbist_err_i ; // error //---------------------------------------------------- // CPU Configuration @@ -415,19 +411,16 @@ wire uart_rst_n ; // uart reset wire i2c_rst_n ; // i2c reset wire usb_rst_n ; // i2c reset -wire [3:0] boot_remap ; // Boot Remap -wire [3:0] dcache_remap ; // Remap the dcache address +wire bist_rst_n ; // i2c reset wire cpu_clk ; wire rtc_clk ; wire usb_clk ; wire wbd_clk_int ; +wire wbd_clk_wh ; +wire wbd_clk_spi ; wire wbd_clk_pinmux ; -//wire wbd_clk_int1 ; -//wire wbd_clk_int2 ; wire wbd_int_rst_n ; -//wire wbd_int1_rst_n ; -//wire wbd_int2_rst_n ; wire [31:0] fuse_mhartid ; wire [15:0] irq_lines ; @@ -445,10 +438,6 @@ wire [3:0] cfg_cska_qspi ; // clock skew adjust for spi wire [3:0] cfg_cska_pinmux ; // clock skew adjust for pinmux wire [3:0] cfg_cska_qspi_co ; // clock skew adjust for global reg -wire [3:0] cfg_cska_mbist1 ; -wire [3:0] cfg_cska_mbist2 ; -wire [3:0] cfg_cska_mbist3 ; -wire [3:0] cfg_cska_mbist4 ; // Bus Repeater Signals output from Wishbone Interface wire [3:0] cfg_cska_riscv_rp ; // clock skew adjust for riscv @@ -456,10 +445,6 @@ wire [3:0] cfg_cska_qspi_rp ; // clock skew adjust for spi wire [3:0] cfg_cska_pinmux_rp ; // clock skew adjust for pinmux wire [3:0] cfg_cska_qspi_co_rp ; // clock skew adjust for global reg -wire [3:0] cfg_cska_mbist1_rp ; -wire [3:0] cfg_cska_mbist2_rp ; -wire [3:0] cfg_cska_mbist3_rp ; -wire [3:0] cfg_cska_mbist4_rp ; wire [31:0] fuse_mhartid_rp ; // Repeater wire [15:0] irq_lines_rp ; // Repeater @@ -469,10 +454,7 @@ wire wbd_clk_qspi_rp ; wire wbd_clk_uart_rp ; wire wbd_clk_pinmux_rp ; -wire wbd_clk_mbist1_rp ; -wire wbd_clk_mbist2_rp ; -wire wbd_clk_mbist3_rp ; -wire wbd_clk_mbist4_rp ; +wire wbd_clk_pinmux_skew ; // Progammable Clock Skew inserted signals wire wbd_clk_wi_skew ; // clock for wishbone interconnect with clock skew @@ -481,10 +463,6 @@ wire wbd_clk_spi_skew ; // clock for spi with clock skew wire wbd_clk_glbl_skew ; // clock for global reg with clock skew wire wbd_clk_wh_skew ; // clock for global reg -wire wbd_clk_mbist_skew ; // clock for global reg -wire wbd_clk_mbist2_skew ; // clock for global reg -wire wbd_clk_mbist3_skew ; // clock for global reg -wire wbd_clk_mbist4_skew ; // clock for global reg @@ -536,37 +514,23 @@ wire pulse1m_mclk ; wire h_reset_n ; -`ifndef SCR1_TCM_MEM -// SRAM-0 PORT-0 - DMEM I/F -wire sram0_clk0 ; // CLK -wire sram0_csb0 ; // CS# -wire sram0_web0 ; // WE# -wire [8:0] sram0_addr0 ; // Address -wire [3:0] sram0_wmask0 ; // WMASK# -wire [31:0] sram0_din0 ; // Write Data -wire [31:0] sram0_dout0 ; // Read Data +`ifndef YCR1_TCM_MEM -// SRAM-0 PORT-1, IMEM I/F -wire sram0_clk1 ; // CLK -wire sram0_csb1 ; // CS# -wire [8:0] sram0_addr1 ; // Address -wire [31:0] sram0_dout1 ; // Read Data +// DFFRAM I/F -// SRAM-1 PORT-0 - DMEM I/F -wire sram1_clk0 ; // CLK -wire sram1_csb0 ; // CS# -wire sram1_web0 ; // WE# -wire [8:0] sram1_addr0 ; // Address -wire [3:0] sram1_wmask0 ; // WMASK# -wire [31:0] sram1_din0 ; // Write Data -wire [31:0] sram1_dout0 ; // Read Data - -// SRAM-1 PORT-1, IMEM I/F -wire sram1_clk1 ; // CLK -wire sram1_csb1 ; // CS# -wire [8:0] sram1_addr1 ; // Address -wire [31:0] sram1_dout1 ; // Read Data - +wire tcm_dffram_clk0 ; // CLK +wire tcm_dffram_cs0 ; // Chip Select +wire [7:0] tcm_dffram_addr0 ; // Address +wire [3:0] tcm_dffram_wmask0 ; // Write Mask +wire [31:0] tcm_dffram_din0 ; // Write Data +wire [31:0] tcm_dffram_dout0 ; // Read Data + +wire tcm_dffram_clk1 ; // CLK +wire tcm_dffram_cs1 ; // Chip Select +wire [7:0] tcm_dffram_addr1 ; // Address +wire [3:0] tcm_dffram_wmask1 ; // Write Mask +wire [31:0] tcm_dffram_din1 ; // Write Data +wire [31:0] tcm_dffram_dout1 ; // Read Data `endif // SPIM I/F @@ -585,71 +549,7 @@ wire uartm_rxd ; wire uartm_txd ; -//---------------------------------------------------------- -// BIST I/F -// --------------------------------------------------------- -wire bist_en ; -wire bist_run ; -wire bist_load ; -wire bist_sdi ; -wire bist_shift ; -wire bist_sdo ; - -wire bist_done ; -wire [3:0] bist_error ; -wire [3:0] bist_correct ; -wire [3:0] bist_error_cnt0 ; -wire [3:0] bist_error_cnt1 ; -wire [3:0] bist_error_cnt2 ; -wire [3:0] bist_error_cnt3 ; - -// With Repeater Buffer -wire bist_en_rp ; -wire bist_run_rp ; -wire bist_load_rp ; - -wire bist_sdi_rp ; -wire bist_shift_rp ; -wire bist_sdo_rp ; - -wire bist_done_rp ; -wire [3:0] bist_error_rp ; -wire [3:0] bist_correct_rp ; -wire [3:0] bist_error_cnt0_rp ; -wire [3:0] bist_error_cnt1_rp ; -wire [3:0] bist_error_cnt2_rp ; -wire [3:0] bist_error_cnt3_rp ; - -// towards memory MBIST1 -// PORT-A -wire [BIST_NO_SRAM-1:0] mem_clk_a ; -wire [BIST1_ADDR_WD-1:2] mem0_addr_a ; -wire [BIST1_ADDR_WD-1:2] mem1_addr_a ; -wire [BIST1_ADDR_WD-1:2] mem2_addr_a ; -wire [BIST1_ADDR_WD-1:2] mem3_addr_a ; -wire [BIST_NO_SRAM-1:0] mem_cen_a ; -wire [BIST_NO_SRAM-1:0] mem_web_a ; -wire [BIST_DATA_WD/8-1:0] mem0_mask_a ; -wire [BIST_DATA_WD/8-1:0] mem1_mask_a ; -wire [BIST_DATA_WD/8-1:0] mem2_mask_a ; -wire [BIST_DATA_WD/8-1:0] mem3_mask_a ; -wire [BIST_DATA_WD-1:0] mem0_din_a ; -wire [BIST_DATA_WD-1:0] mem1_din_a ; -wire [BIST_DATA_WD-1:0] mem2_din_a ; -wire [BIST_DATA_WD-1:0] mem3_din_a ; -wire [BIST_DATA_WD-1:0] mem0_dout_a ; -wire [BIST_DATA_WD-1:0] mem1_dout_a ; -wire [BIST_DATA_WD-1:0] mem2_dout_a ; -wire [BIST_DATA_WD-1:0] mem3_dout_a ; - -// PORT-B -wire [BIST_NO_SRAM-1:0] mem_clk_b ; -wire [BIST_NO_SRAM-1:0] mem_cen_b ; -wire [BIST1_ADDR_WD-1:2] mem0_addr_b ; -wire [BIST1_ADDR_WD-1:2] mem1_addr_b ; -wire [BIST1_ADDR_WD-1:2] mem2_addr_b ; -wire [BIST1_ADDR_WD-1:2] mem3_addr_b ; wire [3:0] spi_csn ; @@ -657,89 +557,77 @@ // Clock Skew Ctrl //////////////////////////////////////////////////////// -assign cfg_cska_wi = cfg_clk_ctrl1[3:0]; -assign cfg_cska_wh = cfg_clk_ctrl1[7:4]; -assign cfg_cska_riscv = cfg_clk_ctrl1[11:8]; -assign cfg_cska_qspi = cfg_clk_ctrl1[15:12]; -assign cfg_cska_uart = cfg_clk_ctrl1[19:16]; -assign cfg_cska_pinmux = cfg_clk_ctrl1[23:20]; -assign cfg_cska_qspi_co = cfg_clk_ctrl1[27:24]; +assign cfg_cska_wi = cfg_clk_ctrl1[3:0]; +assign cfg_cska_wh = cfg_clk_ctrl1[7:4]; +assign cfg_cska_riscv = cfg_clk_ctrl1[11:8]; +assign cfg_cska_qspi = cfg_clk_ctrl1[15:12]; +assign cfg_cska_uart = cfg_clk_ctrl1[19:16]; +assign cfg_cska_pinmux = cfg_clk_ctrl1[23:20]; +assign cfg_cska_qspi_co = cfg_clk_ctrl1[27:24]; -assign cfg_cska_mbist1 = cfg_clk_ctrl2[3:0]; -assign cfg_cska_mbist2 = cfg_clk_ctrl2[7:4]; -assign cfg_cska_mbist3 = cfg_clk_ctrl2[11:8]; -assign cfg_cska_mbist4 = cfg_clk_ctrl2[15:12]; -assign dcache_remap = cfg_clk_ctrl2[27:24]; -assign boot_remap = cfg_clk_ctrl2[31:28]; -//assign la_data_out = {riscv_debug,spi_debug,sdram_debug}; assign la_data_out[127:0] = {pinmux_debug,spi_debug,riscv_debug}; -//clk_buf u_buf1_wb_rstn (.clk_i(wbd_int_rst_n),.clk_o(wbd_int1_rst_n)); -//clk_buf u_buf2_wb_rstn (.clk_i(wbd_int1_rst_n),.clk_o(wbd_int2_rst_n)); -// -//clk_buf u_buf1_wbclk (.clk_i(wbd_clk_int),.clk_o(wbd_clk_int1)); -//clk_buf u_buf2_wbclk (.clk_i(wbd_clk_int1),.clk_o(wbd_clk_int2)); wb_host u_wb_host( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .user_clock1 (wb_clk_i ), - .user_clock2 (user_clock2 ), + .user_clock1 (wb_clk_i ), + .user_clock2 (user_clock2 ), - .cpu_clk (cpu_clk ), - .rtc_clk (rtc_clk ), - .usb_clk (usb_clk ), + .cpu_clk (cpu_clk ), + .rtc_clk (rtc_clk ), + .usb_clk (usb_clk ), - .wbd_int_rst_n (wbd_int_rst_n ), - .cpu_rst_n (cpu_rst_n ), - .qspim_rst_n (qspim_rst_n ), - .sspim_rst_n (sspim_rst_n ), // spi reset - .uart_rst_n (uart_rst_n ), // uart reset - .i2cm_rst_n (i2c_rst_n ), // i2c reset - .usb_rst_n (usb_rst_n ), // usb reset - .bist_rst_n (bist_rst_n ), // BIST Reset + .wbd_int_rst_n (wbd_int_rst_n ), + .cpu_rst_n (cpu_rst_n ), + .qspim_rst_n (qspim_rst_n ), + .sspim_rst_n (sspim_rst_n ), // spi reset + .uart_rst_n (uart_rst_n ), // uart reset + .i2cm_rst_n (i2c_rst_n ), // i2c reset + .usb_rst_n (usb_rst_n ), // usb reset + .bist_rst_n (bist_rst_n ), // BIST Reset // Master Port - .wbm_rst_i (wb_rst_i ), - .wbm_clk_i (wb_clk_i ), - .wbm_cyc_i (wbs_cyc_i ), - .wbm_stb_i (wbs_stb_i ), - .wbm_adr_i (wbs_adr_i ), - .wbm_we_i (wbs_we_i ), - .wbm_dat_i (wbs_dat_i ), - .wbm_sel_i (wbs_sel_i ), - .wbm_dat_o (wbs_dat_o ), - .wbm_ack_o (wbs_ack_o ), - .wbm_err_o ( ), + .wbm_rst_i (wb_rst_i ), + .wbm_clk_i (wb_clk_i ), + .wbm_cyc_i (wbs_cyc_i ), + .wbm_stb_i (wbs_stb_i ), + .wbm_adr_i (wbs_adr_i ), + .wbm_we_i (wbs_we_i ), + .wbm_dat_i (wbs_dat_i ), + .wbm_sel_i (wbs_sel_i ), + .wbm_dat_o (wbs_dat_o ), + .wbm_ack_o (wbs_ack_o ), + .wbm_err_o ( ), // Clock Skeq Adjust - .wbd_clk_int (wbd_clk_int ), - .wbd_clk_wh (wbd_clk_wh ), - .cfg_cska_wh (cfg_cska_wh ), + .wbd_clk_int (wbd_clk_int ), + .wbd_clk_wh (wbd_clk_wh ), + .cfg_cska_wh (cfg_cska_wh ), // Slave Port - .wbs_clk_out (wbd_clk_int ), - .wbs_clk_i (wbd_clk_wh ), - .wbs_cyc_o (wbd_int_cyc_i ), - .wbs_stb_o (wbd_int_stb_i ), - .wbs_adr_o (wbd_int_adr_i ), - .wbs_we_o (wbd_int_we_i ), - .wbs_dat_o (wbd_int_dat_i ), - .wbs_sel_o (wbd_int_sel_i ), - .wbs_dat_i (wbd_int_dat_o ), - .wbs_ack_i (wbd_int_ack_o ), - .wbs_err_i (wbd_int_err_o ), + .wbs_clk_out (wbd_clk_int ), + .wbs_clk_i (wbd_clk_wh ), + .wbs_cyc_o (wbd_int_cyc_i ), + .wbs_stb_o (wbd_int_stb_i ), + .wbs_adr_o (wbd_int_adr_i ), + .wbs_we_o (wbd_int_we_i ), + .wbs_dat_o (wbd_int_dat_i ), + .wbs_sel_o (wbd_int_sel_i ), + .wbs_dat_i (wbd_int_dat_o ), + .wbs_ack_i (wbd_int_ack_o ), + .wbs_err_i (wbd_int_err_o ), - .cfg_clk_ctrl1 (cfg_clk_ctrl1 ), - .cfg_clk_ctrl2 (cfg_clk_ctrl2 ), + .cfg_clk_ctrl1 (cfg_clk_ctrl1 ), + .cfg_clk_ctrl2 (cfg_clk_ctrl2 ), - .la_data_in (la_data_in[17:0] ), + .la_data_in (la_data_in[17:0] ), - .uartm_rxd (uartm_rxd ), - .uartm_txd (uartm_txd ) + .uartm_rxd (uartm_rxd ), + .uartm_txd (uartm_txd ) ); @@ -752,267 +640,255 @@ //------------------------------------------------------------------------------ ycr1_top_wb u_riscv_top ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .wbd_clk_int (wbd_clk_risc_rp ), - .cfg_cska_riscv (cfg_cska_riscv_rp ), - .wbd_clk_riscv (wbd_clk_riscv_skew ), + .wbd_clk_int (wbd_clk_risc_rp ), + .cfg_cska_riscv (cfg_cska_riscv_rp ), + .wbd_clk_riscv (wbd_clk_riscv_skew ), // Reset - .pwrup_rst_n (wbd_int_rst_n ), - .rst_n (wbd_int_rst_n ), - .cpu_rst_n (cpu_rst_n ), - .riscv_debug (riscv_debug ), + .pwrup_rst_n (wbd_int_rst_n ), + .rst_n (wbd_int_rst_n ), + .cpu_rst_n (cpu_rst_n ), + .riscv_debug (riscv_debug ), // Clock - .core_clk (cpu_clk ), - .rtc_clk (rtc_clk ), + .core_clk_mclk (cpu_clk ), + .core_clk (cpu_clk ), + .rtc_clk (rtc_clk ), // Fuses - .fuse_mhartid (fuse_mhartid_rp ), + .fuse_mhartid (fuse_mhartid_rp ), // IRQ - .irq_lines (irq_lines_rp ), - .soft_irq (soft_irq_rp ), // TODO - Interrupts + .irq_lines (irq_lines_rp ), + .soft_irq (soft_irq_rp ), // TODO - Interrupts // DFT - // .test_mode (1'b0 ), // Moved inside IP - // .test_rst_n (1'b1 ), // Moved inside IP + // .test_mode (1'b0 ), // Moved inside IP + // .test_rst_n (1'b1 ), // Moved inside IP -`ifndef SCR1_TCM_MEM - // SRAM-0 PORT-0 - .sram0_clk0 (sram0_clk0 ), - .sram0_csb0 (sram0_csb0 ), - .sram0_web0 (sram0_web0 ), - .sram0_addr0 (sram0_addr0 ), - .sram0_wmask0 (sram0_wmask0 ), - .sram0_din0 (sram0_din0 ), - .sram0_dout0 (sram0_dout0 ), - - // SRAM-0 PORT-0 - .sram0_clk1 (sram0_clk1 ), - .sram0_csb1 (sram0_csb1 ), - .sram0_addr1 (sram0_addr1 ), - .sram0_dout1 (sram0_dout1 ), +`ifndef YCR1_TCM_MEM + // DFFRAM I/F + .tcm_dffram_clk0 (tcm_dffram_clk0 ), // CLK + .tcm_dffram_cs0 (tcm_dffram_cs0 ), // Chip Select + .tcm_dffram_addr0 (tcm_dffram_addr0 ), // Address + .tcm_dffram_wmask0 (tcm_dffram_wmask0 ), // Write Mask + .tcm_dffram_din0 (tcm_dffram_din0 ), // Write Data + .tcm_dffram_dout0 (tcm_dffram_dout0 ), // Read Data + + .tcm_dffram_clk1 (tcm_dffram_clk1 ), // CLK + .tcm_dffram_cs1 (tcm_dffram_cs1 ), // Chip Select + .tcm_dffram_addr1 (tcm_dffram_addr1 ), // Address + .tcm_dffram_wmask1 (tcm_dffram_wmask1 ), // Write Mask + .tcm_dffram_din1 (tcm_dffram_din1 ), // Write Data + .tcm_dffram_dout1 (tcm_dffram_dout1 ), // Read Data - // // SRAM-1 PORT-0 - // .sram1_clk0 (sram1_clk0 ), - // .sram1_csb0 (sram1_csb0 ), - // .sram1_web0 (sram1_web0 ), - // .sram1_addr0 (sram1_addr0 ), - // .sram1_wmask0 (sram1_wmask0 ), - // .sram1_din0 (sram1_din0 ), - // .sram1_dout0 (sram1_dout0 ), - // - // // SRAM PORT-0 - // .sram1_clk1 (sram1_clk1 ), - // .sram1_csb1 (sram1_csb1 ), - // .sram1_addr1 (sram1_addr1 ), - // .sram1_dout1 (sram1_dout1 ), `endif - .wb_rst_n (wbd_int_rst_n ), - .wb_clk (wbd_clk_riscv_skew ), + .wb_rst_n (wbd_int_rst_n ), + .wb_clk (wbd_clk_riscv_skew ), // Instruction cache memory interface - .wb_icache_stb_o (wbd_riscv_icache_stb_i ), - .wb_icache_adr_o (wbd_riscv_icache_adr_i ), - .wb_icache_we_o (wbd_riscv_icache_we_i ), - .wb_icache_sel_o (wbd_riscv_icache_sel_i ), - .wb_icache_bl_o (wbd_riscv_icache_bl_i ), - .wb_icache_bry_o (wbd_riscv_icache_bry_i ), - .wb_icache_dat_i (wbd_riscv_icache_dat_o ), - .wb_icache_ack_i (wbd_riscv_icache_ack_o ), - .wb_icache_lack_i (wbd_riscv_icache_lack_o ), - .wb_icache_err_i (wbd_riscv_icache_err_o ), + .wb_icache_stb_o (wbd_riscv_icache_stb_i ), + .wb_icache_adr_o (wbd_riscv_icache_adr_i ), + .wb_icache_we_o (wbd_riscv_icache_we_i ), + .wb_icache_sel_o (wbd_riscv_icache_sel_i ), + .wb_icache_bl_o (wbd_riscv_icache_bl_i ), + .wb_icache_bry_o (wbd_riscv_icache_bry_i ), + .wb_icache_dat_i (wbd_riscv_icache_dat_o ), + .wb_icache_ack_i (wbd_riscv_icache_ack_o ), + .wb_icache_lack_i (wbd_riscv_icache_lack_o ), + .wb_icache_err_i (wbd_riscv_icache_err_o ), - .icache_mem_clk0 (icache_mem_clk0 ), // CLK - .icache_mem_csb0 (icache_mem_csb0 ), // CS# - .icache_mem_web0 (icache_mem_web0 ), // WE# - .icache_mem_addr0 (icache_mem_addr0 ), // Address - .icache_mem_wmask0 (icache_mem_wmask0 ), // WMASK# - .icache_mem_din0 (icache_mem_din0 ), // Write Data -// .icache_mem_dout0 (icache_mem_dout0 ), // Read Data - - - .icache_mem_clk1 (icache_mem_clk1 ), // CLK - .icache_mem_csb1 (icache_mem_csb1 ), // CS# - .icache_mem_addr1 (icache_mem_addr1 ), // Address - .icache_mem_dout1 (icache_mem_dout1 ), // Read Data + // DFFRAM I/F + .icache_dffram_clk0 (icache_dffram_clk0 ), // CLK + .icache_dffram_cs0 (icache_dffram_cs0 ), // Chip Select + .icache_dffram_addr0 (icache_dffram_addr0 ), // Address + .icache_dffram_wmask0 (icache_dffram_wmask0 ), // Write Mask + .icache_dffram_din0 (icache_dffram_din0 ), // Write Data + .icache_dffram_dout0 (icache_dffram_dout0 ), // Read Data + + .icache_dffram_clk1 (icache_dffram_clk1 ), // CLK + .icache_dffram_cs1 (icache_dffram_cs1 ), // Chip Select + .icache_dffram_addr1 (icache_dffram_addr1 ), // Address + .icache_dffram_wmask1 (icache_dffram_wmask1 ), // Write Mask + .icache_dffram_din1 (icache_dffram_din1 ), // Write Data + .icache_dffram_dout1 (icache_dffram_dout1 ), // Read Data // Data cache memory interface - .wb_dcache_stb_o (wbd_riscv_dcache_stb_i ), - .wb_dcache_adr_o (wbd_riscv_dcache_adr_i ), - .wb_dcache_we_o (wbd_riscv_dcache_we_i ), - .wb_dcache_dat_o (wbd_riscv_dcache_dat_i ), - .wb_dcache_sel_o (wbd_riscv_dcache_sel_i ), - .wb_dcache_bl_o (wbd_riscv_dcache_bl_i ), - .wb_dcache_bry_o (wbd_riscv_dcache_bry_i ), - .wb_dcache_dat_i (wbd_riscv_dcache_dat_o ), - .wb_dcache_ack_i (wbd_riscv_dcache_ack_o ), - .wb_dcache_lack_i (wbd_riscv_dcache_lack_o ), - .wb_dcache_err_i (wbd_riscv_dcache_err_o ), + .wb_dcache_stb_o (wbd_riscv_dcache_stb_i ), + .wb_dcache_adr_o (wbd_riscv_dcache_adr_i ), + .wb_dcache_we_o (wbd_riscv_dcache_we_i ), + .wb_dcache_dat_o (wbd_riscv_dcache_dat_i ), + .wb_dcache_sel_o (wbd_riscv_dcache_sel_i ), + .wb_dcache_bl_o (wbd_riscv_dcache_bl_i ), + .wb_dcache_bry_o (wbd_riscv_dcache_bry_i ), + .wb_dcache_dat_i (wbd_riscv_dcache_dat_o ), + .wb_dcache_ack_i (wbd_riscv_dcache_ack_o ), + .wb_dcache_lack_i (wbd_riscv_dcache_lack_o ), + .wb_dcache_err_i (wbd_riscv_dcache_err_o ), - .dcache_mem_clk0 (dcache_mem_clk0 ), // CLK - .dcache_mem_csb0 (dcache_mem_csb0 ), // CS# - .dcache_mem_web0 (dcache_mem_web0 ), // WE# - .dcache_mem_addr0 (dcache_mem_addr0 ), // Address - .dcache_mem_wmask0 (dcache_mem_wmask0 ), // WMASK# - .dcache_mem_din0 (dcache_mem_din0 ), // Write Data - .dcache_mem_dout0 (dcache_mem_dout0 ), // Read Data - - - .dcache_mem_clk1 (dcache_mem_clk1 ), // CLK - .dcache_mem_csb1 (dcache_mem_csb1 ), // CS# - .dcache_mem_addr1 (dcache_mem_addr1 ), // Address - .dcache_mem_dout1 (dcache_mem_dout1 ), // Read Data + // DFFRAM I/F + .dcache_dffram_clk0 (dcache_dffram_clk0 ), // CLK + .dcache_dffram_cs0 (dcache_dffram_cs0 ), // Chip Select + .dcache_dffram_addr0 (dcache_dffram_addr0 ), // Address + .dcache_dffram_wmask0 (dcache_dffram_wmask0 ), // Write Mask + .dcache_dffram_din0 (dcache_dffram_din0 ), // Write Data + .dcache_dffram_dout0 (dcache_dffram_dout0 ), // Read Data + + .dcache_dffram_clk1 (dcache_dffram_clk1 ), // CLK + .dcache_dffram_cs1 (dcache_dffram_cs1 ), // Chip Select + .dcache_dffram_addr1 (dcache_dffram_addr1 ), // Address + .dcache_dffram_wmask1 (dcache_dffram_wmask1 ), // Write Mask + .dcache_dffram_din1 (dcache_dffram_din1 ), // Write Data + .dcache_dffram_dout1 (dcache_dffram_dout1 ), // Read Data // Data memory interface - .wbd_dmem_stb_o (wbd_riscv_dmem_stb_i ), - .wbd_dmem_adr_o (wbd_riscv_dmem_adr_i ), - .wbd_dmem_we_o (wbd_riscv_dmem_we_i ), - .wbd_dmem_dat_o (wbd_riscv_dmem_dat_i ), - .wbd_dmem_sel_o (wbd_riscv_dmem_sel_i ), - .wbd_dmem_dat_i (wbd_riscv_dmem_dat_o ), - .wbd_dmem_ack_i (wbd_riscv_dmem_ack_o ), - .wbd_dmem_err_i (wbd_riscv_dmem_err_o ) + .wbd_dmem_stb_o (wbd_riscv_dmem_stb_i ), + .wbd_dmem_adr_o (wbd_riscv_dmem_adr_i ), + .wbd_dmem_we_o (wbd_riscv_dmem_we_i ), + .wbd_dmem_dat_o (wbd_riscv_dmem_dat_i ), + .wbd_dmem_sel_o (wbd_riscv_dmem_sel_i ), + .wbd_dmem_dat_i (wbd_riscv_dmem_dat_o ), + .wbd_dmem_ack_i (wbd_riscv_dmem_ack_o ), + .wbd_dmem_err_i (wbd_riscv_dmem_err_o ) +); +`ifndef YCR1_TCM_MEM + +DFFRAM u_tcm_1KB_mem0 ( +`ifdef USE_POWER_PINS + .VPWR (vccd1 ),// area 1 1.8V supply + .VGND (vssd1 ),// area 1 digital ground +`endif + .CLK (tcm_dffram_clk0 ), + .WE (tcm_dffram_wmask0 ), + .EN (tcm_dffram_cs0 ), + .Di (tcm_dffram_din0 ), + .Do (tcm_dffram_dout0 ), + .A (tcm_dffram_addr0 ) ); -`ifndef SCR1_TCM_MEM -sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb( +DFFRAM u_tcm_1KB_mem1 ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// area 1 1.8V supply - .vssd1 (vssd1 ),// area 1 digital ground + .VPWR (vccd1 ),// area 1 1.8V supply + .VGND (vssd1 ),// area 1 digital ground `endif -// Port 0: RW - .clk0 (sram0_clk0 ), - .csb0 (sram0_csb0 ), - .web0 (sram0_web0 ), - .wmask0 (sram0_wmask0 ), - .addr0 (sram0_addr0 ), - .din0 (sram0_din0 ), - .dout0 (sram0_dout0 ), -// Port 1: R - .clk1 (sram0_clk1 ), - .csb1 (sram0_csb1 ), - .addr1 (sram0_addr1 ), - .dout1 (sram0_dout1 ) - ); + .CLK (tcm_dffram_clk1 ), + .WE (tcm_dffram_wmask1 ), + .EN (tcm_dffram_cs1 ), + .Di (tcm_dffram_din1 ), + .Do (tcm_dffram_dout1 ), + .A (tcm_dffram_addr1 ) +); -/*** -sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram1_2kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (sram1_clk0 ), - .csb0 (sram1_csb0 ), - .web0 (sram1_web0 ), - .wmask0 (sram1_wmask0 ), - .addr0 (sram1_addr0 ), - .din0 (sram1_din0 ), - .dout0 (sram1_dout0 ), -// Port 1: R - .clk1 (sram1_clk1 ), - .csb1 (sram1_csb1 ), - .addr1 (sram1_addr1 ), - .dout1 (sram1_dout1 ) - ); -***/ `endif -sky130_sram_2kbyte_1rw1r_32x512_8 u_icache_2kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (icache_mem_clk0 ), - .csb0 (icache_mem_csb0 ), - .web0 (icache_mem_web0 ), - .wmask0 (icache_mem_wmask0 ), - .addr0 (icache_mem_addr0 ), - .din0 (icache_mem_din0 ), - .dout0 ( ), -// Port 1: R - .clk1 (icache_mem_clk1 ), - .csb1 (icache_mem_csb1 ), - .addr1 (icache_mem_addr1 ), - .dout1 (icache_mem_dout1 ) - ); -sky130_sram_2kbyte_1rw1r_32x512_8 u_dcache_2kb( +DFFRAM u_icache_1KB_mem0 ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .VPWR (vccd1 ),// area 1 1.8V supply + .VGND (vssd1 ),// area 1 digital ground `endif -// Port 0: RW - .clk0 (dcache_mem_clk0 ), - .csb0 (dcache_mem_csb0 ), - .web0 (dcache_mem_web0 ), - .wmask0 (dcache_mem_wmask0 ), - .addr0 (dcache_mem_addr0 ), - .din0 (dcache_mem_din0 ), - .dout0 (dcache_mem_dout0 ), -// Port 1: R - .clk1 (dcache_mem_clk1 ), - .csb1 (dcache_mem_csb1 ), - .addr1 (dcache_mem_addr1 ), - .dout1 (dcache_mem_dout1 ) - ); + .CLK (icache_dffram_clk0 ), + .WE (icache_dffram_wmask0 ), + .EN (icache_dffram_cs0 ), + .Di (icache_dffram_din0 ), + .Do (icache_dffram_dout0 ), + .A (icache_dffram_addr0 ) +); + +DFFRAM u_icache_1KB_mem1 ( +`ifdef USE_POWER_PINS + .VPWR (vccd1 ),// area 1 1.8V supply + .VGND (vssd1 ),// area 1 digital ground +`endif + .CLK (icache_dffram_clk1 ), + .WE (icache_dffram_wmask1 ), + .EN (icache_dffram_cs1 ), + .Di (icache_dffram_din1 ), + .Do (icache_dffram_dout1 ), + .A (icache_dffram_addr1 ) +); + + +DFFRAM u_dcache_1KB_mem0 ( +`ifdef USE_POWER_PINS + .VPWR (vccd1 ),// area 1 1.8V supply + .VGND (vssd1 ),// area 1 digital ground +`endif + .CLK (dcache_dffram_clk0 ), + .WE (dcache_dffram_wmask0 ), + .EN (dcache_dffram_cs0 ), + .Di (dcache_dffram_din0 ), + .Do (dcache_dffram_dout0 ), + .A (dcache_dffram_addr0 ) +); + +DFFRAM u_dcache_1KB_mem1 ( +`ifdef USE_POWER_PINS + .VPWR (vccd1 ),// area 1 1.8V supply + .VGND (vssd1 ),// area 1 digital ground +`endif + .CLK (dcache_dffram_clk1 ), + .WE (dcache_dffram_wmask1 ), + .EN (dcache_dffram_cs1 ), + .Di (dcache_dffram_din1 ), + .Do (dcache_dffram_dout1 ), + .A (dcache_dffram_addr1 ) +); /********************************************************* * SPI Master -* This is implementation of an SPI master that is controlled via an AXI bus . +* This is of an SPI master that is controlled via an AXI bus . * It has FIFOs for transmitting and receiving data. * It supports both the normal SPI mode and QPI mode with 4 data lines. * *******************************************************/ qspim_top -# ( +# ( `ifndef SYNTHESIS .WB_WIDTH (WB_WIDTH ) `endif ) u_qspi_master ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .mclk (wbd_clk_spi ), - .rst_n (qspim_rst_n ), + .mclk (wbd_clk_spi ), + .rst_n (qspim_rst_n ), // Clock Skew Adjust - .cfg_cska_sp_co (cfg_cska_qspi_co_rp ), - .cfg_cska_spi (cfg_cska_qspi_rp ), - .wbd_clk_int (wbd_clk_qspi_rp ), - .wbd_clk_spi (wbd_clk_spi ), + .cfg_cska_sp_co (cfg_cska_qspi_co_rp ), + .cfg_cska_spi (cfg_cska_qspi_rp ), + .wbd_clk_int (wbd_clk_qspi_rp ), + .wbd_clk_spi (wbd_clk_spi ), - .wbd_stb_i (wbd_spim_stb_o ), - .wbd_adr_i (wbd_spim_adr_o ), - .wbd_we_i (wbd_spim_we_o ), - .wbd_dat_i (wbd_spim_dat_o ), - .wbd_sel_i (wbd_spim_sel_o ), - .wbd_bl_i (wbd_spim_bl_o ), - .wbd_bry_i (wbd_spim_bry_o ), - .wbd_dat_o (wbd_spim_dat_i ), - .wbd_ack_o (wbd_spim_ack_i ), - .wbd_lack_o (wbd_spim_lack_i ), - .wbd_err_o (wbd_spim_err_i ), + .wbd_stb_i (wbd_spim_stb_o ), + .wbd_adr_i (wbd_spim_adr_o ), + .wbd_we_i (wbd_spim_we_o ), + .wbd_dat_i (wbd_spim_dat_o ), + .wbd_sel_i (wbd_spim_sel_o ), + .wbd_bl_i (wbd_spim_bl_o ), + .wbd_bry_i (wbd_spim_bry_o ), + .wbd_dat_o (wbd_spim_dat_i ), + .wbd_ack_o (wbd_spim_ack_i ), + .wbd_lack_o (wbd_spim_lack_i ), + .wbd_err_o (wbd_spim_err_i ), - .spi_debug (spi_debug ), + .spi_debug (spi_debug ), // Pad Interface - .spi_sdi (sflash_di ), - .spi_clk (sflash_sck ), - .spi_csn (spi_csn ), - .spi_sdo (sflash_do ), - .spi_oen (sflash_oen ) + .spi_sdi (sflash_di ), + .spi_clk (sflash_sck ), + .spi_csn (spi_csn ), + .spi_sdo (sflash_do ), + .spi_oen (sflash_oen ) ); @@ -1020,555 +896,289 @@ wb_interconnect #( `ifndef SYNTHESIS - .CH_CLK_WD (8 ), - .CH_DATA_WD (116 ) + .CH_CLK_WD (4 ), + .CH_DATA_WD (69 ) `endif ) u_intercon ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .ch_clk_in ({ - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int, - wbd_clk_int} ), - .ch_clk_out ({ - wbd_clk_mbist4_rp, - wbd_clk_mbist3_rp, - wbd_clk_mbist2_rp, - wbd_clk_mbist1_rp, - wbd_clk_pinmux_rp, - wbd_clk_uart_rp, - wbd_clk_qspi_rp, - wbd_clk_risc_rp} ), - .ch_data_in ({ - bist_error_cnt3[3:0], - bist_correct[3], - bist_error[3], - - bist_error_cnt2[3:0], - bist_correct[2], - bist_error[2], - - bist_error_cnt1[3:0], - bist_correct[1], - bist_error[1], - - bist_error_cnt0[3:0], - bist_correct[0], - bist_error[0], - bist_done, - bist_sdo, - bist_shift, - bist_sdi, - bist_load, - bist_run, - bist_en, + .ch_clk_in ({ + wbd_clk_int, + wbd_clk_int, + wbd_clk_int, + wbd_clk_int} ), + .ch_clk_out ({ + wbd_clk_pinmux_rp, + wbd_clk_uart_rp, + wbd_clk_qspi_rp, + wbd_clk_risc_rp} ), + .ch_data_in ({ + soft_irq, + irq_lines[15:0], + fuse_mhartid[31:0], - soft_irq, - irq_lines[15:0], - fuse_mhartid[31:0], + cfg_cska_qspi_co[3:0], + cfg_cska_pinmux[3:0], + cfg_cska_uart[3:0], + cfg_cska_qspi[3:0], + cfg_cska_riscv[3:0] + } ), + .ch_data_out ({ - cfg_cska_mbist4[3:0], - cfg_cska_mbist3[3:0], - cfg_cska_mbist2[3:0], - cfg_cska_mbist1[3:0], - cfg_cska_qspi_co[3:0], - cfg_cska_pinmux[3:0], - cfg_cska_uart[3:0], - cfg_cska_qspi[3:0], - cfg_cska_riscv[3:0] - } ), - .ch_data_out ({ - bist_error_cnt3_rp[3:0], - bist_correct_rp[3], - bist_error_rp[3], + soft_irq_rp, + irq_lines_rp[15:0], + fuse_mhartid_rp[31:0], - bist_error_cnt2_rp[3:0], - bist_correct_rp[2], - bist_error_rp[2], - - bist_error_cnt1_rp[3:0], - bist_correct_rp[1], - bist_error_rp[1], - - bist_error_cnt0_rp[3:0], - bist_correct_rp[0], - bist_error_rp[0], - bist_done_rp, - bist_sdo_rp, - bist_shift_rp, - bist_sdi_rp, - bist_load_rp, - bist_run_rp, - bist_en_rp, - - soft_irq_rp, - irq_lines_rp[15:0], - fuse_mhartid_rp[31:0], - - cfg_cska_mbist4_rp[3:0], - cfg_cska_mbist3_rp[3:0], - cfg_cska_mbist2_rp[3:0], - cfg_cska_mbist1_rp[3:0], - cfg_cska_qspi_co_rp[3:0], - cfg_cska_pinmux_rp[3:0], - cfg_cska_uart_rp[3:0], - cfg_cska_qspi_rp[3:0], - cfg_cska_riscv_rp[3:0] - }), + cfg_cska_qspi_co_rp[3:0], + cfg_cska_pinmux_rp[3:0], + cfg_cska_uart_rp[3:0], + cfg_cska_qspi_rp[3:0], + cfg_cska_riscv_rp[3:0] + } ), // Clock Skew adjust - .wbd_clk_int (wbd_clk_int ), - .cfg_cska_wi (cfg_cska_wi ), - .wbd_clk_wi (wbd_clk_wi_skew ), + .wbd_clk_int (wbd_clk_int ), + .cfg_cska_wi (cfg_cska_wi ), + .wbd_clk_wi (wbd_clk_wi_skew ), - .clk_i (wbd_clk_wi_skew ), - .rst_n (wbd_int_rst_n ), - .dcache_remap (dcache_remap ), - .boot_remap (boot_remap ), + .clk_i (wbd_clk_wi_skew ), + .rst_n (wbd_int_rst_n ), // Master 0 Interface - .m0_wbd_dat_i (wbd_int_dat_i ), - .m0_wbd_adr_i (wbd_int_adr_i ), - .m0_wbd_sel_i (wbd_int_sel_i ), - .m0_wbd_we_i (wbd_int_we_i ), - .m0_wbd_cyc_i (wbd_int_cyc_i ), - .m0_wbd_stb_i (wbd_int_stb_i ), - .m0_wbd_dat_o (wbd_int_dat_o ), - .m0_wbd_ack_o (wbd_int_ack_o ), - .m0_wbd_err_o (wbd_int_err_o ), + .m0_wbd_dat_i (wbd_int_dat_i ), + .m0_wbd_adr_i (wbd_int_adr_i ), + .m0_wbd_sel_i (wbd_int_sel_i ), + .m0_wbd_we_i (wbd_int_we_i ), + .m0_wbd_cyc_i (wbd_int_cyc_i ), + .m0_wbd_stb_i (wbd_int_stb_i ), + .m0_wbd_dat_o (wbd_int_dat_o ), + .m0_wbd_ack_o (wbd_int_ack_o ), + .m0_wbd_err_o (wbd_int_err_o ), // Master 1 Interface - .m1_wbd_dat_i (wbd_riscv_dmem_dat_i ), - .m1_wbd_adr_i (wbd_riscv_dmem_adr_i ), - .m1_wbd_sel_i (wbd_riscv_dmem_sel_i ), - .m1_wbd_we_i (wbd_riscv_dmem_we_i ), - .m1_wbd_cyc_i (wbd_riscv_dmem_stb_i ), - .m1_wbd_stb_i (wbd_riscv_dmem_stb_i ), - .m1_wbd_dat_o (wbd_riscv_dmem_dat_o ), - .m1_wbd_ack_o (wbd_riscv_dmem_ack_o ), - .m1_wbd_err_o (wbd_riscv_dmem_err_o ), + .m1_wbd_dat_i (wbd_riscv_dmem_dat_i ), + .m1_wbd_adr_i (wbd_riscv_dmem_adr_i ), + .m1_wbd_sel_i (wbd_riscv_dmem_sel_i ), + .m1_wbd_we_i (wbd_riscv_dmem_we_i ), + .m1_wbd_cyc_i (wbd_riscv_dmem_stb_i ), + .m1_wbd_stb_i (wbd_riscv_dmem_stb_i ), + .m1_wbd_dat_o (wbd_riscv_dmem_dat_o ), + .m1_wbd_ack_o (wbd_riscv_dmem_ack_o ), + .m1_wbd_err_o (wbd_riscv_dmem_err_o ), // Master 2 Interface - .m2_wbd_dat_i (wbd_riscv_dcache_dat_i ), - .m2_wbd_adr_i (wbd_riscv_dcache_adr_i ), - .m2_wbd_sel_i (wbd_riscv_dcache_sel_i ), - .m2_wbd_bl_i (wbd_riscv_dcache_bl_i ), - .m2_wbd_bry_i (wbd_riscv_dcache_bry_i ), - .m2_wbd_we_i (wbd_riscv_dcache_we_i ), - .m2_wbd_cyc_i (wbd_riscv_dcache_stb_i ), - .m2_wbd_stb_i (wbd_riscv_dcache_stb_i ), - .m2_wbd_dat_o (wbd_riscv_dcache_dat_o ), - .m2_wbd_ack_o (wbd_riscv_dcache_ack_o ), - .m2_wbd_lack_o (wbd_riscv_dcache_lack_o ), - .m2_wbd_err_o (wbd_riscv_dcache_err_o ), + .m2_wbd_dat_i (wbd_riscv_dcache_dat_i ), + .m2_wbd_adr_i (wbd_riscv_dcache_adr_i ), + .m2_wbd_sel_i (wbd_riscv_dcache_sel_i ), + .m2_wbd_bl_i (wbd_riscv_dcache_bl_i ), + .m2_wbd_bry_i (wbd_riscv_dcache_bry_i ), + .m2_wbd_we_i (wbd_riscv_dcache_we_i ), + .m2_wbd_cyc_i (wbd_riscv_dcache_stb_i ), + .m2_wbd_stb_i (wbd_riscv_dcache_stb_i ), + .m2_wbd_dat_o (wbd_riscv_dcache_dat_o ), + .m2_wbd_ack_o (wbd_riscv_dcache_ack_o ), + .m2_wbd_lack_o (wbd_riscv_dcache_lack_o ), + .m2_wbd_err_o (wbd_riscv_dcache_err_o ), // Master 3 Interface - .m3_wbd_adr_i (wbd_riscv_icache_adr_i ), - .m3_wbd_sel_i (wbd_riscv_icache_sel_i ), - .m3_wbd_bl_i (wbd_riscv_icache_bl_i ), - .m3_wbd_bry_i (wbd_riscv_icache_bry_i ), - .m3_wbd_we_i (wbd_riscv_icache_we_i ), - .m3_wbd_cyc_i (wbd_riscv_icache_stb_i ), - .m3_wbd_stb_i (wbd_riscv_icache_stb_i ), - .m3_wbd_dat_o (wbd_riscv_icache_dat_o ), - .m3_wbd_ack_o (wbd_riscv_icache_ack_o ), - .m3_wbd_lack_o (wbd_riscv_icache_lack_o ), - .m3_wbd_err_o (wbd_riscv_icache_err_o ), + .m3_wbd_adr_i (wbd_riscv_icache_adr_i ), + .m3_wbd_sel_i (wbd_riscv_icache_sel_i ), + .m3_wbd_bl_i (wbd_riscv_icache_bl_i ), + .m3_wbd_bry_i (wbd_riscv_icache_bry_i ), + .m3_wbd_we_i (wbd_riscv_icache_we_i ), + .m3_wbd_cyc_i (wbd_riscv_icache_stb_i ), + .m3_wbd_stb_i (wbd_riscv_icache_stb_i ), + .m3_wbd_dat_o (wbd_riscv_icache_dat_o ), + .m3_wbd_ack_o (wbd_riscv_icache_ack_o ), + .m3_wbd_lack_o (wbd_riscv_icache_lack_o ), + .m3_wbd_err_o (wbd_riscv_icache_err_o ), // Slave 0 Interface - // .s0_wbd_err_i (1'b0 ), - Moved inside IP - .s0_wbd_dat_i (wbd_spim_dat_i ), - .s0_wbd_ack_i (wbd_spim_ack_i ), - .s0_wbd_lack_i (wbd_spim_lack_i ), - .s0_wbd_dat_o (wbd_spim_dat_o ), - .s0_wbd_adr_o (wbd_spim_adr_o ), - .s0_wbd_bry_o (wbd_spim_bry_o ), - .s0_wbd_bl_o (wbd_spim_bl_o ), - .s0_wbd_sel_o (wbd_spim_sel_o ), - .s0_wbd_we_o (wbd_spim_we_o ), - .s0_wbd_cyc_o (wbd_spim_cyc_o ), - .s0_wbd_stb_o (wbd_spim_stb_o ), + // .s0_wbd_err_i (1'b0 ), - Moved inside IP + .s0_wbd_dat_i (wbd_spim_dat_i ), + .s0_wbd_ack_i (wbd_spim_ack_i ), + .s0_wbd_lack_i (wbd_spim_lack_i ), + .s0_wbd_dat_o (wbd_spim_dat_o ), + .s0_wbd_adr_o (wbd_spim_adr_o ), + .s0_wbd_bry_o (wbd_spim_bry_o ), + .s0_wbd_bl_o (wbd_spim_bl_o ), + .s0_wbd_sel_o (wbd_spim_sel_o ), + .s0_wbd_we_o (wbd_spim_we_o ), + .s0_wbd_cyc_o (wbd_spim_cyc_o ), + .s0_wbd_stb_o (wbd_spim_stb_o ), // Slave 1 Interface - // .s1_wbd_err_i (1'b0 ), - Moved inside IP - .s1_wbd_dat_i (wbd_uart_dat_i ), - .s1_wbd_ack_i (wbd_uart_ack_i ), - .s1_wbd_dat_o (wbd_uart_dat_o ), - .s1_wbd_adr_o (wbd_uart_adr_o ), - .s1_wbd_sel_o (wbd_uart_sel_o ), - .s1_wbd_we_o (wbd_uart_we_o ), - .s1_wbd_cyc_o (wbd_uart_cyc_o ), - .s1_wbd_stb_o (wbd_uart_stb_o ), + // .s1_wbd_err_i (1'b0 ), - Moved inside IP + .s1_wbd_dat_i (wbd_uart_dat_i ), + .s1_wbd_ack_i (wbd_uart_ack_i ), + .s1_wbd_dat_o (wbd_uart_dat_o ), + .s1_wbd_adr_o (wbd_uart_adr_o ), + .s1_wbd_sel_o (wbd_uart_sel_o ), + .s1_wbd_we_o (wbd_uart_we_o ), + .s1_wbd_cyc_o (wbd_uart_cyc_o ), + .s1_wbd_stb_o (wbd_uart_stb_o ), // Slave 2 Interface - // .s2_wbd_err_i (1'b0 ), - Moved inside IP - .s2_wbd_dat_i (wbd_glbl_dat_i ), - .s2_wbd_ack_i (wbd_glbl_ack_i ), - .s2_wbd_dat_o (wbd_glbl_dat_o ), - .s2_wbd_adr_o (wbd_glbl_adr_o ), - .s2_wbd_sel_o (wbd_glbl_sel_o ), - .s2_wbd_we_o (wbd_glbl_we_o ), - .s2_wbd_cyc_o (wbd_glbl_cyc_o ), - .s2_wbd_stb_o (wbd_glbl_stb_o ), + // .s2_wbd_err_i (1'b0 ), - Moved inside IP + .s2_wbd_dat_i (wbd_glbl_dat_i ), + .s2_wbd_ack_i (wbd_glbl_ack_i ), + .s2_wbd_dat_o (wbd_glbl_dat_o ), + .s2_wbd_adr_o (wbd_glbl_adr_o ), + .s2_wbd_sel_o (wbd_glbl_sel_o ), + .s2_wbd_we_o (wbd_glbl_we_o ), + .s2_wbd_cyc_o (wbd_glbl_cyc_o ), + .s2_wbd_stb_o (wbd_glbl_stb_o ) - // Slave 3 Interface - // .s3_wbd_err_i (1'b0 ), - Moved inside IP - .s3_wbd_dat_i (wbd_mbist_dat_i ), - .s3_wbd_ack_i (wbd_mbist_ack_i ), - .s3_wbd_lack_i (wbd_mbist_lack_i ), - .s3_wbd_dat_o (wbd_mbist_dat_o ), - .s3_wbd_adr_o (wbd_mbist_adr_o ), - .s3_wbd_sel_o (wbd_mbist_sel_o ), - .s3_wbd_bry_o (wbd_mbist_bry_o ), - .s3_wbd_bl_o (wbd_mbist_bl_o ), - .s3_wbd_we_o (wbd_mbist_we_o ), - .s3_wbd_cyc_o (wbd_mbist_cyc_o ), - .s3_wbd_stb_o (wbd_mbist_stb_o ) ); uart_i2c_usb_spi_top u_uart_i2c_usb_spi ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .wbd_clk_int (wbd_clk_uart_rp ), - .cfg_cska_uart (cfg_cska_uart_rp ), - .wbd_clk_uart (wbd_clk_uart_skew ), + .wbd_clk_int (wbd_clk_uart_rp ), + .cfg_cska_uart (cfg_cska_uart_rp ), + .wbd_clk_uart (wbd_clk_uart_skew ), - .uart_rstn (uart_rst_n ), // uart reset - .i2c_rstn (i2c_rst_n ), // i2c reset - .usb_rstn (usb_rst_n ), // USB reset - .spi_rstn (sspim_rst_n ), // SPI reset - .app_clk (wbd_clk_uart_skew ), - .usb_clk (usb_clk ), + .uart_rstn (uart_rst_n ), // uart reset + .i2c_rstn (i2c_rst_n ), // i2c reset + .usb_rstn (usb_rst_n ), // USB reset + .spi_rstn (sspim_rst_n ), // SPI reset + .app_clk (wbd_clk_uart_skew ), + .usb_clk (usb_clk ), // Reg Bus Interface Signal - .reg_cs (wbd_uart_stb_o ), - .reg_wr (wbd_uart_we_o ), - .reg_addr (wbd_uart_adr_o[7:0] ), - .reg_wdata (wbd_uart_dat_o ), - .reg_be (wbd_uart_sel_o ), + .reg_cs (wbd_uart_stb_o ), + .reg_wr (wbd_uart_we_o ), + .reg_addr (wbd_uart_adr_o[7:0] ), + .reg_wdata (wbd_uart_dat_o ), + .reg_be (wbd_uart_sel_o ), // Outputs - .reg_rdata (wbd_uart_dat_i ), - .reg_ack (wbd_uart_ack_i ), + .reg_rdata (wbd_uart_dat_i ), + .reg_ack (wbd_uart_ack_i ), // Pad interface - .scl_pad_i (i2cm_clk_i ), - .scl_pad_o (i2cm_clk_o ), - .scl_pad_oen_o (i2cm_clk_oen ), + .scl_pad_i (i2cm_clk_i ), + .scl_pad_o (i2cm_clk_o ), + .scl_pad_oen_o (i2cm_clk_oen ), - .sda_pad_i (i2cm_data_i ), - .sda_pad_o (i2cm_data_o ), - .sda_padoen_o (i2cm_data_oen ), + .sda_pad_i (i2cm_data_i ), + .sda_pad_o (i2cm_data_o ), + .sda_padoen_o (i2cm_data_oen ), - .i2cm_intr_o (i2cm_intr_o ), + .i2cm_intr_o (i2cm_intr_o ), - .uart_rxd (uart_rxd ), - .uart_txd (uart_txd ), + .uart_rxd (uart_rxd ), + .uart_txd (uart_txd ), - .usb_in_dp (usb_dp_i ), - .usb_in_dn (usb_dn_i ), + .usb_in_dp (usb_dp_i ), + .usb_in_dn (usb_dn_i ), - .usb_out_dp (usb_dp_o ), - .usb_out_dn (usb_dn_o ), - .usb_out_tx_oen (usb_oen ), + .usb_out_dp (usb_dp_o ), + .usb_out_dn (usb_dn_o ), + .usb_out_tx_oen (usb_oen ), - .usb_intr_o (usb_intr_o ), + .usb_intr_o (usb_intr_o ), // SPIM Master - .sspim_sck (sspim_sck ), - .sspim_so (sspim_so ), - .sspim_si (sspim_si ), - .sspim_ssn (sspim_ssn ) + .sspim_sck (sspim_sck ), + .sspim_so (sspim_so ), + .sspim_si (sspim_si ), + .sspim_ssn (sspim_ssn ) ); - pinmux u_pinmux( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif //clk skew adjust - .cfg_cska_pinmux (cfg_cska_pinmux_rp ), - .wbd_clk_int (wbd_clk_pinmux_rp ), - .wbd_clk_pinmux (wbd_clk_pinmux_skew ), + .cfg_cska_pinmux (cfg_cska_pinmux_rp ), + .wbd_clk_int (wbd_clk_pinmux_rp ), + .wbd_clk_pinmux (wbd_clk_pinmux_skew ), // System Signals // Inputs - .mclk (wbd_clk_pinmux_skew ), - .h_reset_n (wbd_int_rst_n ), + .mclk (wbd_clk_pinmux_skew ), + .h_reset_n (wbd_int_rst_n ), // Reg Bus Interface Signal - .reg_cs (wbd_glbl_stb_o ), - .reg_wr (wbd_glbl_we_o ), - .reg_addr (wbd_glbl_adr_o ), - .reg_wdata (wbd_glbl_dat_o ), - .reg_be (wbd_glbl_sel_o ), + .reg_cs (wbd_glbl_stb_o ), + .reg_wr (wbd_glbl_we_o ), + .reg_addr (wbd_glbl_adr_o ), + .reg_wdata (wbd_glbl_dat_o ), + .reg_be (wbd_glbl_sel_o ), // Outputs - .reg_rdata (wbd_glbl_dat_i ), - .reg_ack (wbd_glbl_ack_i ), + .reg_rdata (wbd_glbl_dat_i ), + .reg_ack (wbd_glbl_ack_i ), // Risc configuration - .fuse_mhartid (fuse_mhartid ), - .irq_lines (irq_lines ), - .soft_irq (soft_irq ), - .user_irq (user_irq ), - .usb_intr (usb_intr_o ), - .i2cm_intr (i2cm_intr_o ), + .fuse_mhartid (fuse_mhartid ), + .irq_lines (irq_lines ), + .soft_irq (soft_irq ), + .user_irq (user_irq ), + .usb_intr (usb_intr_o ), + .i2cm_intr (i2cm_intr_o ), // Digital IO - .digital_io_out (io_out ), - .digital_io_oen (io_oeb ), - .digital_io_in (io_in ), + .digital_io_out (io_out ), + .digital_io_oen (io_oeb ), + .digital_io_in (io_in ), // SFLASH I/F - .sflash_sck (sflash_sck ), - .sflash_ss (spi_csn ), - .sflash_oen (sflash_oen ), - .sflash_do (sflash_do ), - .sflash_di (sflash_di ), + .sflash_sck (sflash_sck ), + .sflash_ss (spi_csn ), + .sflash_oen (sflash_oen ), + .sflash_do (sflash_do ), + .sflash_di (sflash_di ), // USB I/F - .usb_dp_o (usb_dp_o ), - .usb_dn_o (usb_dn_o ), - .usb_oen (usb_oen ), - .usb_dp_i (usb_dp_i ), - .usb_dn_i (usb_dn_i ), + .usb_dp_o (usb_dp_o ), + .usb_dn_o (usb_dn_o ), + .usb_oen (usb_oen ), + .usb_dp_i (usb_dp_i ), + .usb_dn_i (usb_dn_i ), // UART I/F - .uart_txd (uart_txd ), - .uart_rxd (uart_rxd ), + .uart_txd (uart_txd ), + .uart_rxd (uart_rxd ), // I2CM I/F - .i2cm_clk_o (i2cm_clk_o ), - .i2cm_clk_i (i2cm_clk_i ), - .i2cm_clk_oen (i2cm_clk_oen ), - .i2cm_data_oen (i2cm_data_oen ), - .i2cm_data_o (i2cm_data_o ), - .i2cm_data_i (i2cm_data_i ), + .i2cm_clk_o (i2cm_clk_o ), + .i2cm_clk_i (i2cm_clk_i ), + .i2cm_clk_oen (i2cm_clk_oen ), + .i2cm_data_oen (i2cm_data_oen ), + .i2cm_data_o (i2cm_data_o ), + .i2cm_data_i (i2cm_data_i ), // SPI MASTER - .spim_sck (sspim_sck ), - .spim_ss (sspim_ssn ), - .spim_miso (sspim_so ), - .spim_mosi (sspim_si ), + .spim_sck (sspim_sck ), + .spim_ss (sspim_ssn ), + .spim_miso (sspim_so ), + .spim_mosi (sspim_si ), // UART MASTER I/F - .uartm_rxd (uartm_rxd ), - .uartm_txd (uartm_txd ), + .uartm_rxd (uartm_rxd ), + .uartm_txd (uartm_txd ), - .pulse1m_mclk (pulse1m_mclk ), + .pulse1m_mclk (pulse1m_mclk ), - .pinmux_debug (pinmux_debug ), + .pinmux_debug (pinmux_debug ) - // BIST I/F - .bist_en (bist_en ), - .bist_run (bist_run ), - .bist_load (bist_load ), - - .bist_sdi (bist_sdi ), - .bist_shift (bist_shift ), - .bist_sdo (bist_sdo_rp ), - - .bist_done (bist_done_rp ), - .bist_error (bist_error_rp ), - .bist_correct (bist_correct_rp ), - .bist_error_cnt0 (bist_error_cnt0_rp ), - .bist_error_cnt1 (bist_error_cnt1_rp ), - .bist_error_cnt2 (bist_error_cnt2_rp ), - .bist_error_cnt3 (bist_error_cnt3_rp ) ); -//------------- MBIST - 512x32 ---- - -mbist_wrapper #( - `ifndef SYNTHESIS - .BIST_NO_SRAM (4 ), - .BIST_ADDR_WD (BIST1_ADDR_WD-2 ), - .BIST_DATA_WD (BIST_DATA_WD ), - .BIST_ADDR_START (9'h000 ), - .BIST_ADDR_END (9'h1FB ), - .BIST_REPAIR_ADDR_START (9'h1FC ), - .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST1_ADDR_WD-2 ) - `endif - ) - u_mbist ( - -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - - // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist1_rp ), - .cfg_cska_mbist (cfg_cska_mbist1_rp ), - .wbd_clk_mbist (wbd_clk_mbist_skew ), - - // WB I/F - .wb_clk2_i (wbd_clk_mbist_skew ), - .wb_clk_i (wbd_clk_mbist_skew ), - .wb_stb_i (wbd_mbist_stb_o), - .wb_cs_i (wbd_mbist_adr_o[12:11]), - .wb_adr_i (wbd_mbist_adr_o[BIST1_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist_we_o ), - .wb_dat_i (wbd_mbist_dat_o), - .wb_sel_i (wbd_mbist_sel_o), - .wb_bl_i (wbd_mbist_bl_o), - .wb_bry_i (wbd_mbist_bry_o), - .wb_dat_o (wbd_mbist_dat_i), - .wb_ack_o (wbd_mbist_ack_i), - .wb_lack_o (wbd_mbist_lack_i), - .wb_err_o ( ), - - .rst_n (bist_rst_n ), - - - .bist_en (bist_en_rp ), - .bist_run (bist_run_rp ), - .bist_shift (bist_shift_rp ), - .bist_load (bist_load_rp ), - .bist_sdi (bist_sdi_rp ), - - .bist_error_cnt3 (bist_error_cnt3 ), - .bist_error_cnt2 (bist_error_cnt2 ), - .bist_error_cnt1 (bist_error_cnt1 ), - .bist_error_cnt0 (bist_error_cnt0 ), - .bist_correct (bist_correct ), - .bist_error (bist_error ), - .bist_done (bist_done ), - .bist_sdo (bist_sdo ), - - // towards memory - // PORT-A - .mem_clk_a (mem_clk_a ), - .mem_addr_a0 (mem0_addr_a ), - .mem_addr_a1 (mem1_addr_a ), - .mem_addr_a2 (mem2_addr_a ), - .mem_addr_a3 (mem3_addr_a ), - .mem_cen_a (mem_cen_a ), - .mem_web_a (mem_web_a ), - .mem_mask_a0 (mem0_mask_a ), - .mem_mask_a1 (mem1_mask_a ), - .mem_mask_a2 (mem2_mask_a ), - .mem_mask_a3 (mem3_mask_a ), - .mem_din_a0 (mem0_din_a ), - .mem_din_a1 (mem1_din_a ), - .mem_din_a2 (mem2_din_a ), - .mem_din_a3 (mem3_din_a ), - .mem_dout_a0 (mem0_dout_a ), - .mem_dout_a1 (mem1_dout_a ), - .mem_dout_a2 (mem2_dout_a ), - .mem_dout_a3 (mem3_dout_a ), - // PORT-B - .mem_clk_b (mem_clk_b ), - .mem_cen_b (mem_cen_b ), - .mem_addr_b0 (mem0_addr_b ), - .mem_addr_b1 (mem1_addr_b ), - .mem_addr_b2 (mem2_addr_b ), - .mem_addr_b3 (mem3_addr_b ) - - -); - -sky130_sram_2kbyte_1rw1r_32x512_8 u_sram0_2kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem_clk_a[0] ), - .csb0 (mem_cen_a[0] ), - .web0 (mem_web_a[0] ), - .wmask0 (mem0_mask_a ), - .addr0 (mem0_addr_a ), - .din0 (mem0_din_a ), - .dout0 (mem0_dout_a ), -// Port 1: R - .clk1 (mem_clk_b[0] ), - .csb1 (mem_cen_b[0] ), - .addr1 (mem0_addr_b ), - .dout1 ( ) - ); - -sky130_sram_2kbyte_1rw1r_32x512_8 u_sram1_2kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem_clk_a[1] ), - .csb0 (mem_cen_a[1] ), - .web0 (mem_web_a[1] ), - .wmask0 (mem1_mask_a ), - .addr0 (mem1_addr_a ), - .din0 (mem1_din_a ), - .dout0 (mem1_dout_a ), -// Port 1: R - .clk1 (mem_clk_b[1] ), - .csb1 (mem_cen_b[1] ), - .addr1 (mem1_addr_b ), - .dout1 ( ) - ); - -sky130_sram_2kbyte_1rw1r_32x512_8 u_sram2_2kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem_clk_a[2] ), - .csb0 (mem_cen_a[2] ), - .web0 (mem_web_a[2] ), - .wmask0 (mem2_mask_a ), - .addr0 (mem2_addr_a ), - .din0 (mem2_din_a ), - .dout0 (mem2_dout_a ), -// Port 1: R - .clk1 (mem_clk_b[2] ), - .csb1 (mem_cen_b[2] ), - .addr1 (mem2_addr_b ), - .dout1 ( ) - ); - - -sky130_sram_2kbyte_1rw1r_32x512_8 u_sram3_2kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem_clk_a[3] ), - .csb0 (mem_cen_a[3] ), - .web0 (mem_web_a[3] ), - .wmask0 (mem3_mask_a ), - .addr0 (mem3_addr_a ), - .din0 (mem3_din_a ), - .dout0 (mem3_dout_a ), -// Port 1: R - .clk1 (mem_clk_b[3] ), - .csb1 (mem_cen_b[3] ), - .addr1 (mem3_addr_b ), - .dout1 ( ) - ); - /*** sar_adc u_adc (
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index ef22d72..7e062f0 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -119,16 +119,6 @@ input logic clk_i, input logic rst_n, - input logic [3:0] boot_remap, // When remap is enabled - // [0] - 0x0000_0000 - 0x0000_07FF Map to MBIST1 - // [1] - 0x0000_0800 - 0x0000_0FFF Map to MBIST2 - // [2] - 0x0000_1000 - 0x0000_17FF Map to MBIST3 - // [3] - 0x0000_1800 - 0x0000_1FFF Map to MBIST4 - input logic [3:0] dcache_remap, // When dcache remap is enabled, - // [0] - 0x0800_0000 - 0x0800_07FF Map to MBIST1 - // [1] - 0x0800_0800 - 0x0800_0FFF Map to MBIST2 - // [2] - 0x0800_1000 - 0x0800_17FF Map to MBIST3 - // [3] - 0x0800_1800 - 0x0800_1FFF Map to MBIST4 // Master 0 Interface input logic [31:0] m0_wbd_dat_i, @@ -215,22 +205,8 @@ output logic [3:0] s2_wbd_sel_o, output logic s2_wbd_we_o, output logic s2_wbd_cyc_o, - output logic s2_wbd_stb_o, + output logic s2_wbd_stb_o - // Slave 3 Interface - // MBIST - input logic [31:0] s3_wbd_dat_i, - input logic s3_wbd_ack_i, - input logic s3_wbd_lack_i, - // input logic s3_wbd_err_i, - output logic [31:0] s3_wbd_dat_o, - output logic [12:0] s3_wbd_adr_o, - output logic [3:0] s3_wbd_sel_o, - output logic [9:0] s3_wbd_bl_o, - output logic s3_wbd_bry_o, - output logic s3_wbd_we_o, - output logic s3_wbd_cyc_o, - output logic s3_wbd_stb_o ); //////////////////////////////////////////////////////////////////// @@ -242,7 +218,6 @@ parameter TARGET_SPI_REG = 4'b0000; parameter TARGET_UART = 4'b0001; parameter TARGET_PINMUX = 4'b0010; -parameter TARGET_MBIST = 4'b0011; // WishBone Wr Interface typedef struct packed { @@ -282,13 +257,11 @@ type_wb_wr_intf s0_wb_wr; type_wb_wr_intf s1_wb_wr; type_wb_wr_intf s2_wb_wr; -type_wb_wr_intf s3_wb_wr; // Slave Read Interface type_wb_rd_intf s0_wb_rd; type_wb_rd_intf s1_wb_rd; type_wb_rd_intf s2_wb_rd; -type_wb_rd_intf s3_wb_rd; type_wb_wr_intf m_bus_wr; // Multiplexed Master I/F @@ -322,10 +295,6 @@ // 0x1001_0080 to 0x1001_00BF - USB // 0x1001_00C0 to 0x1001_00FF - SSPIM // 0x1002_0000 to 0x1002_00FF - PINMUX -// 0x1003_0000 to 0x1003_07FF - SRAM-0 (2KB) -// 0x1003_0800 to 0x1003_0FFF - SRAM-1 (2KB) -// 0x1003_1000 to 0x1003_17FF - SRAM-2 (2KB) -// 0x1003_1800 to 0x1003_1FFF - SRAM-3 (2KB) // 0x3080_0000 to 0x3080_00FF - WB HOST (This decoding happens at wb_host block) // --------------------------------------------------------------------------- // @@ -333,7 +302,6 @@ (m0_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG : // SPI REG (m0_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : // UART/I2C/USB/SPI (m0_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : // PINMUX - (m0_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST : // MBIST 4'b0000; //------------------------------ @@ -345,54 +313,23 @@ // 0x1001_0080 to 0x1001_00BF - USB // 0x1001_00C0 to 0x1001_00FF - SSPIM // 0x1002_0000 to 0x1002_00FF - PINMUX -// 0x1003_0000 to 0x1003_07FF - SRAM-0 (2KB) -// 0x1003_0800 to 0x1003_0FFF - SRAM-1 (2KB) -// 0x1003_1000 to 0x1003_17FF - SRAM-2 (2KB) -// 0x1003_1800 to 0x1003_1FFF - SRAM-3 (2KB) //----------------------------- // -wire [3:0] m1_wbd_tid_i = (boot_remap[0] && m1_wbd_adr_i[31:11] == 21'h0) ? TARGET_MBIST: - (boot_remap[1] && m1_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST: - (boot_remap[2] && m1_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST: - (boot_remap[3] && m1_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST: - (dcache_remap[0] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_0) ? TARGET_MBIST: - (dcache_remap[1] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_1) ? TARGET_MBIST: - (dcache_remap[2] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_0) ? TARGET_MBIST: - (dcache_remap[3] && m1_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_1) ? TARGET_MBIST: - (m1_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : +wire [3:0] m1_wbd_tid_i = (m1_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : (m1_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG : (m1_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : (m1_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : - (m1_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST : 4'b0000; -wire [3:0] m2_wbd_tid_i = (boot_remap[0] && m2_wbd_adr_i[31:11] == 21'h0) ? TARGET_MBIST: - (boot_remap[1] && m2_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST: - (boot_remap[2] && m2_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST: - (boot_remap[3] && m2_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST: - (dcache_remap[0] && m2_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_0) ? TARGET_MBIST: - (dcache_remap[1] && m2_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_1) ? TARGET_MBIST: - (dcache_remap[2] && m2_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_0) ? TARGET_MBIST: - (dcache_remap[3] && m2_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_1) ? TARGET_MBIST: - (m2_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : +wire [3:0] m2_wbd_tid_i = (m2_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : (m2_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG : (m2_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : (m2_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : - (m2_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST : 4'b0000; -wire [3:0] m3_wbd_tid_i = (boot_remap[0] && m3_wbd_adr_i[31:11] == 21'h0) ? TARGET_MBIST: - (boot_remap[1] && m3_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST: - (boot_remap[2] && m3_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST: - (boot_remap[3] && m3_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST: - (dcache_remap[0] && m3_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_0) ? TARGET_MBIST: - (dcache_remap[1] && m3_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0000_1) ? TARGET_MBIST: - (dcache_remap[2] && m3_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_0) ? TARGET_MBIST: - (dcache_remap[3] && m3_wbd_adr_i[31:11] == 21'b0000_1000_0000_0000_0001_1) ? TARGET_MBIST: - (m3_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : +wire [3:0] m3_wbd_tid_i = (m3_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : (m3_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG : (m3_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : (m3_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : - (m3_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST : 4'b0000; //---------------------------------------- // Master Mapping @@ -484,14 +421,6 @@ assign s2_wbd_cyc_o = s2_wb_wr.wbd_cyc ; assign s2_wbd_stb_o = s2_wb_wr.wbd_stb ; - assign s3_wbd_dat_o = s3_wb_wr.wbd_dat[31:0] ; - assign s3_wbd_adr_o = s3_wb_wr.wbd_adr[12:0] ; // MBIST Need 13 bit - assign s3_wbd_sel_o = s3_wb_wr.wbd_sel[3:0] ; - assign s3_wbd_bl_o = s3_wb_wr.wbd_bl ; - assign s3_wbd_bry_o = s3_wb_wr.wbd_bry ; - assign s3_wbd_we_o = s3_wb_wr.wbd_we ; - assign s3_wbd_cyc_o = s3_wb_wr.wbd_cyc ; - assign s3_wbd_stb_o = s3_wb_wr.wbd_stb ; assign s0_wb_rd.wbd_dat = s0_wbd_dat_i ; @@ -509,10 +438,6 @@ assign s2_wb_rd.wbd_lack = s2_wbd_ack_i ; assign s2_wb_rd.wbd_err = 1'b0; // s2_wbd_err_i ; - unused - assign s3_wb_rd.wbd_dat = s3_wbd_dat_i ; - assign s3_wb_rd.wbd_ack = s3_wbd_ack_i ; - assign s3_wb_rd.wbd_lack = s3_wbd_lack_i ; - assign s3_wb_rd.wbd_err = 1'b0; // s3_wbd_err_i ; - unused // // arbitor @@ -549,7 +474,6 @@ 4'h0: s_bus_rd = s0_wb_rd; 4'h1: s_bus_rd = s1_wb_rd; 4'h2: s_bus_rd = s2_wb_rd; - 4'h3: s_bus_rd = s3_wb_rd; default: s_bus_rd = s0_wb_rd; endcase end @@ -559,7 +483,6 @@ assign s0_wb_wr = (s_wbd_tid == 3'b000) ? s_bus_wr : 'h0; assign s1_wb_wr = (s_wbd_tid == 3'b001) ? s_bus_wr : 'h0; assign s2_wb_wr = (s_wbd_tid == 3'b010) ? s_bus_wr : 'h0; -assign s3_wb_wr = (s_wbd_tid == 3'b011) ? s_bus_wr : 'h0; // Connect Slave to Master assign m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0;
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c index defc5ce..e61495a 160000 --- a/verilog/rtl/yifive/ycr1c +++ b/verilog/rtl/yifive/ycr1c
@@ -1 +1 @@ -Subproject commit defc5ce7ce231aa0c5944a897a0144f9613944be +Subproject commit e61495abf5c9236e00da7d2ef1f39a7b3451a087