semaphore added and pinmux register are re-arranged
diff --git a/README.md b/README.md index 47c8a4f..8261a32 100644 --- a/README.md +++ b/README.md
@@ -337,36 +337,18 @@ <td align="center"> SSPI</td> </tr> <tr> + <td align="center"> 0x1001_01C0 to 0x1001_013F</td> + <td align="center"> 0x1001_01C0 to 0x1001_013F</td> + <td align="center"> 0x1001_01C0 to 0x1001_013F</td> + <td align="center"> SSPI</td> + </tr> + <tr> <td align="center"> 0x1002_0080 to 0x1002_00FF</td> <td align="center"> 0x1002_0080 to 0x1002_00FF</td> <td align="center"> 0x1002_0080 to 0x1002_00FF</td> <td align="center"> PINMUX</td> </tr> <tr> - <td align="center"> 0x1003_0080 to 0x1003_07FF</td> - <td align="center"> 0x1003_0080 to 0x1003_07FF</td> - <td align="center"> 0x1003_0080 to 0x1003_07FF</td> - <td align="center"> SRAM-0 (2KB)</td> - </tr> - <tr> - <td align="center"> 0x1003_0800 to 0x1003_0FFF</td> - <td align="center"> 0x1003_0800 to 0x1003_0FFF</td> - <td align="center"> 0x1003_0800 to 0x1003_0FFF</td> - <td align="center"> SRAM-1 (2KB)</td> - </tr> - <tr> - <td align="center"> 0x1003_1000 to 0x1003_17FF</td> - <td align="center"> 0x1003_1000 to 0x1003_17FF</td> - <td align="center"> 0x1003_1000 to 0x1003_17FF</td> - <td align="center"> SRAM-2 (2KB)</td> - </tr> - <tr> - <td align="center"> 0x1003_1800 to 0x1003_1FFF</td> - <td align="center"> 0x1003_1800 to 0x1003_1FFF</td> - <td align="center"> 0x1003_1800 to 0x1003_1FFF</td> - <td align="center"> SRAM-3 (2KB)</td> - </tr> - <tr> <td align="center"> -</td> <td align="center"> -</td> <td align="center"> 0x3080_0000 to 0x3080_00FF</td> @@ -565,42 +547,6 @@ -# Repository contents - -``` -|verilog -| ├─ rtl -| | |- syntacore -| | | |─ scr1 -| | | | ├─ **docs** | **SCR1 documentation** -| | | | | ├─ scr1_eas.pdf | SCR1 External Architecture Specification -| | | | | └─ scr1_um.pdf | SCR1 User Manual -| | | | |─ **src** | **SCR1 RTL source and testbench files** -| | | | | ├─ includes | Header files -| | | | | ├─ core | Core top source files -| | | | | ├─ top | Cluster source files -| | | | |─ **synth** | **SCR1 RTL Synthesis files ** -| | |- Qspi_master -| | | |- src | Qard SPI Master Source files -| | |-wb_interconnect -| | | |- src | 3x4 Wishbone Interconnect -| | |- digital_core -| | | |- src | Digital core Source files -| | |- lib | common library source files -| |- dv -| | |- la_test1 | carevel LA test -| | |- risc_boot | user core risc boot test -| | |- wb_port | user wishbone test -| | |- user_risc_boot | user standalone test without carevel soc -| |- gl | ** GLS Source files ** -| -|- openlane - |- spi_master | spi_master openlane scripts - |- syntacore | Risc Core openlane scripts - |- user_project_wrapper | carvel user project wrapper - -``` - # Prerequisites - Docker (ensure docker daemon is running) -- tested with version 19.03.12, but any recent version should suffice. @@ -719,6 +665,13 @@ make verify-riscv_regress - standalone riscv compliance test suite make verify-arduino_risc_boot - standalone riscv core-0 boot using arduino tool set make verify-arduino_hello_world - standalone riscv core-0 hello world test using arduino tool set + make verify-arduino_digital_port_control - standalone riscv core-0 digital port control using arduino tool set + make verify-arduino_ascii_table - standalone riscv core-0 ascii table using arduino tool set + make verify-arduino_character_analysis - standalone riscv core-0 character analysis using arduino tool set + make verify-arduino_multi_serial - standalone riscv core-0 multi uart test using arduino tool set + make verify-arduino_switchCase2 - standalone riscv core-0 switch case using arduino tool set + make verify-arduino_risc_boot - standalone riscv core-0 boot test using arduino tool set + make verify-arduino_string - standalone riscv core-0 string usage test using arduino tool set make verify-user_uart SIM=RTL DUMP=OFF - Standalone user uart-0 test using user risc core with waveform dump off
diff --git a/openlane/pinmux/base.sdc b/openlane/pinmux_top/base.sdc similarity index 100% rename from openlane/pinmux/base.sdc rename to openlane/pinmux_top/base.sdc
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux_top/config.tcl similarity index 81% rename from openlane/pinmux/config.tcl rename to openlane/pinmux_top/config.tcl index c27d14e..57819dc 100755 --- a/openlane/pinmux/config.tcl +++ b/openlane/pinmux_top/config.tcl
@@ -20,7 +20,7 @@ set script_dir [file dirname [file normalize [info script]]] # Name -set ::env(DESIGN_NAME) pinmux +set ::env(DESIGN_NAME) pinmux_top set ::env(DESIGN_IS_CORE) "0" set ::env(FP_PDN_CORE_RING) "0" @@ -42,11 +42,19 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux_top.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux_reg.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_intr.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm.sv \ - $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/glbl_reg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_reg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_intr.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm_reg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer_reg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/semaphore_reg.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type1.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type2.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \ @@ -82,7 +90,7 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.38" +set ::env(PL_TARGET_DENSITY) "0.40" set ::env(CELL_PAD) "4" set ::env(FP_IO_VEXTEND) {6}
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg similarity index 99% rename from openlane/pinmux/pin_order.cfg rename to openlane/pinmux_top/pin_order.cfg index baa31fd..6dc053a 100644 --- a/openlane/pinmux/pin_order.cfg +++ b/openlane/pinmux_top/pin_order.cfg
@@ -129,6 +129,7 @@ reg_cs 200 0 reg_wr +reg_addr\[8\] reg_addr\[7\] reg_addr\[6\] reg_addr\[5\]
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index b30b602..e33180a 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -67,20 +67,19 @@ set ::env(VERILOG_FILES_BLACKBOX) "\ $::env(DESIGN_DIR)/../../verilog/gl/qspim_top.v \ $::env(DESIGN_DIR)/../../verilog/gl/wb_interconnect.v \ - $::env(DESIGN_DIR)/../../verilog/gl/pinmux.v \ + $::env(DESIGN_DIR)/../../verilog/gl/pinmux_top.v \ $::env(DESIGN_DIR)/../../verilog/gl/uart_i2c_usb_spi_top.v \ $::env(DESIGN_DIR)/../../verilog/gl/wb_host.v \ $::env(DESIGN_DIR)/../../verilog/gl/ycr_intf.v \ $::env(DESIGN_DIR)/../../verilog/gl/ycr_core_top.v \ $::env(DESIGN_DIR)/../../verilog/gl/ycr_iconnect.v \ $::env(DESIGN_DIR)/../../verilog/gl/digital_pll.v \ - $::env(DESIGN_DIR)/../../verilog/rtl/sar_adc_10b/sar_adc_10b.v \ $::env(PDK_ROOT)/sky130B/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \ " set ::env(EXTRA_LEFS) "\ $lef_root/qspim_top.lef \ - $lef_root/pinmux.lef \ + $lef_root/pinmux_top.lef \ $lef_root/wb_interconnect.lef \ $lef_root/uart_i2c_usb_spi_top.lef \ $lef_root/wb_host.lef \ @@ -93,7 +92,7 @@ set ::env(EXTRA_GDS_FILES) "\ $gds_root/qspim_top.gds \ - $gds_root/pinmux.gds \ + $gds_root/pinmux_top.gds \ $gds_root/wb_interconnect.gds \ $gds_root/uart_i2c_usb_spi_top.gds \ $gds_root/wb_host.gds \
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index fe3302c..2d8237e 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -731,6 +731,7 @@ s2_wbd_stb_o 1600 0 2 s2_wbd_we_o +s2_wbd_adr_o\[8\] s2_wbd_adr_o\[7\] s2_wbd_adr_o\[6\] s2_wbd_adr_o\[5\]
diff --git a/signoff/pinmux_top/OPENLANE_VERSION b/signoff/pinmux_top/OPENLANE_VERSION new file mode 100644 index 0000000..d5588cd --- /dev/null +++ b/signoff/pinmux_top/OPENLANE_VERSION
@@ -0,0 +1 @@ +openlane 6ab944bc23688cae6dc6fa32444891a1e57715c8
diff --git a/signoff/pinmux_top/PDK_SOURCES b/signoff/pinmux_top/PDK_SOURCES new file mode 100644 index 0000000..e8e14ea --- /dev/null +++ b/signoff/pinmux_top/PDK_SOURCES
@@ -0,0 +1 @@ +open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl index 5d73c61..ab32382 100644 --- a/sta/scripts/caravel_timing.tcl +++ b/sta/scripts/caravel_timing.tcl
@@ -1,26 +1,26 @@ set ::env(USER_ROOT) ".." - set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-6/caravel" - set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw6" + set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-7/caravel" + set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw7/sky130B" - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core.v read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/DFFRAM.v read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core_wrapper.v @@ -50,7 +50,7 @@ read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v - read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v + read_verilog $::env(USER_ROOT)/verilog/gl/pinmux_top.v read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v @@ -149,7 +149,7 @@ read_spef -path mprj/u_riscv_top.u_connect $::env(USER_ROOT)/spef/ycr_iconnect.spef read_spef -path mprj/u_riscv_top.u_intf $::env(USER_ROOT)/spef/ycr_intf.spef read_spef -path mprj/u_riscv_top.i_core_top_0 $::env(USER_ROOT)/spef/ycr_core_top.spef - read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux.spef + read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux_top.spef read_spef -path mprj/u_qspi_master $::env(USER_ROOT)/spef/qspim_top.spef read_spef -path mprj/u_uart_i2c_usb_spi $::env(USER_ROOT)/spef/uart_i2c_usb_spi_top.spef read_spef -path mprj/u_wb_host $::env(USER_ROOT)/spef/wb_host.spef
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index 950b657..8b10c8b 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -51,8 +51,8 @@ set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}] set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}] -set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] +set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}] set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}]
diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile index 83a3bb4..27654a3 100644 --- a/verilog/dv/Makefile +++ b/verilog/dv/Makefile
@@ -19,7 +19,7 @@ .SUFFIXES: .SILENT: clean all -PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec user_cache_bypass user_gpio user_spi_isp arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial arduino_arrays arduino_switchCase2 arduino_character_analysis +PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec user_cache_bypass user_gpio user_spi_isp arduino_risc_boot arduino_hello_world arduino_ascii_table arduino_multi_serial arduino_arrays arduino_switchCase2 arduino_character_analysis arduino_string arduino_digital_port_control user_sspi user_aes user_sema all: ${PATTERNS} for i in ${PATTERNS}; do \
diff --git a/verilog/dv/arduino_arrays/arduino_arrays_tb.v b/verilog/dv/arduino_arrays/arduino_arrays_tb.v index 5e96037..acd36fe 100644 --- a/verilog/dv/arduino_arrays/arduino_arrays_tb.v +++ b/verilog/dv/arduino_arrays/arduino_arrays_tb.v
@@ -195,7 +195,7 @@ #1; // Remove WB and SPI Reset and CORE under Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); // QSPI SRAM:CS#2 Switch to QSPI Mode wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 @@ -206,16 +206,16 @@ // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); end else if(d_risc_id == 2) begin $display("STATUS: Working with Risc core 2"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); end else if(d_risc_id == 3) begin $display("STATUS: Working with Risc core 3"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); end repeat (100) @(posedge clock); // wait for Processor Get Ready @@ -318,6 +318,10 @@ ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK + `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work initial begin
diff --git a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v index 9f2be69..b6c4c4c 100644 --- a/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v +++ b/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v
@@ -181,14 +181,14 @@ initial begin - uart_data_bit = 2'b11; - uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; - uart_stick_parity = 0; // 1: force even parity - uart_parity_en = 0; // parity enable - uart_even_odd_parity = 1; // 0: odd parity; 1: even parity - tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400 - uart_timeout = 2000;// wait time limit - uart_fifo_enable = 0; // fifo mode disable + uart_data_bit = 2'b11; + uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; + uart_stick_parity = 0; // 1: force even parity + uart_parity_en = 0; // parity enable + uart_even_odd_parity = 1; // 0: odd parity; 1: even parity + tb_set_uart_baud(50000000,1152000,uart_divisor);// 50Mhz Ref clock, Baud Rate: 230400 + uart_timeout = 2000;// wait time limit + uart_fifo_enable = 0; // fifo mode disable $value$plusargs("risc_core_id=%d", d_risc_id); @@ -201,61 +201,59 @@ repeat (2) @(posedge clock); #1; - // Remove all the reset - if(d_risc_id == 0) begin - $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); - end else if(d_risc_id == 1) begin - $display("STATUS: Working with Risc core 1"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F); - end else if(d_risc_id == 2) begin - $display("STATUS: Working with Risc core 2"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F); - end else if(d_risc_id == 3) begin - $display("STATUS: Working with Risc core 3"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F); - end + // Remove all the reset + if(d_risc_id == 0) begin + $display("STATUS: Working with Risc core 0"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + end else if(d_risc_id == 1) begin + $display("STATUS: Working with Risc core 1"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); + end else if(d_risc_id == 2) begin + $display("STATUS: Working with Risc core 2"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); + end else if(d_risc_id == 3) begin + $display("STATUS: Working with Risc core 3"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); + end - repeat (100) @(posedge clock); // wait for Processor Get Ready + repeat (100) @(posedge clock); // wait for Processor Get Ready - tb_uart.debug_mode = 0; // disable debug display - tb_uart.uart_init; - tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, - uart_stick_parity, uart_timeout, uart_divisor); + tb_uart.debug_mode = 0; // disable debug display + tb_uart.uart_init; + tb_uart.control_setup (uart_data_bit, uart_stop_bits, uart_parity_en, uart_even_odd_parity, uart_stick_parity, uart_timeout, uart_divisor); - repeat (45000) @(posedge clock); // wait for Processor Get Ready - flag = 0; + repeat (45000) @(posedge clock); // wait for Processor Get Ready + flag = 0; check_sum = 0; - - - fork - begin - while(flag == 0) - begin - tb_uart.read_char(read_data,flag); - if(flag == 0) begin - $write ("%c",read_data); - check_sum = check_sum+read_data; + + fork + begin + while(flag == 0) + begin + tb_uart.read_char(read_data,flag); + if(flag == 0) begin + $write ("%c",read_data); + check_sum = check_sum+read_data; end - end - end - begin - repeat (3000000) @(posedge clock); // wait for Processor Get Ready - end - join_any - - #100 - tb_uart.report_status(uart_rx_nu, uart_tx_nu); - - test_fail = 0; + end + end + begin + repeat (3000000) @(posedge clock); // wait for Processor Get Ready + end + join_any + + #100 + tb_uart.report_status(uart_rx_nu, uart_tx_nu); + + test_fail = 0; $display("Total Rx Char: %d Check Sum : %x ",uart_rx_nu, check_sum); - // Check - // if all the 4224 byte received - // if no error - if(uart_rx_nu != 4224) test_fail = 1; - if(check_sum != 32'h3f01b) test_fail = 1; - if(tb_uart.err_cnt != 0) test_fail = 1; + // Check + // if all the 4224 byte received + // if no error + if(uart_rx_nu != 4224) test_fail = 1; + if(check_sum != 32'h3f01b) test_fail = 1; + if(tb_uart.err_cnt != 0) test_fail = 1; $display("###################################################"); @@ -318,6 +316,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v index 3525840..46490b2 100644 --- a/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v +++ b/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v
@@ -228,7 +228,7 @@ repeat (2) @(posedge clock); #1; // Remove WB and SPI Reset and CORE under Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); // QSPI SRAM:CS#2 Switch to QSPI Mode wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 @@ -238,16 +238,16 @@ // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); end else if(d_risc_id == 2) begin $display("STATUS: Working with Risc core 2"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); end else if(d_risc_id == 3) begin $display("STATUS: Working with Risc core 3"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); end repeat (100) @(posedge clock); // wait for Processor Get Ready @@ -361,6 +361,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v index 64d6d49..b205431 100644 --- a/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v +++ b/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v
@@ -177,7 +177,7 @@ #1; // Remove WB and SPI Reset and CORE under Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); // QSPI SRAM:CS#2 Switch to QSPI Mode wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 @@ -188,16 +188,16 @@ // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); end else if(d_risc_id == 2) begin $display("STATUS: Working with Risc core 2"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); end else if(d_risc_id == 3) begin $display("STATUS: Working with Risc core 3"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); end repeat (100) @(posedge clock); // wait for Processor Get Ready @@ -291,6 +291,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK //------------------------------------------------------------------------------------- // Integrate the Serial SPI to ad5204/5206 (4-/6-Channel Digital Potentiometers)
diff --git a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v index f440419..43cfed0 100644 --- a/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v +++ b/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v
@@ -202,16 +202,16 @@ // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); end else if(d_risc_id == 2) begin $display("STATUS: Working with Risc core 2"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); end else if(d_risc_id == 3) begin $display("STATUS: Working with Risc core 3"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); end repeat (100) @(posedge clock); // wait for Processor Get Ready @@ -319,6 +319,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v index 98948a9..1ed24fc 100644 --- a/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v +++ b/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v
@@ -322,6 +322,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK //--------------------------- // I2C
diff --git a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v index eda8c5a..5dfd94e 100644 --- a/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v +++ b/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v
@@ -207,16 +207,16 @@ // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); end else if(d_risc_id == 2) begin $display("STATUS: Working with Risc core 2"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); end else if(d_risc_id == 3) begin $display("STATUS: Working with Risc core 3"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); end repeat (100) @(posedge clock); // wait for Processor Get Ready @@ -348,6 +348,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp b/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp index ca5efa0..c663a26 100644 --- a/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp +++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp
@@ -1,34 +1,18 @@ #include <Arduino.h> #define uint32_t long -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) -#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018) -#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C) -#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020) -#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024) -#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028) -#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C) -#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030) -#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034) -#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038) -#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C) -#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040) -#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044) -#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048) -#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C) -#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050) -#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054) -#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058) -#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C) -#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060) -#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064) -#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068) -#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C) +#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID +#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0 +#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1 +#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask +#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt +#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel +#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0 +#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1 +#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2 +#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3 +#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4 +#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5 @@ -36,12 +20,12 @@ void loop(); void setup() { // put your setup code here, to run once: - reg_mprj_globl_reg22 = 0x11223344; - reg_mprj_globl_reg23 = 0x22334455; - reg_mprj_globl_reg24 = 0x33445566; - reg_mprj_globl_reg25 = 0x44556677; - reg_mprj_globl_reg26 = 0x55667788; - reg_mprj_globl_reg27 = 0x66778899; + reg_mprj_globl_soft0 = 0x11223344; + reg_mprj_globl_soft1 = 0x22334455; + reg_mprj_globl_soft2 = 0x33445566; + reg_mprj_globl_soft3 = 0x44556677; + reg_mprj_globl_soft4 = 0x55667788; + reg_mprj_globl_soft5 = 0x66778899; }
diff --git a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v index fb25cf0..bb933b7 100644 --- a/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v +++ b/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v
@@ -137,10 +137,10 @@ // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); end @@ -162,12 +162,12 @@ // 0x3000002C = 0x66778899; test_fail = 0; - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899); @@ -231,6 +231,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/arduino_string/arduino_string_tb.v b/verilog/dv/arduino_string/arduino_string_tb.v index 8fabb59..3b23622 100644 --- a/verilog/dv/arduino_string/arduino_string_tb.v +++ b/verilog/dv/arduino_string/arduino_string_tb.v
@@ -206,16 +206,16 @@ // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); end else if(d_risc_id == 2) begin $display("STATUS: Working with Risc core 2"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); end else if(d_risc_id == 3) begin $display("STATUS: Working with Risc core 3"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); end repeat (100) @(posedge clock); // wait for Processor Get Ready @@ -320,6 +320,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v index 8d80814..70592df 100644 --- a/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v +++ b/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v
@@ -248,7 +248,7 @@ repeat (2) @(posedge clock); #1; // Remove WB and SPI Reset, Keep SDARM and CORE under Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); // QSPI SRAM:CS#2 Switch to QSPI Mode wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 @@ -259,16 +259,16 @@ // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); end else if(d_risc_id == 2) begin $display("STATUS: Working with Risc core 2"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h41F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); end else if(d_risc_id == 3) begin $display("STATUS: Working with Risc core 3"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h81F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); end repeat (100) @(posedge clock); // wait for Processor Get Ready @@ -377,6 +377,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/c_func/inc/ext_reg_map.h b/verilog/dv/c_func/inc/ext_reg_map.h new file mode 100644 index 0000000..cdb04f3 --- /dev/null +++ b/verilog/dv/c_func/inc/ext_reg_map.h
@@ -0,0 +1,83 @@ +//-------------------------------------------------------------------- +// Register Address Map As Seen By the External/Caravel RISCV Core +//-------------------------------------------------------------------- + +//------------------------------------- +// PinMux Register +// ------------------------------------ +#define reg_glbl_chip_id (*(volatile uint32_t*)0x30020000) // reg_0 - Chip ID +#define reg_glbl_cfg0 (*(volatile uint32_t*)0x30020004) // reg_1 - Global Config-0 +#define reg_glbl_cfg1 (*(volatile uint32_t*)0x30020008) // reg_2 - Global Config-1 +#define reg_glbl_intr_msk (*(volatile uint32_t*)0x3002000C) // reg_3 - Global Interrupt Mask +#define reg_glbl_intr (*(volatile uint32_t*)0x30020010) // reg_4 - Global Interrupt +#define reg_glbl_multi_func (*(volatile uint32_t*)0x30020014) // reg_5 - GPIO Multi Function +#define reg_glbl_soft_reg_0 (*(volatile uint32_t*)0x30020018) // reg_6 - Soft Register-0 +#define reg_glbl_soft_reg_1 (*(volatile uint32_t*)0x3002001C) // reg_7 - Sof Register-1 +#define reg_glbl_soft_reg_2 (*(volatile uint32_t*)0x30020020) // reg_8 - Sof Register-2 +#define reg_glbl_soft_reg_3 (*(volatile uint32_t*)0x30020024) // reg_9 - Sof Register-3 +#define reg_glbl_soft_reg_4 (*(volatile uint32_t*)0x30020028) // reg_10 - Sof Register-4 +#define reg_glbl_soft_reg_5 (*(volatile uint32_t*)0x3002002C) // reg_11 - Sof Register-5 + +#define reg_gpio_dsel (*(volatile uint32_t*)0x30020040) // reg_0 - GPIO Direction Select +#define reg_gpio_type (*(volatile uint32_t*)0x30020044) // reg_1 - GPIO TYPE - Static/Waveform +#define reg_gpio_idata (*(volatile uint32_t*)0x30020048) // reg_2 - GPIO Data In +#define reg_gpio_odata (*(volatile uint32_t*)0x3002004C) // reg_3 - GPIO Data Out +#define reg_gpio_intr_stat (*(volatile uint32_t*)0x30020050) // reg_4 - GPIO Interrupt status +#define reg_gpio_intr_clr (*(volatile uint32_t*)0x30020050) // reg_5 - GPIO Interrupt Clear +#define reg_gpio_intr_set (*(volatile uint32_t*)0x30020054) // reg_6 - GPIO Interrupt Set +#define reg_gpio_intr_mask (*(volatile uint32_t*)0x30020058) // reg_7 - GPIO Interrupt Mask +#define reg_gpio_pos_intr (*(volatile uint32_t*)0x3002005C) // reg_8 - GPIO Posedge Interrupt +#define reg_gpio_neg_intr (*(volatile uint32_t*)0x30020060) // reg_9 - GPIO Neg Interrupt + +#define reg_pinmux_glbl_cfg (*(volatile uint32_t*)0x30020080) // reg_0 - PWM Reg-0 +#define reg_pinmux_cfg_pwm0 (*(volatile uint32_t*)0x30020084) // reg_1 - PWM Reg-0 +#define reg_pinmux_cfg_pwm1 (*(volatile uint32_t*)0x30020088) // reg_2 - PWM Reg-1 +#define reg_pinmux_cfg_pwm2 (*(volatile uint32_t*)0x3002008C) // reg_3 - PWM Reg-2 +#define reg_pinmux_cfg_pwm3 (*(volatile uint32_t*)0x30020090) // reg_4 - PWM Reg-3 +#define reg_pinmux_cfg_pwm4 (*(volatile uint32_t*)0x30020094) // reg_5 - PWM Reg-4 +#define reg_pinmux_cfg_pwm5 (*(volatile uint32_t*)0x30020098) // reg_6 - PWM Reg-5 + +#define reg_timer_glbl_cfg (*(volatile uint32_t*)0x300200C0) // reg_0 - Global config +#define reg_timer_cfg_timer0 (*(volatile uint32_t*)0x300200C4) // reg_1 - Timer-0 +#define reg_timer_cfg_timer1 (*(volatile uint32_t*)0x300200C8) // reg_2 - Timer-1 +#define reg_timer_cfg_timer2 (*(volatile uint32_t*)0x300200CC) // reg_3 - Timer-2 + +#define reg_sema_lock0 (*(volatile uint32_t*)0x30020100) // reg_0 - Hardware Lock-0 +#define reg_sema_lock1 (*(volatile uint32_t*)0x30020104) // reg_1 - Hardware Lock-1 +#define reg_sema_lock2 (*(volatile uint32_t*)0x30020108) // reg_2 - Hardware Lock-2 +#define reg_sema_lock3 (*(volatile uint32_t*)0x3002010C) // reg_3 - Hardware Lock-3 +#define reg_sema_lock4 (*(volatile uint32_t*)0x30020110) // reg_4 - Hardware Lock-4 +#define reg_sema_lock5 (*(volatile uint32_t*)0x30020114) // reg_5 - Hardware Lock-5 +#define reg_sema_lock6 (*(volatile uint32_t*)0x30020118) // reg_6 - Hardware Lock-6 +#define reg_sema_lock7 (*(volatile uint32_t*)0x3002011C) // reg_7 - Hardware Lock-7 +#define reg_sema_lock8 (*(volatile uint32_t*)0x30020120) // reg_8 - Hardware Lock-8 +#define reg_sema_lock9 (*(volatile uint32_t*)0x30020124) // reg_9 - Hardware Lock-9 +#define reg_sema_lock10 (*(volatile uint32_t*)0x30020128) // reg_10 - Hardware Lock-10 +#define reg_sema_lock11 (*(volatile uint32_t*)0x3002012C) // reg_11 - Hardware Lock-11 +#define reg_sema_lock12 (*(volatile uint32_t*)0x30020130) // reg_12 - Hardware Lock-12 +#define reg_sema_lock13 (*(volatile uint32_t*)0x30020134) // reg_13 - Hardware Lock-13 +#define reg_sema_lock14 (*(volatile uint32_t*)0x30020138) // reg_14 - Hardware Lock-14 +#define reg_sema_lock_cfg (*(volatile uint32_t*)0x3002013C) // reg_15 - Hardware Lock config +#define reg_sema_lock_stat (*(volatile uint32_t*)0x3002013C) // reg_15 - Hardware Lock Status + + +#define reg_uart0_ctrl (*(volatile uint32_t*)0x30010000) // Reg-0 +#define reg_uart0_intr_stat (*(volatile uint32_t*)0x30010004) // Reg-1 +#define reg_uart0_baud_ctrl1 (*(volatile uint32_t*)0x30010008) // Reg-2 +#define reg_uart0_baud_ctrl2 (*(volatile uint32_t*)0x3001000C) // Reg-3 +#define reg_uart0_status (*(volatile uint32_t*)0x30010010) // Reg-4 +#define reg_uart0_txdata (*(volatile uint32_t*)0x30010014) // Reg-5 +#define reg_uart0_rxdata (*(volatile uint32_t*)0x30010018) // Reg-6 +#define reg_uart0_txfifo_stat (*(volatile uint32_t*)0x3001001C) // Reg-7 +#define reg_uart0_rxfifo_stat (*(volatile uint32_t*)0x30010020) // Reg-8 + +#define reg_uart1_ctrl (*(volatile uint32_t*)0x30010100) // Reg-0 +#define reg_uart1_intr_stat (*(volatile uint32_t*)0x30010104) // Reg-1 +#define reg_uart1_baud_ctrl1 (*(volatile uint32_t*)0x30010108) // Reg-2 +#define reg_uart1_baud_ctrl2 (*(volatile uint32_t*)0x3001010C) // Reg-3 +#define reg_uart1_status (*(volatile uint32_t*)0x30010110) // Reg-4 +#define reg_uart1_txdata (*(volatile uint32_t*)0x30010114) // Reg-5 +#define reg_uart1_rxdata (*(volatile uint32_t*)0x30010118) // Reg-6 +#define reg_uart1_txfifo_stat (*(volatile uint32_t*)0x3001011C) // Reg-7 +#define reg_uart1_rxfifo_stat (*(volatile uint32_t*)0x30010120) // Reg-8 +
diff --git a/verilog/dv/c_func/inc/int_reg_map.h b/verilog/dv/c_func/inc/int_reg_map.h new file mode 100644 index 0000000..669499d --- /dev/null +++ b/verilog/dv/c_func/inc/int_reg_map.h
@@ -0,0 +1,83 @@ +//-------------------------------------------------------------------- +// Register Address Map As Seen By the Internal RISCV Core +//-------------------------------------------------------------------- + +//------------------------------------- +// PinMux Register +// ------------------------------------ +#define reg_glbl_chip_id (*(volatile uint32_t*)0x10020000) // reg_0 - Chip ID +#define reg_glbl_cfg0 (*(volatile uint32_t*)0x10020004) // reg_1 - Global Config-0 +#define reg_glbl_cfg1 (*(volatile uint32_t*)0x10020008) // reg_2 - Global Config-1 +#define reg_glbl_intr_msk (*(volatile uint32_t*)0x1002000C) // reg_3 - Global Interrupt Mask +#define reg_glbl_intr (*(volatile uint32_t*)0x10020010) // reg_4 - Global Interrupt +#define reg_glbl_multi_func (*(volatile uint32_t*)0x10020014) // reg_5 - GPIO Multi Function +#define reg_glbl_soft_reg_0 (*(volatile uint32_t*)0x10020018) // reg_6 - Soft Register-0 +#define reg_glbl_soft_reg_1 (*(volatile uint32_t*)0x1002001C) // reg_7 - Sof Register-1 +#define reg_glbl_soft_reg_2 (*(volatile uint32_t*)0x10020020) // reg_8 - Sof Register-2 +#define reg_glbl_soft_reg_3 (*(volatile uint32_t*)0x10020024) // reg_9 - Sof Register-3 +#define reg_glbl_soft_reg_4 (*(volatile uint32_t*)0x10020028) // reg_10 - Sof Register-4 +#define reg_glbl_soft_reg_5 (*(volatile uint32_t*)0x1002002C) // reg_11 - Sof Register-5 + +#define reg_gpio_dsel (*(volatile uint32_t*)0x10020040) // reg_0 - GPIO Direction Select +#define reg_gpio_type (*(volatile uint32_t*)0x10020044) // reg_1 - GPIO TYPE - Static/Waveform +#define reg_gpio_idata (*(volatile uint32_t*)0x10020048) // reg_2 - GPIO Data In +#define reg_gpio_odata (*(volatile uint32_t*)0x1002004C) // reg_3 - GPIO Data Out +#define reg_gpio_intr_stat (*(volatile uint32_t*)0x10020050) // reg_4 - GPIO Interrupt status +#define reg_gpio_intr_clr (*(volatile uint32_t*)0x10020050) // reg_5 - GPIO Interrupt Clear +#define reg_gpio_intr_set (*(volatile uint32_t*)0x10020054) // reg_6 - GPIO Interrupt Set +#define reg_gpio_intr_mask (*(volatile uint32_t*)0x10020058) // reg_7 - GPIO Interrupt Mask +#define reg_gpio_pos_intr (*(volatile uint32_t*)0x1002005C) // reg_8 - GPIO Posedge Interrupt +#define reg_gpio_neg_intr (*(volatile uint32_t*)0x10020060) // reg_9 - GPIO Neg Interrupt + +#define reg_pinmux_glbl_cfg (*(volatile uint32_t*)0x10020080) // reg_0 - PWM Reg-0 +#define reg_pinmux_cfg_pwm0 (*(volatile uint32_t*)0x10020084) // reg_1 - PWM Reg-0 +#define reg_pinmux_cfg_pwm1 (*(volatile uint32_t*)0x10020088) // reg_2 - PWM Reg-1 +#define reg_pinmux_cfg_pwm2 (*(volatile uint32_t*)0x1002008C) // reg_3 - PWM Reg-2 +#define reg_pinmux_cfg_pwm3 (*(volatile uint32_t*)0x10020090) // reg_4 - PWM Reg-3 +#define reg_pinmux_cfg_pwm4 (*(volatile uint32_t*)0x10020094) // reg_5 - PWM Reg-4 +#define reg_pinmux_cfg_pwm5 (*(volatile uint32_t*)0x10020098) // reg_6 - PWM Reg-5 + +#define reg_timer_glbl_cfg (*(volatile uint32_t*)0x100200C0) // reg_0 - Global config +#define reg_timer_cfg_timer0 (*(volatile uint32_t*)0x100200C4) // reg_1 - Timer-0 +#define reg_timer_cfg_timer1 (*(volatile uint32_t*)0x100200C8) // reg_2 - Timer-1 +#define reg_timer_cfg_timer2 (*(volatile uint32_t*)0x100200CC) // reg_3 - Timer-2 + +#define reg_sema_lock0 (*(volatile uint32_t*)0x10020100) // reg_0 - Hardware Lock-0 +#define reg_sema_lock1 (*(volatile uint32_t*)0x10020104) // reg_1 - Hardware Lock-1 +#define reg_sema_lock2 (*(volatile uint32_t*)0x10020108) // reg_2 - Hardware Lock-2 +#define reg_sema_lock3 (*(volatile uint32_t*)0x1002010C) // reg_3 - Hardware Lock-3 +#define reg_sema_lock4 (*(volatile uint32_t*)0x10020110) // reg_4 - Hardware Lock-4 +#define reg_sema_lock5 (*(volatile uint32_t*)0x10020114) // reg_5 - Hardware Lock-5 +#define reg_sema_lock6 (*(volatile uint32_t*)0x10020118) // reg_6 - Hardware Lock-6 +#define reg_sema_lock7 (*(volatile uint32_t*)0x1002011C) // reg_7 - Hardware Lock-7 +#define reg_sema_lock8 (*(volatile uint32_t*)0x10020120) // reg_8 - Hardware Lock-8 +#define reg_sema_lock9 (*(volatile uint32_t*)0x10020124) // reg_9 - Hardware Lock-9 +#define reg_sema_lock10 (*(volatile uint32_t*)0x10020128) // reg_10 - Hardware Lock-10 +#define reg_sema_lock11 (*(volatile uint32_t*)0x1002012C) // reg_11 - Hardware Lock-11 +#define reg_sema_lock12 (*(volatile uint32_t*)0x10020130) // reg_12 - Hardware Lock-12 +#define reg_sema_lock13 (*(volatile uint32_t*)0x10020134) // reg_13 - Hardware Lock-13 +#define reg_sema_lock14 (*(volatile uint32_t*)0x10020138) // reg_14 - Hardware Lock-14 +#define reg_sema_lock_cfg (*(volatile uint32_t*)0x1002013C) // reg_15 - Hardware Lock config +#define reg_sema_lock_stat (*(volatile uint32_t*)0x1002013C) // reg_15 - Hardware Lock Status + + +#define reg_uart0_ctrl (*(volatile uint32_t*)0x10010000) // Reg-0 +#define reg_uart0_intr_stat (*(volatile uint32_t*)0x10010004) // Reg-1 +#define reg_uart0_baud_ctrl1 (*(volatile uint32_t*)0x10010008) // Reg-2 +#define reg_uart0_baud_ctrl2 (*(volatile uint32_t*)0x1001000C) // Reg-3 +#define reg_uart0_status (*(volatile uint32_t*)0x10010010) // Reg-4 +#define reg_uart0_txdata (*(volatile uint32_t*)0x10010014) // Reg-5 +#define reg_uart0_rxdata (*(volatile uint32_t*)0x10010018) // Reg-6 +#define reg_uart0_txfifo_stat (*(volatile uint32_t*)0x1001001C) // Reg-7 +#define reg_uart0_rxfifo_stat (*(volatile uint32_t*)0x10010020) // Reg-8 + +#define reg_uart1_ctrl (*(volatile uint32_t*)0x10010100) // Reg-0 +#define reg_uart1_intr_stat (*(volatile uint32_t*)0x10010104) // Reg-1 +#define reg_uart1_baud_ctrl1 (*(volatile uint32_t*)0x10010108) // Reg-2 +#define reg_uart1_baud_ctrl2 (*(volatile uint32_t*)0x1001010C) // Reg-3 +#define reg_uart1_status (*(volatile uint32_t*)0x10010110) // Reg-4 +#define reg_uart1_txdata (*(volatile uint32_t*)0x10010114) // Reg-5 +#define reg_uart1_rxdata (*(volatile uint32_t*)0x10010118) // Reg-6 +#define reg_uart1_txfifo_stat (*(volatile uint32_t*)0x1001011C) // Reg-7 +#define reg_uart1_rxfifo_stat (*(volatile uint32_t*)0x10010120) // Reg-8 +
diff --git a/verilog/dv/c_func/inc/user_reg_map.h b/verilog/dv/c_func/inc/user_reg_map.h deleted file mode 100644 index 4508fb2..0000000 --- a/verilog/dv/c_func/inc/user_reg_map.h +++ /dev/null
@@ -1,38 +0,0 @@ - - -//------------------------------------- -// PinMux Register -// ------------------------------------ -#define reg_pinmux_chip_id (*(volatile uint32_t*)0x30020000) // reg_0 - Chip ID -#define reg_pinmux_gbl_cfg0 (*(volatile uint32_t*)0x30020004) // reg_1 - Global Config-2 -#define reg_pinmux_gbl_cfg1 (*(volatile uint32_t*)0x30020008) // reg_2 - Global Config-1 -#define reg_pinmux_gbl_intr_msk (*(volatile uint32_t*)0x3002000C) // reg_3 - Global Interrupt Mask -#define reg_pinmux_gbl_intr (*(volatile uint32_t*)0x30020010) // reg_4 - Global Interrupt -#define reg_pinmux_gpio_idata (*(volatile uint32_t*)0x30020014) // reg_5 - GPIO Data In -#define reg_pinmux_gpio_odata (*(volatile uint32_t*)0x30020018) // reg_6 - GPIO Data Out -#define reg_pinmux_gpio_dsel (*(volatile uint32_t*)0x3002001C) // reg_7 - GPIO Direction Select -#define reg_pinmux_gpio_type (*(volatile uint32_t*)0x30020020) // reg_8 - GPIO TYPE - Static/Waveform -#define reg_pinmux_gpio_intr_stat (*(volatile uint32_t*)0x30020024) // reg_9 - GPIO Interrupt status -#define reg_pinmux_gpio_intr_clr (*(volatile uint32_t*)0x30020024) // reg_9 - GPIO Interrupt Clear -#define reg_pinmux_gpio_intr_set (*(volatile uint32_t*)0x30020028) // reg_10 - GPIO Interrupt Set -#define reg_pinmux_gpio_intr_mask (*(volatile uint32_t*)0x3002002C) // reg_11 - GPIO Interrupt Mask -#define reg_pinmux_gpio_pos_intr (*(volatile uint32_t*)0x30020030) // reg_12 - GPIO Posedge Interrupt -#define reg_pinmux_gpio_neg_intr (*(volatile uint32_t*)0x30020034) // reg_13 - GPIO Neg Interrupt -#define reg_pinmux_gpio_multi_func (*(volatile uint32_t*)0x30020038) // reg_14 - GPIO Multi Function -#define reg_pinmux_soft_reg_0 (*(volatile uint32_t*)0x3002003C) // reg_15 - Soft Register -#define reg_pinmux_cfg_pwm0 (*(volatile uint32_t*)0x30020040) // reg_16 - PWM Reg-0 -#define reg_pinmux_cfg_pwm1 (*(volatile uint32_t*)0x30020044) // reg_17 - PWM Reg-1 -#define reg_pinmux_cfg_pwm2 (*(volatile uint32_t*)0x30020048) // reg_18 - PWM Reg-2 -#define reg_pinmux_cfg_pwm3 (*(volatile uint32_t*)0x3002004C) // reg_19 - PWM Reg-3 -#define reg_pinmux_cfg_pwm4 (*(volatile uint32_t*)0x30020050) // reg_20 - PWM Reg-4 -#define reg_pinmux_cfg_pwm5 (*(volatile uint32_t*)0x30020054) // reg_21 - PWM Reg-5 -#define reg_pinmux_soft_reg_1 (*(volatile uint32_t*)0x30020058) // reg_22 - Sof Register -#define reg_pinmux_soft_reg_2 (*(volatile uint32_t*)0x3002005C) // reg_23 - Sof Register -#define reg_pinmux_soft_reg_3 (*(volatile uint32_t*)0x30020060) // reg_24 - Sof Register -#define reg_pinmux_soft_reg_4 (*(volatile uint32_t*)0x30020064) // reg_25 - Sof Register -#define reg_pinmux_soft_reg_5 (*(volatile uint32_t*)0x30020068) // reg_26 - Sof Register -#define reg_pinmux_soft_reg_6 (*(volatile uint32_t*)0x3002006C) // reg_27 - Sof Register -#define reg_pinmux_cfg_timer0 (*(volatile uint32_t*)0x30020070) // reg_28 - Timer-0 -#define reg_pinmux_cfg_timer1 (*(volatile uint32_t*)0x30020074) // reg_28 - Timer-1 -#define reg_pinmux_cfg_timer2 (*(volatile uint32_t*)0x30020078) // reg_28 - Timer-2 -
diff --git a/verilog/dv/common/riscduino_board b/verilog/dv/common/riscduino_board index bb4bce2..09f42e8 160000 --- a/verilog/dv/common/riscduino_board +++ b/verilog/dv/common/riscduino_board
@@ -1 +1 @@ -Subproject commit bb4bce23c19c97fa80f57f89a4a6f023f5d38d95 +Subproject commit 09f42e80c78b05785fb7088fb3bff16b2044c6c8
diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile index a4e04d4..2601fc5 100644 --- a/verilog/dv/risc_boot/Makefile +++ b/verilog/dv/risc_boot/Makefile
@@ -53,7 +53,7 @@ export TOOLS ?= /opt/riscv32i export GCC_PATH ?= $(TOOLS)/bin -export GCC_PREFIX?= riscv32-unknown-linux-gnu +GCC_PREFIX?=riscv32-unknown-elf ############## USER SPECIFIC DEFINE ##################
diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c index 00d308d..8ff48ff 100644 --- a/verilog/dv/risc_boot/risc_boot.c +++ b/verilog/dv/risc_boot/risc_boot.c
@@ -160,11 +160,11 @@ // Remove All Reset - reg_pinmux_gbl_cfg0 = 0x11F; + reg_glbl_cfg0 = 0x11F; // Enable UART Multi Functional Ports - reg_pinmux_gpio_multi_func = 0x100; + reg_glbl_multi_func = 0x100; // configure the user uart reg_mprj_uart_reg0 = 0x7;
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile index 609b7fe..d52ebf4 100644 --- a/verilog/dv/riscv_regress/Makefile +++ b/verilog/dv/riscv_regress/Makefile
@@ -16,7 +16,7 @@ export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog ## YIFIVE FIRMWARE YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware -GCC_PREFIX?=riscv32-unknown-elf +GCC_PREFIX?=riscv64-unknown-elf ## Simulation mode: RTL/GL @@ -158,7 +158,7 @@ todo_list := $(bld_dir)/todo.txt # Environment -export CROSS_PREFIX ?= riscv32-unknown-elf- +export CROSS_PREFIX ?= riscv64-unknown-elf- export RISCV_GCC ?= $(CROSS_PREFIX)gcc export RISCV_OBJDUMP ?= $(CROSS_PREFIX)objdump -D export RISCV_OBJCOPY ?= $(CROSS_PREFIX)objcopy -O verilog
diff --git a/verilog/dv/riscv_regress/tests/isr_sample/timer.h b/verilog/dv/riscv_regress/tests/isr_sample/timer.h index 827b849..c306b2f 100644 --- a/verilog/dv/riscv_regress/tests/isr_sample/timer.h +++ b/verilog/dv/riscv_regress/tests/isr_sample/timer.h
@@ -78,7 +78,7 @@ .macro _run_timer li TMP, MEM_MTIME_CTRL lw TMP2, 0(TMP) - li TMP3, (1 << YCR1_MTIME_CTRL_EN) + li TMP3, (1 << YCR_MTIME_CTRL_EN) or TMP2, TMP2, TMP3 sw TMP2, 0(TMP) .endm @@ -86,7 +86,7 @@ .macro _stop_timer li TMP, MEM_MTIME_CTRL lw TMP2, 0(TMP) - li TMP3, (1 << YCR1_MTIME_CTRL_EN) + li TMP3, (1 << YCR_MTIME_CTRL_EN) not TMP3, TMP3 and TMP2, TMP2, TMP3 sw TMP2, 0(TMP)
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index 8b2dd41..8dde135 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -288,7 +288,7 @@ repeat (2) @(posedge clock); #1; // Remove WB and SPI Reset, Keep SDARM and CORE under Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); // CS#2 Switch to QSPI Mode wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h1000); // Change the Bank Sel 1000 @@ -300,7 +300,13 @@ //wb_user_core_write('h3080_000C,{4'b0000,4'b1111, 24'h0}); // // Remove all the reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + if(d_risc_id == 0) begin + $display("STATUS: Working with Risc core 0"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + end else begin + $display("STATUS: Working with Risc core 1"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); + end end @@ -352,6 +358,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK logic [31:0] riscv_dmem_req_cnt; // cnt dmem req
diff --git a/verilog/dv/uart_master/Makefile b/verilog/dv/uart_master/Makefile index 7bcd2b7..3ec839e 100644 --- a/verilog/dv/uart_master/Makefile +++ b/verilog/dv/uart_master/Makefile
@@ -51,15 +51,12 @@ ## Compiler Information ####################################################################### -export GCC_PATH?= $(TOOLS)/bin -export GCC_PREFIX?= riscv32-unknown-linux-gnu +export TOOLS ?= /opt/riscv32i +export GCC_PATH ?= $(TOOLS)/bin +GCC_PREFIX?=riscv32-unknown-elf -############## USER SPECIFIC DEFINE ################## -YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware - -###################################################### @@ -153,28 +150,30 @@ ############################################################################## %.vvp: %_tb.v %.hex + +## RTL ifeq ($(SIM),RTL) ifeq ($(DUMP),OFF) - iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< else - iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $< endif -endif +endif -## GL +##GL ifeq ($(SIM),GL) - ifeq ($(CONFIG),caravel_user_project) - iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + ifeq ($(DUMP),OFF) + iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ -f$(VERILOG_PATH)/includes/includes.gl.caravel \ -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< else - iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ - -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \ - -f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $< + iverilog -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \ + -f$(VERILOG_PATH)/includes/includes.gl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $< endif endif @@ -223,3 +222,9 @@ \rm -f *.elf *.hex *.bin *.vvp *.log *.vcd *.lst *.hexe .PHONY: clean hex all + + + + + +
diff --git a/verilog/dv/uart_master/uart_master_tb.v b/verilog/dv/uart_master/uart_master_tb.v index 2b021ee..f49daab 100644 --- a/verilog/dv/uart_master/uart_master_tb.v +++ b/verilog/dv/uart_master/uart_master_tb.v
@@ -138,19 +138,19 @@ $display("Monitor: Writing expected value"); test_fail = 0; - uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344); - uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455); - uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566); - uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677); - uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788); - uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899); - uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344); - uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455); - uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566); - uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677); - uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788); - uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899); $display("###################################################"); if(test_fail == 0) begin
diff --git a/verilog/dv/user_aes/user_aes.c b/verilog/dv/user_aes/user_aes.c index f78b8fe..cd1bfec 100644 --- a/verilog/dv/user_aes/user_aes.c +++ b/verilog/dv/user_aes/user_aes.c
@@ -40,36 +40,20 @@ static int test_decrypt_ecb(void); static void test_encrypt_ecb_verbose(void); -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) -#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018) -#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C) -#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020) -#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024) -#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028) -#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C) -#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030) -#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034) -#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038) -#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C) -#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040) -#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044) -#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048) -#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C) -#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050) -#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054) -#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058) -#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C) -#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060) -#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064) -#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068) -#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C) +#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID +#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0 +#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1 +#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask +#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt +#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel +#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0 +#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1 +#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2 +#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3 +#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4 +#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5 -#define reg_mprg_pinmux_gpio_odata (*(volatile uint32_t*)0x10020018) +#define reg_mprg_gpio_odata (*(volatile uint32_t*)0x1002004C) int main(void) { @@ -86,34 +70,34 @@ return 0; #endif - reg_mprg_pinmux_gpio_odata = 0x00000100; - reg_mprj_globl_reg23 = 0x00000000; + reg_mprg_gpio_odata = 0x00000100; + reg_mprj_globl_soft0 = 0x00000000; exit = test_encrypt_cbc(); - reg_mprg_pinmux_gpio_odata = 0x00000200; - reg_mprj_globl_reg23 = exit; + reg_mprg_gpio_odata = 0x00000200; + reg_mprj_globl_soft0 = exit; exit += test_decrypt_cbc(); - reg_mprg_pinmux_gpio_odata = 0x00000300; - reg_mprj_globl_reg23 = exit; + reg_mprg_gpio_odata = 0x00000300; + reg_mprj_globl_soft0 = exit; exit += test_encrypt_ctr(); - reg_mprg_pinmux_gpio_odata = 0x00000400; - reg_mprj_globl_reg23 = exit; + reg_mprg_gpio_odata = 0x00000400; + reg_mprj_globl_soft0 = exit; exit += test_decrypt_ctr(); - reg_mprg_pinmux_gpio_odata = 0x00000500; - reg_mprj_globl_reg23 = exit; + reg_mprg_gpio_odata = 0x00000500; + reg_mprj_globl_soft0 = exit; exit += test_decrypt_ecb(); - reg_mprg_pinmux_gpio_odata = 0x00000600; - reg_mprj_globl_reg23 = exit; + reg_mprg_gpio_odata = 0x00000600; + reg_mprj_globl_soft0 = exit; exit += test_encrypt_ecb(); - reg_mprg_pinmux_gpio_odata = 0x00000700; - reg_mprj_globl_reg23 = exit; + reg_mprg_gpio_odata = 0x00000700; + reg_mprj_globl_soft0 = exit; test_encrypt_ecb_verbose(); - reg_mprg_pinmux_gpio_odata = 0x00000800; - reg_mprj_globl_reg23 = exit; + reg_mprg_gpio_odata = 0x00000800; + reg_mprj_globl_soft0 = exit; if(exit == 0) { - reg_mprg_pinmux_gpio_odata = 0x00001800; + reg_mprg_gpio_odata = 0x00001800; } else { - reg_mprg_pinmux_gpio_odata = 0x0000A800; + reg_mprg_gpio_odata = 0x0000A800; } return exit;
diff --git a/verilog/dv/user_aes/user_aes_tb.v b/verilog/dv/user_aes/user_aes_tb.v index 3d18ba5..769596e 100644 --- a/verilog/dv/user_aes/user_aes_tb.v +++ b/verilog/dv/user_aes/user_aes_tb.v
@@ -163,6 +163,9 @@ `endif initial begin + + $value$plusargs("risc_core_id=%d", d_risc_id); + uart_data_bit = 2'b11; uart_stop_bits = 0; // 0: 1 stop bit; 1: 2 stop bit; uart_stick_parity = 0; // 1: force even parity @@ -180,12 +183,24 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); // Enable UART Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h100); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100); repeat (2) @(posedge clock); #1; - // Remove all the reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + // Remove all the reset + if(d_risc_id == 0) begin + $display("STATUS: Working with Risc core 0"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + end else if(d_risc_id == 1) begin + $display("STATUS: Working with Risc core 1"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); + end else if(d_risc_id == 2) begin + $display("STATUS: Working with Risc core 2"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); + end else if(d_risc_id == 3) begin + $display("STATUS: Working with Risc core 3"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); + end repeat (100) @(posedge clock); // wait for Processor Get Ready @@ -195,9 +210,9 @@ uart_stick_parity, uart_timeout, uart_divisor); // Set the PORT-B Direction as Output - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h0000FF00); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h0000FF00); // Set the GPIO Output data: 0x00000000 - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'h0000000); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h0000000); fork begin @@ -208,7 +223,7 @@ end join_any - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h00000000); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h00000000); $display("###################################################"); if(test_fail == 0) begin @@ -272,6 +287,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index e5fea15..5f1c60b 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -240,35 +240,37 @@ test_step = 10; wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64}); clock_monitor(5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD); - - $display("###################################################"); - $display("Monitor: Checking the PLL:"); - $display("###################################################"); + + `ifndef GL + $display("###################################################"); + $display("Monitor: Checking the PLL:"); + $display("###################################################"); test_step = 11; // Set PLL enable, no DCO mode ; Set PLL output divider to 0x03 - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2}); - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000}); - repeat (100) @(posedge clock); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000}); + repeat (100) @(posedge clock); pll_clock_monitor(5); test_step = 12; // Set PLL enable, DCO mode ; Set PLL output divider to 0x01 - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2}); - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000}); - repeat (100) @(posedge clock); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000}); + repeat (100) @(posedge clock); pll_clock_monitor(4); - $display("###################################################"); - $display("Monitor: Monitor Clock output:"); - $display("###################################################"); + $display("###################################################"); + $display("Monitor: Monitor Clock output:"); + $display("###################################################"); $display("Monitor: CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)"); test_step = 13; - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64}); // Set PLL enable, DCO mode ; Set PLL output divider to 0x01 - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2}); - wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2}); + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000}); dbg_clk_monitor(79,60,5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD); + `endif $display("###################################################"); $display("Monitor: Checking the chip signature :"); @@ -277,9 +279,9 @@ // Remove Wb/PinMux Reset wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h0508_2022); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_9000); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h8273_8343); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h1508_2022); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h0005_0000); end @@ -343,7 +345,7 @@ // IOs - .io_in (io_in) , + .io_in ('h0) , .io_out (io_out) , .io_oeb (io_oeb) , @@ -389,7 +391,7 @@ begin //force clock_mon = u_top.u_wb_host.pll_clk_out[0]; `ifdef GL - force clock_mon = u_top.u_wb_host.u_clkbuf_pll.u_buf.X; + force clock_mon = u_top.u_wb_host.pll_clk_out[0]; `else force clock_mon = u_top.u_wb_host.u_clkbuf_pll.X; `endif
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass.c b/verilog/dv/user_cache_bypass/user_cache_bypass.c index 9c99cd9..a3e9b0d 100644 --- a/verilog/dv/user_cache_bypass/user_cache_bypass.c +++ b/verilog/dv/user_cache_bypass/user_cache_bypass.c
@@ -19,42 +19,28 @@ #define uint32_t long #define uint16_t int -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) -#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018) -#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C) -#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020) -#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024) -#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028) -#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C) -#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030) -#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034) -#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038) -#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C) -#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040) -#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044) -#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048) -#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C) -#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050) -#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054) -#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058) -#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C) -#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060) -#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064) -#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068) -#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C) +#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID +#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0 +#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1 +#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask +#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt +#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel +#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0 +#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1 +#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2 +#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3 +#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4 +#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5 + + // ------------------------------------------------------------------------- // Test copying code into SRAM and running it from there. // ------------------------------------------------------------------------- void test_function() { - reg_mprj_globl_reg24 = 0x33445566; // Sig-3 - reg_mprj_globl_reg25 = 0x44556677; // Sig-4 + reg_mprj_globl_soft2 = 0x33445566; // Sig-2 + reg_mprj_globl_soft3 = 0x44556677; // Sig-3 return; } @@ -69,18 +55,18 @@ src_ptr = &test_function; dst_ptr = func; - reg_mprj_globl_reg22 = 0x11223344; // Sig-1 + reg_mprj_globl_soft0 = 0x11223344; // Sig-0 while (src_ptr < &main) { *(dst_ptr++) = *(src_ptr++); } // Call the routine in SRAM - reg_mprj_globl_reg23 = 0x22334455; // Sig-2 + reg_mprj_globl_soft1 = 0x22334455; // Sig-1 ((void(*)())func)(); - reg_mprj_globl_reg26 = 0x55667788; - reg_mprj_globl_reg27 = 0x66778899; + reg_mprj_globl_soft4 = 0x55667788; + reg_mprj_globl_soft5 = 0x66778899; // Signal end of test }
diff --git a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v index c5d1478..28c8f2c 100644 --- a/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v +++ b/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v
@@ -135,15 +135,15 @@ repeat (2) @(posedge clock); #1; // Set the icahce and dcache bypass - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,{4'b0,2'b11,2'b00,8'b0,16'b0}); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG1,{4'b0,2'b11,2'b00,8'b0,16'b0}); // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); end else begin $display("STATUS: Working with Risc core 1"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); end @@ -165,12 +165,12 @@ // 0x3000002C = 0x66778899; test_fail = 0; - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899); @@ -234,6 +234,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/user_gpio/user_gpio_tb.v b/verilog/dv/user_gpio/user_gpio_tb.v index 5a30dd9..490a3a5 100644 --- a/verilog/dv/user_gpio/user_gpio_tb.v +++ b/verilog/dv/user_gpio/user_gpio_tb.v
@@ -217,7 +217,7 @@ /*****************************/ - wire [15:0] irq_lines = u_top.u_pinmux.u_pinmux_reg.irq_lines; + wire [15:0] irq_lines = u_top.u_pinmux.u_glbl_reg.irq_lines; initial begin clock = 0; @@ -252,34 +252,34 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); // Disable Multi func - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h000); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h000); /************* GPIO As Output ******************/ $display("#####################################"); $display("Step-1: Testing GPIO As Output "); // Set the Direction as Output - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'hFFFFFFFF); // Set the GPIO Output data: 0x55555555 - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'h55555555); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h55555555); cmp_gpio_output(8'h55,8'h55,8'h55,8'h55); // Set the GPIO Output data: 0xAAAAAAAA - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'hAAAAAAAA); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'hAAAAAAAA); cmp_gpio_output(8'hAA,8'hAA,8'hAA,8'hAA); // Set the GPIO Output data: 0x5A5A5A5A5A5A - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'h5A5A5A5A); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'h5A5A5A5A); cmp_gpio_output(8'h5A,8'h5A,8'h5A,8'h5A); // Set the GPIO Output data: 0xA5A5A5A5A5A5 - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_ODATA,'hA5A5A5A5); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_ODATA,'hA5A5A5A5); cmp_gpio_output(8'hA5,8'hA5,8'hA5,8'hA5); /************* GPIO As Input ******************/ $display("#####################################"); $display("Step-2: Testing GPIO As Input "); // Set the Direction as Input - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h00000000); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h00000000); cmp_gpio_input(8'h55,8'h55,8'h55,8'h55); cmp_gpio_input(8'hAA,8'hAA,8'hAA,8'hAA); @@ -290,12 +290,12 @@ $display("#####################################"); $display("Step-3: Testing GPIO As Posedge Interrupt "); // Set the Direction as Input - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h00000000); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h00000000); // Set GPIO for posedge Interrupt - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_MASK,'hFFFFFFFF); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_POS_INTR,'hFFFFFFFF); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_NEG_INTR,'h00000000); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'hFFFF); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_MASK,'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_POS_INTR_SEL,'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_NEG_INTR_SEL,'h00000000); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'hFFFF); // Drive GPIO with 0x55 cmp_gpio_pos_intr(8'h55,8'h55,8'h55,8'h55); @@ -314,12 +314,12 @@ $display("#####################################"); $display("Step-3: Testing GPIO As Negedge Interrupt "); // Set the Direction as Input - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_DSEL,'h00000000); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_DSEL,'h00000000); // Set GPIO for negedge Interrupt - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_MASK,'hFFFFFFFF); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_POS_INTR,'h00000000); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_NEG_INTR,'hFFFFFFFF); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'hFFFF); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_MASK,'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_POS_INTR_SEL,'h00000000); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_NEG_INTR_SEL,'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'hFFFF); // Drive GPIO with 0x55 cmp_gpio_neg_intr(8'h55,8'h55,8'h55,8'h55); @@ -399,6 +399,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work @@ -506,7 +509,7 @@ port_c_out = port_c; port_d_out = port_d; - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,8'h0}); + wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_IDATA,read_data,{port_d,port_c & 8'h7F,port_b,8'h0}); end endtask @@ -523,12 +526,12 @@ cmp_gpio_input(8'h00,8'h00,8'h00,8'h00); // Clear Global Interrupt - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h00008000); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h00008000); // Clear all the Interrupt - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,'hFFFFFFFF); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0); + wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0); // Drive Ports cmp_gpio_input(port_d,port_c,port_b,port_a); @@ -544,10 +547,10 @@ repeat (20) @(posedge clock); // Check the GPIO Interrupt - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,{port_d,port_c & 8'h7F,port_b,8'h0}); + wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,{port_d,port_c & 8'h7F,port_b,8'h0}); // Check The Global Interrupt - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h8000); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h8000); if(irq_lines[15] != 1'b1) begin $display("ERROR: Global GPIO Interrupt not detected"); @@ -555,15 +558,15 @@ end // Clear The GPIO Interrupt - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,32'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,32'hFFFFFFFF); // Clear GPIO Interrupt - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h8000); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h8000); // Check Interrupt are cleared - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h0); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h0); + wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0); if(irq_lines[15] != 1'b0) begin $display("ERROR: Global GPIO Interrupt is not cleared"); `TB_GLBL.test_fail = 1; @@ -584,11 +587,11 @@ cmp_gpio_input(8'hFF,8'hFF,8'hFF,8'hFF); // Clear Global Interrupt - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h00008000); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h00008000); // Clear all the Interrupt - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,'hFFFFFFFF); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,'hFFFFFFFF); + wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0); // Drive Ports cmp_gpio_input(port_d,port_c,port_b,port_a); @@ -603,10 +606,10 @@ repeat (20) @(posedge clock); // Neg edge interrupt is will compliment of input value - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,{port_d ^ 8'hFF,(port_c ^ 8'hFF) & 8'h7F,port_b ^ 8'hFF,8'h0}); + wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,{port_d ^ 8'hFF,(port_c ^ 8'hFF) & 8'h7F,port_b ^ 8'hFF,8'h0}); // Check The Global Interrupt - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h8000); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h8000); if(irq_lines[15] != 1'b1) begin $display("ERROR: Global GPIO Interrupt not detected"); @@ -614,14 +617,14 @@ end // Clear The GPIO Interrupt - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_CLR,32'hFFFFFFFF); + wb_user_core_write(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_CLR,32'hFFFFFFFF); // Clear GPIO Interrupt - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h8000); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,'h8000); // Check Interrupt are cleared - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data,32'h0); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_INTR_STAT,read_data,32'h0); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_STAT,read_data,32'h0); + wb_user_core_read_check(`ADDR_SPACE_GPIO+`GPIO_CFG_INTR_STAT,read_data,32'h0); if(irq_lines[15] != 1'b0) begin $display("ERROR: Global GPIO Interrupt is not cleared");
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v index e41e0d2..0814b1c 100644 --- a/verilog/dv/user_i2cm/user_i2cm_tb.v +++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -146,10 +146,10 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h01); // Enable I2C Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h8000); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h8000); // Remove i2m reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h010); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h010); repeat (100) @(posedge clock); @@ -337,6 +337,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v index e5222cc..584c4c2 100644 --- a/verilog/dv/user_pwm/user_pwm_tb.v +++ b/verilog/dv/user_pwm/user_pwm_tb.v
@@ -144,17 +144,17 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); // Enable PWM Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h03F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h03F); repeat (2) @(posedge clock); #1; // Remove the reset // Remove WB and SPI/UART Reset, Keep CORE under Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); // config 1us based on system clock - 1000/25ns = 40 - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_GLBL,39); test_fail = 0; repeat (200) @(posedge clock); @@ -162,12 +162,12 @@ $display("Step-1, PWM-0: 1ms/2 = 500Hz; PWM-1: 1ms/3; PWM-2: 1ms/4, PWM-3: 1ms/5, PWM-4: 1ms/6, PWM-5: 1ms/7"); test_step = 1; - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM0,'h0000_0000); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM1,'h0000_0001); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM2,'h0001_0001); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM3,'h0001_0002); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM4,'h0002_0002); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_PWM5,'h0002_0003); + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_0,'h0000_0000); + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_1,'h0000_0001); + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_2,'h0001_0001); + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_3,'h0001_0002); + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_4,'h0002_0002); + wb_user_core_write(`ADDR_SPACE_PWM+`PWM_CFG_PWM_5,'h0002_0003); pwm_monitor(OneMsPeriod*2,OneMsPeriod*3,OneMsPeriod*4,OneMsPeriod*5,OneMsPeriod*6,OneMsPeriod*7); repeat (100) @(posedge clock); @@ -300,6 +300,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v index 4fd07e5..89b05bd 100644 --- a/verilog/dv/user_qspi/user_qspi_tb.v +++ b/verilog/dv/user_qspi/user_qspi_tb.v
@@ -203,7 +203,7 @@ repeat (2) @(posedge clock); #1; // Remove only WB and SPI Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h2); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h2); wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_BANK_SEL,'h0000); // Change the Bank Sel 0000 @@ -1195,6 +1195,10 @@ ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK + `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work initial begin
diff --git a/verilog/dv/user_qspi/user_risc_boot.c b/verilog/dv/user_qspi/user_risc_boot.c index 0711b7b..83fb41b 100644 --- a/verilog/dv/user_qspi/user_risc_boot.c +++ b/verilog/dv/user_qspi/user_risc_boot.c
@@ -18,34 +18,18 @@ #define SC_SIM_OUTPORT (0xf0000000) #define uint32_t long -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x30030000) -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x30030004) -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x30030008) -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x3003000C) -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x30030010) -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x30030014) -#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x30030018) -#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x3003001C) -#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x30030020) -#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x30030024) -#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x30030028) -#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x3003002C) -#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x30030030) -#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x30030034) -#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x30030038) -#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x3003003C) -#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x30030040) -#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x30030044) -#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x30030048) -#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x3003004C) -#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x30030050) -#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x30030054) -#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x30030058) -#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x3003005C) -#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x30030060) -#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x30030064) -#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x30030068) -#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x3003006C) +#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID +#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0 +#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1 +#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask +#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt +#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel +#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0 +#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1 +#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2 +#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3 +#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4 +#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5 int main() { @@ -57,12 +41,12 @@ //*out_ptr = 0xDDEEFF00; // Write software Write & Read Register - reg_mprj_globl_reg22 = 0x11223344; - reg_mprj_globl_reg23 = 0x22334455; - reg_mprj_globl_reg24 = 0x33445566; - reg_mprj_globl_reg25 = 0x44556677; - reg_mprj_globl_reg26 = 0x55667788; - reg_mprj_globl_reg27 = 0x66778899; + reg_mprj_globl_soft0 = 0x11223344; + reg_mprj_globl_soft1 = 0x22334455; + reg_mprj_globl_soft2 = 0x33445566; + reg_mprj_globl_soft3 = 0x44556677; + reg_mprj_globl_soft4 = 0x55667788; + reg_mprj_globl_soft5 = 0x66778899; while(1) {} return 0;
diff --git a/verilog/dv/user_risc_boot/user_risc_boot.c b/verilog/dv/user_risc_boot/user_risc_boot.c index 37e424b..c14c9a7 100644 --- a/verilog/dv/user_risc_boot/user_risc_boot.c +++ b/verilog/dv/user_risc_boot/user_risc_boot.c
@@ -18,34 +18,18 @@ #define SC_SIM_OUTPORT (0xf0000000) #define uint32_t long -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) -#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018) -#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C) -#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020) -#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024) -#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028) -#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C) -#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030) -#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034) -#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038) -#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C) -#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040) -#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044) -#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048) -#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C) -#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050) -#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054) -#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058) -#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C) -#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060) -#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064) -#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068) -#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C) +#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID +#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0 +#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1 +#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask +#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt +#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel +#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0 +#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1 +#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2 +#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3 +#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4 +#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5 int main() { @@ -57,12 +41,12 @@ //*out_ptr = 0xDDEEFF00; // Write software Write & Read Register - reg_mprj_globl_reg22 = 0x11223344; - reg_mprj_globl_reg23 = 0x22334455; - reg_mprj_globl_reg24 = 0x33445566; - reg_mprj_globl_reg25 = 0x44556677; - reg_mprj_globl_reg26 = 0x55667788; - reg_mprj_globl_reg27 = 0x66778899; + reg_mprj_globl_soft0 = 0x11223344; + reg_mprj_globl_soft1 = 0x22334455; + reg_mprj_globl_soft2 = 0x33445566; + reg_mprj_globl_soft3 = 0x44556677; + reg_mprj_globl_soft4 = 0x55667788; + reg_mprj_globl_soft5 = 0x66778899; //reg_mprj_globl_reg12 = 0x778899AA; //reg_mprj_globl_reg13 = 0x8899AABB; //reg_mprj_globl_reg14 = 0x99AABBCC;
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v index b26d787..79c705b 100644 --- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v +++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -102,6 +102,7 @@ wire [7:0] mprj_io_0; reg test_fail; reg [31:0] read_data; + integer d_risc_id; @@ -130,6 +131,8 @@ initial begin + $value$plusargs("risc_core_id=%d", d_risc_id); + #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Risc Boot Test Started"); @@ -140,7 +143,13 @@ repeat (2) @(posedge clock); #1; // Remove all the reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + if(d_risc_id == 0) begin + $display("STATUS: Working with Risc core 0"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + end else begin + $display("STATUS: Working with Risc core 1"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); + end // Repeat cycles of 1000 clock edges as needed to complete testbench @@ -161,12 +170,12 @@ // 0x3000002C = 0x66778899; test_fail = 0; - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899); @@ -231,6 +240,11 @@ ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK + + `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work initial begin
diff --git a/verilog/dv/user_sema/Makefile b/verilog/dv/user_sema/Makefile new file mode 100644 index 0000000..c74412f --- /dev/null +++ b/verilog/dv/user_sema/Makefile
@@ -0,0 +1,84 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog + + +## Simulation mode: RTL/GL +SIM?=RTL +DUMP?=OFF + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + + +.SUFFIXES: + +PATTERN = user_sema + +all: ${PATTERN:=.vcd} + + +vvp: ${PATTERN:=.vvp} + +%.vvp: %_tb.v +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + endif +else + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + endif +endif + +%.vcd: %.vvp + vvp $< + + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump + +.PHONY: clean hex all
diff --git a/verilog/dv/user_sema/user_sema_tb.v b/verilog/dv/user_sema/user_sema_tb.v new file mode 100644 index 0000000..a4e08a2 --- /dev/null +++ b/verilog/dv/user_sema/user_sema_tb.v
@@ -0,0 +1,419 @@ +//////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +////////////////////////////////////////////////////////////////////// +//// //// +//// Hardware Semaphore validation Test bench //// +//// //// +//// This file is part of the YIFive cores project //// +//// https://github.com/dineshannayya/yifive_r0.git //// +//// //// +//// Description //// +//// This is a standalone test bench to validate the //// +//// Digital core. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 17th Aug 2022, Dinesh A //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`default_nettype wire + +`timescale 1 ns/10 ps + +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" + +`define TOP user_sema_tb + +module `TOP; +parameter CLK1_PERIOD = 10; +parameter CLK2_PERIOD = 2; + +reg clock ; +reg clock2 ; +reg wb_rst_i ; +reg power1, power2; +reg power3, power4; + +reg wbd_ext_cyc_i; // strobe/request +reg wbd_ext_stb_i; // strobe/request +reg [31:0] wbd_ext_adr_i; // address +reg wbd_ext_we_i; // write +reg [31:0] wbd_ext_dat_i; // data output +reg [3:0] wbd_ext_sel_i; // byte enable + +wire [31:0] wbd_ext_dat_o; // data input +wire wbd_ext_ack_o; // acknowlegement +wire wbd_ext_err_o; // error + +// User I/O +wire [37:0] io_oeb ; +wire [37:0] io_out ; +wire [37:0] io_in ; + +wire [37:0] mprj_io ; +wire [7:0] mprj_io_0 ; +reg test_fail ; +reg [31:0] read_data ; +reg [31:0] exp_data ; +//---------------------------------- +// Uart Configuration +// --------------------------------- +integer test_step; + +integer i,j; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #(CLK1_PERIOD/2) clock <= (clock === 1'b0); + always #(CLK2_PERIOD/2) clock2 <= (clock2 === 1'b0); + + initial begin + test_step = 0; + clock = 0; + clock2 = 0; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + end + + `ifdef WFDUMP + initial begin + $dumpfile("simx.vcd"); + $dumpvars(1, `TOP); + //$dumpvars(1, `TOP.u_top); + //$dumpvars(0, `TOP.u_top.u_pll); + $dumpvars(0, `TOP.u_top.u_wb_host); + //$dumpvars(1, `TOP.u_top.u_intercon); + //$dumpvars(1, `TOP.u_top.u_intercon); + $dumpvars(0, `TOP.u_top.u_pinmux); + end + `endif + + initial begin + wb_rst_i <= 1'b1; + #100; + wb_rst_i <= 1'b0; // Release reset + end + + +initial +begin + + #200; // Wait for reset removal + repeat (10) @(posedge clock); + $display("Monitor: Standalone User Basic Test Started"); + + repeat (2) @(posedge clock); + + test_fail=0; + fork + begin + // Remove Wb/PinMux Reset + wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + // Setting Lock Bit Individually and clearing it imediatly + for(i=0; i < 15; i = i+1) begin + read_data = 'h0; + // Step-1: Wait for Semaphore lock bit to '1' + while(read_data[0] == 0) begin + @(posedge clock) ; + wb_user_core_read(`ADDR_SPACE_SEMA+ (i*4),read_data); + end + // Step-2: Check is Really Lock Bit it Set the corresponding lock status + wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, 1<< i); + // Step-3: Clear the Lock Bit + wb_user_core_write(`ADDR_SPACE_SEMA+(i*4),1); + // Step-4: Check is Really Lock Bit it Cleared the corresponding lock status + wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, 0); + + end + // Setting all Lock Bit and clearing it end + exp_data = 'h0; + for(i=0; i < 15; i = i+1) begin + read_data = 'h0; + // Step-1: Wait for Semaphore lock bit to '1' + while(read_data[0] == 0) begin + @(posedge clock) ; + wb_user_core_read(`ADDR_SPACE_SEMA+(i*4),read_data); + end + exp_data = exp_data | (1<< i); + wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, exp_data); + end + // Step-2: Check all 15 Sema bit set + wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, 32'h7FFF); + exp_data = 32'h7FFF; + for(i=0; i < 15; i = i+1) begin + // Step-3: clear the Sema Bit + wb_user_core_write(`ADDR_SPACE_SEMA+(i*4),32'h1); + exp_data = exp_data ^ (1<< i); + wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, exp_data); + end + // Step-3: All hardware lock bit is cleared + wb_user_core_read_check(`ADDR_SPACE_SEMA+`SEMA_CFG_STATUS,read_data, 32'h0); + end + + begin + repeat (30000) @(posedge clock); + // $display("+1000 cycles"); + test_fail = 1; + end + join_any + disable fork; //disable pending fork activity + + + $display("###################################################"); + if(test_fail == 0) begin + `ifdef GL + $display("Monitor: Semaphore Test (GL) Passed"); + `else + $display("Monitor: Semaphore Test (RTL) Passed"); + `endif + end else begin + `ifdef GL + $display("Monitor: Semaphore Test (GL) Failed"); + `else + $display("Monitor: Semaphore Test (RTL) Failed"); + `endif + end + $display("###################################################"); + #100 + $finish; +end + + +wire USER_VDD1V8 = 1'b1; +wire VSS = 1'b0; + + +user_project_wrapper u_top( +`ifdef USE_POWER_PINS + .vccd1(USER_VDD1V8), // User area 1 1.8V supply + .vssd1(VSS), // User area 1 digital ground +`endif + .wb_clk_i (clock), // System clock + .user_clock2 (clock2), // Real-time clock + .wb_rst_i (wb_rst_i), // Regular Reset signal + + .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request + .wbs_stb_i (wbd_ext_stb_i), // strobe/request + .wbs_adr_i (wbd_ext_adr_i), // address + .wbs_we_i (wbd_ext_we_i), // write + .wbs_dat_i (wbd_ext_dat_i), // data output + .wbs_sel_i (wbd_ext_sel_i), // byte enable + + .wbs_dat_o (wbd_ext_dat_o), // data input + .wbs_ack_o (wbd_ext_ack_o), // acknowlegement + + + // Logic Analyzer Signals + .la_data_in ('1) , + .la_data_out (), + .la_oenb ('0), + + + // IOs + .io_in (io_in) , + .io_out (io_out) , + .io_oeb (io_oeb) , + + .user_irq () + +); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK + +`ifndef GL // Drive Power for Hold Fix Buf + // All standard cell need power hook-up for functionality work + initial begin + + + end +`endif + + + + + + +task wb_user_core_write; +input [31:0] address; +input [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h1; // write + wbd_ext_dat_i =data; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read; +input [31:0] address; +output [31:0] data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data); + repeat (2) @(posedge clock); +end +endtask + +task wb_user_core_read_check; +input [31:0] address; +output [31:0] data; +input [31:0] cmp_data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + repeat (1) @(negedge clock); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + test_fail = 1; + end else begin + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + end + repeat (2) @(posedge clock); +end +endtask + +`ifdef GL + +wire wbd_spi_stb_i = u_top.u_qspi_master.wbd_stb_i; +wire wbd_spi_ack_o = u_top.u_qspi_master.wbd_ack_o; +wire wbd_spi_we_i = u_top.u_qspi_master.wbd_we_i; +wire [31:0] wbd_spi_adr_i = u_top.u_qspi_master.wbd_adr_i; +wire [31:0] wbd_spi_dat_i = u_top.u_qspi_master.wbd_dat_i; +wire [31:0] wbd_spi_dat_o = u_top.u_qspi_master.wbd_dat_o; +wire [3:0] wbd_spi_sel_i = u_top.u_qspi_master.wbd_sel_i; + +wire wbd_uart_stb_i = u_top.u_uart_i2c_usb_spi.reg_cs; +wire wbd_uart_ack_o = u_top.u_uart_i2c_usb_spi.reg_ack; +wire wbd_uart_we_i = u_top.u_uart_i2c_usb_spi.reg_wr; +wire [8:0] wbd_uart_adr_i = u_top.u_uart_i2c_usb_spi.reg_addr; +wire [7:0] wbd_uart_dat_i = u_top.u_uart_i2c_usb_spi.reg_wdata; +wire [7:0] wbd_uart_dat_o = u_top.u_uart_i2c_usb_spi.reg_rdata; +wire wbd_uart_sel_i = u_top.u_uart_i2c_usb_spi.reg_be; + +`endif + +/** +`ifdef GL +//----------------------------------------------------------------------------- +// RISC IMEM amd DMEM Monitoring TASK +//----------------------------------------------------------------------------- + +`define RISC_CORE user_uart_tb.u_top.u_core.u_riscv_top + +always@(posedge `RISC_CORE.wb_clk) begin + if(`RISC_CORE.wbd_imem_ack_i) + $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i); + if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o); + if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o) + $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i); +end + +`endif +**/ +endmodule +`default_nettype wire
diff --git a/verilog/dv/user_spi_isp/user_spi_isp_tb.v b/verilog/dv/user_spi_isp/user_spi_isp_tb.v index a0e0fb5..0bbca8c 100644 --- a/verilog/dv/user_spi_isp/user_spi_isp_tb.v +++ b/verilog/dv/user_spi_isp/user_spi_isp_tb.v
@@ -154,19 +154,19 @@ $display("Monitor: Writing expected value"); test_fail = 0; - u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344); - u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455); - u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566); - u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677); - u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788); - u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899); + u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344); + u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455); + u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566); + u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677); + u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788); + u_spim.reg_wr_dword(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899); - u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344); - u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455); - u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566); - u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677); - u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788); - u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899); + u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344); + u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455); + u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566); + u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677); + u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788); + u_spim.reg_rd_dword_cmp(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899); @@ -229,6 +229,9 @@ ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work initial begin
diff --git a/verilog/dv/user_sram_exec/user_sram_exec.c b/verilog/dv/user_sram_exec/user_sram_exec.c index 62546a8..3f36137 100644 --- a/verilog/dv/user_sram_exec/user_sram_exec.c +++ b/verilog/dv/user_sram_exec/user_sram_exec.c
@@ -20,42 +20,26 @@ #define uint32_t long #define uint16_t int -#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) -#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) -#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) -#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) -#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) -#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) -#define reg_mprj_globl_reg6 (*(volatile uint32_t*)0x10020018) -#define reg_mprj_globl_reg7 (*(volatile uint32_t*)0x1002001C) -#define reg_mprj_globl_reg8 (*(volatile uint32_t*)0x10020020) -#define reg_mprj_globl_reg9 (*(volatile uint32_t*)0x10020024) -#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028) -#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C) -#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030) -#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034) -#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038) -#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C) -#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040) -#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044) -#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048) -#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C) -#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050) -#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054) -#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058) -#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C) -#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060) -#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064) -#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068) -#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C) +#define reg_mprj_globl_reg0 (*(volatile uint32_t*)0x10020000) // Chip ID +#define reg_mprj_globl_reg1 (*(volatile uint32_t*)0x10020004) // Global Config-0 +#define reg_mprj_globl_reg2 (*(volatile uint32_t*)0x10020008) // Global Config-1 +#define reg_mprj_globl_reg3 (*(volatile uint32_t*)0x1002000C) // Global Interrupt Mask +#define reg_mprj_globl_reg4 (*(volatile uint32_t*)0x10020010) // Global Interrupt +#define reg_mprj_globl_reg5 (*(volatile uint32_t*)0x10020014) // Multi functional sel +#define reg_mprj_globl_soft0 (*(volatile uint32_t*)0x10020018) // Sof Register-0 +#define reg_mprj_globl_soft1 (*(volatile uint32_t*)0x1002001C) // Sof Register-1 +#define reg_mprj_globl_soft2 (*(volatile uint32_t*)0x10020020) // Sof Register-2 +#define reg_mprj_globl_soft3 (*(volatile uint32_t*)0x10020024) // Sof Register-3 +#define reg_mprj_globl_soft4 (*(volatile uint32_t*)0x10020028) // Sof Register-4 +#define reg_mprj_globl_soft5 (*(volatile uint32_t*)0x1002002C) // Sof Register-5 // ------------------------------------------------------------------------- // Test copying code into SRAM and running it from there. // ------------------------------------------------------------------------- void test_function() { - reg_mprj_globl_reg24 = 0x33445566; // Sig-3 - reg_mprj_globl_reg25 = 0x44556677; // Sig-4 + reg_mprj_globl_soft2 = 0x33445566; // Sig-2 + reg_mprj_globl_soft3 = 0x44556677; // Sig-3 return; } @@ -70,18 +54,18 @@ src_ptr = &test_function; dst_ptr = func; - reg_mprj_globl_reg22 = 0x11223344; // Sig-1 + reg_mprj_globl_soft0 = 0x11223344; // Sig-0 while (src_ptr < &main) { *(dst_ptr++) = *(src_ptr++); } // Call the routine in SRAM - reg_mprj_globl_reg23 = 0x22334455; // Sig-2 + reg_mprj_globl_soft1 = 0x22334455; // Sig-1 ((void(*)())func)(); - reg_mprj_globl_reg26 = 0x55667788; - reg_mprj_globl_reg27 = 0x66778899; + reg_mprj_globl_soft4 = 0x55667788; // Sig-4 + reg_mprj_globl_soft5 = 0x66778899; // Sig-5 // Signal end of test }
diff --git a/verilog/dv/user_sram_exec/user_sram_exec_tb.v b/verilog/dv/user_sram_exec/user_sram_exec_tb.v index 2aaad02..555fc4b 100644 --- a/verilog/dv/user_sram_exec/user_sram_exec_tb.v +++ b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
@@ -137,10 +137,16 @@ // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); - end else begin + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); + end else if(d_risc_id == 2) begin + $display("STATUS: Working with Risc core 2"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); + end else if(d_risc_id == 3) begin + $display("STATUS: Working with Risc core 3"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); end @@ -162,12 +168,12 @@ // 0x3000002C = 0x66778899; test_fail = 0; - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788); - wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,read_data,32'h11223344); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,read_data,32'h22334455); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,read_data,32'h33445566); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,read_data,32'h44556677); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,read_data,32'h55667788); + wb_user_core_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,read_data,32'h66778899); @@ -231,6 +237,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v index 7a50429..eee28ca 100644 --- a/verilog/dv/user_sspi/user_sspi_tb.v +++ b/verilog/dv/user_sspi/user_sspi_tb.v
@@ -142,14 +142,14 @@ // Enable SPI Multi Functional Ports // wire cfg_spim_enb = cfg_multi_func_sel[10]; // wire [3:0] cfg_spim_cs_enb = cfg_multi_func_sel[14:11]; - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h7C00); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h7C00); repeat (2) @(posedge clock); #1; // Remove the reset // Remove WB and SPI/UART Reset, Keep CORE under Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); test_fail = 0; @@ -448,6 +448,11 @@ ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK + + `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work initial begin
diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v index b27d655..35c2e05 100644 --- a/verilog/dv/user_timer/user_timer_tb.v +++ b/verilog/dv/user_timer/user_timer_tb.v
@@ -146,13 +146,13 @@ // Remove the reset // Remove WB and SPI/UART Reset, Keep CORE under Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h01F); // config 1us based on system clock - 1000/25ns = 40 - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_GLBL,39); // Enable Timer Interrupt - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'h700); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_INTR_MSK,'h700); test_fail = 0; repeat (200) @(posedge clock); @@ -160,25 +160,25 @@ $display("Step-1, Timer-0: 1us * 100 = 100us; Timer-1: 200us; Timer-2: 300us"); test_step = 1; - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0001_0063); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0001_00C7); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0001_012B); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0001_0063); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0001_00C7); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0001_012B); timer_monitor(OneUsPeriod*100,OneUsPeriod*200,OneUsPeriod*300); $display("Checking the Timer Interrupt generation and clearing"); // Disable the Timer - To avoid multiple interrupt generation // during status check and interrupt clearing - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0000_0063); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0000_00C7); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0000_012B); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0000_0063); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0000_00C7); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0000_012B); - wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data); + wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data); if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b111)) begin $display("STATUS: Timer Interrupt detected "); // Clearing the Timer Interrupt - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h700); - wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data); + wb_user_core_write(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_CLR,'h700); + wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data); if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b000)) begin $display("ERROR: Timer Interrupt not cleared "); test_fail = 1; @@ -192,25 +192,25 @@ $display("Step-2, Timer-0: 1us * 200 = 200us; Timer-1: 300us; Timer-2: 400us"); test_step = 2; - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0001_00C7); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0001_012B); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0001_018F); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0001_00C7); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0001_012B); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0001_018F); timer_monitor(OneUsPeriod*200,OneUsPeriod*300,OneUsPeriod*400); $display("Checking the Timer Interrupt generation and clearing"); // Disable the Timer - To avoid multiple interrupt generation // during status check and interrupt clearing - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER0,'h0000_0063); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER1,'h0000_00C7); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_CFG_TIMER2,'h0000_012B); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_0,'h0000_0063); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_1,'h0000_00C7); + wb_user_core_write(`ADDR_SPACE_TIMER+`TIMER_CFG_TIMER_2,'h0000_012B); - wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data); + wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data); if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b111)) begin $display("STATUS: Timer Interrupt detected "); // Clearing the Timer Interrupt - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,'h700); - wb_user_core_read(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR,read_data); + wb_user_core_write(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_CLR,'h700); + wb_user_core_read(`ADDR_SPACE_GLBL+`GPIO_CFG_INTR_STAT,read_data); if((u_top.u_pinmux.irq_lines[10:8] == 3'b111) && (read_data[10:8] == 3'b000)) begin $display("ERROR: Timer Interrupt not cleared "); test_fail = 1; @@ -335,6 +335,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index f59c3a8..0096617 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -123,6 +123,8 @@ reg [7:0] uart_write_data [0:39]; reg uart_fifo_enable ; // fifo mode disable + integer d_risc_id; + integer i,j; // External clock is used by default. Make this artificially fast for the @@ -144,7 +146,8 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(0, user_uart_tb); + $dumpvars(1, user_uart_tb); + $dumpvars(1, user_uart_tb.u_top); end `endif @@ -164,6 +167,8 @@ uart_timeout = 500;// wait time limit uart_fifo_enable = 0; // fifo mode disable + $value$plusargs("risc_core_id=%d", d_risc_id); + #200; // Wait for reset removal repeat (10) @(posedge clock); $display("Monitor: Standalone User Uart Test Started"); @@ -172,12 +177,24 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); // Enable UART Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h100); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h100); repeat (2) @(posedge clock); #1; // Remove all the reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F); + if(d_risc_id == 0) begin + $display("STATUS: Working with Risc core 0"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h11F); + end else if(d_risc_id == 1) begin + $display("STATUS: Working with Risc core 1"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h21F); + end else if(d_risc_id == 2) begin + $display("STATUS: Working with Risc core 2"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h41F); + end else if(d_risc_id == 3) begin + $display("STATUS: Working with Risc core 3"); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h81F); + end repeat (100) @(posedge clock); // wait for Processor Get Ready @@ -283,6 +300,11 @@ ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK + + `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work initial begin
diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v index 44587e4..6a2d3c5 100644 --- a/verilog/dv/user_uart1/user_uart1_tb.v +++ b/verilog/dv/user_uart1/user_uart1_tb.v
@@ -176,23 +176,23 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); // Enable UART Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h200); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h200); repeat (2) @(posedge clock); #1; // Remove all the reset if(d_risc_id == 0) begin $display("STATUS: Working with Risc core 0"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h143); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h143); end else if(d_risc_id == 1) begin $display("STATUS: Working with Risc core 1"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h243); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h243); end else if(d_risc_id == 2) begin $display("STATUS: Working with Risc core 2"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h443); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h443); end else if(d_risc_id == 3) begin $display("STATUS: Working with Risc core 2"); - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h84F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h84F); end repeat (100) @(posedge clock); // wait for Processor Get Ready @@ -299,6 +299,11 @@ ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK + + `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work initial begin
diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v index 40d7b07..95f2049 100644 --- a/verilog/dv/user_uart_master/user_uart_master_tb.v +++ b/verilog/dv/user_uart_master/user_uart_master_tb.v
@@ -195,19 +195,19 @@ $display("Monitor: Writing expected value"); test_fail = 0; - uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344); - uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455); - uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566); - uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677); - uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788); - uartm_reg_write(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788); + uartm_reg_write(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899); - uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344); - uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455); - uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566); - uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677); - uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788); - uartm_reg_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_0,32'h11223344); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_1,32'h22334455); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_2,32'h33445566); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_3,32'h44556677); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_4,32'h55667788); + uartm_reg_read_check(`ADDR_SPACE_GLBL+`GLBL_CFG_SOFT_REG_5,32'h66778899); @@ -269,6 +269,9 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK `ifndef GL // Drive Power for Hold Fix Buf // All standard cell need power hook-up for functionality work
diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v index 5974990..778156e 100644 --- a/verilog/dv/user_usb/user_usb_tb.v +++ b/verilog/dv/user_usb/user_usb_tb.v
@@ -176,7 +176,7 @@ wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); // Enable SPI Multi Functional Ports - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_MUTI_FUNC,'h400); repeat (2) @(posedge clock); #1; @@ -188,7 +188,7 @@ // Remove the reset // Remove WB and SPI/UART Reset, Keep CORE under Reset - wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h03F); + wb_user_core_write(`ADDR_SPACE_GLBL+`GLBL_CFG_CFG0,'h03F); test_fail = 0; @@ -257,6 +257,11 @@ .user_irq () ); +// SSPI Slave I/F +assign io_in[0] = 1'b1; // RESET +assign io_in[16] = 1'b0 ; // SPIS SCK + + usb_agent u_usb_agent(); test_control test_control();
diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile index 5ae8623..3ec839e 100644 --- a/verilog/dv/wb_port/Makefile +++ b/verilog/dv/wb_port/Makefile
@@ -53,7 +53,7 @@ export TOOLS ?= /opt/riscv32i export GCC_PATH ?= $(TOOLS)/bin -export GCC_PREFIX?= riscv32-unknown-linux-gnu +GCC_PREFIX?=riscv32-unknown-elf
diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c index c626610..ef2d0a1 100644 --- a/verilog/dv/wb_port/wb_port.c +++ b/verilog/dv/wb_port/wb_port.c
@@ -98,31 +98,32 @@ reg_mprj_wbhost_reg0 = 0x1; // Remove Reset - reg_pinmux_gbl_cfg0 = 0x01f; + reg_glbl_cfg0 = 0x01f; - if (reg_pinmux_chip_id != 0x82681301) bFail = 1; + if (reg_pinmux_chip_id != 0x82681501) bFail = 1; + if (bFail == 1) reg_mprj_datal = 0xAB610000; // write software write & read Register - reg_pinmux_soft_reg_1 = 0x11223344; - reg_pinmux_soft_reg_2 = 0x22334455; - reg_pinmux_soft_reg_3 = 0x33445566; - reg_pinmux_soft_reg_4 = 0x44556677; - reg_pinmux_soft_reg_5 = 0x55667788; - reg_pinmux_soft_reg_6 = 0x66778899; + reg_glbl_soft_reg_0 = 0x11223344; + reg_glbl_soft_reg_1 = 0x22334455; + reg_glbl_soft_reg_2 = 0x33445566; + reg_glbl_soft_reg_3 = 0x44556677; + reg_glbl_soft_reg_4 = 0x55667788; + reg_glbl_soft_reg_5 = 0x66778899; - if (reg_pinmux_soft_reg_1 != 0x11223344) bFail = 1; - if (bFail == 1) reg_mprj_datal = 0xAB610000; - if (reg_pinmux_soft_reg_2 != 0x22334455) bFail = 1; + if (reg_glbl_soft_reg_0 != 0x11223344) bFail = 1; if (bFail == 1) reg_mprj_datal = 0xAB620000; - if (reg_pinmux_soft_reg_3 != 0x33445566) bFail = 1; + if (reg_glbl_soft_reg_1 != 0x22334455) bFail = 1; if (bFail == 1) reg_mprj_datal = 0xAB630000; - if (reg_pinmux_soft_reg_4 != 0x44556677) bFail = 1; + if (reg_glbl_soft_reg_2 != 0x33445566) bFail = 1; if (bFail == 1) reg_mprj_datal = 0xAB640000; - if (reg_pinmux_soft_reg_5 != 0x55667788) bFail = 1; + if (reg_glbl_soft_reg_3 != 0x44556677) bFail = 1; if (bFail == 1) reg_mprj_datal = 0xAB650000; - if (reg_pinmux_soft_reg_6 != 0x66778899) bFail = 1; + if (reg_glbl_soft_reg_4 != 0x55667788) bFail = 1; if (bFail == 1) reg_mprj_datal = 0xAB660000; + if (reg_glbl_soft_reg_5 != 0x66778899) bFail = 1; + if (bFail == 1) reg_mprj_datal = 0xAB670000; if(bFail == 0) { reg_mprj_datal = 0xAB6A0000;
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project index 2fce71e..92122c1 100644 --- a/verilog/includes/includes.rtl.caravel_user_project +++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -7,11 +7,19 @@ +incdir+$(USER_PROJECT_VERILOG)/dv/model +incdir+$(USER_PROJECT_VERILOG)/dv/agents $(USER_PROJECT_VERILOG)/rtl/user_reg_map.v +-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_top.sv -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv --v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_reg.sv +-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/glbl_reg.sv +-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_top.sv -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv +-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_reg.sv +-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_top.sv +-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm_reg.sv -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv +-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_top.sv +-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer_reg.sv -v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv +-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/semaphore_reg.sv -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv -v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv -v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv
diff --git a/verilog/rtl/lib/registers.v b/verilog/rtl/lib/registers.v index e4a87a1..b9a093e 100755 --- a/verilog/rtl/lib/registers.v +++ b/verilog/rtl/lib/registers.v
@@ -288,6 +288,45 @@ endmodule /********************************************************************* + module: generic 16b register +***********************************************************************/ +module gen_16b_reg ( + //List of Inputs + cs, + we, + data_in, + reset_n, + clk, + + //List of Outs + data_out + ); + + parameter RESET_DEFAULT = 16'h0; + input [1:0] we; + input cs; + input [15:0] data_in; + input reset_n; + input clk; + output [15:0] data_out; + + + reg [15:0] data_out; + +always @ (posedge clk or negedge reset_n) begin + if (reset_n == 1'b0) begin + data_out <= RESET_DEFAULT ; + end + else begin + if(cs && we[0]) data_out[7:0] <= data_in[7:0]; + if(cs && we[1]) data_out[15:8] <= data_in[15:8]; + end +end + + +endmodule + +/********************************************************************* module: generic 32b register ***********************************************************************/ module gen_32b_reg (
diff --git a/verilog/rtl/pinmux/src/glbl_reg.sv b/verilog/rtl/pinmux/src/glbl_reg.sv new file mode 100644 index 0000000..6ef9098 --- /dev/null +++ b/verilog/rtl/pinmux/src/glbl_reg.sv
@@ -0,0 +1,437 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// Global Register //// +//// //// +//// This file is part of the riscduino cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +//// Hold all the Global and PinMux Register //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 16th Feb 2021, Dinesh A //// +//// initial version //// +////////////////////////////////////////////////////////////////////// +// +module glbl_reg ( + // System Signals + // Inputs + input logic mclk , + input logic h_reset_n , + + // Global Reset control + output logic [1:0] cpu_core_rst_n , + output logic cpu_intf_rst_n , + output logic qspim_rst_n , + output logic sspim_rst_n , + output logic [1:0] uart_rst_n , + output logic i2cm_rst_n , + output logic usb_rst_n , + + // Reg Bus Interface Signal + input logic reg_cs , + input logic reg_wr , + input logic [3:0] reg_addr , + input logic [31:0] reg_wdata , + input logic [3:0] reg_be , + + // Outputs + output logic [31:0] reg_rdata , + output logic reg_ack , + + input logic [1:0] ext_intr_in , + + // Risc configuration + output logic [15:0] irq_lines , + output logic soft_irq , + output logic [2:0] user_irq , + input logic usb_intr , + input logic i2cm_intr , + + output logic [15:0] cfg_riscv_ctrl , + output logic [31:0] cfg_multi_func_sel ,// multifunction pins + + + input logic [2:0] timer_intr , + input logic gpio_intr + ); + + + +//----------------------------------------------------------------------- +// Internal Wire Declarations +//----------------------------------------------------------------------- + +logic sw_rd_en ; +logic sw_wr_en; +logic [4:0] sw_addr; // addressing 16 registers +logic [31:0] sw_reg_wdata; +logic [3:0] wr_be ; + +logic [31:0] reg_out; +logic [31:0] reg_0; // Chip ID +logic [31:0] reg_1; // Global Reg-0 +logic [31:0] reg_2; // Global Reg-1 +logic [31:0] reg_3; // Global Interrupt Mask +logic [31:0] reg_4; // Global Interrupt Status +logic [31:0] reg_5; // Multi Function Sel +logic [31:0] reg_6; // Software Reg-0 +logic [31:0] reg_7; // Software Reg-1 +logic [31:0] reg_8; // Software Reg-2 +logic [31:0] reg_9; // Software Reg-3 +logic [31:0] reg_10; // Software Reg-4 +logic [31:0] reg_11; // Software Reg-5 + + +logic cs_int; + + +assign sw_addr = reg_addr ; +assign sw_rd_en = reg_cs & !reg_wr; +assign sw_wr_en = reg_cs & reg_wr; +assign wr_be = reg_be; +assign sw_reg_wdata = reg_wdata; + + +always @ (posedge mclk or negedge h_reset_n) +begin : preg_out_Seq + if (h_reset_n == 1'b0) begin + reg_rdata <= 'h0; + reg_ack <= 1'b0; + end else if (reg_cs && !reg_ack) begin + reg_rdata <= reg_out ; + reg_ack <= 1'b1; + end else begin + reg_ack <= 1'b0; + end +end + + + +//----------------------------------------------------------------------- +// register read enable and write enable decoding logic +//----------------------------------------------------------------------- +wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0); +wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1); +wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2); +wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3); +wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4); +wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5); +wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6); +wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7); +wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8); +wire sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9); +wire sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA); +wire sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB); + + +wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0); +wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1); +wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2); +wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3); +wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4); +wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5); +wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6); +wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7); +wire sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8); +wire sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9); +wire sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA); +wire sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB); + +//----------------------------------------------------------------------- +// Individual register assignments +//----------------------------------------------------------------------- + +// Chip ID +// chip-id[3:0] mapping +// 0 - YIFIVE (MPW-2) +// 1 - Riscdunio (MPW-3) +// 2 - Riscdunio (MPW-4) +// 3 - Riscdunio (MPW-5) +// 4 - Riscdunio (MPW-6) +// 5 - Riscdunio (MPW-7) +// 6 - Riscdunio (MPW-8) +// 7 - Riscdunio (MPW-9) + +wire [15:0] manu_id = 16'h8268; // Asci value of RD +wire [3:0] total_core = 4'h1; +wire [3:0] chip_id = 4'h5; +wire [7:0] chip_rev = 8'h01; + +assign reg_0 = {manu_id,total_core,chip_id,chip_rev}; + + +//------------------------------------------ +// reg-1: GLBL_CFG_0 +//------------------------------------------ +wire [31:0] cfg_glb_ctrl = reg_1; + +ctech_buf u_buf_cpu_intf_rst (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n)); +ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n)); +ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n)); +ctech_buf u_buf_uart0_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n[0])); +ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n)); +ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[5]),.X(usb_rst_n)); +ctech_buf u_buf_uart1_rst (.A(cfg_glb_ctrl[6]),.X(uart_rst_n[1])); + +ctech_buf u_buf_cpu0_rst (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0])); +ctech_buf u_buf_cpu1_rst (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1])); + +gen_32b_reg #(32'h0) u_reg_1 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_1 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_1 ) + ); + +//---------------------------------------------- +// reg-2: GLBL_CFG_1 +//------------------------------------------ + +gen_32b_reg #(32'h0) u_reg_2 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_2 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_2 ) + ); + +assign cfg_riscv_ctrl = reg_2[31:16]; + +//----------------------------------------------------------------------- +// reg-3 : Global Interrupt Mask +//----------------------------------------------------------------------- + +gen_32b_reg #(32'h0) u_reg_3 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_3 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_3 ) + ); + +//----------------------------------------------------------------------- +// reg-4 : Global Interrupt Status +//----------------------------------------------------------------- +assign irq_lines = reg_3[15:0] & reg_4[15:0]; +assign soft_irq = reg_3[16] & reg_4[16]; +assign user_irq = reg_3[19:17]& reg_4[19:17]; + + +generic_register #(8,0 ) u_reg4_be0 ( + .we ({8{sw_wr_en_4 & + wr_be[0] }} ), + .data_in (sw_reg_wdata[7:0] ), + .reset_n (h_reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_4[7:0] ) + ); + + +wire [7:0] hware_intr_req = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr,timer_intr[2:0]}; + +generic_intr_stat_reg #(.WD(8), + .RESET_DEFAULT(0)) u_reg4_be1 ( + //inputs + .clk (mclk ), + .reset_n (h_reset_n ), + .reg_we ({8{sw_wr_en_4 & reg_ack & + wr_be[1] }} ), + .reg_din (sw_reg_wdata[15:8] ), + .hware_req (hware_intr_req ), + + //outputs + .data_out (reg_4[15:8] ) + ); + + + +generic_register #(4,0 ) u_reg4_be2 ( + .we ({4{sw_wr_en_4 & + wr_be[2] }} ), + .data_in (sw_reg_wdata[19:16]), + .reset_n (h_reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_4[19:16] ) + ); + +assign reg_4[31:20] = '0; + + +//----------------------------------------------------------------------- +// Logic for cfg_multi_func_sel :Enable GPIO to act as multi function pins +//----------------------------------------------------------------------- +assign cfg_multi_func_sel = reg_5[31:0]; // to be used for read + + +gen_32b_reg #(32'h0) u_reg_5 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_5 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_5 ) + ); + +//----------------------------------------- +// Software Reg-0 : ASCI Representation of RISC = 32'h8273_8343 +// ---------------------------------------- +gen_32b_reg #(32'h8273_8343) u_reg_6 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_6 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_6 ) + ); + +//----------------------------------------- +// Software Reg-1, Release date: <DAY><MONTH><YEAR> +// ---------------------------------------- +gen_32b_reg #(32'h1508_2022) u_reg_7 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_7 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_7 ) + ); + +//----------------------------------------- +// Software Reg-2: Poject Revison 5.0 = 0005000 +// ---------------------------------------- +gen_32b_reg #(32'h0005_0000) u_reg_8 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_8 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_8 ) + ); + +//----------------------------------------- +// Software Reg-3 +// ---------------------------------------- +gen_32b_reg #(32'h0) u_reg_9 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_9 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_9 ) + ); + +//----------------------------------------- +// Software Reg-4 +// ---------------------------------------- +gen_32b_reg #(32'h0) u_reg_10 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_10 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_10 ) + ); + +//----------------------------------------- +// Software Reg-5 +// ---------------------------------------- +gen_32b_reg #(32'h0) u_reg_11 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_11 ), + .we (wr_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_11 ) + ); + + + +//----------------------------------------------------------------------- +// Register Read Path Multiplexer instantiation +//----------------------------------------------------------------------- + +always_comb +begin + reg_out [31:0] = 32'h0; + + case (sw_addr [3:0]) + 4'b0000 : reg_out [31:0] = reg_0 [31:0]; + 4'b0001 : reg_out [31:0] = reg_1 [31:0]; + 4'b0010 : reg_out [31:0] = reg_2 [31:0]; + 4'b0011 : reg_out [31:0] = reg_3 [31:0]; + 4'b0100 : reg_out [31:0] = reg_4 [31:0]; + 4'b0101 : reg_out [31:0] = reg_5 [31:0]; + 4'b0110 : reg_out [31:0] = reg_6 [31:0]; + 4'b0111 : reg_out [31:0] = reg_7 [31:0]; + 4'b1000 : reg_out [31:0] = reg_8 [31:0]; + 4'b1001 : reg_out [31:0] = reg_9 [31:0]; + 4'b1010 : reg_out [31:0] = reg_10 [31:0]; + 4'b1011 : reg_out [31:0] = reg_11 [31:0]; + default : reg_out [31:0] = 32'h0; + endcase +end + + +endmodule
diff --git a/verilog/rtl/pinmux/src/gpio_control.sv b/verilog/rtl/pinmux/src/gpio_control.sv deleted file mode 100644 index 4c917dc..0000000 --- a/verilog/rtl/pinmux/src/gpio_control.sv +++ /dev/null
@@ -1,44 +0,0 @@ - -// GPIO Interrupt Generation -module gpio_intr ( - input logic mclk ,// System clk - input logic h_reset_n ,// system reset - input logic [31:0] gpio_prev_indata ,// previously captured GPIO I/P pins data - input logic [31:0] cfg_gpio_data_in ,// GPIO I/P pins data captured into this - input logic [31:0] cfg_gpio_out_data ,// GPIO statuc O/P data from config reg - input logic [31:0] cfg_gpio_dir_sel ,// decides on GPIO pin is I/P or O/P at pad level - input logic [31:0] cfg_gpio_posedge_int_sel ,// select posedge interrupt - input logic [31:0] cfg_gpio_negedge_int_sel ,// select negedge interrupt - - - output logic [31:0] pad_gpio_out ,// GPIO O/P to the gpio cfg reg - output logic [31:0] gpio_int_event // to the cfg interrupt status reg - -); - - -integer i; -//----------------------------------------------------------------------- -// Logic for interrupt detection -//----------------------------------------------------------------------- - -reg [31:0] local_gpio_int_event; // to the cfg interrupt status reg -always @(cfg_gpio_data_in or cfg_gpio_negedge_int_sel or cfg_gpio_posedge_int_sel - or gpio_prev_indata) -begin - for (i=0; i<32; i=i+1) - begin - // looking for rising edge int - local_gpio_int_event[i] = ((cfg_gpio_posedge_int_sel[i] & ~gpio_prev_indata[i] - & cfg_gpio_data_in[i]) | - (cfg_gpio_negedge_int_sel[i] & gpio_prev_indata[i] & - ~cfg_gpio_data_in[i])); - // looking for falling edge int - end -end - -assign gpio_int_event = local_gpio_int_event[31:0]; // goes as O/P to the cfg reg - -assign pad_gpio_out = cfg_gpio_out_data[31:0] ;// O/P on the GPIO bus - -endmodule
diff --git a/verilog/rtl/pinmux/src/gpio_reg.sv b/verilog/rtl/pinmux/src/gpio_reg.sv new file mode 100644 index 0000000..be61923 --- /dev/null +++ b/verilog/rtl/pinmux/src/gpio_reg.sv
@@ -0,0 +1,325 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// GPIO Register //// +//// //// +//// This file is part of the riscduino cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 15th Aug 2022, Dinesh A //// +//// initial version //// +////////////////////////////////////////////////////////////////////// +// +module gpio_reg ( + // System Signals + // Inputs + input logic mclk , + input logic h_reset_n , + + // Reg Bus Interface Signal + input logic reg_cs , + input logic reg_wr , + input logic [3:0] reg_addr , + input logic [31:0] reg_wdata , + input logic [3:0] reg_be , + + // Outputs + output logic [31:0] reg_rdata , + output logic reg_ack , + + + input logic [31:0] gpio_in_data , + output logic [31:0] gpio_prev_indata ,// previously captured GPIO I/P pins data + input logic [31:0] gpio_int_event , + output logic [31:0] cfg_gpio_out_data ,// GPIO statuc O/P data from config reg + output logic [31:0] cfg_gpio_dir_sel ,// decides on GPIO pin is I/P or O/P at pad level, 0 -> Input, 1 -> Output + output logic [31:0] cfg_gpio_out_type ,// GPIO Type, Unused + output logic [31:0] cfg_multi_func_sel ,// GPIO Multi function type + output logic [31:0] cfg_gpio_posedge_int_sel ,// select posedge interrupt + output logic [31:0] cfg_gpio_negedge_int_sel ,// select negedge interrupt + output logic [31:00] cfg_gpio_data_in , + + output logic gpio_intr + + + ); + +//----------------------------------------------------------------------- +// Internal Wire Declarations +//----------------------------------------------------------------------- + +logic sw_rd_en ; +logic sw_wr_en ; +logic [3:0] sw_addr ; // addressing 16 registers +logic [31:0] sw_reg_wdata ; +logic [3:0] sw_be ; + +logic [31:0] reg_out ; +logic [31:0] reg_0 ; // GPIO Direction Select +logic [31:0] reg_1 ; // GPIO TYPE - Unused +logic [31:0] reg_2 ; // GPIO IN DATA +logic [31:0] reg_3 ; // GPIO OUT DATA +logic [31:0] reg_4 ; // GPIO INTERRUPT STATUS/CLEAR +logic [31:0] reg_5 ; // GPIO INTERRUPT SET +logic [31:0] reg_6 ; // GPIO INTERRUPT MASK +logic [31:0] reg_7 ; // GPIO POSEDGE INTERRUPT SEL +logic [31:0] reg_8 ; // GPIO NEGEDGE INTERRUPT SEL + +assign sw_addr = reg_addr; +assign sw_rd_en = reg_cs & !reg_wr; +assign sw_wr_en = reg_cs & reg_wr; +assign sw_be = reg_be; +assign sw_reg_wdata = reg_wdata; + +//----------------------------------------------------------------------- +// register read enable and write enable decoding logic +//----------------------------------------------------------------------- +wire sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0); +wire sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1); +wire sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2); +wire sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3); +wire sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4); +wire sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5); +wire sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6); +wire sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7); +wire sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8); + +wire sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0); +wire sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1); +wire sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2); +wire sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3); +wire sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4); +wire sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5); +wire sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6); +wire sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7); +wire sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8); + + +always @ (posedge mclk or negedge h_reset_n) +begin : preg_out_Seq + if (h_reset_n == 1'b0) begin + reg_rdata <= 'h0; + reg_ack <= 1'b0; + end else if (reg_cs && !reg_ack) begin + reg_rdata <= reg_out; + reg_ack <= 1'b1; + end else begin + reg_ack <= 1'b0; + end +end + +//----------------------------------------------------------------------- +// Logic for cfg_gpio_dir_sel +//----------------------------------------------------------------------- +assign cfg_gpio_dir_sel = reg_0[31:0]; // data to the GPIO O/P pins + +gen_32b_reg #(32'h0) u_reg_0 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_0 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_0 ) + ); +//----------------------------------------------------------------------- +// Logic for cfg_gpio_out_type +//----------------------------------------------------------------------- +assign cfg_gpio_out_type = reg_1[31:0]; // Un-used + +gen_32b_reg #(32'h0) u_reg_1 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_1 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_1 ) + ); +//----------------------------------------------------------------------- +// Logic for gpio_data_in +//----------------------------------------------------------------------- +logic [31:0] gpio_in_data_s; +logic [31:0] gpio_in_data_ss; +// Double Sync the gpio pin data for edge detection +always @ (posedge mclk or negedge h_reset_n) +begin + if (h_reset_n == 1'b0) begin + reg_2 <= 'h0 ; + gpio_in_data_s <= 32'd0; + gpio_in_data_ss <= 32'd0; + end + else begin + gpio_in_data_s <= gpio_in_data; + gpio_in_data_ss <= gpio_in_data_s; + reg_2 <= gpio_in_data_ss; + end +end + + +assign cfg_gpio_data_in = reg_2[31:0]; // to be used for edge interrupt detect +assign gpio_prev_indata = gpio_in_data_ss; + +//----------------------------------------------------------------------- +// Logic for cfg_gpio_out_data +//----------------------------------------------------------------------- +assign cfg_gpio_out_data = reg_3[31:0]; // data to the GPIO control blk + +gen_32b_reg #(32'h0) u_reg_3 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_3 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_3 ) + ); + + + +//-------------------------------------------------------- +// Interrupt Status Generation +// Note: Reg_4 --> Interrupt Status Register, Writting '1' will clear the +// corresponding interrupt status bit. Writting '0' has no +// effect +// Reg_5 --> Writting one to this register will set the interrupt in +// interrupt status register (reg_4), Writting '0' does not has any +// effect. +/// Always update int_status, even if no register write is occuring. +// Interrupt posting is higher priority than int clear by host +//-------------------------------------------------------- +wire [31:0] gpio_int_status = reg_4; + +generic_intr_stat_reg #(.WD(32), + .RESET_DEFAULT(0)) u_reg_4 ( + //inputs + .clk (mclk ), + .reset_n (h_reset_n ), + .reg_we ({ + {8{sw_wr_en_4 & reg_ack & sw_be[2]}}, + {8{sw_wr_en_4 & reg_ack & sw_be[2]}}, + {8{sw_wr_en_4 & reg_ack & sw_be[1]}}, + {8{sw_wr_en_4 & reg_ack & sw_be[0]}} + } ), + .reg_din (sw_reg_wdata[31:0] ), + .hware_req (gpio_int_event | { + {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[31:24], + {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[23:16], + {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[15:8] , + {8{sw_wr_en_5 & reg_ack}} & sw_reg_wdata[7:0] + } ), + + //outputs + .data_out (reg_4[31:0] ) + ); +//------------------------------------------------- +// Returns same value as interrupt status register +//------------------------------------------------ + +assign reg_5 = reg_4; +//----------------------------------------------------------------------- +// Logic for cfg_gpio_int_mask : GPIO interrupt mask +//----------------------------------------------------------------------- +wire [31:0] cfg_gpio_int_mask = reg_6[31:0]; // to be used for read + +assign gpio_intr = ( | (reg_4 & reg_6) ); // interrupt pin to the RISC + + +// Register-11 +gen_32b_reg #(32'h0) u_reg_6 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_6 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_6 ) + ); +//----------------------------------------------------------------------- +// Logic for cfg_gpio_posedge_int_sel : Enable posedge GPIO interrupt +//----------------------------------------------------------------------- +assign cfg_gpio_posedge_int_sel = reg_7[31:0]; // to be used for read +gen_32b_reg #(32'h0) u_reg_7 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_7 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_7 ) + ); +//----------------------------------------------------------------------- +// Logic for cfg_gpio_negedge_int_sel : Enable negedge GPIO interrupt +//----------------------------------------------------------------------- +assign cfg_gpio_negedge_int_sel = reg_8[31:0]; // to be used for read +gen_32b_reg #(32'h0) u_reg_8 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_8 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_8 ) + ); + + +//----------------------------------------------------------------------- +// Register Read Path Multiplexer instantiation +//----------------------------------------------------------------------- + +always_comb +begin + reg_out [31:0] = 32'h0; + + case (sw_addr [3:0]) + 4'b0000 : reg_out [31:0] = reg_0 [31:0]; + 4'b0001 : reg_out [31:0] = reg_1 [31:0]; + 4'b0010 : reg_out [31:0] = reg_2 [31:0]; + 4'b0011 : reg_out [31:0] = reg_3 [31:0]; + 4'b0100 : reg_out [31:0] = reg_4 [31:0]; + 4'b0101 : reg_out [31:0] = reg_5 [31:0]; + 4'b0110 : reg_out [31:0] = reg_6 [31:0]; + 4'b0111 : reg_out [31:0] = reg_7 [31:0]; + 4'b1000 : reg_out [31:0] = reg_8 [31:0]; + default : reg_out [31:0] = 32'h0; + endcase +end + +endmodule
diff --git a/verilog/rtl/pinmux/src/gpio_top.sv b/verilog/rtl/pinmux/src/gpio_top.sv new file mode 100644 index 0000000..0a7fd02 --- /dev/null +++ b/verilog/rtl/pinmux/src/gpio_top.sv
@@ -0,0 +1,130 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// GPIO Top //// +//// //// +//// This file is part of the riscduino cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +/// //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 15th Aug 2022, Dinesh A //// +//// initial version //// +////////////////////////////////////////////////////////////////////// + +module gpio_top ( + // System Signals + // Inputs + input logic mclk, + input logic h_reset_n, + + // Reg Bus Interface Signal + input logic reg_cs, + input logic reg_wr, + input logic [3:0] reg_addr, + input logic [31:0] reg_wdata, + input logic [3:0] reg_be, + + // Outputs + output logic [31:0] reg_rdata, + output logic reg_ack, + + output logic [31:0] cfg_gpio_dir_sel, + input logic [31:0] pad_gpio_in, + output logic [31:0] pad_gpio_out, + + output logic gpio_intr + + ); + + +logic [31:0] gpio_prev_indata ;// previously captured GPIO I/P pins data +logic [31:0] cfg_gpio_out_data ;// GPIO statuc O/P data from config reg +logic [31:0] cfg_gpio_out_type ;// GPIO Type, Unused +logic [31:0] cfg_multi_func_sel ;// GPIO Multi function type +logic [31:0] cfg_gpio_posedge_int_sel ;// select posedge interrupt +logic [31:0] cfg_gpio_negedge_int_sel ;// select negedge interrupt +logic [31:00] cfg_gpio_data_in ; +logic [31:0] gpio_int_event ; + + +gpio_reg u_reg ( + .mclk (mclk ), + .h_reset_n (h_reset_n ), + + // Reg Bus Interface Signal + .reg_cs (reg_cs ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr ), + .reg_wdata (reg_wdata ), + .reg_be (reg_be ), + + // Outputs + .reg_rdata (reg_rdata ), + .reg_ack (reg_ack ), + + // GPIO input pins + .gpio_in_data (pad_gpio_in ), + .gpio_prev_indata (gpio_prev_indata ), + .gpio_int_event (gpio_int_event ), + + // GPIO config pins + .cfg_gpio_out_data (cfg_gpio_out_data ), + .cfg_gpio_dir_sel (cfg_gpio_dir_sel ), + .cfg_gpio_out_type (cfg_gpio_out_type ), + .cfg_gpio_posedge_int_sel (cfg_gpio_posedge_int_sel), + .cfg_gpio_negedge_int_sel (cfg_gpio_negedge_int_sel), + .cfg_multi_func_sel (cfg_multi_func_sel ), + .cfg_gpio_data_in (cfg_gpio_data_in ), + + .gpio_intr (gpio_intr ) + + + ); + + +gpio_intr_gen u_gpio_intr ( + // System Signals + // Inputs + .mclk (mclk ), + .h_reset_n (h_reset_n ), + + // GPIO cfg input pins + .gpio_prev_indata (gpio_prev_indata ), + .cfg_gpio_data_in (cfg_gpio_data_in ), + .cfg_gpio_dir_sel (cfg_gpio_dir_sel ), + .cfg_gpio_out_data (cfg_gpio_out_data ), + .cfg_gpio_posedge_int_sel(cfg_gpio_posedge_int_sel), + .cfg_gpio_negedge_int_sel(cfg_gpio_negedge_int_sel), + + + // GPIO output pins + .pad_gpio_out (pad_gpio_out ), + .gpio_int_event (gpio_int_event ) + ); + +endmodule
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index e36556c..54c0ef9 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -17,13 +17,13 @@ // ////////////////////////////////////////////////////////////////////// //// //// -//// Pinmux //// +//// Pinmux //// //// //// //// This file is part of the riscduino cores project //// //// https://github.com/dineshannayya/riscduino.git //// //// //// //// Description //// -//// PinMux Manages all the pin multiplexing //// +//// Manages all the pin multiplexing //// //// //// //// To Do: //// //// nothing //// @@ -32,482 +32,9 @@ //// - Dinesh Annayya, dinesha@opencores.org //// //// //// //// Revision : //// -//// 0.1 - 16th Feb 2021, Dinesh A //// -//// initial version //// -//// 0.2 - 6 April 2021, Dinesh A //// -//// 1. SSPI CS# increased from 1 to 4 //// -// 2. UART I/F increase from 1 to 2 //// -//// 0.3 - 8 July 2022, Dinesh A //// -//// In ardunio, SPI chip select are control through //// -//// GPIO, So we have moved the Auto generated SPI CS //// -//// different config bit. I2C config position moved from//// -//// bit[14] to bit [15] //// -//// 0.4 - 20 July 2022, Dinesh A //// -//// On Power On, If RESET* = 0, then system will enter //// -//// in to SPIS slave mode to support boot //// +//// 0.1 - 16th Aug 2022, Dinesh A //// +//// Seperated the pinmux from pinmux_top module //// ////////////////////////////////////////////////////////////////////// - -module pinmux ( - `ifdef USE_POWER_PINS - input logic vccd1,// User area 1 1.8V supply - input logic vssd1,// User area 1 digital ground - `endif - // clock skew adjust - input logic [3:0] cfg_cska_pinmux, - input logic wbd_clk_int, - output logic wbd_clk_pinmux, - // System Signals - // Inputs - input logic mclk, - input logic h_reset_n, - - // Global Reset control - output logic [1:0] cpu_core_rst_n , - output logic cpu_intf_rst_n , - output logic qspim_rst_n , - output logic sspim_rst_n , - output logic [1:0] uart_rst_n , - output logic i2cm_rst_n , - output logic usb_rst_n , - - output logic [15:0] cfg_riscv_ctrl, - - // Reg Bus Interface Signal - input logic reg_cs, - input logic reg_wr, - input logic [7:0] reg_addr, - input logic [31:0] reg_wdata, - input logic [3:0] reg_be, - - // Outputs - output logic [31:0] reg_rdata, - output logic reg_ack, - - // Risc configuration - output logic [15:0] irq_lines, - output logic soft_irq, - output logic [2:0] user_irq, - input logic usb_intr, - input logic i2cm_intr, - - // Digital IO - output logic [37:0] digital_io_out, - output logic [37:0] digital_io_oen, - input logic [37:0] digital_io_in, - - // SFLASH I/F - input logic sflash_sck, - input logic [3:0] sflash_ss, - input logic [3:0] sflash_oen, - input logic [3:0] sflash_do, - output logic [3:0] sflash_di, - - // SSRAM I/F - Temp Masked - //input logic ssram_sck, - //input logic ssram_ss, - //input logic [3:0] ssram_oen, - //input logic [3:0] ssram_do, - //output logic [3:0] ssram_di, - - // USB I/F - input logic usb_dp_o, - input logic usb_dn_o, - input logic usb_oen, - output logic usb_dp_i, - output logic usb_dn_i, - - // UART I/F - input logic [1:0] uart_txd, - output logic [1:0] uart_rxd, - - // I2CM I/F - input logic i2cm_clk_o, - output logic i2cm_clk_i, - input logic i2cm_clk_oen, - input logic i2cm_data_oen, - input logic i2cm_data_o, - output logic i2cm_data_i, - - // SPI MASTER - input logic spim_sck, - input logic [3:0] spim_ssn, - input logic spim_miso, - output logic spim_mosi, - - // SPI SLAVE - output logic spis_sck, - output logic spis_ssn, - input logic spis_miso, - output logic spis_mosi, - - // UART MASTER I/F - output logic uartm_rxd , - input logic uartm_txd , - - output logic pulse1m_mclk, - output logic [31:0] pinmux_debug, - - input logic dbg_clk_mon - - ); - - - -logic sreset_n; // Sync Reset - -/* clock pulse */ -//******************************************************** -logic pulse_1us ; // 1 UsSecond Pulse for waveform Generator -logic pulse_1ms ; // 1 UsSecond Pulse for waveform Generator -logic pulse_1s ; // 1Second Pulse for waveform Generator -logic [9:0] cfg_pulse_1us ; // 1us pulse generation config - - -//--------------------------------------------------------- -// Timer Register -// ------------------------------------------------------- -logic [2:0] cfg_timer_update ; // CPU write to timer register -logic [31:0] cfg_timer0 ; // Timer-0 register -logic [31:0] cfg_timer1 ; // Timer-1 register -logic [31:0] cfg_timer2 ; // Timer-2 register -logic [2:0] timer_intr ; - -//--------------------------------------------------- -// 6 PWM variabled -//--------------------------------------------------- - -logic [5:0] pwm_wfm ; -logic [5:0] cfg_pwm_enb ; -logic [15:0] cfg_pwm0_high ; -logic [15:0] cfg_pwm0_low ; -logic [15:0] cfg_pwm1_high ; -logic [15:0] cfg_pwm1_low ; -logic [15:0] cfg_pwm2_high ; -logic [15:0] cfg_pwm2_low ; -logic [15:0] cfg_pwm3_high ; -logic [15:0] cfg_pwm3_low ; -logic [15:0] cfg_pwm4_high ; -logic [15:0] cfg_pwm4_low ; -logic [15:0] cfg_pwm5_high ; -logic [15:0] cfg_pwm5_low ; - - -wire [31:0] gpio_prev_indata ;// previously captured GPIO I/P pins data -wire [31:0] cfg_gpio_out_data ;// GPIO statuc O/P data from config reg -wire [31:0] cfg_gpio_dir_sel ;// decides on GPIO pin is I/P or O/P at pad level, 0 -> Input, 1 -> Output -wire [31:0] cfg_gpio_out_type ;// GPIO Type, Unused -wire [31:0] cfg_multi_func_sel ;// GPIO Multi function type -wire [31:0] cfg_gpio_posedge_int_sel ;// select posedge interrupt -wire [31:0] cfg_gpio_negedge_int_sel ;// select negedge interrupt -wire [31:00] cfg_gpio_data_in ; - - -reg [7:0] port_a_in; // PORT A Data In -reg [7:0] port_b_in; // PORT B Data In -reg [7:0] port_c_in; // PORT C Data In -reg [7:0] port_d_in; // PORT D Data In - -wire [7:0] port_a_out; // PORT A Data Out -wire [7:0] port_b_out; // PORT B Data Out -wire [7:0] port_c_out; // PORT C Data Out -wire [7:0] port_d_out; // PORT D Data Out -wire [31:0] pad_gpio_in; // GPIO data input from PAD -wire [31:0] pad_gpio_out; // GPIO Data out towards PAD -wire [31:0] gpio_int_event; // GPIO Interrupt indication -reg [1:0] ext_intr_in; // External PAD level interrupt - -// GPIO to PORT Mapping -assign pad_gpio_in[7:0] = port_a_in; -assign pad_gpio_in[15:8] = port_b_in; -assign pad_gpio_in[23:16] = port_c_in; -assign pad_gpio_in[31:24] = port_d_in; - -assign port_a_out = pad_gpio_out[7:0]; -assign port_b_out = pad_gpio_out[15:8]; -assign port_c_out = pad_gpio_out[23:16]; -assign port_d_out = pad_gpio_out[31:24]; - -assign pinmux_debug = '0; // Todo: Need to fix - -// SSRAM I/F - Temp masked -//input logic ssram_sck, -//input logic ssram_ss, -//input logic [3:0] ssram_oen, -//input logic [3:0] ssram_do, -//output logic [3:0] ssram_di, - -// pinmux clock skew control -clk_skew_adjust u_skew_pinmux - ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - .clk_in (wbd_clk_int ), - .sel (cfg_cska_pinmux ), - .clk_out (wbd_clk_pinmux ) - ); - -reset_sync u_rst_sync ( - .scan_mode (1'b0 ), - .dclk (mclk ), // Destination clock domain - .arst_n (h_reset_n ), // active low async reset - .srst_n (sreset_n ) - ); - -gpio_intr_gen u_gpio_intr ( - // System Signals - // Inputs - .mclk (mclk ), - .h_reset_n (sreset_n ), - - // GPIO cfg input pins - .gpio_prev_indata (gpio_prev_indata ), - .cfg_gpio_data_in (cfg_gpio_data_in ), - .cfg_gpio_dir_sel (cfg_gpio_dir_sel ), - .cfg_gpio_out_data (cfg_gpio_out_data ), - .cfg_gpio_posedge_int_sel(cfg_gpio_posedge_int_sel), - .cfg_gpio_negedge_int_sel(cfg_gpio_negedge_int_sel), - - - // GPIO output pins - .pad_gpio_out (pad_gpio_out ), - .gpio_int_event (gpio_int_event ) - ); - - -// 1us pulse -pulse_gen_type2 #(.WD(10)) u_pulse_1us ( - - .clk_pulse_o (pulse_1us ), - .clk (mclk ), - .reset_n (sreset_n ), - .cfg_max_cnt (cfg_pulse_1us ) - - ); - -// 1millisecond pulse -pulse_gen_type1 u_pulse_1ms ( - - .clk_pulse_o (pulse_1ms ), - .clk (mclk ), - .reset_n (sreset_n ), - .trigger (pulse_1us ) - - ); - -// 1 second pulse -pulse_gen_type1 u_pulse_1s ( - - .clk_pulse_o (pulse_1s ), - .clk (mclk ), - .reset_n (sreset_n ), - .trigger (pulse_1ms ) - - ); - - -// Timer - -wire cfg_timer0_enb = cfg_timer0[16]; -wire [1:0] cfg_timer0_clksel = cfg_timer0[18:17]; -wire [15:0] cfg_timer0_compare = cfg_timer0[15:0]; - -timer u_timer_0 - ( - .reset_n (sreset_n ),// system syn reset - .mclk (mclk ),// master clock - .pulse_1us (pulse_1us ), - .pulse_1ms (pulse_1ms ), - .pulse_1s (pulse_1s ), - - .cfg_timer_update (cfg_timer_update[0] ), - .cfg_timer_enb (cfg_timer0_enb ), - .cfg_timer_compare (cfg_timer0_compare ), - .cfg_timer_clksel (cfg_timer0_clksel ),// to select the timer 1us/1ms reference clock - - .timer_intr (timer_intr[0] ) - ); - -// Timer -wire cfg_timer1_enb = cfg_timer1[16]; -wire [1:0] cfg_timer1_clksel = cfg_timer1[18:17]; -wire [15:0] cfg_timer1_compare = cfg_timer1[15:0]; -timer u_timer_1 - ( - .reset_n (sreset_n ),// system syn reset - .mclk (mclk ),// master clock - .pulse_1us (pulse_1us ), - .pulse_1ms (pulse_1ms ), - .pulse_1s (pulse_1s ), - - .cfg_timer_update (cfg_timer_update[1] ), - .cfg_timer_enb (cfg_timer1_enb ), - .cfg_timer_compare (cfg_timer1_compare ), - .cfg_timer_clksel (cfg_timer1_clksel ),// to select the timer 1us/1ms reference clock - - .timer_intr (timer_intr[1] ) - ); - -// Timer -wire cfg_timer2_enb = cfg_timer2[16]; -wire [1:0] cfg_timer2_clksel = cfg_timer2[18:17]; -wire [15:0] cfg_timer2_compare = cfg_timer2[15:0]; -timer u_timer_2 - ( - .reset_n (sreset_n ),// system syn reset - .mclk (mclk ),// master clock - .pulse_1us (pulse_1us ), - .pulse_1ms (pulse_1ms ), - .pulse_1s (pulse_1s ), - - .cfg_timer_update (cfg_timer_update[2] ), - .cfg_timer_enb (cfg_timer2_enb ), - .cfg_timer_compare (cfg_timer2_compare ), - .cfg_timer_clksel (cfg_timer2_clksel ),// to select the timer 1us/1ms reference clock - - .timer_intr (timer_intr[2] ) - ); - - -pinmux_reg u_pinmux_reg( - // System Signals - // Inputs - .mclk (mclk ), - .h_reset_n (sreset_n ), - - .cpu_core_rst_n (cpu_core_rst_n ), - .cpu_intf_rst_n (cpu_intf_rst_n ), - .qspim_rst_n (qspim_rst_n ), - .sspim_rst_n (sspim_rst_n ), - .uart_rst_n (uart_rst_n ), - .i2cm_rst_n (i2cm_rst_n ), - .usb_rst_n (usb_rst_n ), - - .cfg_riscv_ctrl (cfg_riscv_ctrl ), - - - // Reg read/write Interface Inputs - .reg_cs (reg_cs ), - .reg_wr (reg_wr ), - .reg_addr (reg_addr ), - .reg_wdata (reg_wdata ), - .reg_be (reg_be ), - - .reg_rdata (reg_rdata ), - .reg_ack (reg_ack ), - - .ext_intr_in (ext_intr_in ), - - .irq_lines (irq_lines ), - .soft_irq (soft_irq ), - .user_irq (user_irq ), - .usb_intr (usb_intr ), - .i2cm_intr (i2cm_intr ), - - .cfg_pulse_1us (cfg_pulse_1us ), - - - .cfg_pwm0_high (cfg_pwm0_high ), - .cfg_pwm0_low (cfg_pwm0_low ), - .cfg_pwm1_high (cfg_pwm1_high ), - .cfg_pwm1_low (cfg_pwm1_low ), - .cfg_pwm2_high (cfg_pwm2_high ), - .cfg_pwm2_low (cfg_pwm2_low ), - .cfg_pwm3_high (cfg_pwm3_high ), - .cfg_pwm3_low (cfg_pwm3_low ), - .cfg_pwm4_high (cfg_pwm4_high ), - .cfg_pwm4_low (cfg_pwm4_low ), - .cfg_pwm5_high (cfg_pwm5_high ), - .cfg_pwm5_low (cfg_pwm5_low ), - - // GPIO input pins - .gpio_in_data (pad_gpio_in ), - .gpio_int_event (gpio_int_event ), - - // GPIO config pins - .cfg_gpio_out_data (cfg_gpio_out_data ), - .cfg_gpio_dir_sel (cfg_gpio_dir_sel ), - .cfg_gpio_out_type (cfg_gpio_out_type ), - .cfg_gpio_posedge_int_sel (cfg_gpio_posedge_int_sel), - .cfg_gpio_negedge_int_sel (cfg_gpio_negedge_int_sel), - .cfg_multi_func_sel (cfg_multi_func_sel ), - .cfg_gpio_data_in (cfg_gpio_data_in ), - - - // Outputs - .gpio_prev_indata (gpio_prev_indata ) , - - - .timer_intr (timer_intr ), - .cfg_timer_update (cfg_timer_update ), - .cfg_timer0 (cfg_timer0 ), - .cfg_timer1 (cfg_timer1 ), - .cfg_timer2 (cfg_timer2 ) - - - ); - - -// 6 PWM Waveform Generator -pwm u_pwm_0 ( - .waveform (pwm_wfm[0] ), - .h_reset_n (sreset_n ), - .mclk (mclk ), - .pulse1m_mclk (pulse_1ms ), - .cfg_pwm_enb (cfg_pwm_enb[0] ), - .cfg_pwm_high (cfg_pwm0_high ), - .cfg_pwm_low (cfg_pwm0_low ) - ); - -pwm u_pwm_1 ( - .waveform (pwm_wfm[1] ), - .h_reset_n (sreset_n ), - .mclk (mclk ), - .pulse1m_mclk (pulse_1ms ), - .cfg_pwm_enb (cfg_pwm_enb[1] ), - .cfg_pwm_high (cfg_pwm1_high ), - .cfg_pwm_low (cfg_pwm1_low ) - ); - -pwm u_pwm_2 ( - .waveform (pwm_wfm[2] ), - .h_reset_n (sreset_n ), - .mclk (mclk ), - .pulse1m_mclk (pulse_1ms ), - .cfg_pwm_enb (cfg_pwm_enb[2] ), - .cfg_pwm_high (cfg_pwm2_high ), - .cfg_pwm_low (cfg_pwm2_low ) - ); - -pwm u_pwm_3 ( - .waveform (pwm_wfm[3] ), - .h_reset_n (sreset_n ), - .mclk (mclk ), - .pulse1m_mclk (pulse_1ms ), - .cfg_pwm_enb (cfg_pwm_enb[3] ), - .cfg_pwm_high (cfg_pwm3_high ), - .cfg_pwm_low (cfg_pwm3_low ) - ); -pwm u_pwm_4 ( - .waveform (pwm_wfm[4] ), - .h_reset_n (sreset_n ), - .mclk (mclk ), - .pulse1m_mclk (pulse_1ms ), - .cfg_pwm_enb (cfg_pwm_enb[4] ), - .cfg_pwm_high (cfg_pwm4_high ), - .cfg_pwm_low (cfg_pwm4_low ) - ); -pwm u_pwm_5 ( - .waveform (pwm_wfm[5] ), - .h_reset_n (sreset_n ), - .mclk (mclk ), - .pulse1m_mclk (pulse_1ms ), - .cfg_pwm_enb (cfg_pwm_enb[5] ), - .cfg_pwm_high (cfg_pwm5_high ), - .cfg_pwm_low (cfg_pwm5_low ) - ); - /************************************************ * Pin Mapping ATMGE CONFIG * ATMEGA328 caravel Pin Mapping @@ -559,6 +86,99 @@ * Pin-1 RESET is not supported as there is no suppport for fuse config **************/ +module pinmux ( + // Digital IO + output logic [37:0] digital_io_out , + output logic [37:0] digital_io_oen , + input logic [37:0] digital_io_in , + + // Config + input logic [31:0] cfg_gpio_dir_sel , + input logic [31:0] cfg_multi_func_sel , + + output logic[5:0] cfg_pwm_enb , + input logic [5:0] pwm_wfm , + output logic [1:0] ext_intr_in , // External PAD level interrupt + output logic [31:0] pad_gpio_in , // GPIO data input from PAD + input logic [31:0] pad_gpio_out , // GPIO Data out towards PAD + + // SFLASH I/F + input logic sflash_sck , + input logic [3:0] sflash_ss , + input logic [3:0] sflash_oen , + input logic [3:0] sflash_do , + output logic [3:0] sflash_di , + + // SSRAM I/F - Temp Masked + //input logic ssram_sck, + //input logic ssram_ss, + //input logic [3:0] ssram_oen, + //input logic [3:0] ssram_do, + //output logic [3:0] ssram_di, + + // USB I/F + input logic usb_dp_o, + input logic usb_dn_o, + input logic usb_oen, + output logic usb_dp_i, + output logic usb_dn_i, + + // UART I/F + input logic [1:0] uart_txd, + output logic [1:0] uart_rxd, + + // I2CM I/F + input logic i2cm_clk_o, + output logic i2cm_clk_i, + input logic i2cm_clk_oen, + input logic i2cm_data_oen, + input logic i2cm_data_o, + output logic i2cm_data_i, + + // SPI MASTER + input logic spim_sck, + input logic [3:0] spim_ssn, + input logic spim_miso, + output logic spim_mosi, + + // SPI SLAVE + output logic spis_sck, + output logic spis_ssn, + input logic spis_miso, + output logic spis_mosi, + + // UART MASTER I/F + output logic uartm_rxd , + input logic uartm_txd , + + input logic dbg_clk_mon + + ); + + + +reg [7:0] port_a_in; // PORT A Data In +reg [7:0] port_b_in; // PORT B Data In +reg [7:0] port_c_in; // PORT C Data In +reg [7:0] port_d_in; // PORT D Data In + +wire [7:0] port_a_out; // PORT A Data Out +wire [7:0] port_b_out; // PORT B Data Out +wire [7:0] port_c_out; // PORT C Data Out +wire [7:0] port_d_out; // PORT D Data Out + +// GPIO to PORT Mapping +assign pad_gpio_in[7:0] = port_a_in; +assign pad_gpio_in[15:8] = port_b_in; +assign pad_gpio_in[23:16] = port_c_in; +assign pad_gpio_in[31:24] = port_d_in; + +assign port_a_out = pad_gpio_out[7:0]; +assign port_b_out = pad_gpio_out[15:8]; +assign port_c_out = pad_gpio_out[23:16]; +assign port_d_out = pad_gpio_out[31:24]; + + assign cfg_pwm_enb = cfg_multi_func_sel[5:0]; wire [1:0] cfg_int_enb = cfg_multi_func_sel[7:6]; wire [1:0] cfg_uart_enb = cfg_multi_func_sel[9:8];
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv deleted file mode 100644 index 6c88ca7..0000000 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ /dev/null
@@ -1,902 +0,0 @@ -////////////////////////////////////////////////////////////////////////////// -// SPDX-FileCopyrightText: 2021 , Dinesh Annayya -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// SPDX-License-Identifier: Apache-2.0 -// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> -// -////////////////////////////////////////////////////////////////////// -//// //// -//// Pinmux Register //// -//// //// -//// This file is part of the riscduino cores project //// -//// https://github.com/dineshannayya/riscduino.git //// -//// //// -//// Description //// -//// Hold all the Global and PinMux Register //// -//// //// -//// To Do: //// -//// nothing //// -//// //// -//// Author(s): //// -//// - Dinesh Annayya, dinesha@opencores.org //// -//// //// -//// Revision : //// -//// 0.1 - 16th Feb 2021, Dinesh A //// -//// initial version //// -////////////////////////////////////////////////////////////////////// -// -module pinmux_reg ( - // System Signals - // Inputs - input logic mclk, - input logic h_reset_n, - - // Global Reset control - output logic [1:0] cpu_core_rst_n , - output logic cpu_intf_rst_n , - output logic qspim_rst_n , - output logic sspim_rst_n , - output logic [1:0] uart_rst_n , - output logic i2cm_rst_n , - output logic usb_rst_n , - - // Reg Bus Interface Signal - input logic reg_cs, - input logic reg_wr, - input logic [7:0] reg_addr, - input logic [31:0] reg_wdata, - input logic [3:0] reg_be, - - // Outputs - output logic [31:0] reg_rdata, - output logic reg_ack, - - input logic [1:0] ext_intr_in, - - // Risc configuration - output logic [15:0] irq_lines, - output logic soft_irq, - output logic [2:0] user_irq, - input logic usb_intr, - input logic i2cm_intr, - - output logic [9:0] cfg_pulse_1us, - output logic [15:0] cfg_riscv_ctrl, - - //--------------------------------------------------- - // 6 PWM Configuration - //--------------------------------------------------- - - output logic [15:0] cfg_pwm0_high , - output logic [15:0] cfg_pwm0_low , - output logic [15:0] cfg_pwm1_high , - output logic [15:0] cfg_pwm1_low , - output logic [15:0] cfg_pwm2_high , - output logic [15:0] cfg_pwm2_low , - output logic [15:0] cfg_pwm3_high , - output logic [15:0] cfg_pwm3_low , - output logic [15:0] cfg_pwm4_high , - output logic [15:0] cfg_pwm4_low , - output logic [15:0] cfg_pwm5_high , - output logic [15:0] cfg_pwm5_low , - - // GPIO input pins - input logic [31:0] gpio_in_data ,// GPIO I/P pins - input logic [31:0] gpio_int_event ,// from gpio control blk - - - - // GPIO config pins - output logic [31:0] cfg_gpio_out_data ,// to the GPIO control block - output logic [31:0] cfg_gpio_data_in ,// GPIO I/P pins data captured into this - output logic [31:0] cfg_gpio_dir_sel ,// decides on GPIO pin is I/P or O/P at pad level - output logic [31:0] cfg_gpio_out_type ,// O/P is static , '1' : waveform - output logic [31:0] cfg_gpio_posedge_int_sel ,// select posedge interrupt - output logic [31:0] cfg_gpio_negedge_int_sel ,// select negedge interrupt - output logic [31:0] cfg_multi_func_sel ,// multifunction pins - - // Outputs - output logic [31:0] gpio_prev_indata ,// prv data from GPIO I/P pins - - input logic [2:0] timer_intr , - output logic [2:0] cfg_timer_update , - output logic [31:0] cfg_timer0 , - output logic [31:0] cfg_timer1 , - output logic [31:0] cfg_timer2 - ); - - - -//----------------------------------------------------------------------- -// Internal Wire Declarations -//----------------------------------------------------------------------- - -logic sw_rd_en ; -logic sw_wr_en; -logic [4:0] sw_addr; // addressing 16 registers -logic [31:0] sw_reg_wdata; -logic [3:0] wr_be ; - -logic [31:0] reg_out; -logic [31:0] reg_0; // Chip ID -logic [31:0] reg_1; // Risc Fuse Id -logic [31:0] reg_2; // Global config-1 -logic [31:0] reg_3; // Global config-2 -logic [31:0] reg_4; // GPIO Read Data -logic [31:0] reg_5; // GPIO Output Data -logic [31:0] reg_6; // GPIO Dir Sel -logic [31:0] reg_7; // GPIO Type -logic [31:0] reg_8; // Interrupt -logic [31:0] reg_9; // GPIO Interrupt Status -logic [31:0] reg_10; // GPIO Interrupt Status -logic [31:0] reg_11; // GPIO Interrupt Mask -logic [31:0] reg_12; // GPIO Posedge Interrupt Select -logic [31:0] reg_13; // GPIO Negedge Interrupt Select -logic [31:0] reg_14; // Software-Reg_14 -logic [31:0] reg_15; // Software-Reg_15 -logic [31:0] reg_16; // PWN-0 Config -logic [31:0] reg_17; // PWN-1 Config -logic [31:0] reg_18; // PWN-2 Config -logic [31:0] reg_19; // PWN-3 Config -logic [31:0] reg_20; // PWN-4 Config -logic [31:0] reg_21; // PWN-5 Config -logic [31:0] reg_22; // Software-Reg1 -logic [31:0] reg_23; // Software-Reg2 -logic [31:0] reg_24; // Software-Reg3 -logic [31:0] reg_25; // Software-Reg4 -logic [31:0] reg_26; // Software-Reg5 -logic [31:0] reg_27; // Software-Reg6 -logic [31:0] reg_28; // Software-Reg6 -logic [31:0] reg_29; // Software-Reg6 -logic [31:0] reg_30; // Software-Reg6 - - -logic cs_int; -logic gpio_intr; - - -assign sw_addr = reg_addr [6:2]; -assign sw_rd_en = reg_cs & !reg_wr; -assign sw_wr_en = reg_cs & reg_wr; -assign wr_be = reg_be; -assign sw_reg_wdata = reg_wdata; - - -//----------------------------------- -// Edge detection for Logic Bist -// ---------------------------------- - -logic wb_req; -logic wb_req_d; -logic wb_req_pedge; - -always_ff @(negedge h_reset_n or posedge mclk) begin - if ( h_reset_n == 1'b0 ) begin - wb_req <= '0; - wb_req_d <= '0; - end else begin - wb_req <= reg_cs && (reg_ack == 0) ; - wb_req_d <= wb_req; - end -end - -// Detect pos edge of request -assign wb_req_pedge = (wb_req_d ==0) && (wb_req==1'b1); - - -always @ (posedge mclk or negedge h_reset_n) -begin : preg_out_Seq - if (h_reset_n == 1'b0) begin - reg_rdata <= 'h0; - reg_ack <= 1'b0; - end else if (reg_cs && !reg_ack) begin - reg_rdata <= reg_out ; - reg_ack <= 1'b1; - end else begin - reg_ack <= 1'b0; - end -end - - - -//----------------------------------------------------------------------- -// register read enable and write enable decoding logic -//----------------------------------------------------------------------- -wire sw_wr_en_0 = sw_wr_en & (sw_addr == 5'h0); -wire sw_wr_en_1 = sw_wr_en & (sw_addr == 5'h1); -wire sw_wr_en_2 = sw_wr_en & (sw_addr == 5'h2); -wire sw_wr_en_3 = sw_wr_en & (sw_addr == 5'h3); -wire sw_wr_en_4 = sw_wr_en & (sw_addr == 5'h4); -wire sw_wr_en_5 = sw_wr_en & (sw_addr == 5'h5); -wire sw_wr_en_6 = sw_wr_en & (sw_addr == 5'h6); -wire sw_wr_en_7 = sw_wr_en & (sw_addr == 5'h7); -wire sw_wr_en_8 = sw_wr_en & (sw_addr == 5'h8); -wire sw_wr_en_9 = sw_wr_en & (sw_addr == 5'h9); -wire sw_wr_en_10 = sw_wr_en & (sw_addr == 5'hA); -wire sw_wr_en_11 = sw_wr_en & (sw_addr == 5'hB); -wire sw_wr_en_12 = sw_wr_en & (sw_addr == 5'hC); -wire sw_wr_en_13 = sw_wr_en & (sw_addr == 5'hD); -wire sw_wr_en_14 = sw_wr_en & (sw_addr == 5'hE); -wire sw_wr_en_15 = sw_wr_en & (sw_addr == 5'hF); -wire sw_wr_en_16 = sw_wr_en & (sw_addr == 5'h10); -wire sw_wr_en_17 = sw_wr_en & (sw_addr == 5'h11); -wire sw_wr_en_18 = sw_wr_en & (sw_addr == 5'h12); -wire sw_wr_en_19 = sw_wr_en & (sw_addr == 5'h13); -wire sw_wr_en_20 = sw_wr_en & (sw_addr == 5'h14); -wire sw_wr_en_21 = sw_wr_en & (sw_addr == 5'h15); - -wire sw_wr_en_22 = sw_wr_en & (sw_addr == 5'h16); -wire sw_wr_en_23 = sw_wr_en & (sw_addr == 5'h17); -wire sw_wr_en_24 = sw_wr_en & (sw_addr == 5'h18); -wire sw_wr_en_25 = sw_wr_en & (sw_addr == 5'h19); -wire sw_wr_en_26 = sw_wr_en & (sw_addr == 5'h1A); -wire sw_wr_en_27 = sw_wr_en & (sw_addr == 5'h1B); -wire sw_wr_en_28 = sw_wr_en & (sw_addr == 5'h1C); -wire sw_wr_en_29 = sw_wr_en & (sw_addr == 5'h1D); -wire sw_wr_en_30 = sw_wr_en & (sw_addr == 5'h1E); -wire sw_wr_en_31 = sw_wr_en & (sw_addr == 5'h1F); - -wire sw_rd_en_28 = sw_rd_en & (sw_addr == 5'h1C); -wire sw_rd_en_29 = sw_rd_en & (sw_addr == 5'h1D); -wire sw_rd_en_30 = sw_rd_en & (sw_addr == 5'h1E); -wire sw_rd_en_31 = sw_rd_en & (sw_addr == 5'h1F); - - -//----------------------------------------------------------------------- -// Individual register assignments -//----------------------------------------------------------------------- - - -// Chip ID -// chip-id[3:0] mapping -// 0 - YIFIVE (MPW-2) -// 1 - Riscdunio (MPW-3) -// 2 - Riscdunio (MPW-4) -// 3 - Riscdunio (MPW-5) - -wire [15:0] manu_id = 16'h8268; // Asci value of RD -wire [3:0] total_core = 4'h1; -wire [3:0] chip_id = 4'h3; -wire [7:0] chip_rev = 8'h01; - -assign reg_0 = {manu_id,total_core,chip_id,chip_rev}; - - -//------------------------------------------ -// reg-2: GLBL_CFG_0 -//------------------------------------------ -wire [31:0] cfg_glb_ctrl = reg_1; - -ctech_buf u_buf_cpu_intf_rst (.A(cfg_glb_ctrl[0]),.X(cpu_intf_rst_n)); -ctech_buf u_buf_qspim_rst (.A(cfg_glb_ctrl[1]),.X(qspim_rst_n)); -ctech_buf u_buf_sspim_rst (.A(cfg_glb_ctrl[2]),.X(sspim_rst_n)); -ctech_buf u_buf_uart0_rst (.A(cfg_glb_ctrl[3]),.X(uart_rst_n[0])); -ctech_buf u_buf_i2cm_rst (.A(cfg_glb_ctrl[4]),.X(i2cm_rst_n)); -ctech_buf u_buf_usb_rst (.A(cfg_glb_ctrl[5]),.X(usb_rst_n)); -ctech_buf u_buf_uart1_rst (.A(cfg_glb_ctrl[6]),.X(uart_rst_n[1])); - -ctech_buf u_buf_cpu0_rst (.A(cfg_glb_ctrl[8]),.X(cpu_core_rst_n[0])); -ctech_buf u_buf_cpu1_rst (.A(cfg_glb_ctrl[9]),.X(cpu_core_rst_n[1])); - -gen_32b_reg #(32'h0) u_reg_1 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_1 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_1 ) - ); - -//---------------------------------------------- -// reg-2: GLBL_CFG_1 -//------------------------------------------ - -gen_32b_reg #(32'h0) u_reg_2 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_2 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_2 ) - ); - -assign cfg_pulse_1us = reg_2[9:0]; -assign cfg_riscv_ctrl = reg_2[31:16]; - -//----------------------------------------------------------------------- -// reg-3 : Global Interrupt Mask -//----------------------------------------------------------------------- - -gen_32b_reg #(32'h0) u_reg_3 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_3 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_3 ) - ); - -//----------------------------------------------------------------------- -// reg-4 : Global Interrupt Status -//----------------------------------------------------------------- -assign irq_lines = reg_3[15:0] & reg_4[15:0]; -assign soft_irq = reg_3[16] & reg_4[16]; -assign user_irq = reg_3[19:17]& reg_4[19:17]; - - -generic_register #(8,0 ) u_reg4_be0 ( - .we ({8{sw_wr_en_4 & - wr_be[0] }} ), - .data_in (sw_reg_wdata[7:0] ), - .reset_n (h_reset_n ), - .clk (mclk ), - - //List of Outs - .data_out (reg_4[7:0] ) - ); - - -wire [7:0] hware_intr_req = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr,timer_intr[2:0]}; - -generic_intr_stat_reg #(.WD(8), - .RESET_DEFAULT(0)) u_reg4_be1 ( - //inputs - .clk (mclk ), - .reset_n (h_reset_n ), - .reg_we ({8{sw_wr_en_4 & reg_ack & - wr_be[1] }} ), - .reg_din (sw_reg_wdata[15:8] ), - .hware_req (hware_intr_req ), - - //outputs - .data_out (reg_4[15:8] ) - ); - - - -generic_register #(4,0 ) u_reg4_be2 ( - .we ({4{sw_wr_en_4 & - wr_be[2] }} ), - .data_in (sw_reg_wdata[19:16]), - .reset_n (h_reset_n ), - .clk (mclk ), - - //List of Outs - .data_out (reg_4[19:16] ) - ); - -assign reg_4[31:20] = '0; - - -//----------------------------------------------------------------------- -// Logic for gpio_data_in -//----------------------------------------------------------------------- -logic [31:0] gpio_in_data_s; -logic [31:0] gpio_in_data_ss; -// Double Sync the gpio pin data for edge detection -always @ (posedge mclk or negedge h_reset_n) -begin - if (h_reset_n == 1'b0) begin - reg_5 <= 'h0 ; - gpio_in_data_s <= 32'd0; - gpio_in_data_ss <= 32'd0; - end - else begin - gpio_in_data_s <= gpio_in_data; - gpio_in_data_ss <= gpio_in_data_s; - reg_5 <= gpio_in_data_ss; - end -end - - -assign cfg_gpio_data_in = reg_5[31:0]; // to be used for edge interrupt detect -assign gpio_prev_indata = gpio_in_data_ss; - -//----------------------------------------------------------------------- -// Logic for cfg_gpio_out_data -//----------------------------------------------------------------------- -assign cfg_gpio_out_data = reg_6[31:0]; // data to the GPIO control blk - -gen_32b_reg #(32'h0) u_reg_6 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_6 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_6 ) - ); -//----------------------------------------------------------------------- -// Logic for cfg_gpio_dir_sel -//----------------------------------------------------------------------- -assign cfg_gpio_dir_sel = reg_7[31:0]; // data to the GPIO O/P pins - -gen_32b_reg #(32'h0) u_reg_7 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_7 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_7 ) - ); -//----------------------------------------------------------------------- -// Logic for cfg_gpio_out_type -//----------------------------------------------------------------------- -assign cfg_gpio_out_type = reg_8[31:0]; // to be used for read - -gen_32b_reg #(32'h0) u_reg_8 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_8 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_8 ) - ); - - - -//----------------------------------------------------------------------- -// Logic for cfg_int_status -// Always update int_status, even if no register write is occuring. -// Interrupt posting is higher priority than int clear by host -//----------------------------------------------------------------------- -wire [31:0] cfg_gpio_int_status = reg_9[31:0]; // to be used for read - -//-------------------------------------------------------- -// Interrupt Status Generation -// Note: Reg_9 --> Interrupt Status Register, Writting '1' will clear the -// corresponding interrupt status bit. Writting '0' has no -// effect -// Reg_10 --> Writting one to this register will set the interrupt in -// interrupt status register (reg_9), Writting '0' does not has any -// effect. -/// Always update int_status, even if no register write is occuring. -// Interrupt posting is higher priority than int clear by host -//-------------------------------------------------------- -wire [31:0] gpio_int_status = reg_9; - -generic_intr_stat_reg #(.WD(32), - .RESET_DEFAULT(0)) u_reg_9 ( - //inputs - .clk (mclk ), - .reset_n (h_reset_n ), - .reg_we ({ - {8{sw_wr_en_9 & reg_ack & wr_be[2]}}, - {8{sw_wr_en_9 & reg_ack & wr_be[2]}}, - {8{sw_wr_en_9 & reg_ack & wr_be[1]}}, - {8{sw_wr_en_9 & reg_ack & wr_be[0]}} - } ), - .reg_din (sw_reg_wdata[31:0] ), - .hware_req (gpio_int_event | { - {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[31:24], - {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[23:16], - {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[15:8] , - {8{sw_wr_en_10 & reg_ack}} & sw_reg_wdata[7:0] - } ), - - //outputs - .data_out (reg_9[31:0] ) - ); -//------------------------------------------------- -// Returns same value as interrupt status register -//------------------------------------------------ - -assign reg_10 = reg_9; -//----------------------------------------------------------------------- -// Logic for cfg_gpio_int_mask : GPIO interrupt mask -//----------------------------------------------------------------------- -wire [31:0] cfg_gpio_int_mask = reg_11[31:0]; // to be used for read - -assign gpio_intr = ( | (reg_9 & reg_11) ); // interrupt pin to the RISC - - -// Register-11 -gen_32b_reg #(32'h0) u_reg_11 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_11 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_11 ) - ); -//----------------------------------------------------------------------- -// Logic for cfg_gpio_posedge_int_sel : Enable posedge GPIO interrupt -//----------------------------------------------------------------------- -assign cfg_gpio_posedge_int_sel = reg_12[31:0]; // to be used for read -gen_32b_reg #(32'h0) u_reg_12 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_12 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_12 ) - ); -//----------------------------------------------------------------------- -// Logic for cfg_gpio_negedge_int_sel : Enable negedge GPIO interrupt -//----------------------------------------------------------------------- -assign cfg_gpio_negedge_int_sel = reg_13[31:0]; // to be used for read -gen_32b_reg #(32'h0) u_reg_13 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_13 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_13 ) - ); - -//----------------------------------------------------------------------- -// Logic for cfg_multi_func_sel :Enable GPIO to act as multi function pins -//----------------------------------------------------------------------- -assign cfg_multi_func_sel = reg_14[31:0]; // to be used for read - - -gen_32b_reg #(32'h0) u_reg_14 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_14 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_14 ) - ); - -// Reg-15 -gen_32b_reg #(32'h0) u_reg_15 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_15 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_15 ) - ); -//----------------------------------------------------------------------- -// Logic for PWM-0 Config -//----------------------------------------------------------------------- -assign cfg_pwm0_low = reg_16[15:0]; // low period of w/f -assign cfg_pwm0_high = reg_16[31:16]; // high period of w/f - -gen_32b_reg #(32'h0) u_reg_16 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_16 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_16 ) - ); - - -//----------------------------------------------------------------------- -// Logic for PWM-1 Config -//----------------------------------------------------------------------- -assign cfg_pwm1_low = reg_17[15:0]; // low period of w/f -assign cfg_pwm1_high = reg_17[31:16]; // high period of w/f -gen_32b_reg #(32'h0) u_reg_17 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_17 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_17 ) - ); - -//----------------------------------------------------------------------- -// Logic for PWM-2 Config -//----------------------------------------------------------------------- -assign cfg_pwm2_low = reg_18[15:0]; // low period of w/f -assign cfg_pwm2_high = reg_18[31:16]; // high period of w/f -gen_32b_reg #(32'h0) u_reg_18 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_18 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_18 ) - ); - -//----------------------------------------------------------------------- -// Logic for PWM-3 Config -//----------------------------------------------------------------------- -assign cfg_pwm3_low = reg_19[15:0]; // low period of w/f -assign cfg_pwm3_high = reg_19[31:16]; // high period of w/f -gen_32b_reg #(32'h0) u_reg_19 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_19 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_19 ) - ); - -//----------------------------------------------------------------------- -// Logic for PWM-4 Config -//----------------------------------------------------------------------- -assign cfg_pwm4_low = reg_20[15:0]; // low period of w/f -assign cfg_pwm4_high = reg_20[31:16]; // high period of w/f - -gen_32b_reg #(32'h0) u_reg_20 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_20 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_20 ) - ); - -//----------------------------------------------------------------------- -// Logic for PWM-5 Config -//----------------------------------------------------------------------- -assign cfg_pwm5_low = reg_21[15:0]; // low period of w/f -assign cfg_pwm5_high = reg_21[31:16]; // high period of w/f - -gen_32b_reg #(32'h0) u_reg_21 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_21 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_21 ) - ); - - -//----------------------------------------- -// Software Reg-1 : ASCI Representation of RISC = 32'h8273_8343 -// ---------------------------------------- -gen_32b_reg #(32'h8273_8343) u_reg_22 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_22 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_22 ) - ); - -//----------------------------------------- -// Software Reg-2, Release date: <DAY><MONTH><YEAR> -// ---------------------------------------- -gen_32b_reg #(32'h0508_2022) u_reg_23 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_23 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_23 ) - ); - -//----------------------------------------- -// Software Reg-3: Poject Revison 4.9 = 0004900 -// ---------------------------------------- -gen_32b_reg #(32'h0004_9000) u_reg_24 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_24 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_24 ) - ); - -//----------------------------------------- -// Software Reg-4 -// ---------------------------------------- -gen_32b_reg #(32'h0) u_reg_25 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_25 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_25 ) - ); - -//----------------------------------------- -// Software Reg-5 -// ---------------------------------------- -gen_32b_reg #(32'h0) u_reg_26 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_26 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_26 ) - ); - -//----------------------------------------- -// Software Reg-6 -// ---------------------------------------- -gen_32b_reg #(32'h0) u_reg_27 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_27 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_27 ) - ); - - -//----------------------------------------------------------------------- -// reg-28 -// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle -// In first cycle, local register will be updated -// In second cycle, update indication sent to timer block -// ----------------------------------------------------------------- -assign cfg_timer0 = reg_28[18:0]; -assign cfg_timer_update[0] = sw_wr_en_28 & reg_ack; - -gen_32b_reg #(32'h0) u_reg_28 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_28 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_28[31:0] ) - ); - -//----------------------------------------------------------------------- -// reg-29 -// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle -// In first cycle, local register will be updated -// In second cycle, update indication sent to timer block -// ----------------------------------------------------------------- -assign cfg_timer1 = reg_29[18:0]; -assign cfg_timer_update[1] = sw_wr_en_29 & reg_ack; - -gen_32b_reg #(32'h0) u_reg_29 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_29 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_29[31:0] ) - ); - - -//----------------------------------------------------------------------- -// reg-30 -// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle -// In first cycle, local register will be updated -// In second cycle, update indication sent to timer block -// ----------------------------------------------------------------- -assign cfg_timer2 = reg_30[18:0]; -assign cfg_timer_update[2] = sw_wr_en_30 & reg_ack; - -gen_32b_reg #(32'h0) u_reg_30 ( - //List of Inputs - .reset_n (h_reset_n ), - .clk (mclk ), - .cs (sw_wr_en_30 ), - .we (wr_be ), - .data_in (sw_reg_wdata ), - - //List of Outs - .data_out (reg_30[31:0] ) - ); - -//----------------------------------------------------------------------- -// Register Read Path Multiplexer instantiation -//----------------------------------------------------------------------- - -always_comb -begin - reg_out [31:0] = 32'h0; - - case (sw_addr [4:0]) - 5'b00000 : reg_out [31:0] = reg_0 [31:0]; - 5'b00001 : reg_out [31:0] = reg_1 [31:0]; - 5'b00010 : reg_out [31:0] = reg_2 [31:0]; - 5'b00011 : reg_out [31:0] = reg_3 [31:0]; - 5'b00100 : reg_out [31:0] = reg_4 [31:0]; - 5'b00101 : reg_out [31:0] = reg_5 [31:0]; - 5'b00110 : reg_out [31:0] = reg_6 [31:0]; - 5'b00111 : reg_out [31:0] = reg_7 [31:0]; - 5'b01000 : reg_out [31:0] = reg_8 [31:0]; - 5'b01001 : reg_out [31:0] = reg_9 [31:0]; - 5'b01010 : reg_out [31:0] = reg_10 [31:0]; - 5'b01011 : reg_out [31:0] = reg_11 [31:0]; - 5'b01100 : reg_out [31:0] = reg_12 [31:0]; - 5'b01101 : reg_out [31:0] = reg_13 [31:0]; - 5'b01110 : reg_out [31:0] = reg_14 [31:0]; - 5'b01111 : reg_out [31:0] = reg_15 [31:0]; - 5'b10000 : reg_out [31:0] = reg_16 [31:0]; - 5'b10001 : reg_out [31:0] = reg_17 [31:0]; - 5'b10010 : reg_out [31:0] = reg_18 [31:0]; - 5'b10011 : reg_out [31:0] = reg_19 [31:0]; - 5'b10100 : reg_out [31:0] = reg_20 [31:0]; - 5'b10101 : reg_out [31:0] = reg_21 [31:0]; - 5'b10110 : reg_out [31:0] = reg_22 [31:0]; - 5'b10111 : reg_out [31:0] = reg_23 [31:0]; - 5'b11000 : reg_out [31:0] = reg_24 [31:0]; - 5'b11001 : reg_out [31:0] = reg_25 [31:0]; - 5'b11010 : reg_out [31:0] = reg_26 [31:0]; - 5'b11011 : reg_out [31:0] = reg_27 [31:0]; - 5'b11100 : reg_out [31:0] = reg_28 [31:0]; - 5'b11101 : reg_out [31:0] = reg_29 [31:0]; - 5'b11110 : reg_out [31:0] = reg_30 [31:0]; - 5'b11111 : reg_out [31:0] = 32'h0; - default : reg_out [31:0] = 32'h0; - endcase -end - - -endmodule
diff --git a/verilog/rtl/pinmux/src/pinmux_top.sv b/verilog/rtl/pinmux/src/pinmux_top.sv new file mode 100755 index 0000000..c84c1a7 --- /dev/null +++ b/verilog/rtl/pinmux/src/pinmux_top.sv
@@ -0,0 +1,485 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// Pinmux //// +//// //// +//// This file is part of the riscduino cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +//// PinMux Manages all the pin multiplexing //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 16th Feb 2021, Dinesh A //// +//// initial version //// +//// 0.2 - 6 April 2021, Dinesh A //// +//// 1. SSPI CS# increased from 1 to 4 //// +// 2. UART I/F increase from 1 to 2 //// +//// 0.3 - 8 July 2022, Dinesh A //// +//// In ardunio, SPI chip select are control through //// +//// GPIO, So we have moved the Auto generated SPI CS //// +//// different config bit. I2C config position moved from//// +//// bit[14] to bit [15] //// +//// 0.4 - 20 July 2022, Dinesh A //// +//// On Power On, If RESET* = 0, then system will enter //// +//// in to SPIS slave mode to support boot //// +////////////////////////////////////////////////////////////////////// + +module pinmux_top ( + `ifdef USE_POWER_PINS + input logic vccd1,// User area 1 1.8V supply + input logic vssd1,// User area 1 digital ground + `endif + // clock skew adjust + input logic [3:0] cfg_cska_pinmux, + input logic wbd_clk_int, + output logic wbd_clk_pinmux, + // System Signals + // Inputs + input logic mclk, + input logic h_reset_n, + + // Global Reset control + output logic [1:0] cpu_core_rst_n , + output logic cpu_intf_rst_n , + output logic qspim_rst_n , + output logic sspim_rst_n , + output logic [1:0] uart_rst_n , + output logic i2cm_rst_n , + output logic usb_rst_n , + + output logic [15:0] cfg_riscv_ctrl, + + // Reg Bus Interface Signal + input logic reg_cs, + input logic reg_wr, + input logic [8:0] reg_addr, + input logic [31:0] reg_wdata, + input logic [3:0] reg_be, + + // Outputs + output logic [31:0] reg_rdata, + output logic reg_ack, + + // Risc configuration + output logic [15:0] irq_lines, + output logic soft_irq, + output logic [2:0] user_irq, + input logic usb_intr, + input logic i2cm_intr, + + // Digital IO + output logic [37:0] digital_io_out, + output logic [37:0] digital_io_oen, + input logic [37:0] digital_io_in, + + // SFLASH I/F + input logic sflash_sck, + input logic [3:0] sflash_ss, + input logic [3:0] sflash_oen, + input logic [3:0] sflash_do, + output logic [3:0] sflash_di, + + // SSRAM I/F - Temp Masked + //input logic ssram_sck, + //input logic ssram_ss, + //input logic [3:0] ssram_oen, + //input logic [3:0] ssram_do, + //output logic [3:0] ssram_di, + + // USB I/F + input logic usb_dp_o, + input logic usb_dn_o, + input logic usb_oen, + output logic usb_dp_i, + output logic usb_dn_i, + + // UART I/F + input logic [1:0] uart_txd, + output logic [1:0] uart_rxd, + + // I2CM I/F + input logic i2cm_clk_o, + output logic i2cm_clk_i, + input logic i2cm_clk_oen, + input logic i2cm_data_oen, + input logic i2cm_data_o, + output logic i2cm_data_i, + + // SPI MASTER + input logic spim_sck, + input logic [3:0] spim_ssn, + input logic spim_miso, + output logic spim_mosi, + + // SPI SLAVE + output logic spis_sck, + output logic spis_ssn, + input logic spis_miso, + output logic spis_mosi, + + // UART MASTER I/F + output logic uartm_rxd , + input logic uartm_txd , + + output logic pulse1m_mclk, + output logic [31:0] pinmux_debug, + + input logic dbg_clk_mon + + ); + + + +logic sreset_n; // Sync Reset + +/* clock pulse */ +//******************************************************** +logic pulse_1ms ; // 1 Milli Second Pulse for waveform Generator +logic [5:0] cfg_pwm_enb ; + + +//--------------------------------------------------------- +// Timer Register +// ------------------------------------------------------- +logic [2:0] timer_intr ; + +//--------------------------------------------------- +// 6 PWM variabled +//--------------------------------------------------- + +logic [5:0] pwm_wfm ; + + +wire [31:0] cfg_gpio_dir_sel ;// decides on GPIO pin is I/P or O/P at pad level, 0 -> Input, 1 -> Output +wire [31:0] cfg_gpio_out_type ;// GPIO Type, Unused +wire [31:0] cfg_multi_func_sel ;// GPIO Multi function type + + +reg [7:0] port_a_in; // PORT A Data In +reg [7:0] port_b_in; // PORT B Data In +reg [7:0] port_c_in; // PORT C Data In +reg [7:0] port_d_in; // PORT D Data In + +wire [7:0] port_a_out; // PORT A Data Out +wire [7:0] port_b_out; // PORT B Data Out +wire [7:0] port_c_out; // PORT C Data Out +wire [7:0] port_d_out; // PORT D Data Out +wire [31:0] pad_gpio_in; // GPIO data input from PAD +wire [31:0] pad_gpio_out; // GPIO Data out towards PAD +wire [31:0] gpio_int_event; // GPIO Interrupt indication +reg [1:0] ext_intr_in; // External PAD level interrupt + + +assign pinmux_debug = '0; // Todo: Need to fix + +//------------------------------------------------------ +// Register Map Decoding + +`define SEL_GLBL 3'b000 // GLOBAL REGISTER +`define SEL_GPIO 3'b001 // GPIO REGISTER +`define SEL_PWM 3'b010 // PWM REGISTER +`define SEL_TIMER 3'b011 // TIMER REGISTER +`define SEL_SEMA 3'b100 // SEMAPHORE REGISTER + + +//---------------------------------------- +// Register Response Path Mux +// -------------------------------------- +logic [31:0] reg_glbl_rdata; +logic reg_glbl_ack; + +logic [31:0] reg_gpio_rdata; +logic reg_gpio_ack; + +logic [31:0] reg_pwm_rdata; +logic reg_pwm_ack; + +logic [31:0] reg_timer_rdata; +logic reg_timer_ack; + +logic [15:0] reg_sema_rdata; +logic reg_sema_ack; + + +assign reg_rdata = (reg_addr[8:6] == `SEL_GLBL) ? {reg_glbl_rdata} : + (reg_addr[8:6] == `SEL_GPIO) ? {reg_gpio_rdata} : + (reg_addr[8:6] == `SEL_PWM) ? {reg_pwm_rdata} : + (reg_addr[8:6] == `SEL_TIMER) ? reg_timer_rdata : + (reg_addr[8:6] == `SEL_SEMA) ? {16'h0,reg_sema_rdata} : 'h0; + +assign reg_ack = (reg_addr[8:6] == `SEL_GLBL) ? reg_glbl_ack : + (reg_addr[8:6] == `SEL_GPIO) ? reg_gpio_ack : + (reg_addr[8:6] == `SEL_PWM) ? reg_pwm_ack : + (reg_addr[8:6] == `SEL_TIMER) ? reg_timer_ack : + (reg_addr[8:6] == `SEL_SEMA) ? reg_sema_ack : 1'b0; + +wire reg_glbl_cs = (reg_addr[8:6] == `SEL_GLBL) ? reg_cs : 1'b0; +wire reg_gpio_cs = (reg_addr[8:6] == `SEL_GPIO) ? reg_cs : 1'b0; +wire reg_pwm_cs = (reg_addr[8:6] == `SEL_PWM) ? reg_cs : 1'b0; +wire reg_timer_cs = (reg_addr[8:6] == `SEL_TIMER)? reg_cs : 1'b0; +wire reg_sema_cs = (reg_addr[8:6] == `SEL_SEMA) ? reg_cs : 1'b0; + +//--------------------------------------------------------------------- + +// SSRAM I/F - Temp masked +//input logic ssram_sck, +//input logic ssram_ss, +//input logic [3:0] ssram_oen, +//input logic [3:0] ssram_do, +//output logic [3:0] ssram_di, + +// pinmux clock skew control +clk_skew_adjust u_skew_pinmux + ( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground +`endif + .clk_in (wbd_clk_int ), + .sel (cfg_cska_pinmux ), + .clk_out (wbd_clk_pinmux ) + ); + +reset_sync u_rst_sync ( + .scan_mode (1'b0 ), + .dclk (mclk ), // Destination clock domain + .arst_n (h_reset_n ), // active low async reset + .srst_n (sreset_n ) + ); + +//------------------------------------------------------------------ +// Global Register +//------------------------------------------------------------------ +glbl_reg u_glbl_reg( + // System Signals + // Inputs + .mclk (mclk ), + .h_reset_n (sreset_n ), + + .cpu_core_rst_n (cpu_core_rst_n ), + .cpu_intf_rst_n (cpu_intf_rst_n ), + .qspim_rst_n (qspim_rst_n ), + .sspim_rst_n (sspim_rst_n ), + .uart_rst_n (uart_rst_n ), + .i2cm_rst_n (i2cm_rst_n ), + .usb_rst_n (usb_rst_n ), + + .cfg_riscv_ctrl (cfg_riscv_ctrl ), + .cfg_multi_func_sel (cfg_multi_func_sel ), + + + // Reg read/write Interface Inputs + .reg_cs (reg_glbl_cs ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr[5:2] ), + .reg_wdata (reg_wdata ), + .reg_be (reg_be ), + + .reg_rdata (reg_glbl_rdata ), + .reg_ack (reg_glbl_ack ), + + .ext_intr_in (ext_intr_in ), + + .irq_lines (irq_lines ), + .soft_irq (soft_irq ), + .user_irq (user_irq ), + .usb_intr (usb_intr ), + .i2cm_intr (i2cm_intr ), + + + + .timer_intr (timer_intr ), + .gpio_intr (gpio_intr ) + + + ); + +//----------------------------------------------------------------------- +// GPIO Top +//----------------------------------------------------------------------- +gpio_top u_gpio( + // System Signals + // Inputs + .mclk ( mclk ), + .h_reset_n (h_reset_n ), + + // Reg Bus Interface Signal + .reg_cs (reg_gpio_cs ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr[5:2] ), + .reg_wdata (reg_wdata ), + .reg_be (reg_be ), + + // Outputs + .reg_rdata (reg_gpio_rdata ), + .reg_ack (reg_gpio_ack ), + + + .cfg_gpio_dir_sel (cfg_gpio_dir_sel ), + .pad_gpio_in (pad_gpio_in ), + .pad_gpio_out (pad_gpio_out ), + + .gpio_intr (gpio_intr ) + + + ); + +//----------------------------------------------------------------------- +// PWM Top +//----------------------------------------------------------------------- +pwm_top u_pwm( + // System Signals + // Inputs + .mclk ( mclk ), + .h_reset_n (h_reset_n ), + + // Reg Bus Interface Signal + .reg_cs (reg_pwm_cs ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr[4:2] ), + .reg_wdata (reg_wdata ), + .reg_be (reg_be ), + + // Outputs + .reg_rdata (reg_pwm_rdata ), + .reg_ack (reg_pwm_ack ), + + .pulse_1ms (pulse_1ms ), + .cfg_pwm_enb (cfg_pwm_enb ), + .pwm_wfm (pwm_wfm ) + ); + +//----------------------------------------------------------------------- +// Timer Top +//----------------------------------------------------------------------- +timer_top u_timer( + // System Signals + // Inputs + .mclk ( mclk ), + .h_reset_n (h_reset_n ), + + // Reg Bus Interface Signal + .reg_cs (reg_timer_cs ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr[3:2] ), + .reg_wdata (reg_wdata ), + .reg_be (reg_be ), + + // Outputs + .reg_rdata (reg_timer_rdata ), + .reg_ack (reg_timer_ack ), + + .pulse_1ms (pulse_1ms ), + .timer_intr (timer_intr ) + ); + +//----------------------------------------------------------------------- +// Semaphore Register +//----------------------------------------------------------------------- +semaphore_reg u_semaphore( + // System Signals + // Inputs + .mclk ( mclk ), + .h_reset_n (h_reset_n ), + + // Reg Bus Interface Signal + .reg_cs (reg_sema_cs ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr[5:2] ), + .reg_wdata (reg_wdata[15:0] ), + .reg_be (reg_be[1:0] ), + + // Outputs + .reg_rdata (reg_sema_rdata ), + .reg_ack (reg_sema_ack ) + ); + + +pinmux u_pinmux ( + // Digital IO + .digital_io_out (digital_io_out ), + .digital_io_oen (digital_io_oen ), + .digital_io_in (digital_io_in ), + + // Config + .cfg_gpio_dir_sel (cfg_gpio_dir_sel ), + .cfg_multi_func_sel (cfg_multi_func_sel ), + + .cfg_pwm_enb (cfg_pwm_enb ), + .pwm_wfm (pwm_wfm ), + .ext_intr_in (ext_intr_in ), // External PAD level interrupt + .pad_gpio_in (pad_gpio_in ), // GPIO data input from PAD + .pad_gpio_out (pad_gpio_out ), // GPIO Data out towards PAD + + // SFLASH I/F + .sflash_sck (sflash_sck ), + .sflash_ss (sflash_ss ), + .sflash_oen (sflash_oen ), + .sflash_do (sflash_do ), + .sflash_di (sflash_di ), + + // USB I/F + .usb_dp_o (usb_dp_o ), + .usb_dn_o (usb_dn_o ), + .usb_oen (usb_oen ), + .usb_dp_i (usb_dp_i ), + .usb_dn_i (usb_dn_i ), + + // UART I/F + .uart_txd (uart_txd ), + .uart_rxd (uart_rxd ), + + // I2CM I/F + .i2cm_clk_o (i2cm_clk_o ), + .i2cm_clk_i (i2cm_clk_i ), + .i2cm_clk_oen (i2cm_clk_oen ), + .i2cm_data_oen (i2cm_data_oen ), + .i2cm_data_o (i2cm_data_o ), + .i2cm_data_i (i2cm_data_i ), + + // SPI MASTER + .spim_sck (spim_sck ), + .spim_ssn (spim_ssn ), + .spim_miso (spim_miso ), + .spim_mosi (spim_mosi ), + + // SPI SLAVE + .spis_sck (spis_sck ), + .spis_ssn (spis_ssn ), + .spis_miso (spis_miso ), + .spis_mosi (spis_mosi ), + + // UART MASTER I/F + .uartm_rxd (uartm_rxd ), + .uartm_txd (uartm_txd ), + + .dbg_clk_mon (dbg_clk_mon ) + + ); + +endmodule + +
diff --git a/verilog/rtl/pinmux/src/pwm_reg.sv b/verilog/rtl/pinmux/src/pwm_reg.sv new file mode 100644 index 0000000..702c138 --- /dev/null +++ b/verilog/rtl/pinmux/src/pwm_reg.sv
@@ -0,0 +1,255 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// PWM Register //// +//// //// +//// This file is part of the riscduino cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 15th Aug 2022, Dinesh A //// +//// initial version //// +////////////////////////////////////////////////////////////////////// +// +module pwm_reg ( + // System Signals + // Inputs + input logic mclk , + input logic h_reset_n , + + // Reg Bus Interface Signal + input logic reg_cs , + input logic reg_wr , + input logic [2:0] reg_addr , + input logic [31:0] reg_wdata , + input logic [3:0] reg_be , + + // Outputs + output logic [31:0] reg_rdata , + output logic reg_ack , + + output logic [15:0] cfg_pwm0_high , + output logic [15:0] cfg_pwm0_low , + output logic [15:0] cfg_pwm1_high , + output logic [15:0] cfg_pwm1_low , + output logic [15:0] cfg_pwm2_high , + output logic [15:0] cfg_pwm2_low , + output logic [15:0] cfg_pwm3_high , + output logic [15:0] cfg_pwm3_low , + output logic [15:0] cfg_pwm4_high , + output logic [15:0] cfg_pwm4_low , + output logic [15:0] cfg_pwm5_high , + output logic [15:0] cfg_pwm5_low + + ); + +//----------------------------------------------------------------------- +// Internal Wire Declarations +//----------------------------------------------------------------------- + +logic sw_rd_en ; +logic sw_wr_en ; +logic [2:0] sw_addr ; // addressing 16 registers +logic [31:0] sw_reg_wdata ; +logic [3:0] sw_be ; + +logic [31:0] reg_out ; +logic [31:0] reg_0 ; // CONFIG - Unused +logic [31:0] reg_1 ; // PWM-REG-0 +logic [31:0] reg_2 ; // PWM-REG-1 +logic [31:0] reg_3 ; // PWM-REG-2 +logic [31:0] reg_4 ; // PWM-REG-3 +logic [31:0] reg_5 ; // PWM-REG-4 +logic [31:0] reg_6 ; // PWM-REG-5 + +assign sw_addr = reg_addr; +assign sw_rd_en = reg_cs & !reg_wr; +assign sw_wr_en = reg_cs & reg_wr; +assign sw_be = reg_be; +assign sw_reg_wdata = reg_wdata; + +//----------------------------------------------------------------------- +// register read enable and write enable decoding logic +//----------------------------------------------------------------------- +wire sw_wr_en_0 = sw_wr_en & (sw_addr == 3'h0); +wire sw_wr_en_1 = sw_wr_en & (sw_addr == 3'h1); +wire sw_wr_en_2 = sw_wr_en & (sw_addr == 3'h2); +wire sw_wr_en_3 = sw_wr_en & (sw_addr == 3'h3); +wire sw_wr_en_4 = sw_wr_en & (sw_addr == 3'h4); +wire sw_wr_en_5 = sw_wr_en & (sw_addr == 3'h5); +wire sw_wr_en_6 = sw_wr_en & (sw_addr == 3'h6); + +wire sw_rd_en_0 = sw_rd_en & (sw_addr == 3'h0); +wire sw_rd_en_1 = sw_rd_en & (sw_addr == 3'h1); +wire sw_rd_en_2 = sw_rd_en & (sw_addr == 3'h2); +wire sw_rd_en_3 = sw_rd_en & (sw_addr == 3'h3); +wire sw_rd_en_4 = sw_rd_en & (sw_addr == 3'h4); +wire sw_rd_en_5 = sw_rd_en & (sw_addr == 3'h5); +wire sw_rd_en_6 = sw_rd_en & (sw_addr == 3'h6); + + +always @ (posedge mclk or negedge h_reset_n) +begin : preg_out_Seq + if (h_reset_n == 1'b0) begin + reg_rdata <= 'h0; + reg_ack <= 1'b0; + end else if (reg_cs && !reg_ack) begin + reg_rdata <= reg_out; + reg_ack <= 1'b1; + end else begin + reg_ack <= 1'b0; + end +end + +//-------------------------------------------- +// reg-0: Reserve for pwm global config +//--------------------------------------------- +assign reg_0 = 'h0; +//----------------------------------------------------------------------- +// Logic for PWM-0 Config +//----------------------------------------------------------------------- +assign cfg_pwm0_low = reg_1[15:0]; // low period of w/f +assign cfg_pwm0_high = reg_1[31:16]; // high period of w/f + +gen_32b_reg #(32'h0) u_reg_1 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_1 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_1 ) + ); + + +//----------------------------------------------------------------------- +// Logic for PWM-1 Config +//----------------------------------------------------------------------- +assign cfg_pwm1_low = reg_2[15:0]; // low period of w/f +assign cfg_pwm1_high = reg_2[31:16]; // high period of w/f +gen_32b_reg #(32'h0) u_reg_2 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_2 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_2 ) + ); + +//----------------------------------------------------------------------- +// Logic for PWM-2 Config +//----------------------------------------------------------------------- +assign cfg_pwm2_low = reg_3[15:0]; // low period of w/f +assign cfg_pwm2_high = reg_3[31:16]; // high period of w/f +gen_32b_reg #(32'h0) u_reg_3 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_3 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_3 ) + ); + +//----------------------------------------------------------------------- +// Logic for PWM-3 Config +//----------------------------------------------------------------------- +assign cfg_pwm3_low = reg_4[15:0]; // low period of w/f +assign cfg_pwm3_high = reg_4[31:16]; // high period of w/f +gen_32b_reg #(32'h0) u_reg_4 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_4 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_4 ) + ); + +//----------------------------------------------------------------------- +// Logic for PWM-4 Config +//----------------------------------------------------------------------- +assign cfg_pwm4_low = reg_5[15:0]; // low period of w/f +assign cfg_pwm4_high = reg_5[31:16]; // high period of w/f + +gen_32b_reg #(32'h0) u_reg_5 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_5 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_5 ) + ); + +//----------------------------------------------------------------------- +// Logic for PWM-5 Config +//----------------------------------------------------------------------- +assign cfg_pwm5_low = reg_6[15:0]; // low period of w/f +assign cfg_pwm5_high = reg_6[31:16]; // high period of w/f + +gen_32b_reg #(32'h0) u_reg_6 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_6 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_6 ) + ); + + +always_comb +begin + reg_out [31:0] = 32'h0; + + case (sw_addr [2:0]) + 3'b000 : reg_out [31:0] = reg_0 [31:0]; + 3'b001 : reg_out [31:0] = reg_1 [31:0]; + 3'b010 : reg_out [31:0] = reg_2 [31:0]; + 3'b011 : reg_out [31:0] = reg_3 [31:0]; + 3'b100 : reg_out [31:0] = reg_4 [31:0]; + 3'b101 : reg_out [31:0] = reg_5 [31:0]; + 3'b110 : reg_out [31:0] = reg_6 [31:0]; + default : reg_out [31:0] = 32'h0; + endcase +end + +endmodule
diff --git a/verilog/rtl/pinmux/src/pwm_top.sv b/verilog/rtl/pinmux/src/pwm_top.sv new file mode 100644 index 0000000..2b8d3a5 --- /dev/null +++ b/verilog/rtl/pinmux/src/pwm_top.sv
@@ -0,0 +1,172 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// PWM Top //// +//// //// +//// This file is part of the riscduino cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +/// Includes 6 PWM //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 15th Aug 2022, Dinesh A //// +//// initial version //// +////////////////////////////////////////////////////////////////////// + +module pwm_top ( + // System Signals + // Inputs + input logic mclk, + input logic h_reset_n, + + // Reg Bus Interface Signal + input logic reg_cs, + input logic reg_wr, + input logic [2:0] reg_addr, + input logic [31:0] reg_wdata, + input logic [3:0] reg_be, + + // Outputs + output logic [31:0] reg_rdata, + output logic reg_ack, + + + input logic pulse_1ms, + input logic [5:0] cfg_pwm_enb, + output logic [5:0] pwm_wfm + + ); + +//--------------------------------------------------- +// 6 PWM variabled +//--------------------------------------------------- + +logic [15:0] cfg_pwm0_high ; +logic [15:0] cfg_pwm0_low ; +logic [15:0] cfg_pwm1_high ; +logic [15:0] cfg_pwm1_low ; +logic [15:0] cfg_pwm2_high ; +logic [15:0] cfg_pwm2_low ; +logic [15:0] cfg_pwm3_high ; +logic [15:0] cfg_pwm3_low ; +logic [15:0] cfg_pwm4_high ; +logic [15:0] cfg_pwm4_low ; +logic [15:0] cfg_pwm5_high ; +logic [15:0] cfg_pwm5_low ; + + + +pwm_reg u_reg ( + .mclk (mclk ), + .h_reset_n (h_reset_n ), + + // Reg Bus Interface Signal + .reg_cs (reg_cs ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr ), + .reg_wdata (reg_wdata ), + .reg_be (reg_be ), + + // Outputs + .reg_rdata (reg_rdata ), + .reg_ack (reg_ack ), + + .cfg_pwm0_high (cfg_pwm0_high ), + .cfg_pwm0_low (cfg_pwm0_low ), + .cfg_pwm1_high (cfg_pwm1_high ), + .cfg_pwm1_low (cfg_pwm1_low ), + .cfg_pwm2_high (cfg_pwm2_high ), + .cfg_pwm2_low (cfg_pwm2_low ), + .cfg_pwm3_high (cfg_pwm3_high ), + .cfg_pwm3_low (cfg_pwm3_low ), + .cfg_pwm4_high (cfg_pwm4_high ), + .cfg_pwm4_low (cfg_pwm4_low ), + .cfg_pwm5_high (cfg_pwm5_high ), + .cfg_pwm5_low (cfg_pwm5_low ) + + ); + + +// 6 PWM Waveform Generator +pwm u_pwm_0 ( + .waveform (pwm_wfm[0] ), + .h_reset_n (h_reset_n ), + .mclk (mclk ), + .pulse1m_mclk (pulse_1ms ), + .cfg_pwm_enb (cfg_pwm_enb[0] ), + .cfg_pwm_high (cfg_pwm0_high ), + .cfg_pwm_low (cfg_pwm0_low ) + ); + +pwm u_pwm_1 ( + .waveform (pwm_wfm[1] ), + .h_reset_n (h_reset_n ), + .mclk (mclk ), + .pulse1m_mclk (pulse_1ms ), + .cfg_pwm_enb (cfg_pwm_enb[1] ), + .cfg_pwm_high (cfg_pwm1_high ), + .cfg_pwm_low (cfg_pwm1_low ) + ); + +pwm u_pwm_2 ( + .waveform (pwm_wfm[2] ), + .h_reset_n (h_reset_n ), + .mclk (mclk ), + .pulse1m_mclk (pulse_1ms ), + .cfg_pwm_enb (cfg_pwm_enb[2] ), + .cfg_pwm_high (cfg_pwm2_high ), + .cfg_pwm_low (cfg_pwm2_low ) + ); + +pwm u_pwm_3 ( + .waveform (pwm_wfm[3] ), + .h_reset_n (h_reset_n ), + .mclk (mclk ), + .pulse1m_mclk (pulse_1ms ), + .cfg_pwm_enb (cfg_pwm_enb[3] ), + .cfg_pwm_high (cfg_pwm3_high ), + .cfg_pwm_low (cfg_pwm3_low ) + ); +pwm u_pwm_4 ( + .waveform (pwm_wfm[4] ), + .h_reset_n (h_reset_n ), + .mclk (mclk ), + .pulse1m_mclk (pulse_1ms ), + .cfg_pwm_enb (cfg_pwm_enb[4] ), + .cfg_pwm_high (cfg_pwm4_high ), + .cfg_pwm_low (cfg_pwm4_low ) + ); +pwm u_pwm_5 ( + .waveform (pwm_wfm[5] ), + .h_reset_n (h_reset_n ), + .mclk (mclk ), + .pulse1m_mclk (pulse_1ms ), + .cfg_pwm_enb (cfg_pwm_enb[5] ), + .cfg_pwm_high (cfg_pwm5_high ), + .cfg_pwm_low (cfg_pwm5_low ) + ); + +endmodule
diff --git a/verilog/rtl/pinmux/src/semaphore_reg.sv b/verilog/rtl/pinmux/src/semaphore_reg.sv new file mode 100644 index 0000000..c347178 --- /dev/null +++ b/verilog/rtl/pinmux/src/semaphore_reg.sv
@@ -0,0 +1,165 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// Semaphore Register //// +//// //// +//// This file is part of the riscduino cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +//// A semaphore is a variable or abstract data type that //// +//// provides a simple but useful abstraction for controlling //// +//// access by multiple processes to a common resource in a //// +//// parallel programming or multi-user environment. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 15th Aug 2022, Dinesh A //// +//// initial version //// +////////////////////////////////////////////////////////////////////// +// +/*************************************************************** + Special Semaphore Register Implementation + Read access from 0 to 14 will return corresponsonding bit lock status. + If lock is free, then it return '1' and also lock the corresponding bit + If lock is busy, then it return '0' + Write & Read access with address 15 does normal write and read access, + this location should used for only debug purpose + +*****************************************************************/ +module semaphore_reg #(parameter DW = 16, // DATA WIDTH + parameter AW = $clog2(DW), // ADDRESS WIDTH + parameter BW = $clog2(AW) // BYTE WIDTH + ) ( + // System Signals + // Inputs + input logic mclk, + input logic h_reset_n, + + // Reg Bus Interface Signal + input logic reg_cs, + input logic reg_wr, + input logic [AW-1:0] reg_addr, + input logic [DW-1:0] reg_wdata, + input logic [BW-1:0] reg_be, + + // Outputs + output logic [DW-1:0] reg_rdata, + output logic reg_ack + + ); + +//----------------------------------------------------------------------- +// Internal Wire Declarations +//----------------------------------------------------------------------- + +logic sw_rd_en ; +logic sw_wr_en ; +logic [AW-1:0] sw_addr ; // addressing 16 registers +logic [DW-1:0] sw_reg_wdata ; +logic [BW-1:0] sw_be ; + +logic [DW-1:0] reg_out ; +logic [DW-1:0] reg_0 ; +logic sw_wr_en_0 ; + +assign sw_addr = reg_addr; +assign sw_rd_en = reg_cs & !reg_wr; +assign sw_wr_en = reg_cs & reg_wr; + + +always @ (posedge mclk or negedge h_reset_n) +begin : preg_out_Seq + if (h_reset_n == 1'b0) begin + reg_rdata <= 'h0; + reg_ack <= 1'b0; + end else if (reg_cs && !reg_ack) begin + reg_rdata <= reg_out[DW-1:0] ; + reg_ack <= 1'b1; + end else begin + reg_ack <= 1'b0; + end +end + +/*************************************************************** + Special Semaphore Register Implementation + Read access from 0 to 30 will return corresponsonding bit lock status. + If lock is free, then it return '1' and lock the corresponding bit + If lock is busy, then it return '0' and lock the corresponding bit +*****************************************************************/ + +gen_16b_reg #('h0) u_reg_0 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_0 ), + .we (sw_be[BW-1:0] ), + .data_in (sw_reg_wdata[DW-1:0] ), + + //List of Outs + .data_out (reg_0 ) + ); + + +//----------------------------------------------------------------------- +// Register Write Data +//----------------------------------------------------------------------- + +always_comb +begin + sw_reg_wdata = 'h0; + sw_wr_en_0 = 'b0; + sw_be = 'h0; + + // Address 0xF, is Simple Write Register + if(sw_addr == {AW {1'b1}}) begin + sw_reg_wdata = reg_0; + sw_wr_en_0 = sw_wr_en & reg_ack; + sw_be = reg_be[BW-1:0]; + end else begin // 0 to 0xE is Semaphore Register + if(sw_rd_en) begin // Read will always lock the bit '1' + sw_reg_wdata = (reg_0 | ( 1 << sw_addr)) ; + end else begin // To release the Lock Write with '1' + sw_reg_wdata = (reg_0 ^ ((reg_wdata [DW-1:0] & 'h1) << sw_addr)) ; + end + sw_wr_en_0 = reg_ack; + sw_be = {BW{1'b1}}; + end +end + +//----------------------------------------------------------------------- +// Register Read Path Multiplexer instantiation +//----------------------------------------------------------------------- + +always_comb +begin + if(sw_addr == {AW {1'b1}}) begin + reg_out = reg_0; + end else begin + reg_out = (reg_0 >> sw_addr ) ^ 'h1; + end +end + + +endmodule
diff --git a/verilog/rtl/pinmux/src/timer_reg.sv b/verilog/rtl/pinmux/src/timer_reg.sv new file mode 100644 index 0000000..cd48587 --- /dev/null +++ b/verilog/rtl/pinmux/src/timer_reg.sv
@@ -0,0 +1,213 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// Timer Register //// +//// //// +//// This file is part of the riscduino cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 15th Aug 2022, Dinesh A //// +//// initial version //// +////////////////////////////////////////////////////////////////////// +// +module timer_reg ( + // System Signals + // Inputs + input logic mclk , + input logic h_reset_n , + + // Reg Bus Interface Signal + input logic reg_cs , + input logic reg_wr , + input logic [1:0] reg_addr , + input logic [31:0] reg_wdata , + input logic [3:0] reg_be , + + // Outputs + output logic [31:0] reg_rdata , + output logic reg_ack , + + output logic [9:0] cfg_pulse_1us , + output logic [2:0] cfg_timer_update , // CPU write to timer register + output logic [18:0] cfg_timer0 , // Timer-0 register + output logic [18:0] cfg_timer1 , // Timer-1 register + output logic [18:0] cfg_timer2 , // Timer-2 register + output logic [2:0] timer_intr + + ); + +//----------------------------------------------------------------------- +// Internal Wire Declarations +//----------------------------------------------------------------------- + +logic sw_rd_en ; +logic sw_wr_en ; +logic [1:0] sw_addr ; // addressing 16 registers +logic [31:0] sw_reg_wdata ; +logic [3:0] sw_be ; + +logic [31:0] reg_out ; +logic [31:0] reg_0 ; // TIMER GLOBAL CONFIG +logic [31:0] reg_1 ; // TIMER-0 +logic [31:0] reg_2 ; // TIMER-1 +logic [31:0] reg_3 ; // TIMER-2 + +assign sw_addr = reg_addr; +assign sw_rd_en = reg_cs & !reg_wr; +assign sw_wr_en = reg_cs & reg_wr; +assign sw_be = reg_be; +assign sw_reg_wdata = reg_wdata; + +//----------------------------------------------------------------------- +// register read enable and write enable decoding logic +//----------------------------------------------------------------------- +wire sw_wr_en_0 = sw_wr_en & (sw_addr == 2'h0); +wire sw_wr_en_1 = sw_wr_en & (sw_addr == 2'h1); +wire sw_wr_en_2 = sw_wr_en & (sw_addr == 2'h2); +wire sw_wr_en_3 = sw_wr_en & (sw_addr == 2'h3); + +wire sw_rd_en_0 = sw_rd_en & (sw_addr == 2'h0); +wire sw_rd_en_1 = sw_rd_en & (sw_addr == 2'h1); +wire sw_rd_en_2 = sw_rd_en & (sw_addr == 2'h2); +wire sw_rd_en_3 = sw_rd_en & (sw_addr == 2'h3); + + +always @ (posedge mclk or negedge h_reset_n) +begin : preg_out_Seq + if (h_reset_n == 1'b0) begin + reg_rdata <= 'h0; + reg_ack <= 1'b0; + end else if (reg_cs && !reg_ack) begin + reg_rdata <= reg_out; + reg_ack <= 1'b1; + end else begin + reg_ack <= 1'b0; + end +end + + +//---------------------------------------------- +// reg-0: GLBL_CFG +//------------------------------------------ + +gen_32b_reg #('h0) u_reg_0 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_0 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_0 ) + ); + +assign cfg_pulse_1us = reg_0[9:0]; + +//----------------------------------------------------------------------- +// reg-1 +// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle +// In first cycle, local register will be updated +// In second cycle, update indication sent to timer block +// ----------------------------------------------------------------- +assign cfg_timer0 = reg_1[18:0]; +assign cfg_timer_update[0] = sw_wr_en_1 & reg_ack; + +gen_32b_reg #(32'h0) u_reg_1 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_1 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_1[31:0] ) + ); + +//----------------------------------------------------------------------- +// reg-2 +// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle +// In first cycle, local register will be updated +// In second cycle, update indication sent to timer block +// ----------------------------------------------------------------- +assign cfg_timer1 = reg_2[18:0]; +assign cfg_timer_update[1] = sw_wr_en_2 & reg_ack; + +gen_32b_reg #(32'h0) u_reg_2 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_2 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_2[31:0] ) + ); + + +//----------------------------------------------------------------------- +// reg-3 +// Assumption: wr_en is two cycle and reg_ack is asserted in second cycle +// In first cycle, local register will be updated +// In second cycle, update indication sent to timer block +// ----------------------------------------------------------------- +assign cfg_timer2 = reg_3[18:0]; +assign cfg_timer_update[2] = sw_wr_en_3 & reg_ack; + +gen_32b_reg #(32'h0) u_reg_3 ( + //List of Inputs + .reset_n (h_reset_n ), + .clk (mclk ), + .cs (sw_wr_en_3 ), + .we (sw_be ), + .data_in (sw_reg_wdata ), + + //List of Outs + .data_out (reg_3[31:0] ) + ); + +//----------------------------------------------------------------------- +// Register Read Path Multiplexer instantiation +//----------------------------------------------------------------------- + +always_comb +begin + reg_out [31:0] = 32'h0; + + case (sw_addr [1:0]) + 2'b00 : reg_out [31:0] = reg_0 [31:0]; + 2'b01 : reg_out [31:0] = reg_1 [31:0]; + 2'b10 : reg_out [31:0] = reg_2 [31:0]; + 2'b11 : reg_out [31:0] = reg_3 [31:0]; + default : reg_out [31:0] = 32'h0; + endcase +end + +endmodule
diff --git a/verilog/rtl/pinmux/src/timer_top.sv b/verilog/rtl/pinmux/src/timer_top.sv new file mode 100644 index 0000000..ae981dc --- /dev/null +++ b/verilog/rtl/pinmux/src/timer_top.sv
@@ -0,0 +1,191 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// Timer Top //// +//// //// +//// This file is part of the riscduino cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 15th Aug 2022, Dinesh A //// +//// initial version //// +////////////////////////////////////////////////////////////////////// + +module timer_top ( + // System Signals + // Inputs + input logic mclk, + input logic h_reset_n, + + // Reg Bus Interface Signal + input logic reg_cs, + input logic reg_wr, + input logic [1:0] reg_addr, + input logic [31:0] reg_wdata, + input logic [3:0] reg_be, + + // Outputs + output logic [31:0] reg_rdata, + output logic reg_ack, + + output logic pulse_1ms, + output logic [2:0] timer_intr + + ); + +//--------------------------------------------------------- +// Timer Register +// ------------------------------------------------------- +logic [2:0] cfg_timer_update ; // CPU write to timer register +logic [18:0] cfg_timer0 ; // Timer-0 register +logic [18:0] cfg_timer1 ; // Timer-1 register +logic [18:0] cfg_timer2 ; // Timer-2 register + +/* clock pulse */ +//******************************************************** +logic pulse_1us ; // 1 UsSecond Pulse for waveform Generator +logic pulse_1s ; // 1Second Pulse for waveform Generator +logic [9:0] cfg_pulse_1us ; // 1us pulse generation config + +timer_reg u_reg ( + .mclk (mclk ), + .h_reset_n (h_reset_n ), + + // Reg Bus Interface Signal + .reg_cs (reg_cs ), + .reg_wr (reg_wr ), + .reg_addr (reg_addr ), + .reg_wdata (reg_wdata ), + .reg_be (reg_be ), + + // Outputs + .reg_rdata (reg_rdata ), + .reg_ack (reg_ack ), + + .cfg_pulse_1us (cfg_pulse_1us ), + .cfg_timer_update (cfg_timer_update ), + .cfg_timer0 (cfg_timer0 ), + .cfg_timer1 (cfg_timer1 ), + .cfg_timer2 (cfg_timer2 ) + + ); + +// 1us pulse +pulse_gen_type2 #(.WD(10)) u_pulse_1us ( + + .clk_pulse_o (pulse_1us ), + .clk (mclk ), + .reset_n (h_reset_n ), + .cfg_max_cnt (cfg_pulse_1us ) + + ); + +// 1us/1000 to 1millisecond pulse +pulse_gen_type1 u_pulse_1ms ( + + .clk_pulse_o (pulse_1ms ), + .clk (mclk ), + .reset_n (h_reset_n ), + .trigger (pulse_1us ) + + ); + +// 1ms/1000 => 1 second pulse +pulse_gen_type1 u_pulse_1s ( + + .clk_pulse_o (pulse_1s ), + .clk (mclk ), + .reset_n (h_reset_n ), + .trigger (pulse_1ms ) + + ); + +// Timer + +wire [1:0] cfg_timer0_clksel = cfg_timer0[18:17]; +wire cfg_timer0_enb = cfg_timer0[16]; +wire [15:0] cfg_timer0_compare = cfg_timer0[15:0]; + +timer u_timer_0 + ( + .reset_n (sreset_n ),// system syn reset + .mclk (mclk ),// master clock + .pulse_1us (pulse_1us ), + .pulse_1ms (pulse_1ms ), + .pulse_1s (pulse_1s ), + + .cfg_timer_update (cfg_timer_update[0] ), + .cfg_timer_enb (cfg_timer0_enb ), + .cfg_timer_compare (cfg_timer0_compare ), + .cfg_timer_clksel (cfg_timer0_clksel ),// to select the timer 1us/1ms reference clock + + .timer_intr (timer_intr[0] ) + ); + +// Timer +wire [1:0] cfg_timer1_clksel = cfg_timer1[18:17]; +wire cfg_timer1_enb = cfg_timer1[16]; +wire [15:0] cfg_timer1_compare = cfg_timer1[15:0]; +timer u_timer_1 + ( + .reset_n (sreset_n ),// system syn reset + .mclk (mclk ),// master clock + .pulse_1us (pulse_1us ), + .pulse_1ms (pulse_1ms ), + .pulse_1s (pulse_1s ), + + .cfg_timer_update (cfg_timer_update[1] ), + .cfg_timer_enb (cfg_timer1_enb ), + .cfg_timer_compare (cfg_timer1_compare ), + .cfg_timer_clksel (cfg_timer1_clksel ),// to select the timer 1us/1ms reference clock + + .timer_intr (timer_intr[1] ) + ); + +// Timer +wire [1:0] cfg_timer2_clksel = cfg_timer2[18:17]; +wire cfg_timer2_enb = cfg_timer2[16]; +wire [15:0] cfg_timer2_compare = cfg_timer2[15:0]; + +timer u_timer_2 + ( + .reset_n (sreset_n ),// system syn reset + .mclk (mclk ),// master clock + .pulse_1us (pulse_1us ), + .pulse_1ms (pulse_1ms ), + .pulse_1s (pulse_1s ), + + .cfg_timer_update (cfg_timer_update[2] ), + .cfg_timer_enb (cfg_timer2_enb ), + .cfg_timer_compare (cfg_timer2_compare ), + .cfg_timer_clksel (cfg_timer2_clksel ),// to select the timer 1us/1ms reference clock + + .timer_intr (timer_intr[2] ) + ); + + +endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 5cd9e0c..ba18819 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -35,6 +35,7 @@ //// 8. 2KB icache and 2KB dcache //// //// 8. 6 Channel ADC //// //// 9. Pinmux with GPIO and 6 PWM //// +//// //// //// //// To Do: //// //// nothing //// @@ -225,6 +226,16 @@ //// changes in sspim //// //// A. SPI Mode 0 to 3 support added, //// //// B. SPI Duplex mode TX-RX Mode added //// +//// 5.0 Aug 15 2022, Dinesh A //// +//// A. 15 Hardware Semahore added //// +//// B. Pinmux Address Space are Split as //// +//// `define ADDR_SPACE_PINMUX 32'h1002_0000 //// +//// `define ADDR_SPACE_GLBL 32'h1002_0000 //// +//// `define ADDR_SPACE_GPIO 32'h1002_0040 //// +//// `define ADDR_SPACE_PWM 32'h1002_0080 //// +//// `define ADDR_SPACE_TIMER 32'h1002_00C0 //// +//// `define ADDR_SPACE_SEMA 32'h1002_0100 //// +//// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -252,6 +263,32 @@ //// //// ////////////////////////////////////////////////////////////////////// +/********************************************************************* + Memory Map: //// + //// + SOC Memory Map //// + 0x0000_0000 to 0x0FFF_FFFF - QSPIM MEMORY //// + 0x1000_0000 to 0x1000_00FF - QSPIM REG + 0x1001_0000 to 0x1001_003F - UART0 + 0x1001_0040 to 0x1001_007F - I2 + 0x1001_0080 to 0x1001_00BF - USB + 0x1001_00C0 to 0x1001_00FF - SSPIM + 0x1001_0100 to 0x1001_013F - UART1 + 0x1002_0000 to 0x1002_00FF - PINMUX + + Caravel Memory Map: +----------------------------------------------------------------------- + caravel user space is 0x3000_0000 to 0x300F_FFFF + So we have allocated + 0x3008_0000 - 0x3008_00FF - Assigned to WB Host Address Space + Since We need more than 16MB Address space to access SDRAM/SPI we have + added indirect MSB 13 bit address select option + So Address will be {Bank_Sel[15:3], wbm_adr_i[18:0]} + --------------------------------------------------------------------- + 0x3080_0000 to 0x3080_00FF - WB HOST + 0x3000_0000 to 0x307F_FFFF - Indirect Address + {Bank_Sel[15:3],WB ADDR[18:0]} +***********************************************************************/ module user_project_wrapper ( `ifdef USE_POWER_PINS @@ -427,7 +464,7 @@ // Global Register Wishbone Interface //--------------------------------------------------------------------- wire wbd_glbl_stb_o ; // strobe/request -wire [7:0] wbd_glbl_adr_o ; // address +wire [8:0] wbd_glbl_adr_o ; // address wire wbd_glbl_we_o ; // write wire [WB_WIDTH-1:0] wbd_glbl_dat_o ; // data output wire [3:0] wbd_glbl_sel_o ; // byte enable @@ -1222,7 +1259,7 @@ ); -pinmux u_pinmux( +pinmux_top u_pinmux( `ifdef USE_POWER_PINS .vccd1 (vccd1 ),// User area 1 1.8V supply .vssd1 (vssd1 ),// User area 1 digital ground
diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv index 26029c2..d3d85cc 100644 --- a/verilog/rtl/wb_host/src/wb_host.sv +++ b/verilog/rtl/wb_host/src/wb_host.sv
@@ -411,11 +411,11 @@ // Locally there register are define to control the reset and clock for user // area //----------------------------------------------------------------------- -// caravel user space is 0x3000_0000 to 0x3007_FFFF +// caravel user space is 0x3000_0000 to 0x300F_FFFF // So we have allocated // 0x3008_0000 - 0x3008_00FF - Assigned to WB Host Address Space // Since We need more than 16MB Address space to access SDRAM/SPI we have -// added indirect MSB 8 bit address select option +// added indirect MSB 13 bit address select option // So Address will be {Bank_Sel[15:3], wbm_adr_i[18:0]} // --------------------------------------------------------------------- assign reg_sel = wb_req & (wb_adr_i[19] == 1'b1);
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index 9fb6344..7e348fc 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -203,8 +203,8 @@ input logic s2_wbd_ack_i, // input logic s2_wbd_err_i, - unused output logic [31:0] s2_wbd_dat_o, - output logic [7:0] s2_wbd_adr_o, // glbl reg need only 8 bits - output logic [3:0] s2_wbd_sel_o, + output logic [8:0] s2_wbd_adr_o, // glbl reg need only 9 bits + output logic [3:0] s2_wbd_sel_o, output logic s2_wbd_we_o, output logic s2_wbd_cyc_o, output logic s2_wbd_stb_o @@ -677,7 +677,7 @@ assign s1_wbd_stb_o = s1_wb_wr.wbd_stb ; assign s2_wbd_dat_o = s2_wb_wr.wbd_dat ; - assign s2_wbd_adr_o = s2_wb_wr.wbd_adr[7:0] ; // Global Reg Need 8 bit + assign s2_wbd_adr_o = s2_wb_wr.wbd_adr[8:0] ; // Global Reg Need 8 bit assign s2_wbd_sel_o = s2_wb_wr.wbd_sel ; assign s2_wbd_we_o = s2_wb_wr.wbd_we ; assign s2_wbd_cyc_o = s2_wb_wr.wbd_cyc ;