Riscv Regression and Interrupt cleanup
diff --git a/Makefile b/Makefile index dc3de7c..aa23c0e 100644 --- a/Makefile +++ b/Makefile
@@ -35,6 +35,19 @@ # Install caravel as submodule, (1): submodule, (0): clone SUBMODULE?=1 +#RISCV COMPLIANCE test Environment +COREMARK_DIR = verilog/rtl/syntacore/scr1/dependencies/coremark +RISCV_COMP_DIR = verilog/rtl/syntacore/scr1/dependencies/riscv-compliance +RISCV_TEST_DIR = verilog/rtl/syntacore/scr1/dependencies/riscv-tests + +COREMARK_REPO = https://github.com/eembc/coremark +RISCV_COMP_REPO = https://github.com/riscv/riscv-compliance +RISCV_TEST_REPO = https://github.com/riscv/riscv-tests + +COREMARK_BRANCH = 7f420b6bdbff436810ef75381059944e2b0d79e8 +RISCV_COMP_BRANCH = d51259b2a949be3af02e776c39e135402675ac9b +RISCV_TEST_BRANCH = e30978a71921159aec38eeefd848fca4ed39a826 + # Include Caravel Makefile Targets .PHONY: % : check-caravel %: @@ -56,7 +69,7 @@ DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv)) TARGET_PATH=$(shell pwd) VERIFY_COMMAND="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} && make" -$(DV_PATTERNS): verify-% : ./verilog/dv/% +$(DV_PATTERNS): verify-% : ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \ -v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \ -e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \ @@ -176,6 +189,27 @@ exit 1; \ fi +check-coremark_repo: + @if [ ! -d "$(COREMARK_DIR)" ]; then \ + echo "Installing Core Mark Repo.."; \ + git clone $(COREMARK_REPO) $(COREMARK_DIR); \ + cd $(COREMARK_DIR); git checkout $(COREMARK_BRANCH); \ + fi + +check-riscv_comp_repo: + @if [ ! -d "$(RISCV_COMP_DIR)" ]; then \ + echo "Installing Risc V Complance Repo.."; \ + git clone $(RISCV_COMP_REPO) $(RISCV_COMP_DIR); \ + cd $(RISCV_COMP_DIR); git checkout $(RISCV_COMP_BRANCH); \ + fi + +check-riscv_test_repo: + @if [ ! -d "$(RISCV_TEST_DIR)" ]; then \ + echo "Installing RiscV Test Repo.."; \ + git clone $(RISCV_TEST_REPO) $(RISCV_TEST_DIR); \ + cd $(RISCV_TEST_DIR); git checkout $(RISCV_TEST_BRANCH); \ + fi + .PHONY: help help: cd $(CARAVEL_ROOT) && $(MAKE) help
diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc index ac76e84..d815c04 100644 --- a/openlane/wb_interconnect/base.sdc +++ b/openlane/wb_interconnect/base.sdc
@@ -7,16 +7,10 @@ # Timing Constraints ############################################################################### create_clock -name clk_i -period 10.0000 [get_ports {clk_i}] -set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -hold 0.2500 -set_clock_uncertainty -rise_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -setup 0.2500 -set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -hold 0.2500 -set_clock_uncertainty -rise_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -setup 0.2500 -set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -hold 0.2500 -set_clock_uncertainty -fall_from [get_clocks {clk_i}] -rise_to [get_clocks {clk_i}] -setup 0.2500 -set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -hold 0.2500 -set_clock_uncertainty -fall_from [get_clocks {clk_i}] -fall_to [get_clocks {clk_i}] -setup 0.2500 - +set_clock_transition 0.1500 [all_clocks] +set_clock_uncertainty -setup 0.2500 [all_clocks] +set_clock_uncertainty -hold 0.2500 [all_clocks] #Clock Skew adjustment set_case_analysis 0 [get_ports {cfg_cska_wi[0]}]
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv index 7241d94..d31ebe3 100644 --- a/signoff/pinmux/final_summary_report.csv +++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h17m10s,-1,46012.12121212122,0.2475,23006.06060606061,27.04,701.62,5694,0,0,0,0,0,0,-1,1,0,-1,-1,421176,61049,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,309535459.0,5.55,42.43,32.83,10.82,0.75,-1,3565,8555,538,5527,0,0,0,4197,0,0,0,0,0,0,0,4,1341,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h13m47s,-1,46109.09090909091,0.2475,23054.545454545456,27.06,702.63,5706,0,0,0,0,0,0,-1,1,0,-1,-1,428667,61634,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,317697885.0,6.86,43.74,33.48,10.88,0.31,-1,3574,8561,543,5529,0,0,0,4202,0,0,0,0,0,0,0,4,1343,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index a6e08b8..4f25320 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h41m51s,-1,2.529576587795766,10.2784,1.264788293897883,-1,531.06,13,0,0,0,0,0,0,-1,0,0,-1,-1,1176475,8150,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.36,3.16,3.67,0.41,0.59,-1,271,2532,271,2532,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h40m7s,-1,2.529576587795766,10.2784,1.264788293897883,-1,530.05,13,0,0,0,0,0,0,-1,0,0,-1,-1,1176096,8164,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.36,3.16,3.65,0.41,0.64,-1,271,2532,271,2532,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index 04075b4..9ec6823 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -44,10 +44,10 @@ set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}] set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}] -set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}] +set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] +set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] +set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}] set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[0]}] set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[1]}] @@ -59,10 +59,10 @@ set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}] set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}] -set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}] -set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}] -set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}] -set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}] +set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}] +set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}] +set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}] +set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}] set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[0]}] set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[1]}] @@ -164,7 +164,7 @@ puts "\[INFO\]: Setting clock setup uncertainity to: $::env(SYNTH_CLOCK_SETUP_UNCERTAINITY)" puts "\[INFO\]: Setting clock hold uncertainity to: $::env(SYNTH_CLOCK_HOLD_UNCERTAINITY)" set_clock_uncertainty -setup $::env(SYNTH_CLOCK_SETUP_UNCERTAINITY) [all_clocks] -set_clock_uncertainty -setup $::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) [all_clocks] +set_clock_uncertainty -hold $::env(SYNTH_CLOCK_HOLD_UNCERTAINITY) [all_clocks] #set_output_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_pins {mprj/wbs_adr_i[*]}]
diff --git a/verilog/dv/riscv_regress/Makefile b/verilog/dv/riscv_regress/Makefile index 645b9cd..489b40e 100644 --- a/verilog/dv/riscv_regress/Makefile +++ b/verilog/dv/riscv_regress/Makefile
@@ -159,7 +159,7 @@ export RISCV_OBJDUMP ?= $(CROSS_PREFIX)objdump -D export RISCV_ROM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -j .text.init -j .text -j .rodata -j .rodata.str1.4 -O verilog #Seperate the RAM content and write out in 32bit Little endian format to load it to TCM Memory -export RISCV_RAM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -R .text.init -R .text -R .rodata -R .rodata.str1.4 -R .riscv.attributes -O verilog --verilog-data-width=4 --reverse-bytes=4 +export RISCV_RAM_OBJCOPY ?= $(CROSS_PREFIX)objcopy -R .text.init -R .text -R .rodata -R .rodata.str1.4 -R .riscv.attributes -R .comment -R .debug_abbrev -R .debug_loc -R .debug_str -O verilog --verilog-data-width=4 --reverse-bytes=4 export RISCV_READELF ?= $(CROSS_PREFIX)readelf -s ifneq (,$(findstring e,$(ARCH_lowercase))) @@ -174,14 +174,14 @@ ifeq (,$(findstring e,$(ARCH_lowercase))) # These tests cannot be compiled for RVE # Comment this target if you don't want to run the riscv_isa - TARGETS += riscv_isa + #TARGETS += riscv_isa # Comment this target if you don't want to run the riscv_compliance - TARGETS += riscv_compliance + #TARGETS += riscv_compliance endif # Comment this target if you don't want to run the isr_sample -#TARGETS += isr_sample +TARGETS += isr_sample # Comment this target if you don't want to run the coremark #TARGETS += coremark
diff --git a/verilog/dv/riscv_regress/riscv_runtests.sv b/verilog/dv/riscv_regress/riscv_runtests.sv index ee1aeca..40dc43b 100644 --- a/verilog/dv/riscv_regress/riscv_runtests.sv +++ b/verilog/dv/riscv_regress/riscv_runtests.sv
@@ -53,7 +53,7 @@ $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", core2dmem_addr_o_r,`RISC_CORE.dmem2core_rdata_i,`RISC_CORE.dmem2core_resp_i); end **/ -/*** +/** logic [31:0] test_count; `define RISC_CORE u_top.u_riscv_top.i_core_top `define RISC_EXU u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu @@ -70,6 +70,7 @@ end end **/ + always_ff @(posedge clk) begin bit test_pass; int unsigned f_test;
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index 5b06160..1384d19 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -180,6 +180,7 @@ $dumpvars(1, user_risc_regress_tb); $dumpvars(1, user_risc_regress_tb.u_top); $dumpvars(0, user_risc_regress_tb.u_top.u_riscv_top); + $dumpvars(0, user_risc_regress_tb.u_top.u_pinmux); end `endif
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index e959a8e..865e4f9 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -242,8 +242,8 @@ wb_user_core_write('h3080_0000,'h1); wb_user_core_read_check(32'h30020058,read_data,32'h8273_8343); - wb_user_core_read_check(32'h3002005C,read_data,32'h0101_2022); - wb_user_core_read_check(32'h30020060,read_data,32'h0002_3000); + wb_user_core_read_check(32'h3002005C,read_data,32'h0601_2022); + wb_user_core_read_check(32'h30020060,read_data,32'h0002_5000); end
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v index 9693439..05d1bdd 100644 --- a/verilog/dv/user_spi/user_spi_tb.v +++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -232,8 +232,8 @@ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h00428293); - wb_user_core_read_check(32'h0000031C,read_data,32'h06300313); + wb_user_core_read_check(32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read "); $display(" SPI Mode: Normal/Single Bit "); @@ -258,8 +258,8 @@ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h00428293); - wb_user_core_read_check(32'h0000031C,read_data,32'h06300313); + wb_user_core_read_check(32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read "); $display(" SPI Mode: Normal/Single Bit "); @@ -284,8 +284,8 @@ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h00428293); - wb_user_core_read_check(32'h0000031C,read_data,32'h06300313); + wb_user_core_read_check(32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read "); @@ -311,8 +311,8 @@ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h00428293); - wb_user_core_read_check(32'h0000031C,read_data,32'h06300313); + wb_user_core_read_check(32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read with Prefetch"); @@ -338,8 +338,8 @@ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h00428293); - wb_user_core_read_check(32'h0000031C,read_data,32'h06300313); + wb_user_core_read_check(32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read with Prefetch:3DW"); @@ -362,8 +362,8 @@ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h00428293); - wb_user_core_read_check(32'h0000031C,read_data,32'h06300313); + wb_user_core_read_check(32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read with Prefetch:2DW"); @@ -386,8 +386,8 @@ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h00428293); - wb_user_core_read_check(32'h0000031C,read_data,32'h06300313); + wb_user_core_read_check(32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); $display("#############################################"); @@ -411,8 +411,8 @@ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h00428293); - wb_user_core_read_check(32'h0000031C,read_data,32'h06300313); + wb_user_core_read_check(32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display("Testing Direct SPI Memory Read with Prefetch:7DW"); @@ -435,8 +435,8 @@ wb_user_core_read_check(32'h0000030C,read_data,32'h43050049); wb_user_core_read_check(32'h00000310,read_data,32'h0062A023); wb_user_core_read_check(32'h00000314,read_data,32'h004902B7); - wb_user_core_read_check(32'h00000318,read_data,32'h00428293); - wb_user_core_read_check(32'h0000031C,read_data,32'h06300313); + wb_user_core_read_check(32'h00000318,read_data,32'h03130291); + wb_user_core_read_check(32'h0000031C,read_data,32'ha0230630); $display("#############################################"); $display(" Testing Single Word Indirect SPI Memory Read"); @@ -473,9 +473,9 @@ wb_user_core_write(32'h10000014,32'h00000314); wb_user_core_read_check(32'h1000001C,read_data,32'h004902B7); wb_user_core_write(32'h10000014,32'h00000318); - wb_user_core_read_check(32'h1000001C,read_data,32'h00428293); + wb_user_core_read_check(32'h1000001C,read_data,32'h03130291); wb_user_core_write(32'h10000014,32'h0000031C); - wb_user_core_read_check(32'h1000001C,read_data,32'h06300313); + wb_user_core_read_check(32'h1000001C,read_data,32'ha0230630); repeat (100) @(posedge clock); $display("#############################################"); $display(" Testing Two Word Indirect SPI Memory Read"); @@ -505,8 +505,8 @@ wb_user_core_read_check(32'h1000001C,read_data,32'h0062A023); wb_user_core_read_check(32'h1000001C,read_data,32'h004902B7); wb_user_core_write(32'h10000014,32'h00000318); - wb_user_core_read_check(32'h1000001C,read_data,32'h00428293); - wb_user_core_read_check(32'h1000001C,read_data,32'h06300313); + wb_user_core_read_check(32'h1000001C,read_data,32'h03130291); + wb_user_core_read_check(32'h1000001C,read_data,32'ha0230630); repeat (100) @(posedge clock); $display("#############################################"); $display(" Testing Three Word Indirect SPI Memory Read"); @@ -555,8 +555,8 @@ wb_user_core_write(32'h10000014,32'h00000310); wb_user_core_read_check(32'h1000001C,read_data,32'h0062A023); wb_user_core_read_check(32'h1000001C,read_data,32'h004902B7); - wb_user_core_read_check(32'h1000001C,read_data,32'h00428293); - wb_user_core_read_check(32'h1000001C,read_data,32'h06300313); + wb_user_core_read_check(32'h1000001C,read_data,32'h03130291); + wb_user_core_read_check(32'h1000001C,read_data,32'ha0230630); repeat (100) @(posedge clock); $display("#############################################"); $display(" Testing Five Word Indirect SPI Memory Read"); @@ -598,8 +598,8 @@ wb_user_core_read_check(32'h1000001C,read_data,32'h43050049); wb_user_core_read_check(32'h1000001C,read_data,32'h0062A023); wb_user_core_read_check(32'h1000001C,read_data,32'h004902B7); - wb_user_core_read_check(32'h1000001C,read_data,32'h00428293); - wb_user_core_read_check(32'h1000001C,read_data,32'h06300313); + wb_user_core_read_check(32'h1000001C,read_data,32'h03130291); + wb_user_core_read_check(32'h1000001C,read_data,32'ha0230630); $display("#############################################"); $display(" Sector Erase Command ");
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv index e3b9044..24c8ae6 100644 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -334,33 +334,49 @@ //----------------------------------------------------------------------- // reg-6 //----------------------------------------------------------------- -assign irq_lines = {gpio_intr,ext_intr_in[1:0],usb_intr,i2cm_intr,reg_6[10:0]}; -assign soft_irq = reg_6[11]; -assign user_irq = reg_6[14:12]; +assign irq_lines = reg_6[15:0]; +assign soft_irq = reg_6[16]; +assign user_irq = reg_6[19:17]; + generic_register #(8,0 ) u_reg6_be0 ( .we ({8{sw_wr_en_6 & - wr_be[0] }} ), - .data_in (sw_reg_wdata[7:0] ), + wr_be[0] }} ), + .data_in (sw_reg_wdata[7:0] ), + .reset_n (h_reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_6[7:0] ) + ); + +generic_register #(3,0 ) u_reg6_be1_1 ( + .we ({3{sw_wr_en_6 & + wr_be[1] }} ), + .data_in (sw_reg_wdata[10:8] ), + .reset_n (h_reset_n ), + .clk (mclk ), + + //List of Outs + .data_out (reg_6[10:8] ) + ); + + +assign reg_6[15:11] = {gpio_intr, ext_intr_in[1:0], usb_intr, i2cm_intr}; + + +generic_register #(4,0 ) u_reg6_be2 ( + .we ({4{sw_wr_en_6 & + wr_be[2] }} ), + .data_in (sw_reg_wdata[19:16]), .reset_n (h_reset_n ), .clk (mclk ), //List of Outs - .data_out (reg_6[7:0] ) + .data_out (reg_6[19:16] ) ); -generic_register #(7,0 ) u_reg6_be1 ( - .we ({7{sw_wr_en_6 & - wr_be[1] }} ), - .data_in (sw_reg_wdata[14:8]), - .reset_n (h_reset_n ), - .clk (mclk ), - - //List of Outs - .data_out (reg_6[14:8] ) - ); - -assign reg_6[31:15] = '0; +assign reg_6[31:20] = '0; // Register-7 gen_32b_reg #(32'h0) u_reg_7 ( @@ -668,7 +684,7 @@ //----------------------------------------- // Software Reg-2, Release date: <DAY><MONTH><YEAR> // ---------------------------------------- -gen_32b_reg #(32'h0601_2022) u_reg_23 ( +gen_32b_reg #(32'h0801_2022) u_reg_23 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -681,9 +697,9 @@ ); //----------------------------------------- -// Software Reg-3: Poject Revison 2.5 = 0002500 +// Software Reg-3: Poject Revison 2.6 = 0002600 // ---------------------------------------- -gen_32b_reg #(32'h0002_5000) u_reg_24 ( +gen_32b_reg #(32'h0002_6000) u_reg_24 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ),
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld b/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld index 6df6659..92f3893 100644 --- a/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld +++ b/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld
@@ -28,7 +28,8 @@ MEMORY { ROM (rxx) : ORIGIN = 0x0, LENGTH = 64K - RAM (rwx) : ORIGIN = 0x00480000, LENGTH = 4K + TCM (rwx) : ORIGIN = 0x00480000, LENGTH = 4K + RAM (rwx) : ORIGIN = 0x10030000, LENGTH = 8K } STACK_SIZE = 1024; @@ -63,14 +64,14 @@ .data : { *(.data .data.*) . = ALIGN(CL_SIZE); - } >RAM + } >TCM .sdata : { __global_pointer$ = . + 0x800; *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*) *(.sdata .sdata.* .gnu.linkonce.s.*) . = ALIGN(CL_SIZE); - } >RAM + } >TCM /* thread-local data segment */ .tdata : { @@ -79,14 +80,14 @@ *(.tdata .tdata.*) PROVIDE(_tdata_end = .); . = ALIGN(CL_SIZE); - } >RAM + } >TCM .tbss : { PROVIDE(__BSS_START__ = .); *(.tbss .tbss.*) . = ALIGN(CL_SIZE); PROVIDE(_tbss_end = .); - } >RAM + } >TCM /* bss segment */ .sbss : { @@ -105,13 +106,13 @@ /* End of uninitalized data segement */ - .stack ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE : { + .stack ORIGIN(TCM) + LENGTH(TCM) - STACK_SIZE : { FILL(0); PROVIDE(__STACK_START__ = .); . += STACK_SIZE; PROVIDE(__C_STACK_TOP__ = .); PROVIDE(__STACK_END__ = .); - } >RAM + } >TCM /DISCARD/ : { *(.eh_frame .eh_frame.*)
diff --git a/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S b/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S index 288b8fb..d7b3d63 100644 --- a/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S +++ b/verilog/rtl/syntacore/scr1/sim/tests/isr_sample/isr_sample.S
@@ -11,9 +11,9 @@ #define MCAUSE_TMR_IRQ (1 << 31 | IRQ_M_TIMER) // IPIC -#define IRQ_LINES_ADDR 0x3000000C // simulation -#define TRIG_EXT_IRQ_ADDR 0x3000000C // external irq is triggered when tb memory is set to non-zero // Bit [15:0] -#define TRIG_SW_IRQ_ADDR 0x3000000C // software irq is triggered when tb memory is set to non-zero // Bit [16] +#define IRQ_LINES_ADDR 0x10020018 // simulation +#define TRIG_EXT_IRQ_ADDR 0x10020018 // external irq is triggered when tb memory is set to non-zero // Bit [15:0] +#define TRIG_SW_IRQ_ADDR 0x10020018 // software irq is triggered when tb memory is set to non-zero // Bit [16] #define IPIC_EOI 0xBF4 // end of interrupt #define IPIC_SOI 0xBF5 // start of interrupt @@ -178,7 +178,7 @@ /// configuring software interrupt /// csrw mie, zero // disable all interrupts li t0, TRIG_SW_IRQ_ADDR - li t1, 0x00010000 + li t1, 0x00010000 // Soft ireq bit [16] sw t1, (t0) //send command to generate software interrupt li t0, MSIE csrs mie, t0 // enable software interrupt
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 2f5d2c1..0a00b92 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -145,6 +145,8 @@ //// LA[0] is added as soft reset option at wb_port //// //// 2.5 Jan 06, 2022, Dinesh A //// //// TCM RAM Bug fix inside syntacore //// +//// 2.6 Jan 08, 2022, Dinesh A //// +//// Pinmux Interrupt Logic change //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG ////