spisram support added in qspim
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg index eab1c0c..ffdf50f 100644 --- a/openlane/pinmux/pin_order.cfg +++ b/openlane/pinmux/pin_order.cfg
@@ -290,7 +290,10 @@ sflash_oen\[1\] sflash_oen\[2\] sflash_oen\[3\] -sflash_ss +sflash_ss\[0\] +sflash_ss\[1\] +sflash_ss\[2\] +sflash_ss\[3\] sflash_sck sflash_do\[0\] sflash_do\[1\]
diff --git a/signoff/mbist_wrapper/final_summary_report.csv b/signoff/mbist_wrapper/final_summary_report.csv index dde27c1..b34cb4b 100644 --- a/signoff/mbist_wrapper/final_summary_report.csv +++ b/signoff/mbist_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/mbist_wrapper,mbist_wrapper,mbist_wrapper,flow_completed,0h4m34s,-1,14342.857142857143,0.315,7171.428571428572,9.9,644.01,2259,0,0,0,0,0,0,-1,2,0,0,-1,167687,24265,-0.67,-5.59,-1,-1.19,-1,-0.67,-2630.72,-1,-1.19,-1,126574452.0,3.03,19.02,3.65,4.89,0.0,-1,1595,5654,730,4741,0,0,0,1483,0,0,0,0,0,0,0,4,737,586,15,138,4082,0,4220,90.9090909090909,11,10,AREA 0,4,50,1,140,140,0.3,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/mbist_wrapper,mbist_wrapper,mbist_wrapper,flow_completed,0h12m21s,-1,22596.825396825396,0.315,11298.412698412698,14.27,692.75,3559,0,0,0,0,0,0,-1,14,0,0,-1,493339,48549,-0.67,-6.16,-1,-1.48,-1,-0.67,-2838.32,-1,-1.64,-1,413236407.0,0.23,48.61,12.47,22.58,0.0,-1,2596,7282,753,5382,0,0,0,2664,0,0,0,0,0,0,0,4,1049,798,17,138,4082,0,4220,90.9090909090909,11,10,AREA 0,4,50,1,140,140,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv index a88c45c..7337820 100644 --- a/signoff/pinmux/final_summary_report.csv +++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h24m9s,-1,46109.09090909091,0.2475,23054.545454545456,27.06,722.6,5706,0,0,0,0,0,0,-1,1,0,-1,-1,429797,61501,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,317748797.0,6.41,43.62,33.59,11.07,0.27,-1,3574,8561,543,5529,0,0,0,4202,0,0,0,0,0,0,0,4,1343,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h16m12s,-1,46109.09090909091,0.2475,23054.545454545456,27.07,714.13,5706,0,0,0,0,0,0,-1,1,0,-1,-1,434666,61807,0.0,-0.01,-1,0.0,-1,0.0,-0.03,-1,0.0,-1,320204079.0,5.99,43.88,33.8,11.89,0.3,-1,3574,8564,543,5532,0,0,0,4202,0,0,0,0,0,0,0,4,1343,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim/final_summary_report.csv b/signoff/qspim/final_summary_report.csv index e17c115..eafe299 100644 --- a/signoff/qspim/final_summary_report.csv +++ b/signoff/qspim/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h20m0s,-1,65850.50505050505,0.2475,32925.25252525252,37.63,745.37,8149,0,0,0,0,0,0,-1,1,0,-1,-1,373982,74376,0.0,-4.44,-1,0.0,-1,0.0,-2107.85,-1,0.0,-1,236380045.0,0.0,37.41,33.44,4.51,0.78,-1,7004,10337,741,4073,0,0,0,7930,0,0,0,0,0,0,0,4,1937,2441,22,388,3234,0,3622,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.42,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h18m13s,-1,69139.39393939394,0.2475,34569.69696969697,39.57,778.62,8556,0,0,0,0,0,0,-1,1,0,-1,-1,423083,80674,-0.2,-5.37,-1,0.0,-1,-6.1,-2269.63,-1,0.0,-1,266384048.0,0.0,40.72,38.22,6.38,1.41,-1,7371,11035,803,4466,0,0,0,8344,0,0,0,0,0,0,0,4,2003,2524,22,388,3234,0,3622,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.42,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index cdbf6b0..393d72c 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h49m16s,-1,2.724159402241594,10.2784,1.362079701120797,-1,536.59,14,0,0,0,0,0,0,-1,0,0,-1,-1,1480871,10235,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,64380.84,4.37,5.34,0.99,0.77,-1,313,2874,313,2874,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,100,90,0.55,0.0,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h7m7s,-1,2.724159402241594,10.2784,1.362079701120797,-1,536.8,14,0,0,0,0,0,0,-1,0,0,-1,-1,1487509,10317,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,64380.99,4.37,5.42,1.03,0.72,-1,313,2877,313,2877,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,100,90,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/verilog/dv/model/spiram.v b/verilog/dv/model/spiram.v new file mode 100644 index 0000000..cd33c11 --- /dev/null +++ b/verilog/dv/model/spiram.v
@@ -0,0 +1,329 @@ +`default_nettype none +/* + * SPDX-FileCopyrightText: 2022 <Dinesh Annayya> + * + * Riscdunio + * + * Copyright (C) 2022 Dinesh Annayya <dinesha.opencore.org> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * SPDX-License-Identifier: ISC + */ + +`timescale 1 ns / 1 ps + +// +// Simple SPI Ram simulation model for 128Kx8 LOW VOLTAGE, FAST SERIAL SRAM +// (IS62/65WVS1288GALL) +// +// This model samples io input signals 1ns before the SPI clock edge and +// updates output signals 1ns after the SPI clock edge. +// +// Supported commands: +// 0x03, 0x02, 0x3B , 0x38, 0xFF, 0x05 , 0x01 +// Instruction Hex Description +// READ 0x03 Read data from memory array beginning at selected address +// WRITE 0x02 Write data to memory array beginning at selected address +// ESDI 0x3B Enter SDI mode +// ESQI 0x38 Enter SQI mode +// RSTDQI 0xFF Reset SDI/SQI mode +// RDMR 0x05 Read Mode Register +// WRMR 0x01 Write Mode Register +// + +module spiram #( + parameter mem_file_name = "firmware.hex" +)( + input csb, + input clk, + inout io0, // MOSI + inout io1, // MISO + inout io2, + inout io3 +); + localparam verbose = 0; + localparam integer latency = 8; + + reg [7:0] buffer; + reg [3:0] reset_count = 0; + reg [3:0] reset_monitor = 0; + integer bitcount = 0; + integer bytecount = 0; + integer dummycount = 0; + + reg [7:0] spi_cmd; + reg [23:0] spi_addr; + + reg [7:0] spi_in; + reg [7:0] spi_out; + reg spi_io_vld; + + + localparam [1:0] sspi = 1; + localparam [1:0] dspi = 2; + localparam [1:0] qspi = 3; + + localparam [3:0] mode_sspi_rd = 1; + localparam [3:0] mode_sspi_wr = 2; + localparam [3:0] mode_dspi_rd = 3; + localparam [3:0] mode_dspi_wr = 4; + localparam [3:0] mode_qspi_rd = 5; + localparam [3:0] mode_qspi_wr = 6; + + reg [3:0] spi_phase = mode_sspi_rd; + reg [3:0] spi_data_phase = 0; + reg [3:0] spi_mode = sspi; + + reg io0_oe = 0; + reg io1_oe = 0; + reg io2_oe = 0; + reg io3_oe = 0; + + reg io0_dout = 0; + reg io1_dout = 0; + reg io2_dout = 0; + reg io3_dout = 0; + + assign #1 io0 = io0_oe ? io0_dout : 1'bz; + assign #1 io1 = io1_oe ? io1_dout : 1'bz; + assign #1 io2 = io2_oe ? io2_dout : 1'bz; + assign #1 io3 = io3_oe ? io3_dout : 1'bz; + + wire io0_delayed; + wire io1_delayed; + wire io2_delayed; + wire io3_delayed; + + assign #1 io0_delayed = io0; + assign #1 io1_delayed = io1; + assign #1 io2_delayed = io2; + assign #1 io3_delayed = io3; + + // 128KB RAM + reg [7:0] memory [0:128*1024-1]; + + initial begin + if (!(mem_file_name == "none")) + $readmemh(mem_file_name,memory); + end + + task spi_action; + begin + spi_in = buffer; + + if (bytecount == 1) begin + spi_cmd = buffer; + + if (spi_cmd == 8'h 3b) begin + spi_mode = dspi; + end + + if (spi_cmd == 8'h 38) begin + spi_mode = qspi; + end + + if (spi_cmd == 8'h ff) begin + spi_mode = sspi; + end + + // spi read + if (spi_cmd == 8'h 03 && spi_mode == sspi) + spi_phase = mode_sspi_rd; + + // spi write + if (spi_cmd == 8'h 02 && spi_mode == sspi) + spi_phase = mode_sspi_wr; + + // dual spi read + if (spi_cmd == 8'h 03 && spi_mode == dspi) + spi_phase = mode_dspi_rd; + + // dual spi write + if (spi_cmd == 8'h 02 && spi_mode == dspi) + spi_phase = mode_dspi_wr; + + // quad spi read + if (spi_cmd == 8'h 03 && spi_mode == qspi) + spi_phase = mode_qspi_rd; + + // quad spi write + if (spi_cmd == 8'h 02 && spi_mode == qspi) + spi_phase = mode_qspi_wr; + end + + if (spi_cmd == 'h 03 || (spi_cmd == 'h 02)) begin + if (bytecount == 2) + spi_addr[23:16] = buffer; + + if (bytecount == 3) + spi_addr[15:8] = buffer; + + if (bytecount == 4) begin + spi_addr[7:0] = buffer; + spi_data_phase = spi_phase; + end + + // Dummy by selection at end of address phase for read + // mode only + if (bytecount == 4 && spi_mode == sspi && spi_cmd ==8'h03 ) + dummycount = 8; + if (bytecount == 4 && spi_mode == dspi && spi_cmd ==8'h03) + dummycount = 4; + if (bytecount == 4 && spi_mode == qspi && spi_cmd ==8'h03) + dummycount = 2; + + if (bytecount >= 4 && spi_cmd ==8'h03) begin // Data Read Phase + buffer = memory[spi_addr]; + //$display("%m: Read Memory Address: %x Data: %x",spi_addr,buffer); + spi_addr = spi_addr + 1; + end + if (bytecount > 4 && spi_cmd ==8'h02) begin // Data Write Phase + memory[spi_addr] = buffer; + //$display("%m: Write Memory Address: %x Data: %x",spi_addr,buffer); + spi_addr = spi_addr + 1; + end + end + + spi_out = buffer; + spi_io_vld = 1; + + if (verbose) begin + if (bytecount == 1) + $write("<SPI-START>"); + $write("<SPI:%02x:%02x>", spi_in, spi_out); + end + + end + endtask + + + always @(csb) begin + if (csb) begin + if (verbose) begin + $display(""); + $fflush; + end + buffer = 0; + bitcount = 0; + bytecount = 0; + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + spi_data_phase = 0; + + end + end + + + always @(csb, clk) begin + spi_io_vld = 0; + if (!csb && !clk) begin + if (dummycount > 0) begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end else + case (spi_data_phase) + mode_sspi_rd: begin + io0_oe = 0; + io1_oe = 1; + io2_oe = 0; + io3_oe = 0; + io1_dout = buffer[7]; + end + mode_sspi_wr: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + mode_dspi_wr: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + mode_dspi_rd: begin + io0_oe = 1; + io1_oe = 1; + io2_oe = 0; + io3_oe = 0; + io0_dout = buffer[6]; + io1_dout = buffer[7]; + end + mode_qspi_wr: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + mode_qspi_rd: begin + io0_oe = 1; + io1_oe = 1; + io2_oe = 1; + io3_oe = 1; + io0_dout = buffer[4]; + io1_dout = buffer[5]; + io2_dout = buffer[6]; + io3_dout = buffer[7]; + end + default: begin + io0_oe = 0; + io1_oe = 0; + io2_oe = 0; + io3_oe = 0; + end + endcase + end + end + + always @(posedge clk) begin + if (!csb) begin + if (dummycount > 0) begin + dummycount = dummycount - 1; + end else + case (spi_mode) + sspi: begin + buffer = {buffer, io0}; + bitcount = bitcount + 1; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + dspi: begin + buffer = {buffer, io1, io0}; + bitcount = bitcount + 2; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + qspi: begin + buffer = {buffer, io3, io2, io1, io0}; + bitcount = bitcount + 4; + if (bitcount == 8) begin + bitcount = 0; + bytecount = bytecount + 1; + spi_action; + end + end + endcase + end + end +endmodule
diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v index fec74e4..bc4db63 100644 --- a/verilog/dv/risc_boot/risc_boot_tb.v +++ b/verilog/dv/risc_boot/risc_boot_tb.v
@@ -312,7 +312,7 @@ //----------------------------------------- wire user_flash_clk = mprj_io[24]; - wire user_flash_csb = mprj_io[25]; + wire user_flash_csb = mprj_io[28]; //tri user_flash_io0 = mprj_io[26]; //tri user_flash_io1 = mprj_io[27]; //tri user_flash_io2 = mprj_io[28]; @@ -325,13 +325,13 @@ .TimingModel("S25FL512SAGMFI010_F_30pF")) u_spi_flash_256mb ( // Data Inputs/Outputs - .SI (mprj_io[26]), - .SO (mprj_io[27]), + .SI (mprj_io[29]), + .SO (mprj_io[30]), // Controls .SCK (user_flash_clk), .CSNeg (user_flash_csb), - .WPNeg (mprj_io[28]), - .HOLDNeg (mprj_io[29]), + .WPNeg (mprj_io[31]), + .HOLDNeg (mprj_io[32]), .RSTNeg (RSTB) );
diff --git a/verilog/dv/riscv_regress/riscv_runtests.sv b/verilog/dv/riscv_regress/riscv_runtests.sv index 7a398c2..0396ed2 100644 --- a/verilog/dv/riscv_regress/riscv_runtests.sv +++ b/verilog/dv/riscv_regress/riscv_runtests.sv
@@ -156,7 +156,7 @@ `endif fd = $fopen(tmpstr, "w"); while ((start != stop)) begin - test_data = u_top.u_mbist.u_sram0_2kb.mem[(start & 32'h1FFF)]; + test_data = u_top.u_sram0_2kb.mem[(start & 32'h1FFF)]; $fwrite(fd, "%x", test_data); $fwrite(fd, "%s", "\n"); start += 4; @@ -180,7 +180,7 @@ // other-wise need to switch bank // -------------------------------------------------- //$writememh("sram0_out.hex",u_top.u_tsram0_2kb.mem,0,511); - test_data = u_top.u_mbist.u_sram0_2kb.mem[((start >> 2) & 32'h1FFF)]; + test_data = u_top.u_sram0_2kb.mem[((start >> 2) & 32'h1FFF)]; //$display("Compare Addr: %x ref_data : %x, test_data: %x",start,ref_data,test_data); test_pass &= (ref_data == test_data); if(ref_data != test_data)
diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v index 41f5bb4..0636940 100644 --- a/verilog/dv/riscv_regress/user_risc_regress_tb.v +++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v
@@ -217,12 +217,12 @@ for(i = 0 ; i < 2048; i = i +4) begin mem_data = {tem_mem[i+3],tem_mem[i+2],tem_mem[i+1],tem_mem[i+0]}; //$display("Filling Mem Location : %x with data : %x",i, mem_data); - u_top.u_mbist.u_sram0_2kb.mem[i/4] = mem_data; + u_top.u_sram0_2kb.mem[i/4] = mem_data; end for(i = 2048 ; i < 4096; i = i +4) begin mem_data = {tem_mem[i+3],tem_mem[i+2],tem_mem[i+1],tem_mem[i+0]}; //$display("Filling Mem Location : %x with data : %x",i, mem_data); - u_top.u_mbist.u_sram1_2kb.mem[(2048-i)/4] = mem_data; + u_top.u_sram1_2kb.mem[(2048-i)/4] = mem_data; end //for(i =32'h00; i < 32'h100; i = i+1) @@ -326,21 +326,21 @@ // ---------------------------------------------------- wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_csb = io_out[28]; // Creating Pad Delay - wire #1 io_oeb_26 = io_oeb[26]; - wire #1 io_oeb_27 = io_oeb[27]; - wire #1 io_oeb_28 = io_oeb[28]; wire #1 io_oeb_29 = io_oeb[29]; - tri flash_io0 = (io_oeb_26== 1'b0) ? io_out[26] : 1'bz; - tri flash_io1 = (io_oeb_27== 1'b0) ? io_out[27] : 1'bz; - tri flash_io2 = (io_oeb_28== 1'b0) ? io_out[28] : 1'bz; - tri flash_io3 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + wire #1 io_oeb_30 = io_oeb[30]; + wire #1 io_oeb_31 = io_oeb[31]; + wire #1 io_oeb_32 = io_oeb[32]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; - assign io_in[26] = flash_io0; - assign io_in[27] = flash_io1; - assign io_in[28] = flash_io2; - assign io_in[29] = flash_io3; + assign io_in[29] = flash_io0; + assign io_in[30] = flash_io1; + assign io_in[31] = flash_io2; + assign io_in[32] = flash_io3; // Quard flash
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index faa6d8c..e674c34 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -242,8 +242,8 @@ wb_user_core_write('h3080_0000,'h1); wb_user_core_read_check(32'h30020058,read_data,32'h8273_8343); - wb_user_core_read_check(32'h3002005C,read_data,32'h0202_2022); - wb_user_core_read_check(32'h30020060,read_data,32'h0003_2000); + wb_user_core_read_check(32'h3002005C,read_data,32'h0802_2022); + wb_user_core_read_check(32'h30020060,read_data,32'h0003_3000); end
diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v index 07e2bf9..826774d 100644 --- a/verilog/dv/user_i2cm/user_i2cm_tb.v +++ b/verilog/dv/user_i2cm/user_i2cm_tb.v
@@ -355,21 +355,21 @@ // ---------------------------------------------------- wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_csb = io_out[28]; // Creating Pad Delay - wire #1 io_oeb_26 = io_oeb[26]; - wire #1 io_oeb_27 = io_oeb[27]; - wire #1 io_oeb_28 = io_oeb[28]; wire #1 io_oeb_29 = io_oeb[29]; - tri flash_io0 = (io_oeb_26== 1'b0) ? io_out[26] : 1'bz; - tri flash_io1 = (io_oeb_27== 1'b0) ? io_out[27] : 1'bz; - tri flash_io2 = (io_oeb_28== 1'b0) ? io_out[28] : 1'bz; - tri flash_io3 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + wire #1 io_oeb_30 = io_oeb[30]; + wire #1 io_oeb_31 = io_oeb[31]; + wire #1 io_oeb_32 = io_oeb[32]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; - assign io_in[26] = flash_io0; - assign io_in[27] = flash_io1; - assign io_in[28] = flash_io2; - assign io_in[29] = flash_io3; + assign io_in[29] = flash_io0; + assign io_in[30] = flash_io1; + assign io_in[31] = flash_io2; + assign io_in[32] = flash_io3; // Quard flash
diff --git a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v index 076c60a..c570e18 100644 --- a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v +++ b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
@@ -851,80 +851,80 @@ repeat (1) @(posedge clock); #1; - if(u_top.u_mbist.u_sram0_2kb.web0 == 1'b0 && - ((num_fault[0] > 0 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[0]) || - (num_fault[0] > 1 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[1]) || - (num_fault[0] > 2 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[2]) || - (num_fault[0] > 3 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[3]) || - (num_fault[0] > 4 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[4]) || - (num_fault[0] > 5 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[5]) || - (num_fault[0] > 6 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[6]) || - (num_fault[0] > 7 && u_top.u_mbist.u_sram0_2kb.addr0 == faultaddr[7]))) + if(u_top.u_sram0_2kb.web0 == 1'b0 && + ((num_fault[0] > 0 && u_top.u_sram0_2kb.addr0 == faultaddr[0]) || + (num_fault[0] > 1 && u_top.u_sram0_2kb.addr0 == faultaddr[1]) || + (num_fault[0] > 2 && u_top.u_sram0_2kb.addr0 == faultaddr[2]) || + (num_fault[0] > 3 && u_top.u_sram0_2kb.addr0 == faultaddr[3]) || + (num_fault[0] > 4 && u_top.u_sram0_2kb.addr0 == faultaddr[4]) || + (num_fault[0] > 5 && u_top.u_sram0_2kb.addr0 == faultaddr[5]) || + (num_fault[0] > 6 && u_top.u_sram0_2kb.addr0 == faultaddr[6]) || + (num_fault[0] > 7 && u_top.u_sram0_2kb.addr0 == faultaddr[7]))) begin if(fault_type == 0) // Struck at 0 - force u_top.u_mbist.u_sram0_2kb.din0 = u_top.u_mbist.mem0_din_a & 32'hFFFF_FFFE; + force u_top.u_sram0_2kb.din0 = u_top.mem0_din_a & 32'hFFFF_FFFE; else - force u_top.u_mbist.u_sram0_2kb.din0 = u_top.u_mbist.mem0_din_a | 32'h1; + force u_top.u_sram0_2kb.din0 = u_top.mem0_din_a | 32'h1; -> error_insert; end else begin - release u_top.u_mbist.u_sram0_2kb.din0; + release u_top.u_sram0_2kb.din0; end - if(u_top.u_mbist.u_sram1_2kb.web0 == 1'b0 && - ((num_fault[1] > 0 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[0]+1) || - (num_fault[1] > 1 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[1]+1) || - (num_fault[1] > 2 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[2]+1) || - (num_fault[1] > 3 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[3]+1) || - (num_fault[1] > 4 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[4]+1) || - (num_fault[1] > 5 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[5]+1) || - (num_fault[1] > 6 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[6]+1) || - (num_fault[1] > 7 && u_top.u_mbist.u_sram1_2kb.addr0 == faultaddr[7]+1))) + if(u_top.u_sram1_2kb.web0 == 1'b0 && + ((num_fault[1] > 0 && u_top.u_sram1_2kb.addr0 == faultaddr[0]+1) || + (num_fault[1] > 1 && u_top.u_sram1_2kb.addr0 == faultaddr[1]+1) || + (num_fault[1] > 2 && u_top.u_sram1_2kb.addr0 == faultaddr[2]+1) || + (num_fault[1] > 3 && u_top.u_sram1_2kb.addr0 == faultaddr[3]+1) || + (num_fault[1] > 4 && u_top.u_sram1_2kb.addr0 == faultaddr[4]+1) || + (num_fault[1] > 5 && u_top.u_sram1_2kb.addr0 == faultaddr[5]+1) || + (num_fault[1] > 6 && u_top.u_sram1_2kb.addr0 == faultaddr[6]+1) || + (num_fault[1] > 7 && u_top.u_sram1_2kb.addr0 == faultaddr[7]+1))) begin if(fault_type == 0) // Struck at 0 - force u_top.u_mbist.u_sram1_2kb.din0 = u_top.u_mbist.mem1_din_a & 32'hFFFF_FFFE; + force u_top.u_sram1_2kb.din0 = u_top.mem1_din_a & 32'hFFFF_FFFE; else - force u_top.u_mbist.u_sram1_2kb.din0 = u_top.u_mbist.mem1_din_a | 32'h1; + force u_top.u_sram1_2kb.din0 = u_top.mem1_din_a | 32'h1; -> error_insert; end else begin - release u_top.u_mbist.u_sram1_2kb.din0; + release u_top.u_sram1_2kb.din0; end - if(u_top.u_mbist.u_sram2_2kb.web0 == 1'b0 && - ((num_fault[2] > 0 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[0]+2) || - (num_fault[2] > 1 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[1]+2) || - (num_fault[2] > 2 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[2]+2) || - (num_fault[2] > 3 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[3]+2) || - (num_fault[2] > 4 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[4]+2) || - (num_fault[2] > 5 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[5]+2) || - (num_fault[2] > 6 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[6]+2) || - (num_fault[2] > 7 && u_top.u_mbist.u_sram2_2kb.addr0 == faultaddr[7]+2))) + if(u_top.u_sram2_2kb.web0 == 1'b0 && + ((num_fault[2] > 0 && u_top.u_sram2_2kb.addr0 == faultaddr[0]+2) || + (num_fault[2] > 1 && u_top.u_sram2_2kb.addr0 == faultaddr[1]+2) || + (num_fault[2] > 2 && u_top.u_sram2_2kb.addr0 == faultaddr[2]+2) || + (num_fault[2] > 3 && u_top.u_sram2_2kb.addr0 == faultaddr[3]+2) || + (num_fault[2] > 4 && u_top.u_sram2_2kb.addr0 == faultaddr[4]+2) || + (num_fault[2] > 5 && u_top.u_sram2_2kb.addr0 == faultaddr[5]+2) || + (num_fault[2] > 6 && u_top.u_sram2_2kb.addr0 == faultaddr[6]+2) || + (num_fault[2] > 7 && u_top.u_sram2_2kb.addr0 == faultaddr[7]+2))) begin if(fault_type == 0) // Struck at 0 - force u_top.u_mbist.u_sram2_2kb.din0 = u_top.u_mbist.mem2_din_a & 32'hFFFF_FFFE; + force u_top.u_sram2_2kb.din0 = u_top.mem2_din_a & 32'hFFFF_FFFE; else - force u_top.u_mbist.u_sram2_2kb.din0 = u_top.u_mbist.mem2_din_a | 32'h1; + force u_top.u_sram2_2kb.din0 = u_top.mem2_din_a | 32'h1; -> error_insert; end else begin - release u_top.u_mbist.u_sram2_2kb.din0; + release u_top.u_sram2_2kb.din0; end - if(u_top.u_mbist.u_sram3_2kb.web0 == 1'b0 && - ((num_fault[3] > 0 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[0]+3) || - (num_fault[3] > 1 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[1]+3) || - (num_fault[3] > 2 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[2]+3) || - (num_fault[3] > 3 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[3]+3) || - (num_fault[3] > 4 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[4]+3) || - (num_fault[3] > 5 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[5]+3) || - (num_fault[3] > 6 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[6]+3) || - (num_fault[3] > 7 && u_top.u_mbist.u_sram3_2kb.addr0 == faultaddr[7]+3))) + if(u_top.u_sram3_2kb.web0 == 1'b0 && + ((num_fault[3] > 0 && u_top.u_sram3_2kb.addr0 == faultaddr[0]+3) || + (num_fault[3] > 1 && u_top.u_sram3_2kb.addr0 == faultaddr[1]+3) || + (num_fault[3] > 2 && u_top.u_sram3_2kb.addr0 == faultaddr[2]+3) || + (num_fault[3] > 3 && u_top.u_sram3_2kb.addr0 == faultaddr[3]+3) || + (num_fault[3] > 4 && u_top.u_sram3_2kb.addr0 == faultaddr[4]+3) || + (num_fault[3] > 5 && u_top.u_sram3_2kb.addr0 == faultaddr[5]+3) || + (num_fault[3] > 6 && u_top.u_sram3_2kb.addr0 == faultaddr[6]+3) || + (num_fault[3] > 7 && u_top.u_sram3_2kb.addr0 == faultaddr[7]+3))) begin if(fault_type == 0) // Struck at 0 - force u_top.u_mbist.u_sram3_2kb.din0 = u_top.u_mbist.mem3_din_a & 32'hFFFF_FFFE; + force u_top.u_sram3_2kb.din0 = u_top.mem3_din_a & 32'hFFFF_FFFE; else - force u_top.u_mbist.u_sram3_2kb.din0 = u_top.u_mbist.mem3_din_a | 32'h1; + force u_top.u_sram3_2kb.din0 = u_top.mem3_din_a | 32'h1; -> error_insert; end else begin - release u_top.u_mbist.u_sram3_2kb.din0; + release u_top.u_sram3_2kb.din0; end //if(u_top.u_sram5_1kb.web0 == 1'b0 &&
diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v index ab96410..fff2408 100644 --- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v +++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
@@ -257,22 +257,21 @@ // ---------------------------------------------------- wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_csb = io_out[28]; // Creating Pad Delay - wire #1 io_oeb_26 = io_oeb[26]; - wire #1 io_oeb_27 = io_oeb[27]; - wire #1 io_oeb_28 = io_oeb[28]; wire #1 io_oeb_29 = io_oeb[29]; - tri flash_io0 = (io_oeb_26== 1'b0) ? io_out[26] : 1'bz; - tri flash_io1 = (io_oeb_27== 1'b0) ? io_out[27] : 1'bz; - tri flash_io2 = (io_oeb_28== 1'b0) ? io_out[28] : 1'bz; - tri flash_io3 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + wire #1 io_oeb_30 = io_oeb[30]; + wire #1 io_oeb_31 = io_oeb[31]; + wire #1 io_oeb_32 = io_oeb[32]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; - assign io_in[26] = flash_io0; - assign io_in[27] = flash_io1; - assign io_in[28] = flash_io2; - assign io_in[29] = flash_io3; - + assign io_in[29] = flash_io0; + assign io_in[30] = flash_io1; + assign io_in[31] = flash_io2; + assign io_in[32] = flash_io3; // Quard flash s25fl256s #(.mem_file_name("user_risc_boot.hex"),
diff --git a/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v b/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v index 1350b07..32a28b8 100644 --- a/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v +++ b/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v
@@ -156,13 +156,13 @@ tem_mem_32b[i] = {tem_mem[(i*4)+3],tem_mem[(i*4)+2],tem_mem[(i*4)+1],tem_mem[(i*4)]}; $writememh("sram_bank0.hex",tem_mem_32b,0,511); - $readmemh("sram_bank0.hex",u_top.u_mbist.u_sram0_2kb.mem,0,511); + $readmemh("sram_bank0.hex",u_top.u_sram0_2kb.mem,0,511); for(i =512; i < 1023; i = i+1) tem_mem_32b[i-512] = {tem_mem[(i*4)+3],tem_mem[(i*4)+2],tem_mem[(i*4)+1],tem_mem[(i*4)]}; $writememh("sram_bank1.hex",tem_mem_32b,0,511); - $readmemh("sram_bank1.hex",u_top.u_mbist.u_sram1_2kb.mem,0,511); + $readmemh("sram_bank1.hex",u_top.u_sram1_2kb.mem,0,511); // Enable the SRAM Remap to boot region wb_user_core_write('h3080_000C,{4'b1111,28'h0});
diff --git a/verilog/dv/user_spi/user_spi_tb.v b/verilog/dv/user_spi/user_spi_tb.v index 486d6ea..d16bfa8 100644 --- a/verilog/dv/user_spi/user_spi_tb.v +++ b/verilog/dv/user_spi/user_spi_tb.v
@@ -82,21 +82,24 @@ `include "s25fl256s.sv" `include "uprj_netlists.v" `include "mt48lc8m8a2.v" +`include "spiram.v" // REGISTER MAP - `define QSPIM_GLBL_CTRL 32'h10000000 - `define QSPIM_DMEM_CTRL1 32'h10000004 - `define QSPIM_DMEM_CTRL2 32'h10000008 + `define QSPIM_GLBL_CTRL 32'h10000000 + `define QSPIM_DMEM_G0_RD_CTRL 32'h10000004 + `define QSPIM_DMEM_G0_WR_CTRL 32'h10000008 + `define QSPIM_DMEM_G1_RD_CTRL 32'h1000000C + `define QSPIM_DMEM_G1_WR_CTRL 32'h10000010 - `define QSPIM_DMEM_CS_AMAP 32'h1000000C - `define QSPIM_DMEM_CA_AMASK 32'h10000010 + `define QSPIM_DMEM_CS_AMAP 32'h10000014 + `define QSPIM_DMEM_CA_AMASK 32'h10000018 - `define QSPIM_IMEM_CTRL1 32'h10000014 - `define QSPIM_IMEM_CTRL2 32'h10000018 - `define QSPIM_IMEM_ADDR 32'h1000001C - `define QSPIM_IMEM_WDATA 32'h10000020 - `define QSPIM_IMEM_RDATA 32'h10000024 - `define QSPIM_SPI_STATUS 32'h10000028 + `define QSPIM_IMEM_CTRL1 32'h1000001C + `define QSPIM_IMEM_CTRL2 32'h10000020 + `define QSPIM_IMEM_ADDR 32'h10000024 + `define QSPIM_IMEM_WDATA 32'h10000028 + `define QSPIM_IMEM_RDATA 32'h1000002C + `define QSPIM_SPI_STATUS 32'h10000030 module user_spi_tb; reg clock; @@ -226,6 +229,78 @@ test_fail = 0; repeat (200) @(posedge clock); + wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 + // CS#2 SSPI Indirect RAM READ ACCESS- + wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); + wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h4,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03}); + wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h03020100); + wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000004); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h07060504); + wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000008); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0b0a0908); + wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000000C); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h0f0e0d0c); + + wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000200); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h11111111); + wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000204); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h22222222); + wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000208); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h33333333); + wb_user_core_write(`QSPIM_IMEM_ADDR,32'h0000020C); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h44444444); + + // CS#2 SSPI Indiect Write DATA + wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); + wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02}); + wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000); + wb_user_core_write(`QSPIM_IMEM_WDATA,32'h00112233); + wb_user_core_write(`QSPIM_IMEM_WDATA,32'h44556677); + wb_user_core_write(`QSPIM_IMEM_WDATA,32'h8899AABB); + wb_user_core_write(`QSPIM_IMEM_WDATA,32'hCCDDEEFF); + + // CS#2 SSPI Indirect READ DATA + wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); + wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03}); + wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h00112233); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h44556677); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h8899AABB); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'hCCDDEEFF); + + + // CS#2 Switch to QSPI Mode + wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0100}); + wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'h38}); + wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0); + + + // CS#2 QUAD Indirect Write DATA + wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100}); + wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CAW,8'h00,8'h02}); + wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000); + wb_user_core_write(`QSPIM_IMEM_WDATA,32'h01234557); + wb_user_core_write(`QSPIM_IMEM_WDATA,32'h89ABCDEF); + wb_user_core_write(`QSPIM_IMEM_WDATA,32'h12345678); + wb_user_core_write(`QSPIM_IMEM_WDATA,32'h9ABCDEF0); + + + // CS#2 QUAD Indirect READ DATA + wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100}); + wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h10,2'b00,2'b10,P_FSM_CADR,8'h00,8'h03}); + wb_user_core_write(`QSPIM_IMEM_ADDR,32'h00000000); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h01234557); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h89ABCDEF); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h12345678); + wb_user_core_read_check(`QSPIM_IMEM_RDATA,read_data,32'h9ABCDEF0); + + // CS#2 Switch From QSPI to SSPI Mode + wb_user_core_write(`QSPIM_IMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_QUAD,P_QUAD,4'b0100}); + wb_user_core_write(`QSPIM_IMEM_CTRL2,{8'h0,2'b00,2'b00,P_FSM_C,8'h00,8'hFF}); + wb_user_core_write(`QSPIM_IMEM_WDATA,32'h0); + ///////////////////// End of CS#1 Indirect Memory Access Testing /////////////////////////////////// + $display("#############################################"); $display(" Read Identification (RDID:0x9F) "); $display("#############################################"); @@ -241,8 +316,7 @@ $display("#############################################"); // QDDR Config wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0100,P_MODE_SWITCH_AT_ADDR,P_QDDR,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_DMEM_CTRL2,{8'h04,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hED}); + wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0100,2'b10,P_MODE_SWITCH_AT_ADDR,P_QDDR,P_SINGLE,8'h00,8'hED}); wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 wb_user_core_read_check(32'h00000200,read_data,32'h00000093); wb_user_core_read_check(32'h00000204,read_data,32'h00000113); @@ -268,8 +342,7 @@ $display("SEQ: Command -> Address -> Read Data "); $display("#############################################"); wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_DMEM_CTRL2,{8'h04,2'b00,2'b10,P_FSM_CAR,8'h00,8'h03}); + wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAR,4'b0000,2'b10,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,8'h00,8'h03}); wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 wb_user_core_read_check(32'h00000200,read_data,32'h00000093); wb_user_core_read_check(32'h00000204,read_data,32'h00000113); @@ -294,8 +367,7 @@ $display("SEQ: Command -> Address -> Dummy -> Read Data"); $display("#############################################"); wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_DMEM_CTRL2,{8'h04,2'b00,2'b10,P_FSM_CADR,8'h00,8'h0B}); + wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CADR,4'b0000,2'b10,P_MODE_SWITCH_IDLE,P_SINGLE,P_SINGLE,8'h00,8'h0B}); wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 wb_user_core_read_check(32'h00000200,read_data,32'h00000093); wb_user_core_read_check(32'h00000204,read_data,32'h00000113); @@ -321,8 +393,7 @@ $display("SEQ: Command -> Address -> Dummy -> Read Data"); $display("#############################################"); wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0000,P_MODE_SWITCH_AT_DATA,P_DOUBLE,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_DMEM_CTRL2,{8'h04,2'b00,2'b10,P_FSM_CADR,8'h00,8'h3B}); + wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CADR,4'b0000,2'b10,P_MODE_SWITCH_AT_DATA,P_DOUBLE,P_SINGLE,8'h00,8'h3B}); wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 wb_user_core_read_check(32'h00000200,read_data,32'h00000093); wb_user_core_read_check(32'h00000204,read_data,32'h00000113); @@ -348,8 +419,7 @@ $display("SEQ: Command -> Address -> Dummy -> Read Data"); $display("#############################################"); wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_DMEM_CTRL2,{8'h20,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); + wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 wb_user_core_read_check(32'h00000200,read_data,32'h00000093); wb_user_core_read_check(32'h00000204,read_data,32'h00000113); @@ -372,8 +442,7 @@ $display("Testing Direct SPI Memory Read with Prefetch:3DW"); $display("#############################################"); wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_DMEM_CTRL2,{8'hC,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); + wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 wb_user_core_read_check(32'h00000200,read_data,32'h00000093); wb_user_core_read_check(32'h00000204,read_data,32'h00000113); @@ -396,8 +465,7 @@ $display("Testing Direct SPI Memory Read with Prefetch:2DW"); $display("#############################################"); wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_DMEM_CTRL2,{8'h8,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); + wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 wb_user_core_read_check(32'h00000200,read_data,32'h00000093); wb_user_core_read_check(32'h00000204,read_data,32'h00000113); @@ -421,8 +489,7 @@ $display("Testing Direct SPI Memory Read with Prefetch:1DW"); $display("#############################################"); wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_DMEM_CTRL2,{8'h4,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); + wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 wb_user_core_read_check(32'h00000200,read_data,32'h00000093); wb_user_core_read_check(32'h00000204,read_data,32'h00000113); @@ -445,8 +512,7 @@ $display("Testing Direct SPI Memory Read with Prefetch:7DW"); $display("#############################################"); wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10 - wb_user_core_write(`QSPIM_DMEM_CTRL1,{16'h0,1'b0,1'b0,4'b0001,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,4'b0001}); - wb_user_core_write(`QSPIM_DMEM_CTRL2,{8'h1C,2'b00,2'b10,P_FSM_CAMDR,8'h00,8'hEB}); + wb_user_core_write(`QSPIM_DMEM_G0_RD_CTRL,{P_FSM_CAMDR,4'b0001,2'b10,P_MODE_SWITCH_AT_ADDR,P_QUAD,P_SINGLE,8'h00,8'hEB}); wb_user_core_write('h3080_0004,'h00); // Change the Bank Sel 00 wb_user_core_read_check(32'h00000200,read_data,32'h00000093); wb_user_core_read_check(32'h00000204,read_data,32'h00000113); @@ -1161,21 +1227,21 @@ // ---------------------------------------------------- wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_csb = io_out[28]; // Creating Pad Delay - wire #1 io_oeb_26 = io_oeb[26]; - wire #1 io_oeb_27 = io_oeb[27]; - wire #1 io_oeb_28 = io_oeb[28]; wire #1 io_oeb_29 = io_oeb[29]; - tri #1 flash_io0 = (io_oeb_26== 1'b0) ? io_out[26] : 1'bz; - tri #1 flash_io1 = (io_oeb_27== 1'b0) ? io_out[27] : 1'bz; - tri #1 flash_io2 = (io_oeb_28== 1'b0) ? io_out[28] : 1'bz; - tri #1 flash_io3 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + wire #1 io_oeb_30 = io_oeb[30]; + wire #1 io_oeb_31 = io_oeb[31]; + wire #1 io_oeb_32 = io_oeb[32]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; - assign io_in[26] = flash_io0; - assign io_in[27] = flash_io1; - assign io_in[28] = flash_io2; - assign io_in[29] = flash_io3; + assign io_in[29] = flash_io0; + assign io_in[30] = flash_io1; + assign io_in[31] = flash_io2; + assign io_in[32] = flash_io3; // Quad flash @@ -1195,7 +1261,19 @@ ); + wire spiram_csb = io_out[26]; + spiram #(.mem_file_name("flash1.hex")) + u_sfram ( + // Data Inputs/Outputs + .io0 (flash_io0), + .io1 (flash_io1), + // Controls + .clk (flash_clk), + .csb (spiram_csb), + .io2 (flash_io2), + .io3 (flash_io3) + ); task wb_user_core_write;
diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v index 7171ba6..6c7f255 100644 --- a/verilog/dv/user_uart/user_uart_tb.v +++ b/verilog/dv/user_uart/user_uart_tb.v
@@ -300,21 +300,21 @@ // ---------------------------------------------------- wire flash_clk = io_out[24]; - wire flash_csb = io_out[25]; + wire flash_csb = io_out[28]; // Creating Pad Delay - wire #1 io_oeb_26 = io_oeb[26]; - wire #1 io_oeb_27 = io_oeb[27]; - wire #1 io_oeb_28 = io_oeb[28]; wire #1 io_oeb_29 = io_oeb[29]; - tri flash_io0 = (io_oeb_26== 1'b0) ? io_out[26] : 1'bz; - tri flash_io1 = (io_oeb_27== 1'b0) ? io_out[27] : 1'bz; - tri flash_io2 = (io_oeb_28== 1'b0) ? io_out[28] : 1'bz; - tri flash_io3 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + wire #1 io_oeb_30 = io_oeb[30]; + wire #1 io_oeb_31 = io_oeb[31]; + wire #1 io_oeb_32 = io_oeb[32]; + tri #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz; + tri #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz; + tri #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz; + tri #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz; - assign io_in[26] = flash_io0; - assign io_in[27] = flash_io1; - assign io_in[28] = flash_io2; - assign io_in[29] = flash_io3; + assign io_in[29] = flash_io0; + assign io_in[30] = flash_io1; + assign io_in[31] = flash_io2; + assign io_in[32] = flash_io3; // Quard flash @@ -336,8 +336,6 @@ ); - - //--------------------------- // UART Agent integration // --------------------------
diff --git a/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv b/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv index 77e50d4..07c5ce3 100644 --- a/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv +++ b/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv
@@ -143,6 +143,14 @@ parameter NO_SRAM_WD = (BIST_NO_SRAM+1)/2; parameter BIST1_ADDR_WD = 11; // 512x32 SRAM +logic mem_req; // strobe/request +logic [(BIST_NO_SRAM+1)/2-1:0] mem_cs; +logic [BIST_ADDR_WD-1:0] mem_addr; // address +logic mem_we ; // write +logic [BIST_DATA_WD-1:0] mem_wdata; // data output +logic [BIST_DATA_WD/8-1:0] mem_wmask; // byte enable +logic [BIST_DATA_WD-1:0] mem_rdata; // data input + mbist_wb #( .BIST_NO_SRAM (4 ), @@ -241,32 +249,32 @@ // towards memory // PORT-A - .mem_clk_a (mem_clk_a ), - .mem_addr_a0 (mem0_addr_a ), - .mem_addr_a1 (mem1_addr_a ), - .mem_addr_a2 (mem2_addr_a ), - .mem_addr_a3 (mem3_addr_a ), - .mem_cen_a (mem_cen_a ), - .mem_web_a (mem_web_a ), - .mem_mask_a0 (mem0_mask_a ), - .mem_mask_a1 (mem1_mask_a ), - .mem_mask_a2 (mem2_mask_a ), - .mem_mask_a3 (mem3_mask_a ), - .mem_din_a0 (mem0_din_a ), - .mem_din_a1 (mem1_din_a ), - .mem_din_a2 (mem2_din_a ), - .mem_din_a3 (mem3_din_a ), - .mem_dout_a0 (mem0_dout_a ), - .mem_dout_a1 (mem1_dout_a ), - .mem_dout_a2 (mem2_dout_a ), - .mem_dout_a3 (mem3_dout_a ), + .mem_clk_a (mem_clk_a ), + .mem_addr_a0 (mem_addr_a0 ), + .mem_addr_a1 (mem_addr_a1 ), + .mem_addr_a2 (mem_addr_a2 ), + .mem_addr_a3 (mem_addr_a3 ), + .mem_cen_a (mem_cen_a ), + .mem_web_a (mem_web_a ), + .mem_mask_a0 (mem_mask_a0 ), + .mem_mask_a1 (mem_mask_a1 ), + .mem_mask_a2 (mem_mask_a2 ), + .mem_mask_a3 (mem_mask_a3 ), + .mem_din_a0 (mem_din_a0 ), + .mem_din_a1 (mem_din_a1 ), + .mem_din_a2 (mem_din_a2 ), + .mem_din_a3 (mem_din_a3 ), + .mem_dout_a0 (mem_dout_a0 ), + .mem_dout_a1 (mem_dout_a1 ), + .mem_dout_a2 (mem_dout_a2 ), + .mem_dout_a3 (mem_dout_a3 ), // PORT-B - .mem_clk_b (mem_clk_b ), - .mem_cen_b (mem_cen_b ), - .mem_addr_b0 (mem0_addr_b ), - .mem_addr_b1 (mem1_addr_b ), - .mem_addr_b2 (mem2_addr_b ), - .mem_addr_b3 (mem3_addr_b ) + .mem_clk_b (mem_clk_b ), + .mem_cen_b (mem_cen_b ), + .mem_addr_b0 (mem_addr_b0 ), + .mem_addr_b1 (mem_addr_b1 ), + .mem_addr_b2 (mem_addr_b2 ), + .mem_addr_b3 (mem_addr_b3 ) );
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index 12d5625..46a69a4 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -76,7 +76,7 @@ // SFLASH I/F input logic sflash_sck, - input logic sflash_ss, + input logic [3:0] sflash_ss, input logic [3:0] sflash_oen, input logic [3:0] sflash_do, output logic [3:0] sflash_di, @@ -446,14 +446,14 @@ * * Additional Pad used for Externam ROM/RAM * sflash_sck digital_io[24] -* sflash_ss digital_io[25] -* sflash_io0 digital_io[26] -* sflash_io1 digital_io[27] -* sflash_io2 digital_io[28] -* sflash_io3 digital_io[29] -* reserved digital_io[30] -* reserved digital_io[31] -* reserved digital_io[32] +* sflash_ss[3] digital_io[25] +* sflash_ss[2] digital_io[26] +* sflash_ss[1] digital_io[27] +* sflash_ss[0] digital_io[28] +* sflash_io0 digital_io[29] +* sflash_io1 digital_io[30] +* sflash_io2 digital_io[31] +* sflash_io3 digital_io[32] * reserved digital_io[33] * uartm_rxd digital_io[34] * uartm_txd digital_io[35] @@ -563,10 +563,10 @@ port_c_in[5] = digital_io_in[23]; if(cfg_i2cm_enb) i2cm_clk_i = digital_io_in[23]; - sflash_di[0] = digital_io_in[26]; - sflash_di[1] = digital_io_in[27]; - sflash_di[2] = digital_io_in[28]; - sflash_di[3] = digital_io_in[29]; + sflash_di[0] = digital_io_in[29]; + sflash_di[1] = digital_io_in[30]; + sflash_di[2] = digital_io_in[31]; + sflash_di[3] = digital_io_in[32]; // UAR MASTER I/F uartm_rxd = digital_io_in[34]; @@ -664,16 +664,16 @@ // Serial Flash digital_io_out[24] = sflash_sck ; - digital_io_out[25] = sflash_ss ; - digital_io_out[26] = sflash_do[0] ; - digital_io_out[27] = sflash_do[1] ; - digital_io_out[28] = sflash_do[2] ; - digital_io_out[29] = sflash_do[3] ; + digital_io_out[25] = sflash_ss[3] ; + digital_io_out[26] = sflash_ss[2] ; + digital_io_out[27] = sflash_ss[1] ; + digital_io_out[28] = sflash_ss[0] ; + digital_io_out[29] = sflash_do[0] ; + digital_io_out[30] = sflash_do[1] ; + digital_io_out[31] = sflash_do[2] ; + digital_io_out[32] = sflash_do[3] ; // Reserved - digital_io_out[30] = 1'b0; - digital_io_out[31] = 1'b0; - digital_io_out[32] = 1'b0; digital_io_out[33] = 1'b0; // UART MASTER I/f @@ -776,15 +776,15 @@ // Serial Flash digital_io_oen[24] = 1'b0 ; digital_io_oen[25] = 1'b0 ; - digital_io_oen[26] = sflash_oen[0]; - digital_io_oen[27] = sflash_oen[1]; - digital_io_oen[28] = sflash_oen[2]; - digital_io_oen[29] = sflash_oen[3]; + digital_io_oen[26] = 1'b0 ; + digital_io_oen[27] = 1'b0 ; + digital_io_oen[28] = 1'b0 ; + digital_io_oen[29] = sflash_oen[0]; + digital_io_oen[30] = sflash_oen[1]; + digital_io_oen[31] = sflash_oen[2]; + digital_io_oen[32] = sflash_oen[3]; // Reserved - digital_io_oen[30] = 1'b0 ; - digital_io_oen[31] = 1'b0 ; - digital_io_oen[32] = 1'b0 ; digital_io_oen[33] = 1'b0 ; // UART MASTER digital_io_oen[34] = 1'b1; // RXD
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv index c59c28f..f854dae 100644 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -721,7 +721,7 @@ //----------------------------------------- // Software Reg-2, Release date: <DAY><MONTH><YEAR> // ---------------------------------------- -gen_32b_reg #(32'h0202_2022) u_reg_23 ( +gen_32b_reg #(32'h0802_2022) u_reg_23 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -734,9 +734,9 @@ ); //----------------------------------------- -// Software Reg-3: Poject Revison 3.2 = 0003200 +// Software Reg-3: Poject Revison 3.3 = 0003300 // ---------------------------------------- -gen_32b_reg #(32'h0003_2000) u_reg_24 ( +gen_32b_reg #(32'h0003_3000) u_reg_24 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ),
diff --git a/verilog/rtl/qspim b/verilog/rtl/qspim index 50b382d..644fc5e 160000 --- a/verilog/rtl/qspim +++ b/verilog/rtl/qspim
@@ -1 +1 @@ -Subproject commit 50b382d05288f8b0d59c8c9e575719d4f3f00911 +Subproject commit 644fc5e86bf08279ed257519456199e85d9584f9
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index 3e91285..865063a 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -156,6 +156,11 @@ //// 3.2 Feb 02, 2022, Dinesh A //// //// Bug fix around icache/dcache and wishbone burst //// //// access clean-up //// +//// 3.3 Feb 08, 2022, Dinesh A //// +//// support added spisram support in qspim ip //// +//// There are 4 chip select available in qspim //// +//// CS#0/CS#1 targeted for SPI FLASH //// +//// CS#2/CS#3 targeted for SPI SRAM //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -481,7 +486,7 @@ // SFLASH I/F wire sflash_sck ; -wire sflash_ss ; +wire [3:0] sflash_ss ; wire [3:0] sflash_oen ; wire [3:0] sflash_do ; wire [3:0] sflash_di ;