strap design database update
diff --git a/openlane/pinmux_top/config.tcl b/openlane/pinmux_top/config.tcl index 0be5bbd..aec92b4 100755 --- a/openlane/pinmux_top/config.tcl +++ b/openlane/pinmux_top/config.tcl
@@ -58,14 +58,18 @@ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/ws281x_top.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/ws281x_driver.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/ws281x_reg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/strap_ctrl.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/glbl_rst_reg.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type1.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type2.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_fifo.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_ctl.v \ " +set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/ ] set ::env(SYNTH_DEFINES) [list SYNTHESIS ] set ::env(SYNTH_READ_BLACKBOX_LIB) 1 @@ -94,13 +98,20 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.40" +set ::env(PL_TARGET_DENSITY) "0.38" set ::env(CELL_PAD) "4" -set ::env(GRT_ADJUSTMENT) {0.2} +#set ::env(GRT_ADJUSTMENT) {0.2} -set ::env(FP_IO_VEXTEND) {6} -set ::env(FP_IO_HEXTEND) {6} +###################################################################################### +# Metal-2/3 Signal are Routed near to block boundary is creating DRC violation at Top-level +# during pad connectivity + +#set ::env(GRT_OBS) " \ +# met2 0 2 500 3, \ +# met2 0 747 500 748, \ +# met3 2 0 3 750, \ +# met3 497 0 498 750" # helps in anteena fix @@ -111,8 +122,8 @@ set ::env(FP_PDN_VPITCH) 100 set ::env(FP_PDN_HPITCH) 100 -set ::env(FP_PDN_VWIDTH) 5 -set ::env(FP_PDN_HWIDTH) 5 +set ::env(FP_PDN_VWIDTH) 6.2 +set ::env(FP_PDN_HWIDTH) 6.2 #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} @@ -121,6 +132,10 @@ set ::env(DIODE_INSERTION_STRATEGY) 4 +#LVS Issue - DEF Base looks to having issue +set ::env(MAGIC_EXT_USE_GDS) {1} + + set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" set ::env(QUIT_ON_MAGIC_DRC) "1" set ::env(QUIT_ON_LVS_ERROR) "1"
diff --git a/openlane/pinmux_top/pin_order.cfg b/openlane/pinmux_top/pin_order.cfg index bbb7284..724e4f3 100644 --- a/openlane/pinmux_top/pin_order.cfg +++ b/openlane/pinmux_top/pin_order.cfg
@@ -2,8 +2,7 @@ #MANUAL_PLACE #S -h_reset_n 000 0 2 -cpu_core_rst_n\[1\] +cpu_core_rst_n\[1\] 000 0 2 cpu_core_rst_n\[0\] cpu_intf_rst_n qspim_rst_n @@ -63,7 +62,82 @@ spis_miso spis_mosi -pinmux_debug\[0\] 0100 0 2 +cfg_strap_pad_ctrl 0100 0 4 +user_clock1 +user_clock2 +int_pll_clock +xtal_clk +e_reset_n +p_reset_n +s_reset_n +rtc_clk +usb_clk +strap_sticky\[31\] +strap_sticky\[30\] +strap_sticky\[29\] +strap_sticky\[28\] +strap_sticky\[27\] +strap_sticky\[26\] +strap_sticky\[25\] +strap_sticky\[24\] +strap_sticky\[23\] +strap_sticky\[22\] +strap_sticky\[21\] +strap_sticky\[20\] +strap_sticky\[19\] +strap_sticky\[18\] +strap_sticky\[17\] +strap_sticky\[16\] +strap_sticky\[15\] +strap_sticky\[14\] +strap_sticky\[13\] +strap_sticky\[12\] +strap_sticky\[11\] +strap_sticky\[10\] +strap_sticky\[9\] +strap_sticky\[8\] +strap_sticky\[7\] +strap_sticky\[6\] +strap_sticky\[5\] +strap_sticky\[4\] +strap_sticky\[3\] +strap_sticky\[2\] +strap_sticky\[1\] +strap_sticky\[0\] +system_strap\[31\] +system_strap\[30\] +system_strap\[29\] +system_strap\[28\] +system_strap\[27\] +system_strap\[26\] +system_strap\[25\] +system_strap\[24\] +system_strap\[23\] +system_strap\[22\] +system_strap\[21\] +system_strap\[20\] +system_strap\[19\] +system_strap\[18\] +system_strap\[17\] +system_strap\[16\] +system_strap\[15\] +system_strap\[14\] +system_strap\[13\] +system_strap\[12\] +system_strap\[11\] +system_strap\[10\] +system_strap\[9\] +system_strap\[8\] +system_strap\[7\] +system_strap\[6\] +system_strap\[5\] +system_strap\[4\] +system_strap\[3\] +system_strap\[2\] +system_strap\[1\] +system_strap\[0\] + +pinmux_debug\[0\] 0300 0 2 pinmux_debug\[1\] pinmux_debug\[2\] pinmux_debug\[3\] @@ -145,6 +219,7 @@ reg_cs 200 0 reg_wr +reg_addr\[9\] reg_addr\[8\] reg_addr\[7\] reg_addr\[6\] @@ -320,7 +395,8 @@ #E -digital_io_in\[0\] 0000 0 4 + +digital_io_in\[0\] 0200 0 4 digital_io_out\[0\] digital_io_oen\[0\] digital_io_in\[1\]
diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl index 0ce98bf..f715632 100755 --- a/openlane/qspim_top/config.tcl +++ b/openlane/qspim_top/config.tcl
@@ -85,13 +85,13 @@ # helps in anteena fix set ::env(USE_ARC_ANTENNA_CHECK) "0" -set ::env(FP_IO_VEXTEND) 4 -set ::env(FP_IO_HEXTEND) 4 +#set ::env(FP_IO_VEXTEND) 4 +#set ::env(FP_IO_HEXTEND) 4 set ::env(FP_PDN_VPITCH) 100 set ::env(FP_PDN_HPITCH) 100 -set ::env(FP_PDN_VWIDTH) 5 -set ::env(FP_PDN_HWIDTH) 5 +set ::env(FP_PDN_VWIDTH) 6.2 +set ::env(FP_PDN_HWIDTH) 6.2 #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4}
diff --git a/openlane/qspim_top/pin_order.cfg b/openlane/qspim_top/pin_order.cfg index a0c3c37..9f93b81 100644 --- a/openlane/qspim_top/pin_order.cfg +++ b/openlane/qspim_top/pin_order.cfg
@@ -53,8 +53,6 @@ spi_oen\[1\] spi_oen\[0\] -#N -rst_n #W cfg_cska_sp_co\[3\] 0000 0 2 @@ -185,3 +183,12 @@ wbd_ack_o wbd_lack_o wbd_err_o + + +#S +rst_n +cfg_init_bypass +strap_sram +strap_pre_sram +strap_flash\[1\] +strap_flash\[0\]
diff --git a/openlane/uart_i2cm_usb_spi_top/base.sdc b/openlane/uart_i2cm_usb_spi_top/base.sdc index 35bba97..3218d29 100644 --- a/openlane/uart_i2cm_usb_spi_top/base.sdc +++ b/openlane/uart_i2cm_usb_spi_top/base.sdc
@@ -60,7 +60,7 @@ set_output_delay -max 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}] set_output_delay -max 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}] -set_output_delay -min -2.7500 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}] +set_output_delay -min 1.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_ack}] set_output_delay -min -2.7500 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_rdata[*]}] set_multicycle_path -setup -from [get_ports {reg_addr[*]}] -to [get_ports {reg_ack}] 2
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl index 39350c5..b317ba7 100644 --- a/openlane/uart_i2cm_usb_spi_top/config.tcl +++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -92,7 +92,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) "absolute" -set ::env(DIE_AREA) [list 0.0 0.0 520.0 725.0] +set ::env(DIE_AREA) [list 0.0 0.0 520.0 800.0] @@ -103,18 +103,18 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.46" +set ::env(PL_TARGET_DENSITY) "0.42" # helps in anteena fix set ::env(USE_ARC_ANTENNA_CHECK) "0" -set ::env(FP_IO_VEXTEND) 4 -set ::env(FP_IO_HEXTEND) 4 +#set ::env(FP_IO_VEXTEND) 4 +#set ::env(FP_IO_HEXTEND) 4 set ::env(FP_PDN_VPITCH) 100 set ::env(FP_PDN_HPITCH) 100 -set ::env(FP_PDN_VWIDTH) 5 -set ::env(FP_PDN_HWIDTH) 5 +set ::env(FP_PDN_VWIDTH) 6.2 +set ::env(FP_PDN_HWIDTH) 6.2 #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} @@ -125,8 +125,8 @@ set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1} #set ::env(GLB_RT_ADJUSTMENT) {0.25} -set ::env(GLB_RT_LAYER_ADJUSTMENTS) {0.25,0,0,0,0,0} -set ::env(CELL_PAD) {2} +set ::env(GRT_LAYER_ADJUSTMENTS) {0.25,0,0,0,0,0} +set ::env(CELL_PAD) {8} set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" set ::env(QUIT_ON_MAGIC_DRC) "1"
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index e33180a..da00168 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -56,7 +56,7 @@ ### Macro Placement set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg -#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn_cfg.tcl +set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn_cfg.tcl set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc @@ -110,17 +110,30 @@ #set ::env(GLB_RT_MAXLAYER) 6 set ::env(RT_MAX_LAYER) {met5} -set ::env(FP_PDN_CHECK_NODES) 0 - - ## Internal Macros ### Macro PDN Connections -set ::env(FP_PDN_ENABLE_MACROS_GRID) "1" -#set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1" +set ::env(FP_PDN_ENABLE_MACROS_GRID) {1} +set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "0" +set ::env(FP_PDN_CHECK_NODES) 1 +set ::env(FP_PDN_ENABLE_RAILS) 0 +set ::env(FP_PDN_IRDROP) "1" +set ::env(FP_PDN_HORIZONTAL_HALO) "10" +set ::env(FP_PDN_VERTICAL_HALO) "10" +set ::env(FP_PDN_VOFFSET) "5" +set ::env(FP_PDN_VPITCH) "60" +set ::env(FP_PDN_HOFFSET) "5" +set ::env(FP_PDN_HPITCH) "60" +set ::env(FP_PDN_HWIDTH) {6.2} +set ::env(FP_PDN_VWIDTH) {6.2} +set ::env(FP_PDN_HSPACING) {20} +set ::env(FP_PDN_VSPACING) {20} + +set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2} +set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2} set ::env(VDD_NET) {vccd1} -set ::env(VDD_PIN) {vccd1} set ::env(GND_NET) {vssd1} +set ::env(VDD_PIN) {vccd1} set ::env(GND_PIN) {vssd1} @@ -128,17 +141,15 @@ li1 150 130 833.1 546.54,\ met1 150 130 833.1 546.54,\ met2 150 130 833.1 546.54,\ - met3 150 130 833.1 546.54,\ - + met3 150 130 833.1 546.54,\ li1 950 130 1633.1 546.54,\ met1 950 130 1633.1 546.54,\ met2 950 130 1633.1 546.54,\ - met3 950 130 1633.1 546.54,\ - - li1 150 750 833.1 1166.54,\ - met1 150 750 833.1 1166.54,\ - met2 150 750 833.1 1166.54,\ - met3 150 750 833.1 1166.54,\ + met3 950 130 1633.1 546.54,\ + li1 150 750 833.1 1166.54,\ + met1 150 750 833.1 1166.54,\ + met2 150 750 833.1 1166.54,\ + met3 150 750 833.1 1166.54,\ met5 0 0 2920 3520" #set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 1, vdda2 vssa2 1" @@ -167,7 +178,6 @@ set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0 set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0 set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0 -set ::env(FP_PDN_ENABLE_RAILS) 0 set ::env(DIODE_INSERTION_STRATEGY) 0 set ::env(FILL_INSERTION) 0 set ::env(TAP_DECAP_INSERTION) 0 @@ -178,14 +188,4 @@ set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" -set ::env(FP_PDN_IRDROP) "1" -set ::env(FP_PDN_HORIZONTAL_HALO) "10" -set ::env(FP_PDN_VERTICAL_HALO) "10" - -# - -set ::env(FP_PDN_VOFFSET) "5" -set ::env(FP_PDN_VPITCH) "180" -set ::env(FP_PDN_HOFFSET) "5" -set ::env(FP_PDN_HPITCH) "180"
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index 91b751d..323239d 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,6 +1,6 @@ u_qspi_master 2250 650 N u_uart_i2c_usb_spi 2250 1350 N -u_pinmux 2250 2150 N +u_pinmux 2250 2250 N u_riscv_top.i_core_top_0 50 1400 N u_riscv_top.u_connect 725 1400 N @@ -10,6 +10,6 @@ u_tsram0_2kb 150 750 N -u_intercon 1850 650 N -u_wb_host 1750 100 N -u_pll 2305 105 N +u_intercon 1850 650 N +u_wb_host 1750 100 N +u_pll 2300 68 N
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl index 79a0f85..c1e213d 100644 --- a/openlane/user_project_wrapper/pdn_cfg.tcl +++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -92,7 +92,8 @@ -width $::env(FP_PDN_VWIDTH) \ -pitch $::env(FP_PDN_VPITCH) \ -offset $::env(FP_PDN_VOFFSET) \ - -nets "$::env(VDD_NET) $::env(GND_NET)" \ + -spacing $::env(FP_PDN_VSPACING) \ + -nets "$::env(VDD_NET) $::env(GND_NET)" \ -starts_with POWER -extend_to_core_ring add_pdn_stripe \ @@ -101,6 +102,7 @@ -width $::env(FP_PDN_HWIDTH) \ -pitch $::env(FP_PDN_HPITCH) \ -offset $::env(FP_PDN_HOFFSET) \ + -spacing $::env(FP_PDN_HSPACING) \ -nets "$::env(VDD_NET) $::env(GND_NET)" \ -starts_with POWER -extend_to_core_ring
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl index 527f4cc..f69b2c4 100755 --- a/openlane/wb_host/config.tcl +++ b/openlane/wb_host/config.tcl
@@ -42,6 +42,7 @@ set ::env(VERILOG_FILES) "\ $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wb_host.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wb_reset_fsm.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_fifo.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_wb.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_ctl.v \ @@ -52,6 +53,7 @@ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_txfsm.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_rxfsm.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/lib/double_sync_low.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_div8.v \ $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart2wb.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart2_core.sv \ @@ -60,6 +62,7 @@ $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/sspis_if.sv \ $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/spi2wb.sv \ " +set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/ ] set ::env(SYNTH_READ_BLACKBOX_LIB) 1 set ::env(SYNTH_DEFINES) [list SYNTHESIS ] @@ -92,13 +95,13 @@ -set ::env(FP_IO_VEXTEND) 4 -set ::env(FP_IO_HEXTEND) 4 +#set ::env(FP_IO_VEXTEND) 4 +#set ::env(FP_IO_HEXTEND) 4 set ::env(FP_PDN_VPITCH) 100 set ::env(FP_PDN_HPITCH) 100 -set ::env(FP_PDN_VWIDTH) 5 -set ::env(FP_PDN_HWIDTH) 5 +set ::env(FP_PDN_VWIDTH) 6.2 +set ::env(FP_PDN_HWIDTH) 6.2 #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4}
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg index d0a5a57..2c6a14d 100644 --- a/openlane/wb_host/pin_order.cfg +++ b/openlane/wb_host/pin_order.cfg
@@ -4,10 +4,8 @@ #W -usb_clk 0000 0 4 cpu_clk 0100 0 2 -rtc_clk @@ -350,3 +348,73 @@ wbs_cyc_o +cfg_strap_pad_ctrl +e_reset_n +int_pll_clock +p_reset_n +s_reset_n +xtal_clk +strap_sticky\[31\] +strap_sticky\[30\] +strap_sticky\[29\] +strap_sticky\[28\] +strap_sticky\[27\] +strap_sticky\[26\] +strap_sticky\[25\] +strap_sticky\[24\] +strap_sticky\[23\] +strap_sticky\[22\] +strap_sticky\[21\] +strap_sticky\[20\] +strap_sticky\[19\] +strap_sticky\[18\] +strap_sticky\[17\] +strap_sticky\[16\] +strap_sticky\[15\] +strap_sticky\[14\] +strap_sticky\[13\] +strap_sticky\[12\] +strap_sticky\[11\] +strap_sticky\[10\] +strap_sticky\[9\] +strap_sticky\[8\] +strap_sticky\[7\] +strap_sticky\[6\] +strap_sticky\[5\] +strap_sticky\[4\] +strap_sticky\[3\] +strap_sticky\[2\] +strap_sticky\[1\] +strap_sticky\[0\] +system_strap\[31\] +system_strap\[30\] +system_strap\[29\] +system_strap\[28\] +system_strap\[27\] +system_strap\[26\] +system_strap\[25\] +system_strap\[24\] +system_strap\[23\] +system_strap\[22\] +system_strap\[21\] +system_strap\[20\] +system_strap\[19\] +system_strap\[18\] +system_strap\[17\] +system_strap\[16\] +system_strap\[15\] +system_strap\[14\] +system_strap\[13\] +system_strap\[12\] +system_strap\[11\] +system_strap\[10\] +system_strap\[9\] +system_strap\[8\] +system_strap\[7\] +system_strap\[6\] +system_strap\[5\] +system_strap\[4\] +system_strap\[3\] +system_strap\[2\] +system_strap\[1\] +system_strap\[0\]
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index b82a6da..de21996 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -135,3 +135,7 @@ ## FANOUT Reduced to take care of long routes set ::env(SYNTH_MAX_FANOUT) "2" +set ::env(FP_PDN_VPITCH) 100 +set ::env(FP_PDN_HPITCH) 100 +set ::env(FP_PDN_VWIDTH) 6.2 +set ::env(FP_PDN_HWIDTH) 6.2
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index 4bf2c2b..93ca457 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -763,6 +763,7 @@ s2_wbd_stb_o 1600 0 2 s2_wbd_we_o +s2_wbd_adr_o\[9\] s2_wbd_adr_o\[8\] s2_wbd_adr_o\[7\] s2_wbd_adr_o\[6\]
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl index faaab7a..3c4ead4 100644 --- a/openlane/ycr_core_top/config.tcl +++ b/openlane/ycr_core_top/config.tcl
@@ -74,10 +74,10 @@ ## Floorplan set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 550 950 " +set ::env(DIE_AREA) "0 0 540 950 " -set ::env(PL_TARGET_DENSITY) 0.50 -set ::env(CELL_PAD) "4" +set ::env(PL_TARGET_DENSITY) 0.45 +set ::env(CELL_PAD) "8" ## Routing set ::env(GRT_ADJUSTMENT) 0.2 @@ -96,3 +96,7 @@ #Need to cross-check why global timing opimization creating setup vio with hugh hold fix set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" +set ::env(FP_PDN_VPITCH) 100 +set ::env(FP_PDN_HPITCH) 100 +set ::env(FP_PDN_VWIDTH) 6.2 +set ::env(FP_PDN_HWIDTH) 6.2
diff --git a/openlane/ycr_iconnect/config.tcl b/openlane/ycr_iconnect/config.tcl index e9f5eee..6745049 100644 --- a/openlane/ycr_iconnect/config.tcl +++ b/openlane/ycr_iconnect/config.tcl
@@ -79,20 +79,10 @@ set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1} ### PDN -#set ::env(FP_PDN_CHECK_NODES) "0" -#set ::env(FP_PDN_HORIZONTAL_HALO) "10" -#set ::env(FP_PDN_VERTICAL_HALO) "10" -# -#set ::env(FP_PDN_VOFFSET) "5" -#set ::env(FP_PDN_VPITCH) "80" -#set ::env(FP_PDN_VSPACING) "15.5" -#set ::env(FP_PDN_VWIDTH) "3.1" -# -#set ::env(FP_PDN_HOFFSET) "10" -#set ::env(FP_PDN_HPITCH) "100" -#set ::env(FP_PDN_HSPACING) "10" -#set ::env(FP_PDN_HWIDTH) "3.1" - +set ::env(FP_PDN_VPITCH) 100 +set ::env(FP_PDN_HPITCH) 100 +set ::env(FP_PDN_VWIDTH) 6.2 +set ::env(FP_PDN_HWIDTH) 6.2 #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4}
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl index 51b6c8b..8ef2d04 100644 --- a/openlane/ycr_intf/config.tcl +++ b/openlane/ycr_intf/config.tcl
@@ -69,8 +69,8 @@ set ::env(PL_TARGET_DENSITY) 0.37 -set ::env(FP_IO_VEXTEND) {6} -set ::env(FP_IO_HEXTEND) {6} +#set ::env(FP_IO_VEXTEND) {6} +#set ::env(FP_IO_HEXTEND) {6} set ::env(RT_MAX_LAYER) {met4} #set ::env(GLB_RT_MAXLAYER) "5" @@ -86,3 +86,8 @@ #Need to cross-check why global timing opimization creating setup vio with hugh hold fix set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" +#PDN +set ::env(FP_PDN_VPITCH) 100 +set ::env(FP_PDN_HPITCH) 100 +set ::env(FP_PDN_VWIDTH) 6.2 +set ::env(FP_PDN_HWIDTH) 6.2
diff --git a/spef/digital_pll.spef.gz b/spef/digital_pll.spef.gz new file mode 100644 index 0000000..8c0bfb5 --- /dev/null +++ b/spef/digital_pll.spef.gz Binary files differ
diff --git a/spef/pinmux_top.spef.gz b/spef/pinmux_top.spef.gz new file mode 100644 index 0000000..a5affea --- /dev/null +++ b/spef/pinmux_top.spef.gz Binary files differ
diff --git a/spef/qspim_top.spef.gz b/spef/qspim_top.spef.gz new file mode 100644 index 0000000..97756af --- /dev/null +++ b/spef/qspim_top.spef.gz Binary files differ
diff --git a/spef/uart_i2c_usb_spi_top.spef.gz b/spef/uart_i2c_usb_spi_top.spef.gz new file mode 100644 index 0000000..064acf0 --- /dev/null +++ b/spef/uart_i2c_usb_spi_top.spef.gz Binary files differ
diff --git a/spef/user_project_wrapper.spef.gz b/spef/user_project_wrapper.spef.gz new file mode 100644 index 0000000..e858ae3 --- /dev/null +++ b/spef/user_project_wrapper.spef.gz Binary files differ
diff --git a/spef/wb_host.spef.gz b/spef/wb_host.spef.gz new file mode 100644 index 0000000..f95b554 --- /dev/null +++ b/spef/wb_host.spef.gz Binary files differ
diff --git a/spef/wb_interconnect.spef.gz b/spef/wb_interconnect.spef.gz new file mode 100644 index 0000000..1b549ba --- /dev/null +++ b/spef/wb_interconnect.spef.gz Binary files differ
diff --git a/spef/ycr_core_top.spef.gz b/spef/ycr_core_top.spef.gz new file mode 100644 index 0000000..28a1c21 --- /dev/null +++ b/spef/ycr_core_top.spef.gz Binary files differ
diff --git a/spef/ycr_iconnect.spef.gz b/spef/ycr_iconnect.spef.gz new file mode 100644 index 0000000..8eda882 --- /dev/null +++ b/spef/ycr_iconnect.spef.gz Binary files differ
diff --git a/spef/ycr_intf.spef.gz b/spef/ycr_intf.spef.gz new file mode 100644 index 0000000..6bd2b86 --- /dev/null +++ b/spef/ycr_intf.spef.gz Binary files differ
diff --git a/verilog/gl/digital_pll.v.gz b/verilog/gl/digital_pll.v.gz new file mode 100644 index 0000000..3b3a0a7 --- /dev/null +++ b/verilog/gl/digital_pll.v.gz Binary files differ
diff --git a/verilog/gl/pinmux_top.v.gz b/verilog/gl/pinmux_top.v.gz new file mode 100644 index 0000000..45e74f3 --- /dev/null +++ b/verilog/gl/pinmux_top.v.gz Binary files differ
diff --git a/verilog/gl/qspim_top.v.gz b/verilog/gl/qspim_top.v.gz new file mode 100644 index 0000000..b70a49c --- /dev/null +++ b/verilog/gl/qspim_top.v.gz Binary files differ
diff --git a/verilog/gl/uart_i2c_usb_spi_top.v.gz b/verilog/gl/uart_i2c_usb_spi_top.v.gz new file mode 100644 index 0000000..f070157 --- /dev/null +++ b/verilog/gl/uart_i2c_usb_spi_top.v.gz Binary files differ
diff --git a/verilog/gl/wb_host.v.gz b/verilog/gl/wb_host.v.gz new file mode 100644 index 0000000..44e6327 --- /dev/null +++ b/verilog/gl/wb_host.v.gz Binary files differ
diff --git a/verilog/gl/wb_interconnect.v.gz b/verilog/gl/wb_interconnect.v.gz new file mode 100644 index 0000000..9b66c59 --- /dev/null +++ b/verilog/gl/wb_interconnect.v.gz Binary files differ
diff --git a/verilog/gl/ycr_core_top.v.gz b/verilog/gl/ycr_core_top.v.gz new file mode 100644 index 0000000..76a5ead --- /dev/null +++ b/verilog/gl/ycr_core_top.v.gz Binary files differ
diff --git a/verilog/gl/ycr_iconnect.v.gz b/verilog/gl/ycr_iconnect.v.gz new file mode 100644 index 0000000..86ca85b --- /dev/null +++ b/verilog/gl/ycr_iconnect.v.gz Binary files differ
diff --git a/verilog/gl/ycr_intf.v.gz b/verilog/gl/ycr_intf.v.gz new file mode 100644 index 0000000..94c5fa9 --- /dev/null +++ b/verilog/gl/ycr_intf.v.gz Binary files differ