MPW6 RTL and DV setup

diff --git a/verilog/dv/Makefile b/verilog/dv/Makefile
index ca64f10..bc570fe 100644
--- a/verilog/dv/Makefile
+++ b/verilog/dv/Makefile

@@ -19,7 +19,7 @@
 .SUFFIXES:
 .SILENT: clean all
 
-PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master
+PATTERNS = wb_port risc_boot user_risc_boot user_uart user_uart1 user_qspi user_i2cm riscv_regress user_basic user_usb user_pwm user_timer user_uart_master uart_master user_sram_exec
 
 all:  ${PATTERNS}
 	for i in ${PATTERNS}; do \

diff --git a/verilog/dv/firmware/common_bthread.c b/verilog/dv/firmware/common_bthread.c
new file mode 100644
index 0000000..e5508c6
--- /dev/null
+++ b/verilog/dv/firmware/common_bthread.c

@@ -0,0 +1,137 @@
+//========================================================================
+// common-bthread
+//========================================================================
+
+#include "common_bthread.h"
+
+//------------------------------------------------------------------------
+// Global data structures
+//------------------------------------------------------------------------
+
+spawn_func_ptr g_thread_spawn_func_ptrs[4];
+void*          g_thread_spawn_func_args[4];
+
+volatile int   g_thread_flags[4] = {0,0,0,0};
+
+
+//------------------------------------------------------------------------
+// bthread_init
+//------------------------------------------------------------------------
+
+void bthread_init()
+{
+  int core_id = bthread_get_core_id();
+
+  // If it's core zero, fall through
+
+  if ( core_id == 0 ) {
+
+    for ( int i = 0; i < 4; i++ )
+      g_thread_flags[i] = 0;
+
+    // mark core zero to be 1.
+
+    g_thread_flags[0] = 1;
+    return;
+  }
+
+  else {
+
+    // Core 1-3 will wait here in the worker loop
+
+    while (1) {
+
+      // Wait until woken up by core 0. We insert some extra nops here to
+      // avoid banging on the memory system too hard.
+
+      while( g_thread_flags[core_id] == 0 ) {
+        __asm__ __volatile__ ( "nop;"
+                               "nop;"
+                               "nop;"
+                               "nop;"
+                               "nop;"
+                               "nop;"
+                               "nop;"
+                               "nop;"
+                               "nop;"
+                               "nop;": : : "memory" );
+      }
+
+      // Execute the spawn function
+
+      (*g_thread_spawn_func_ptrs[core_id])
+        ( g_thread_spawn_func_args[core_id] );
+
+      // Unset the flag so the master core knows this work core is done.
+
+      g_thread_flags[core_id] = 0;
+
+    }
+
+  }
+}
+
+
+//------------------------------------------------------------------------
+// bthread_spawn
+//------------------------------------------------------------------------
+// Spawn a function to a given worker core (thread). Need to provide:
+//
+//   thread_id     : ID of the thread we are spawning to
+//   start_routine : Spawned function
+//   arg           : A pointer to the argument.
+//
+
+int bthread_spawn( int thread_id, void (*start_routine)(void*), void* arg )
+{
+  int ncores = bthread_get_num_cores();
+
+  // If the master core spawns work onto itself then that is an error.
+
+  if ( thread_id == 0 ) {
+    return -1;
+  }
+
+  // If thread id is too large return an error
+
+  if ( thread_id >= ncores || thread_id < 0 )
+    return -1;
+
+  // Check to see if the thread is already in use. If so, then return
+  // an error.
+
+  if ( g_thread_flags[thread_id] )
+    return -1;
+
+  // Set function and argument pointer
+
+  g_thread_spawn_func_args[thread_id] = arg;
+  g_thread_spawn_func_ptrs[thread_id] = start_routine;
+
+  // Wake up worker thread
+
+  g_thread_flags[thread_id] = 1;
+
+  return 0;
+}
+
+
+//------------------------------------------------------------------------
+// bthread_join
+//------------------------------------------------------------------------
+// Wait for the given thread to finish executing its work.
+
+int bthread_join( int thread_id )
+{
+  // Thread id out of range, return an error.
+
+  if( thread_id < 1 || thread_id >= 4 )
+    return -1;
+
+  // Wait until the given thread is no longer in use.
+
+  while ( g_thread_flags[thread_id] )
+    ;
+
+  return 0;
+}

diff --git a/verilog/dv/firmware/common_bthread.h b/verilog/dv/firmware/common_bthread.h
new file mode 100644
index 0000000..dcadf07
--- /dev/null
+++ b/verilog/dv/firmware/common_bthread.h

@@ -0,0 +1,107 @@
+//========================================================================
+// common-bthread
+//========================================================================
+// We use a very simple "runtime" to parallelize our apps. We called it
+// bthread because it is a set of bare minimum "threading" library
+// functions to parallelize a program across multiple cores.
+//
+// All cores start from the main function. We need to call the
+// bthread_init() function at the beginning of main(). Basically only
+// core 0 can pass through the bthread_init function and continue
+// executing. The rest of cores (if any) will be trapped in the
+// bthread_init() function, waiting in a loop we call the worker loop. In
+// each iteration of the worker loop, a core will check if the flag is
+// set by core 0. If it is, then it will execute the function core 0
+// stored in a shared location, then reset its flag. Cores other than
+// core 0 will stay in the worker loop indefinitely.
+//
+// We call core 0 the master core, and we call the other cores the worker
+// cores. The master core "spawns work" on a worker core using the
+// bthread_spawn function. The master core needs the function pointer,
+// the argument pointer, and a worker core's ID. It stores the function
+// pointer and the argument pointer to a global location, then sets the
+// flag for the given worker core.
+//
+// The master core can wait for a worker core to finish by using the
+// bthread_join function. It waits for a designated worker core until the
+// worker core finishes executing its function (if any) then returns.
+
+#ifndef COMMON_BTHREAD_H
+#define COMMON_BTHREAD_H
+
+//------------------------------------------------------------------------
+// Global data structures
+//------------------------------------------------------------------------
+
+typedef void (*spawn_func_ptr)(void*);
+
+
+extern spawn_func_ptr g_thread_spawn_func_ptrs[4];
+extern void*          g_thread_spawn_func_args[4];
+
+volatile extern int   g_thread_flags[4];
+
+
+//------------------------------------------------------------------------
+// bthread_get_num_cores
+//------------------------------------------------------------------------
+// Returns the number of cores.
+
+inline
+int bthread_get_num_cores()
+{
+  int num_cores;
+  asm( "csrr %0, 0xFC1;"
+       : "=r"(num_cores)
+       :
+  );
+  return num_cores;
+}
+
+
+//------------------------------------------------------------------------
+// bthread_get_core_id
+//------------------------------------------------------------------------
+// Returns the core ID.
+
+inline
+int bthread_get_core_id()
+{
+  int core_id;
+  asm( "csrr %0, 0xF14;"
+       : "=r"(core_id)
+       :
+  );
+  return core_id;
+}
+
+
+//------------------------------------------------------------------------
+// bthread_init
+//------------------------------------------------------------------------
+// This function _MUST_ be called right at the beginning of the main().
+// It will only let core 0 pass through. All other cores will be trapped
+// in a worker loop, waiting be woken up by the core 0 (bthread_spawn).
+
+void bthread_init();
+
+//------------------------------------------------------------------------
+// bthread_spawn
+//------------------------------------------------------------------------
+// Spawn a function to a given worker core (thread). Need to provide:
+//
+//   thread_id     : ID of the thread we are spawning to
+//   start_routine : Spawned function
+//   arg           : A pointer to the argument.
+//
+
+int bthread_spawn( int thread_id, void (*start_routine)(void*), void* arg );
+
+//------------------------------------------------------------------------
+// bthread_join
+//------------------------------------------------------------------------
+// Wait for the given thread to finish executing its work.
+
+int bthread_join( int thread_id );
+
+#endif /* COMMON_BTHREAD_H */

diff --git a/verilog/dv/firmware/common_misc.h b/verilog/dv/firmware/common_misc.h
new file mode 100644
index 0000000..8556c35
--- /dev/null
+++ b/verilog/dv/firmware/common_misc.h

@@ -0,0 +1,97 @@
+//========================================================================
+// common-misc
+//========================================================================
+
+#ifndef COMMON_MISC_H
+#define COMMON_MISC_H
+
+#include <stdio.h>
+#include <stdlib.h>
+
+//------------------------------------------------------------------------
+// Typedefs
+//------------------------------------------------------------------------
+
+typedef unsigned char byte;
+typedef unsigned int  uint;
+
+//------------------------------------------------------------------------
+// exit
+//------------------------------------------------------------------------
+// exit the program with the given status code
+
+
+inline
+void exit( int i )
+{
+  int msg = 0x00010000 | i;
+  asm ( "csrw 0x7C0, %0;" :: "r"(msg) );
+}
+
+
+//------------------------------------------------------------------------
+// test_fail
+//------------------------------------------------------------------------
+
+
+inline
+void test_fail( int index, int val, int ref )
+{
+  int status = 0x00020001;
+  asm( "csrw 0x7C0, %0;"
+       "csrw 0x7C0, %1;"
+       "csrw 0x7C0, %2;"
+       "csrw 0x7C0, %3;"
+       :
+       : "r" (status), "r" (index), "r" (val), "r" (ref)
+  );
+}
+
+
+//------------------------------------------------------------------------
+// test_pass
+//------------------------------------------------------------------------
+
+
+inline
+void test_pass()
+{
+  int status = 0x00020000;
+  asm( "csrw 0x7C0, %0;"
+       :
+       : "r" (status)
+  );
+}
+
+//------------------------------------------------------------------------
+// test_stats_on
+//------------------------------------------------------------------------
+
+
+inline
+void test_stats_on()
+{
+  int status = 1;
+  asm( "csrw 0x7C1, %0;"
+       :
+       : "r" (status)
+  );
+}
+
+
+//------------------------------------------------------------------------
+// test_stats_off
+//------------------------------------------------------------------------
+
+inline
+void test_stats_off()
+{
+  int status = 0;
+  asm( "csrw 0x7C1, %0;"
+       :
+       : "r" (status)
+  );
+}
+
+#endif /* COMMON_MISC_H */
+

diff --git a/verilog/dv/risc_boot/Makefile b/verilog/dv/risc_boot/Makefile
index 3ed4d9b..8d46511 100644
--- a/verilog/dv/risc_boot/Makefile
+++ b/verilog/dv/risc_boot/Makefile

@@ -140,7 +140,7 @@
 %.lst: %.elf
 	${GCC_PREFIX}-objdump -d -S $< > $@
 
-%.hex: %.elf
+%.hex: %.elf %.lst
 	${GCC_PREFIX}-objcopy -O verilog $< $@ 
 	# to fix flash base address
 	sed -ie 's/@10/@00/g' $@
@@ -164,26 +164,26 @@
 ## RTL
 ifeq ($(SIM),RTL)
    ifeq ($(DUMP),OFF)
-	iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+	iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
         -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
         -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
     else  
-	iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+	iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
         -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
         -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
    endif
-endif 
+endif
 
-## GL
+##GL
 ifeq ($(SIM),GL)
-    ifeq ($(CONFIG),caravel_user_project)
-		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
         -f$(VERILOG_PATH)/includes/includes.gl.caravel \
         -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
     else
-		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
-        -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \
-		-f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $<
+	iverilog -g2005-sv -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+        -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
     endif
 endif 
 

diff --git a/verilog/dv/risc_boot/risc_boot.c b/verilog/dv/risc_boot/risc_boot.c
index 7de5444..00d308d 100644
--- a/verilog/dv/risc_boot/risc_boot.c
+++ b/verilog/dv/risc_boot/risc_boot.c

@@ -141,7 +141,7 @@
     reg_mprj_io_6 =  GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
     reg_mprj_io_5 =  GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
     reg_mprj_io_4 =  GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
-    reg_mprj_io_3 =  GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
+    //reg_mprj_io_3 =  GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
     reg_mprj_io_2 =  GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
     reg_mprj_io_1 =  GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
     reg_mprj_io_0 =  GPIO_MODE_USER_STD_BIDIRECTIONAL_PULLUP;
@@ -150,6 +150,7 @@
     reg_mprj_xfer = 1;
     while (reg_mprj_xfer == 1);
 
+    reg_la0_data = 0x001; // Remove Soft Reset
     reg_la0_data = 0x000;
     reg_la0_data = 0x001; // Remove Soft Reset
 

diff --git a/verilog/dv/risc_boot/risc_boot_tb.v b/verilog/dv/risc_boot/risc_boot_tb.v
index e879f99..e9865d9 100644
--- a/verilog/dv/risc_boot/risc_boot_tb.v
+++ b/verilog/dv/risc_boot/risc_boot_tb.v

@@ -121,6 +121,9 @@
 		clock = 0;
 	end
 
+pullup(mprj_io[3]); 
+
+
 	`ifdef WFDUMP
         initial
         begin
@@ -130,7 +133,6 @@
            //$dumpvars(2,risc_boot_tb.uut);
            $dumpvars(1,risc_boot_tb.uut.mprj);
            $dumpvars(0,risc_boot_tb.uut.mprj.u_wb_host);
-           $dumpvars(1,risc_boot_tb.uut.mprj.u_riscv_top);
            //$dumpvars(0,risc_boot_tb.tb_uart);
            //$dumpvars(0,risc_boot_tb.u_user_spiflash);
 	   $display("Waveform Dump started");

diff --git a/verilog/dv/riscv_regress/riscv_runtests.sv b/verilog/dv/riscv_regress/riscv_runtests.sv
index 25c14a5..0dca105 100644
--- a/verilog/dv/riscv_regress/riscv_runtests.sv
+++ b/verilog/dv/riscv_regress/riscv_runtests.sv

@@ -34,7 +34,7 @@
  logic [`SCR1_DMEM_AWIDTH-1:0]           core2dmem_addr_o_r;           // DMEM address
  logic                                   core2dmem_cmd_o_r;
  
- `define RISC_CORE  i_top.i_core_top
+ `define RISC_CORE  i_top.i_core_top_0
  
  always@(posedge `RISC_CORE.clk) begin
      if(`RISC_CORE.imem2core_req_ack_i && `RISC_CORE.core2imem_req_o)
@@ -55,7 +55,7 @@
 **/
 /***
   logic [31:0] test_count;
- `define RISC_CORE  u_top.u_riscv_top.i_core_top
+ `define RISC_CORE  u_top.u_riscv_top.i_core_top_0
  `define RISC_EXU  u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu
 
  initial begin
@@ -71,6 +71,10 @@
  end
 ***/
 
+wire [31:0] pc_curr_ff         = u_top.u_riscv_top.i_core_top_0.i_pipe_top.i_pipe_exu.pc_curr_ff         ;
+wire [31:0] exu2pipe_pc_curr_o = u_top.u_riscv_top.i_core_top_0.i_pipe_top.i_pipe_exu.exu2pipe_pc_curr_o ;
+wire [31:0] mprf_int_10        = u_top.u_riscv_top.i_core_top_0.i_pipe_top.i_pipe_mprf.mprf_int[10]      ;
+
 always @(posedge clk) begin
     bit test_pass;
     int unsigned                            f_test;
@@ -78,11 +82,11 @@
     if (test_running) begin
         test_pass = 1;
         rst_init <= 1'b0;
-	if(u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu.pc_curr_ff === 32'hxxxx_xxxx) begin
+	if(pc_curr_ff === 32'hxxxx_xxxx) begin
 	   $display("ERROR: CURRENT PC Counter State is Known");
 	   $finish;
 	end
-        if ((u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_exu.exu2pipe_pc_curr_o == YCR1_SIM_EXIT_ADDR) & ~rst_init & &rst_cnt) begin
+        if ((exu2pipe_pc_curr_o == YCR1_SIM_EXIT_ADDR) & ~rst_init & &rst_cnt) begin
 
             `ifdef VERILATOR
                 logic [255:0] full_filename;
@@ -203,10 +207,10 @@
                 `endif  // SIGNATURE_OUT
             end else begin // Non compliance mode
                 test_running <= 1'b0;
-		if(u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10] != 0)
-		   $display("ERROR: mprf_int[10]: %x not zero",u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10]);
+		if(mprf_int_10 != 0)
+		   $display("ERROR: mprf_int[10]: %x not zero",mprf_int_10);
 
-                test_pass = (u_top.u_riscv_top.i_core_top.i_pipe_top.i_pipe_mprf.mprf_int[10] == 0);
+                test_pass = (mprf_int_10 == 0);
                 tests_total     += 1;
                 tests_passed    += test_pass;
                 `ifndef SIGNATURE_OUT
@@ -236,7 +240,7 @@
             if (f_test != 0) begin
             // Launch new test
                 `ifdef YCR1_TRACE_LOG_EN
-                    u_top.u_riscv_top.i_core_top.i_pipe_top.i_tracelog.test_name = test_file;
+                    u_top.u_riscv_top.i_core_top_0.i_pipe_top.i_tracelog.test_name = test_file;
                 `endif // SCR1_TRACE_LOG_EN
                 //i_memory_tb.test_file = test_file;
                 //i_memory_tb.test_file_init = 1'b1;

diff --git a/verilog/dv/riscv_regress/run_iverilog b/verilog/dv/riscv_regress/run_iverilog
index fbd8e05..3fa6890 100755
--- a/verilog/dv/riscv_regress/run_iverilog
+++ b/verilog/dv/riscv_regress/run_iverilog

@@ -27,6 +27,8 @@
 ../../user_risc_regress_tb.v \
 -o user_risc_regress_tb.vvp
 
+
+
 iverilog-vpi ../../../vpi/system/system.c
 
 vvp  -M. -msystem  user_risc_regress_tb.vvp +test_info=./test_info +test_results=./test_results.txt | tee sim_results.txt

diff --git a/verilog/dv/riscv_regress/user_risc_regress_tb.v b/verilog/dv/riscv_regress/user_risc_regress_tb.v
index 518084f..b1a0b63 100644
--- a/verilog/dv/riscv_regress/user_risc_regress_tb.v
+++ b/verilog/dv/riscv_regress/user_risc_regress_tb.v

@@ -74,7 +74,6 @@
 `timescale 1 ns / 1 ns
 
 `include "uprj_netlists.v"
-`include "mt48lc8m8a2.v"
 `include "is62wvs1288.v"
 `include "user_reg_map.v"
 
@@ -473,6 +472,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;

diff --git a/verilog/dv/user_basic/Makefile b/verilog/dv/user_basic/Makefile
index a00533a..c1ad8ae 100644
--- a/verilog/dv/user_basic/Makefile
+++ b/verilog/dv/user_basic/Makefile

@@ -24,7 +24,6 @@
 #######################################################################
 
 DESIGNS?=../../..
-TOOLS?=/opt/riscv64i/
 
 export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
 
@@ -43,7 +42,6 @@
 
 all:  ${PATTERN:=.vcd}
 
-hex:  ${PATTERN:=.hex}
 
 vvp:  ${PATTERN:=.vvp}
 
@@ -52,16 +50,26 @@
    ifeq ($(DUMP),OFF)
 	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
     else  
 	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
    endif
 else  
-	iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
 endif
 
 %.vcd: %.vvp

diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index 4aa572c..1face2a 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v

@@ -20,7 +20,6 @@
 ////                                                              ////
 ////  This file is part of the YIFive cores project               ////
 ////  https://github.com/dineshannayya/yifive_r0.git              ////
-////  http://www.opencores.org/cores/yifive/                      ////
 ////                                                              ////
 ////  Description                                                 ////
 ////   This is a standalone test bench to validate the            ////
@@ -74,7 +73,7 @@
 
 `timescale 1 ns/10 ps
 
-`include "DFFRAM/DFFRAM.v"
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 
 module user_basic_tb;
 parameter CLK1_PERIOD = 10;
@@ -151,7 +150,13 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(4, user_basic_tb);
+	   	$dumpvars(1, user_basic_tb);
+	   	//$dumpvars(1, user_basic_tb.u_top);
+	   	//$dumpvars(0, user_basic_tb.u_top.u_pll);
+	   	$dumpvars(0, user_basic_tb.u_top.u_wb_host);
+	   	//$dumpvars(1, user_basic_tb.u_top.u_intercon);
+	   	//$dumpvars(1, user_basic_tb.u_top.u_intercon);
+	   	//$dumpvars(1, user_basic_tb.u_top.u_pinmux);
 	   end
        `endif
 
@@ -160,6 +165,8 @@
 		#100;
 		wb_rst_i <= 1'b0;	    	// Release reset
 	end
+
+
 initial
 begin
 
@@ -173,80 +180,111 @@
    fork
       begin
 	  // Default Value Check
-          // cfg_glb_ctrl         = reg_0[6:0];
-          // uart_i2c_usb_sel     = reg_0[8:7];
-          // cfg_wb_clk_ctrl      = reg_0[11:9];
-          // cfg_rtc_clk_ctrl     = reg_0[19:12];
-          // cfg_cpu_clk_ctrl     = reg_0[23:20];
-          // cfg_usb_clk_ctrl     = reg_0[31:24];
-	  $display("Step-1, CPU: CLOCK1, RTC: CLOCK2 *2, USB: CLOCK2, WBS:CLOCK1");
+	  // cfg_wb_clk_ctrl      = cfg_clk_ctrl2[7:0];
+          // cfg_rtc_clk_ctrl     = cfg_clk_ctrl2[15:8];
+          // cfg_cpu_clk_ctrl     = cfg_clk_ctrl2[23:16];
+          // cfg_usb_clk_ctrl     = cfg_clk_ctrl2[31:24];
+
+
+	  $display("Step-1, CPU: CLOCK1, USB: CLOCK2,RTC: CLOCK2 *2, WBS:CLOCK1");
 	  test_step = 1;
-          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h0,4'h0,8'h0,4'h0,8'h00});
-	  clock_monitor(CLK1_PERIOD,CLK2_PERIOD*2,CLK2_PERIOD,CLK1_PERIOD);
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h0,8'h0,8'h0,8'h0});
+	  clock_monitor(CLK1_PERIOD,CLK1_PERIOD,CLK2_PERIOD*2,CLK1_PERIOD);
 
-	  $display("Step-2, CPU: CLOCK2, RTC: CLOCK2/(2+1), USB: CLOCK2/2, WBS:CLOCK2");
+	  $display("Step-2, CPU: CLOCK2, USB: CLOCK2/2, RTC: CLOCK2/(2+1), WBS:CLOCK2");
 	  test_step = 2;
-          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h80,4'h8,8'h1,4'h8,8'h00});
-	  clock_monitor(CLK2_PERIOD,(3)*CLK2_PERIOD,2*CLK2_PERIOD,CLK2_PERIOD);
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h40,8'h60,8'h1,8'h40});
+	  clock_monitor(CLK2_PERIOD,2*CLK2_PERIOD,(3)*CLK2_PERIOD,CLK2_PERIOD);
 
-	  $display("Step-3, CPU: CLOCK1/2, RTC: CLOCK2/(2+2), USB: CLOCK2/(2+1), WBS:CLOCK1/2");
+	  $display("Step-3, CPU: CLOCK1/2,USB: CLOCK2/(2+1), RTC: CLOCK2/(2+2), WBS:CLOCK1/2");
 	  test_step = 3;
-          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h81,4'h4,8'h2,4'h4,8'h00});
-	  clock_monitor(2*CLK1_PERIOD,(4)*CLK2_PERIOD,3*CLK2_PERIOD,2*CLK1_PERIOD);
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h20,8'h61,8'h2,8'h20});
+	  clock_monitor(2*CLK1_PERIOD,(3)*CLK2_PERIOD,4*CLK2_PERIOD,2*CLK1_PERIOD);
 
-	  $display("Step-4, CPU: CLOCK1/3, RTC: CLOCK2/(2+3), USB: CLOCK2/(2+2), WBS:CLOCK1/3");
+	  $display("Step-4, CPU: CLOCK1/3, USB: CLOCK2/(2+2), RTC: CLOCK2/(2+3), WBS:CLOCK1/3");
 	  test_step = 4;
-          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h82,4'h5,8'h3,4'h5,8'h00});
-	  clock_monitor(3*CLK1_PERIOD,5*CLK2_PERIOD,4*CLK2_PERIOD,3*CLK1_PERIOD);
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h21,8'h62,8'h3,8'h21});
+	  clock_monitor(3*CLK1_PERIOD,4*CLK2_PERIOD,5*CLK2_PERIOD,3*CLK1_PERIOD);
 
-	  $display("Step-5, CPU: CLOCK1/4, RTC: CLOCK2/(2+4), USB: CLOCK2/(2+3), WBS:CLOCK1/4");
+	  $display("Step-5, CPU: CLOCK1/4, USB: CLOCK2/(2+3), RTC: CLOCK2/(2+4), WBS:CLOCK1/4");
 	  test_step = 5;
-          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h83,4'h6,8'h4,4'h6,8'h00});
-	  clock_monitor(4*CLK1_PERIOD,6*CLK2_PERIOD,5*CLK2_PERIOD,4*CLK1_PERIOD);
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h22,8'h63,8'h4,8'h22});
+	  clock_monitor(4*CLK1_PERIOD,5*CLK2_PERIOD,6*CLK2_PERIOD,4*CLK1_PERIOD);
 
-	  $display("Step-6, CPU: CLOCK1/(2+3), RTC: CLOCK2/(2+5), USB: CLOCK2/(2+4), WBS:CLOCK1/(2+3)");
+	  $display("Step-6, CPU: CLOCK1/(2+3),USB: CLOCK2/(2+4), RTC: CLOCK2/(2+5), WBS:CLOCK1/(2+3)");
 	  test_step = 6;
-          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h84,4'h7,8'h5,4'h7,8'h00});
-	  clock_monitor(5*CLK1_PERIOD,7*CLK2_PERIOD,6*CLK2_PERIOD,5*CLK1_PERIOD);
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h23,8'h64,8'h5,8'h23});
+	  clock_monitor(5*CLK1_PERIOD,6*CLK2_PERIOD,7*CLK2_PERIOD,5*CLK1_PERIOD);
 
-	  $display("Step-7, CPU: CLOCK2/(2), RTC: CLOCK2/(2+6), USB: CLOCK2/(2+5), WBS:CLOCK2/(2)");
+	  $display("Step-7, CPU: CLOCK2/(2), USB: CLOCK2/(2+5), RTC: CLOCK2/(2+6), WBS:CLOCK2/(2)");
 	  test_step = 7;
-          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h85,4'hC,8'h6,4'hC,8'h00});
-	  clock_monitor(2*CLK2_PERIOD,8*CLK2_PERIOD,7*CLK2_PERIOD,2*CLK2_PERIOD);
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h60,8'h65,8'h6,8'h60});
+	  clock_monitor(2*CLK2_PERIOD,7*CLK2_PERIOD,8*CLK2_PERIOD,2*CLK2_PERIOD);
 
-	  $display("Step-8, CPU: CLOCK2/3, RTC: CLOCK2/(2+7), USB: CLOCK2/(2+6), WBS:CLOCK2/3");
+	  $display("Step-8, CPU: CLOCK2/3, USB: CLOCK2/(2+6), RTC: CLOCK2/(2+7), WBS:CLOCK2/3");
 	  test_step = 8;
-          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h86,4'hD,8'h7,4'hD,8'h00});
-	  clock_monitor(3*CLK2_PERIOD,9*CLK2_PERIOD,8*CLK2_PERIOD,3*CLK2_PERIOD);
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h61,8'h66,8'h7,8'h61});
+	  clock_monitor(3*CLK2_PERIOD,8*CLK2_PERIOD,9*CLK2_PERIOD,3*CLK2_PERIOD);
 
-	  $display("Step-9, CPU: CLOCK2/4, RTC: CLOCK2/(2+8), USB: CLOCK2/(2+7), WBS:CLOCK2/4");
+	  $display("Step-9, CPU: CLOCK2/4,USB: CLOCK2/(2+7), RTC: CLOCK2/(2+8), WBS:CLOCK2/4");
 	  test_step = 9;
-          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h87,4'hE,8'h8,4'hE,8'h00});
-	  clock_monitor(4*CLK2_PERIOD,10*CLK2_PERIOD,9*CLK2_PERIOD,4*CLK2_PERIOD);
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h62,8'h67,8'h8,8'h62});
+	  clock_monitor(4*CLK2_PERIOD,9*CLK2_PERIOD,10*CLK2_PERIOD,4*CLK2_PERIOD);
 
-	  $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+128), USB: CLOCK2/(2+8), WBS:CLOCK1/(2+3)");
+	  $display("Step-10, CPU: CLOCK2/(2+3), USB: CLOCK2/(2+8), RTC: CLOCK2/(2+128), WBS:CLOCK1/(2+3)");
 	  test_step = 10;
-          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h88,4'hF,8'h80,4'hF,8'h00});
-	  clock_monitor(5*CLK2_PERIOD,130*CLK2_PERIOD,10*CLK2_PERIOD,5*CLK2_PERIOD);
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h68,8'h80,8'h63});
+	  clock_monitor(5*CLK2_PERIOD,10*CLK2_PERIOD,130*CLK2_PERIOD,5*CLK2_PERIOD);
 
-	  $display("Step-10, CPU: CLOCK2/(2+3), RTC: CLOCK2/(2+255), USB: CLOCK2/(2+9), WBS:CLOCK2/(2+3)");
+	  $display("Step-11, CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)");
 	  test_step = 10;
-          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h89,4'hF,8'hFF,4'hF,8'h00});
-	  clock_monitor(5*CLK2_PERIOD,257*CLK2_PERIOD,11*CLK2_PERIOD,5*CLK2_PERIOD);
+          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});
+	  clock_monitor(5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD);
+  
+         $display("###################################################");
+         $display("Monitor: Checking the PLL:");
+         $display("###################################################");
+	 test_step = 11;
+	 // Set PLL enable, no DCO mode ; Set PLL output divider to 0x03
+         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
+         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b0,5'h3,26'h00000});
+         repeat (100) @(posedge clock);
+	 pll_clock_monitor(5);
+
+	 test_step = 12;
+	 // Set PLL enable, DCO mode ; Set PLL output divider to 0x01
+         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
+         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
+         repeat (100) @(posedge clock);
+	 pll_clock_monitor(4);
 
          $display("###################################################");
+         $display("Monitor: Monitor Clock output:");
+         $display("###################################################");
+	 $display("Monitor: CPU: CLOCK2/(2+3), USB: CLOCK2/(2+9), RTC: CLOCK2/(2+255), WBS:CLOCK2/(2+4)");
+	 test_step = 13;
+         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h63,8'h69,8'hFF,8'h64});
+
+	 // Set PLL enable, DCO mode ; Set PLL output divider to 0x01
+         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b000,4'b0000,8'h2});
+         wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_PLL_CTRL,{1'b1,5'h0,26'h0000});
+	 dbg_clk_monitor(79,60,5*CLK2_PERIOD,11*CLK2_PERIOD,257*CLK2_PERIOD,6*CLK2_PERIOD);
+         
+	 $display("###################################################");
          $display("Monitor: Checking the chip signature :");
+         $display("###################################################");
+	 test_step = 14;
          // Remove Wb/PinMux Reset
          wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
 	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343);
-	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h0604_2022);
-	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_2000);
+	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h0306_2022);
+	 wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_5000);
 
       end
    
       begin
-      repeat (20000) @(posedge clock);
+      repeat (30000) @(posedge clock);
    		// $display("+1000 cycles");
       test_fail = 1;
       end
@@ -324,28 +362,76 @@
 
 task clock_monitor;
 input [15:0] exp_cpu_period;
-input [15:0] exp_rtc_period;
 input [15:0] exp_usb_period;
+input [15:0] exp_rtc_period;
 input [15:0] exp_wbs_period;
 begin
    force clock_mon = u_top.u_wb_host.cpu_clk;
    check_clock_period("CPU CLock",exp_cpu_period);
    release clock_mon;
 
-   force clock_mon = u_top.u_wb_host.rtc_clk;
-   check_clock_period("RTC Clock",exp_rtc_period);
-   release clock_mon;
-
    force clock_mon = u_top.u_wb_host.usb_clk;
    check_clock_period("USB Clock",exp_usb_period);
    release clock_mon;
 
+   force clock_mon = u_top.u_wb_host.rtc_clk;
+   check_clock_period("RTC Clock",exp_rtc_period);
+   release clock_mon;
+
    force clock_mon = u_top.u_wb_host.wbs_clk_out;
    check_clock_period("WBS Clock",exp_wbs_period);
    release clock_mon;
 end
 endtask
 
+task pll_clock_monitor;
+input [15:0] exp_period;
+begin
+   //force clock_mon = u_top.u_wb_host.pll_clk_out[0];
+   `ifdef GL
+      force clock_mon = u_top.u_wb_host.u_clkbuf_pll.u_buf.X;
+    `else
+      force clock_mon = u_top.u_wb_host.u_clkbuf_pll.X;
+    `endif
+   check_clock_period("PLL CLock",exp_period);
+   release clock_mon;
+end
+endtask
+
+
+wire dbg_clk_mon = io_out[33];
+
+task dbg_clk_monitor;
+input [15:0] exp_pll_div16_period;
+input [15:0] exp_pll_ref_period;
+input [15:0] exp_cpu_period;
+input [15:0] exp_usb_period;
+input [15:0] exp_rtc_period;
+input [15:0] exp_wbs_period;
+begin
+   force clock_mon = dbg_clk_mon;
+
+   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0000,8'h2});
+   check_clock_period("PLL CLock",exp_pll_div16_period);
+
+   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0001,8'h2});
+   check_clock_period("PLL REF Clock",exp_pll_ref_period);
+
+   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0010,8'h2});
+   check_clock_period("WBS Clock",exp_wbs_period);
+
+   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0011,8'h2});
+   check_clock_period("CPU CLock",exp_cpu_period);
+
+   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0100,8'h2});
+   check_clock_period("RTC Clock",exp_rtc_period);
+
+   wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{16'h0,1'b1,3'b100,4'b0101,8'h2});
+   check_clock_period("USB Clock",exp_usb_period);
+   release clock_mon;
+end
+endtask
+
 //----------------------------------
 // Check the clock period
 //----------------------------------
@@ -416,6 +502,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -445,6 +532,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -466,29 +554,21 @@
 
 `ifdef GL
 
-wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
-wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
-wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
-wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
 
-wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
-wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
-wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
-wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
 
 `endif
 

diff --git a/verilog/dv/user_gpio/.user_timer_tb.v.swp b/verilog/dv/user_gpio/.user_timer_tb.v.swp
new file mode 100644
index 0000000..b5202d8
--- /dev/null
+++ b/verilog/dv/user_gpio/.user_timer_tb.v.swp
Binary files differ

diff --git a/verilog/dv/user_gpio/Makefile b/verilog/dv/user_gpio/Makefile
new file mode 100644
index 0000000..c072436
--- /dev/null
+++ b/verilog/dv/user_gpio/Makefile

@@ -0,0 +1,100 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+## Caravel Pointers
+CARAVEL_ROOT ?= ../../../caravel
+CARAVEL_PATH ?= $(CARAVEL_ROOT)
+CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
+CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
+CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
+CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
+
+
+## User Project Pointers
+UPRJ_VERILOG_PATH ?= ../../../verilog
+UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
+UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
+UPRJ_BEHAVIOURAL_MODELS = ../model
+UPRJ_BEHAVIOURAL_AGENTS = ../agents
+UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
+UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/i2cm/src/includes
+UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
+
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
+GCC64_PREFIX?=riscv64-unknown-elf
+
+## RISCV GCC 
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/opt/pdk/sky130A
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+.SUFFIXES:
+
+PATTERN = user_gpio
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
+	-I $(UPRJ_INCLUDE_PATH3) \
+	$< -o $@ 
+    else  
+	iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
+	-I $(UPRJ_INCLUDE_PATH3) \
+	$< -o $@ 
+   endif
+else  
+	iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \
+	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+	$< -o $@ 
+endif
+
+%.vcd: %.vvp
+	vvp $<
+
+%.hex: 
+	echo @"This is user boot test, noting to compile the mangment core code"
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.vvp *.vcd *.log *.fst
+
+.PHONY: clean hex all

diff --git a/verilog/dv/user_gpio/user_gpio_tb.v b/verilog/dv/user_gpio/user_gpio_tb.v
new file mode 100644
index 0000000..a9e5944
--- /dev/null
+++ b/verilog/dv/user_gpio/user_gpio_tb.v

@@ -0,0 +1,520 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Standalone User validation Test bench                       ////
+////                                                              ////
+////  This file is part of the YIFive cores project               ////
+////  https://github.com/dineshannayya/yifive_r0.git              ////
+////  http://www.opencores.org/cores/yifive/                      ////
+////                                                              ////
+////  Description                                                 ////
+////   This is a standalone test bench to validate the            ////
+////   gpio interfaface through External WB i/F.                  ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 01 Oct 2021, Dinesh A                               ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+// Note in caravel, 0x30XX_XXXX only come to user interface
+// So, using wb_host bank select we have changing MSB address [31:24] = 0x10
+`define ADDR_SPACE_UART    32'h3001_0000
+`define ADDR_SPACE_SSPI    32'h3001_00C0
+`define ADDR_SPACE_PINMUX  32'h3002_0000
+
+`define TB_GLBL    user_gpio_tb
+
+`include "uprj_netlists.v"
+`include "is62wvs1288.v"
+`include "user_reg_map.v"
+
+
+module user_gpio_tb;
+	reg clock;
+	reg wb_rst_i;
+	reg power1, power2;
+	reg power3, power4;
+
+        reg        wbd_ext_cyc_i;  // strobe/request
+        reg        wbd_ext_stb_i;  // strobe/request
+        reg [31:0] wbd_ext_adr_i;  // address
+        reg        wbd_ext_we_i;  // write
+        reg [31:0] wbd_ext_dat_i;  // data output
+        reg [3:0]  wbd_ext_sel_i;  // byte enable
+
+        wire [31:0] wbd_ext_dat_o;  // data input
+        wire        wbd_ext_ack_o;  // acknowlegement
+        wire        wbd_ext_err_o;  // error
+
+	// User I/O
+	wire [37:0] io_oeb;
+	wire [37:0] io_out;
+	wire [37:0] io_in;
+
+
+	reg [1:0] spi_chip_no;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+	reg        test_fail;
+	reg [31:0] read_data;
+        integer    test_step;
+        wire       clock_mon;
+
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+
+	initial begin
+		OneUsPeriod = 1;
+		clock = 0;
+                wbd_ext_cyc_i ='h0;  // strobe/request
+                wbd_ext_stb_i ='h0;  // strobe/request
+                wbd_ext_adr_i ='h0;  // address
+                wbd_ext_we_i  ='h0;  // write
+                wbd_ext_dat_i ='h0;  // data output
+                wbd_ext_sel_i ='h0;  // byte enable
+	end
+
+	`ifdef WFDUMP
+	   initial begin
+	   	$dumpfile("simx.vcd");
+	   	$dumpvars(1, `TB_GLBL);
+	   	$dumpvars(0, `TB_GLBL.u_top.u_pinmux);
+	   end
+       `endif
+
+	initial begin
+		$dumpon;
+
+		#200; // Wait for reset removal
+	        repeat (10) @(posedge clock);
+		$display("Monitor: Standalone User Risc Boot Test Started");
+
+		// Remove Wb Reset
+		wb_user_core_write('h3080_0000,'h1);
+
+	        repeat (2) @(posedge clock);
+		#1;
+                wb_user_core_write('h3080_0004,'h10); // Change the Bank Sel 10
+
+                // Remove the reset
+		// Remove WB and SPI/UART Reset, Keep CORE under Reset
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h01F);
+
+		// config 1us based on system clock - 1000/25ns = 40 
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG1,39);
+
+		// Enable GPIO Interrupt
+                wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_INTR_MSK,'h8000);
+
+		test_fail = 0;
+	        repeat (200) @(posedge clock);
+
+
+		repeat (100) @(posedge clock);
+			// $display("+1000 cycles");
+
+          	if(test_fail == 0) begin
+		   `ifdef GL
+	    	       $display("Monitor: GPIO Mode (GL) Passed");
+		   `else
+		       $display("Monitor: GPIO Mode (RTL) Passed");
+		   `endif
+	        end else begin
+		    `ifdef GL
+	    	        $display("Monitor: GPIO Mode (GL) Failed");
+		    `else
+		        $display("Monitor: GPIO Mode (RTL) Failed");
+		    `endif
+		 end
+	    	$display("###################################################");
+	        $finish;
+	end
+
+	initial begin
+		wb_rst_i <= 1'b1;
+		#100;
+		wb_rst_i <= 1'b0;	    	// Release reset
+	end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+    .vccd1(USER_VDD1V8),	// User area 1 1.8V supply
+    .vssd1(VSS),	// User area 1 digital ground
+`endif
+    .wb_clk_i        (clock),  // System clock
+    .user_clock2     (1'b1),  // Real-time clock
+    .wb_rst_i        (wb_rst_i),  // Regular Reset signal
+
+    .wbs_cyc_i   (wbd_ext_cyc_i),  // strobe/request
+    .wbs_stb_i   (wbd_ext_stb_i),  // strobe/request
+    .wbs_adr_i   (wbd_ext_adr_i),  // address
+    .wbs_we_i    (wbd_ext_we_i),  // write
+    .wbs_dat_i   (wbd_ext_dat_i),  // data output
+    .wbs_sel_i   (wbd_ext_sel_i),  // byte enable
+
+    .wbs_dat_o   (wbd_ext_dat_o),  // data input
+    .wbs_ack_o   (wbd_ext_ack_o),  // acknowlegement
+
+ 
+    // Logic Analyzer Signals
+    .la_data_in      ('1) ,
+    .la_data_out     (),
+    .la_oenb         ('0),
+ 
+
+    // IOs
+    .io_in          (io_in)  ,
+    .io_out         (io_out) ,
+    .io_oeb         (io_oeb) ,
+
+    .user_irq       () 
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+
+    end
+`endif    
+
+//------------------------------------------------------
+//  Integrate the Serial flash with qurd support to
+//  user core using the gpio pads
+//  ----------------------------------------------------
+   wire flash_io1;
+   wire flash_clk = io_out[16];
+   wire spiram_csb = io_out[13];
+   tri  #1 flash_io0 = io_out[15];
+   assign io_in[14] = flash_io1;
+
+   tri  #1 flash_io2 = 1'b1;
+   tri  #1 flash_io3 = 1'b1;
+
+
+   is62wvs1288 #(.mem_file_name("flash1.hex"))
+	u_sfram (
+         // Data Inputs/Outputs
+           .io0     (flash_io0),
+           .io1     (flash_io1),
+           // Controls
+           .clk    (flash_clk),
+           .csb    (spiram_csb),
+           .io2    (flash_io2),
+           .io3    (flash_io3)
+    );
+
+
+//----------------------------------------------------
+//  Task
+// --------------------------------------------------
+task test_err;
+begin
+     test_fail = 1;
+end
+endtask
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h1;  // write
+  wbd_ext_dat_i =data;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("STATUS: WB USER ACCESS WRITE Address : 0x%x, Data : 0x%x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  //$display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  if(data !== cmp_data) begin
+     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+     `TB_GLBL.test_fail = 1;
+  end else begin
+     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  end
+  repeat (2) @(posedge clock);
+end
+endtask
+// GPIO Pin Mapping
+//Pin-1        PC6/RESET*          digital_io[0]
+//Pin-2        PD0/RXD             digital_io[1]
+//Pin-3        PD1/TXD             digital_io[2]
+//Pin-4        PD2/INT0            digital_io[3]
+//Pin-5        PD3/INT1/OC2B(PWM0)  digital_io[4]
+//Pin-6        PD4                 digital_io[5]
+//Pin-9        PB6/XTAL1/TOSC1     digital_io[6]
+//Pin-10       PB7/XTAL2/TOSC2     digital_io[7]
+//Pin-11       PD5/OC0B(PWM1)/T1   digital_io[8]
+//Pin-12       PD6/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2]
+//Pin-13       PD7/A1N1            digital_io[10]/analog_io[3]
+//Pin-14       PB0/CLKO/ICP1       digital_io[11]
+//Pin-15       PB1/OC1A(PWM3)      digital_io[12]
+//Pin-16       PB2/SS/OC1B(PWM4)   digital_io[13]
+//Pin-17       PB3/MOSI/OC2A(PWM5) digital_io[14]
+//Pin-18       PB4/MISO            digital_io[15]
+//Pin-19       PB5/SCK             digital_io[16]
+//Pin-23       PC0/ADC0            digital_io[18]/analog_io[11]
+//Pin-24       PC1/ADC1            digital_io[19]/analog_io[12]
+//Pin-25       PC2/ADC2            digital_io[20]/analog_io[13]
+//Pin-26       PC3/ADC3            digital_io[21]/analog_io[14]
+//Pin-27       PC4/ADC4/SDA        digital_io[22]/analog_io[15]
+//Pin-28       PC5/ADC5/SCL        digital_io[23]/analog_io[16]
+
+// Generate GPIO out data
+
+task gen_gpio_out;
+input  [31:0] datain;
+output [7:0] port_a_out;
+output [7:0] port_b_out;
+output [7:0] port_c_out;
+output [7:0] port_d_out;
+
+reg [7:0] port_a_out;
+reg [7:0] port_b_out;
+reg [7:0] port_c_out;
+reg [7:0] port_d_out;
+begin
+    port_a_out ='h0;
+    port_b_out ='h0;
+    port_c_out ='h0;
+    port_d_out ='h0;
+
+    port_c_out[6] =  datain[0];
+    port_d_out[0] =  datain[1];
+    port_d_out[1] =  datain[2];
+    port_d_out[2] =  datain[3];
+    port_d_out[3] =  datain[4];
+    port_d_out[4] =  datain[5];
+    port_b_out[6] =  datain[6];
+    port_b_out[7] =  datain[7];
+    port_d_out[5] =  datain[8];
+    port_d_out[6] =  datain[9];
+    port_d_out[7] =  datain[10];
+    port_b_out[0] =  datain[11];
+    port_b_out[1] =  datain[12];
+    port_b_out[2] =  datain[13];
+    port_b_out[3] =  datain[14];
+    port_b_out[4] =  datain[15];
+    port_b_out[5] =  datain[16];
+    port_c_out[0] =  datain[18];
+    port_c_out[1] =  datain[19];
+    port_c_out[2] =  datain[20];
+    port_c_out[3] =  datain[21];
+    port_c_out[4] =  datain[22];
+    port_c_out[5] =  datain[23];
+end
+endtask
+
+// generate expected gpio data out
+task exp_gpio_in;
+output [7:0] port_a_in;
+output [7:0] port_b_in;
+output [7:0] port_c_in;
+output [7:0] port_d_in;
+reg [7:0] port_a_in;
+reg [7:0] port_b_in;
+reg [7:0] port_c_in;
+reg [7:0] port_d_in;
+begin
+    port_a_in ='h0;
+    port_b_in ='h0;
+    port_c_in ='h0;
+    port_d_in ='h0;
+    
+    port_c_in[6] =  io_out[0];
+    port_d_in[0] =  io_out[1];
+    port_d_in[1] =  io_out[2];
+    port_d_in[2] =  io_out[3];
+    port_d_in[3] =  io_out[4];
+    port_d_in[4] =  io_out[5];
+    port_b_in[6] =  io_out[6];
+    port_b_in[7] =  io_out[7];
+    port_d_in[5] =  io_out[8];
+    port_d_in[6] =  io_out[9];
+    port_d_in[7] =  io_out[10];
+    port_b_in[0] =  io_out[11];
+    port_b_in[1] =  io_out[12];
+    port_b_in[2] =  io_out[13];
+    port_b_in[3] =  io_out[14];
+    port_b_in[4] =  io_out[15];
+    port_b_in[5] =  io_out[16];
+    port_c_in[0] =  io_out[18];
+    port_c_in[1] =  io_out[19];
+    port_c_in[2] =  io_out[20];
+    port_c_in[3] =  io_out[21];
+    port_c_in[4] =  io_out[22];
+    port_c_in[5] =  io_out[23];
+end
+endtask
+
+
+`ifdef GL
+
+wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
+wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE  user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+    if(`RISC_CORE.wbd_imem_ack_i)
+          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+    if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+    if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+
+endmodule
+`default_nettype wire

diff --git a/verilog/dv/user_i2cm/Makefile b/verilog/dv/user_i2cm/Makefile
index edab839..f01c09d 100644
--- a/verilog/dv/user_i2cm/Makefile
+++ b/verilog/dv/user_i2cm/Makefile

@@ -46,7 +46,6 @@
 
 all:  ${PATTERN:=.vcd}
 
-hex:  ${PATTERN:=.hex}
 
 vvp:  ${PATTERN:=.vvp}
 
@@ -55,16 +54,26 @@
    ifeq ($(DUMP),OFF)
 	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
     else  
 	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
    endif
 else  
-	iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
 endif
 
 %.vcd: %.vvp
@@ -74,6 +83,6 @@
 # ---- Clean ----
 
 clean:
-	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump *.fst
 
 .PHONY: clean hex all

diff --git a/verilog/dv/user_i2cm/user_i2cm_tb.v b/verilog/dv/user_i2cm/user_i2cm_tb.v
index 8bfde16..e0f8219 100644
--- a/verilog/dv/user_i2cm/user_i2cm_tb.v
+++ b/verilog/dv/user_i2cm/user_i2cm_tb.v

@@ -65,7 +65,7 @@
 
 `timescale 1 ns / 1 ns
 
-`include "DFFRAM/DFFRAM.v"
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 `include "i2c_slave_model.v"
 
 module tb_top;
@@ -405,6 +405,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -433,6 +434,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -442,13 +444,11 @@
   wbd_ext_we_i  ='h0;  // write
   wbd_ext_dat_i ='h0;  // data output
   wbd_ext_sel_i ='h0;  // byte enable
-  if(data === cmp_data) begin
-     $display("STATUS: DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+  if(data !== cmp_data) begin
+     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+     test_fail = 1;
   end else begin
-     $display("ERROR: DEBUG WB USER ACCESS READ Address : %x, Exp Data : %x Rxd Data: ",address,cmp_data,data);
-     test_fail= 1;
-     #100
-     $finish;
+     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
   end
   repeat (2) @(posedge clock);
 end
@@ -456,29 +456,21 @@
 
 `ifdef GL
 
-wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
-wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
-wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
-wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
 
-wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire        wbd_uart_stb_i  = u_top.u_uart_i2c.u_uart_core.reg_cs;
-wire        wbd_uart_ack_o  = u_top.u_uart_i2c.u_uart_core.reg_ack;
-wire        wbd_uart_we_i   = u_top.u_uart_i2c.u_uart_core.reg_wr;
-wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c.u_uart_core.reg_addr;
-wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c.u_uart_core.reg_wdata;
-wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c.u_uart_core.reg_rdata;
-wire        wbd_uart_sel_i  = u_top.u_uart_i2c.u_uart_core.reg_be;
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
 
 `endif
 

diff --git a/verilog/dv/user_pwm/Makefile b/verilog/dv/user_pwm/Makefile
index 03f0bcc..c521c74 100644
--- a/verilog/dv/user_pwm/Makefile
+++ b/verilog/dv/user_pwm/Makefile

@@ -55,16 +55,26 @@
    ifeq ($(DUMP),OFF)
 	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
     else  
 	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
    endif
 else  
-	iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
 endif
 
 %.vcd: %.vvp

diff --git a/verilog/dv/user_pwm/user_pwm_tb.v b/verilog/dv/user_pwm/user_pwm_tb.v
index 817a8c6..e5222cc 100644
--- a/verilog/dv/user_pwm/user_pwm_tb.v
+++ b/verilog/dv/user_pwm/user_pwm_tb.v

@@ -20,7 +20,6 @@
 ////                                                              ////
 ////  This file is part of the YIFive cores project               ////
 ////  https://github.com/dineshannayya/yifive_r0.git              ////
-////  http://www.opencores.org/cores/yifive/                      ////
 ////                                                              ////
 ////  Description                                                 ////
 ////   This is a standalone test bench to validate the            ////
@@ -69,7 +68,8 @@
 
 `define TB_GLBL    user_pwm_tb
 
-`include "DFFRAM/DFFRAM.v"
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+
 
 module user_pwm_tb;
 	reg clock;
@@ -359,6 +359,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -388,6 +389,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -410,21 +412,21 @@
 
 `ifdef GL
 
-wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
-wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
-wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
-wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
 
-wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
-wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
-wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
-wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
 
 `endif
 

diff --git a/verilog/dv/user_qspi/Makefile b/verilog/dv/user_qspi/Makefile
index 9c375e6..6b87fce 100644
--- a/verilog/dv/user_qspi/Makefile
+++ b/verilog/dv/user_qspi/Makefile

@@ -55,16 +55,26 @@
    ifeq ($(DUMP),OFF)
 	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
     else  
 	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
    endif
 else  
-	iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
 endif
 
 %.vcd: %.vvp

diff --git a/verilog/dv/user_qspi/user_qspi_tb.v b/verilog/dv/user_qspi/user_qspi_tb.v
index e8ba4ee..4fd07e5 100644
--- a/verilog/dv/user_qspi/user_qspi_tb.v
+++ b/verilog/dv/user_qspi/user_qspi_tb.v

@@ -79,7 +79,7 @@
 
 `timescale 1 ns/1 ps
 
-`include "DFFRAM/DFFRAM.v"
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 `include "is62wvs1288.v"
 
 module user_qspi_tb;
@@ -1297,6 +1297,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -1326,6 +1327,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -1348,29 +1350,21 @@
 
 `ifdef GL
 
-wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
-wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
-wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
-wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
 
-wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
-wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
-wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
-wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
 
 `endif
 

diff --git a/verilog/dv/user_risc_boot/Makefile b/verilog/dv/user_risc_boot/Makefile
index 14a0f1e..da70cab 100644
--- a/verilog/dv/user_risc_boot/Makefile
+++ b/verilog/dv/user_risc_boot/Makefile

@@ -47,7 +47,6 @@
 
 all:  ${PATTERN:=.vcd}
 
-hex:  ${PATTERN:=.hex}
 
 vvp:  ${PATTERN:=.vvp}
 
@@ -62,16 +61,26 @@
    ifeq ($(DUMP),OFF)
 	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
     else  
 	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
    endif
 else  
-	iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
 endif
 
 %.vcd: %.vvp

diff --git a/verilog/dv/user_risc_boot/user_risc_boot_tb.v b/verilog/dv/user_risc_boot/user_risc_boot_tb.v
index fd2fda2..b26d787 100644
--- a/verilog/dv/user_risc_boot/user_risc_boot_tb.v
+++ b/verilog/dv/user_risc_boot/user_risc_boot_tb.v

@@ -74,8 +74,7 @@
 
 `timescale 1 ns / 1 ns
 
-`include "DFFRAM/DFFRAM.v"
-
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 module user_risc_boot_tb;
 	reg clock;
 	reg wb_rst_i;
@@ -321,6 +320,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -350,6 +350,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -371,29 +372,21 @@
 
 `ifdef GL
 
-wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
-wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
-wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
-wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
 
-wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
-wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
-wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
-wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
 
 `endif
 

diff --git a/verilog/dv/user_sram_exec/Makefile b/verilog/dv/user_sram_exec/Makefile
new file mode 100644
index 0000000..44f56ab
--- /dev/null
+++ b/verilog/dv/user_sram_exec/Makefile

@@ -0,0 +1,95 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
+
+DESIGNS?=../../..
+TOOLS?=/opt/riscv64i/
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
+## YIFIVE FIRMWARE
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC64_PREFIX?=riscv64-unknown-elf
+
+
+## Simulation mode: RTL/GL
+SIM?=RTL
+DUMP?=OFF
+RISC_CORE?=0
+
+### To Enable IVERILOG FST DUMP
+export IVERILOG_DUMPER = fst
+
+
+.SUFFIXES:
+
+PATTERN = user_sram_exec
+
+all:  ${PATTERN:=.vcd}
+
+
+vvp:  ${PATTERN:=.vvp}
+
+%.vvp: %_tb.v
+	${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  user_sram_exec.c -o user_sram_exec.o
+	${GCC64_PREFIX}-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las  -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=0 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\"  -D__ASSEMBLY__=1 -c -I./ -I$(YIFIVE_FIRMWARE_PATH)  $(YIFIVE_FIRMWARE_PATH)/crt.S -o crt.o
+	${GCC64_PREFIX}-gcc -o user_sram_exec.elf -T $(YIFIVE_FIRMWARE_PATH)/link.ld user_sram_exec.o crt.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 -N
+	${GCC64_PREFIX}-objcopy -O verilog user_sram_exec.elf user_sram_exec.hex
+	${GCC64_PREFIX}-objdump -D user_sram_exec.elf > user_sram_exec.dump
+	rm crt.o user_sram_exec.o
+ifeq ($(SIM),RTL)
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
+	$< -o $@ 
+   endif
+else  
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
+endif
+
+%.vcd: %.vvp
+	vvp $< +risc_core_id=$(RISC_CORE)
+
+
+# ---- Clean ----
+
+clean:
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
+
+.PHONY: clean hex all

diff --git a/verilog/dv/user_sram_exec/user_sram_exec.c b/verilog/dv/user_sram_exec/user_sram_exec.c
new file mode 100644
index 0000000..62546a8
--- /dev/null
+++ b/verilog/dv/user_sram_exec/user_sram_exec.c

@@ -0,0 +1,88 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#define SC_SIM_OUTPORT (0xf0000000)
+#define uint32_t  long
+#define uint16_t  int
+
+#define reg_mprj_globl_reg0  (*(volatile uint32_t*)0x10020000)
+#define reg_mprj_globl_reg1  (*(volatile uint32_t*)0x10020004)
+#define reg_mprj_globl_reg2  (*(volatile uint32_t*)0x10020008)
+#define reg_mprj_globl_reg3  (*(volatile uint32_t*)0x1002000C)
+#define reg_mprj_globl_reg4  (*(volatile uint32_t*)0x10020010)
+#define reg_mprj_globl_reg5  (*(volatile uint32_t*)0x10020014)
+#define reg_mprj_globl_reg6  (*(volatile uint32_t*)0x10020018)
+#define reg_mprj_globl_reg7  (*(volatile uint32_t*)0x1002001C)
+#define reg_mprj_globl_reg8  (*(volatile uint32_t*)0x10020020)
+#define reg_mprj_globl_reg9  (*(volatile uint32_t*)0x10020024)
+#define reg_mprj_globl_reg10 (*(volatile uint32_t*)0x10020028)
+#define reg_mprj_globl_reg11 (*(volatile uint32_t*)0x1002002C)
+#define reg_mprj_globl_reg12 (*(volatile uint32_t*)0x10020030)
+#define reg_mprj_globl_reg13 (*(volatile uint32_t*)0x10020034)
+#define reg_mprj_globl_reg14 (*(volatile uint32_t*)0x10020038)
+#define reg_mprj_globl_reg15 (*(volatile uint32_t*)0x1002003C)
+#define reg_mprj_globl_reg16 (*(volatile uint32_t*)0x10020040)
+#define reg_mprj_globl_reg17 (*(volatile uint32_t*)0x10020044)
+#define reg_mprj_globl_reg18 (*(volatile uint32_t*)0x10020048)
+#define reg_mprj_globl_reg19 (*(volatile uint32_t*)0x1002004C)
+#define reg_mprj_globl_reg20 (*(volatile uint32_t*)0x10020050)
+#define reg_mprj_globl_reg21 (*(volatile uint32_t*)0x10020054)
+#define reg_mprj_globl_reg22 (*(volatile uint32_t*)0x10020058)
+#define reg_mprj_globl_reg23 (*(volatile uint32_t*)0x1002005C)
+#define reg_mprj_globl_reg24 (*(volatile uint32_t*)0x10020060)
+#define reg_mprj_globl_reg25 (*(volatile uint32_t*)0x10020064)
+#define reg_mprj_globl_reg26 (*(volatile uint32_t*)0x10020068)
+#define reg_mprj_globl_reg27 (*(volatile uint32_t*)0x1002006C)
+// -------------------------------------------------------------------------
+// Test copying code into SRAM and running it from there.
+// -------------------------------------------------------------------------
+
+void test_function()
+{
+    reg_mprj_globl_reg24  = 0x33445566;  // Sig-3
+    reg_mprj_globl_reg25  = 0x44556677;  // Sig-4
+
+    return;
+}
+
+void main()
+{
+    uint16_t func[&main - &test_function];
+    uint16_t *src_ptr;
+    uint16_t *dst_ptr;
+
+
+    src_ptr = &test_function;
+    dst_ptr = func;
+
+    reg_mprj_globl_reg22  = 0x11223344;  // Sig-1
+    while (src_ptr < &main) {
+	*(dst_ptr++) = *(src_ptr++);
+    }
+
+    // Call the routine in SRAM
+    reg_mprj_globl_reg23  = 0x22334455;  // Sig-2
+    
+    ((void(*)())func)();
+
+    reg_mprj_globl_reg26 = 0x55667788; 
+    reg_mprj_globl_reg27 = 0x66778899; 
+
+    // Signal end of test
+}
+

diff --git a/verilog/dv/user_sram_exec/user_sram_exec_tb.v b/verilog/dv/user_sram_exec/user_sram_exec_tb.v
new file mode 100644
index 0000000..2aaad02
--- /dev/null
+++ b/verilog/dv/user_sram_exec/user_sram_exec_tb.v

@@ -0,0 +1,415 @@
+////////////////////////////////////////////////////////////////////////////
+// SPDX-FileCopyrightText:  2021 , Dinesh Annayya
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org>
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  Standalone User validation Test bench                       ////
+////                                                              ////
+////  This file is part of the Riscduino cores project            ////
+////                                                              ////
+////  Description                                                 ////
+////   This is a standalone test bench to validate the            ////
+////   Digital core with Risc core executing code from TCM/SRAM.  ////
+////                                                              ////
+////  To Do:                                                      ////
+////    nothing                                                   ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Dinesh Annayya, dinesha@opencores.org                 ////
+////                                                              ////
+////  Revision :                                                  ////
+////    0.1 - 16th Feb 2021, Dinesh A                             ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`default_nettype wire
+
+`timescale 1 ns / 1 ns
+
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+module user_sram_exec_tb;
+	reg clock;
+	reg wb_rst_i;
+	reg power1, power2;
+	reg power3, power4;
+
+        reg        wbd_ext_cyc_i;  // strobe/request
+        reg        wbd_ext_stb_i;  // strobe/request
+        reg [31:0] wbd_ext_adr_i;  // address
+        reg        wbd_ext_we_i;  // write
+        reg [31:0] wbd_ext_dat_i;  // data output
+        reg [3:0]  wbd_ext_sel_i;  // byte enable
+
+        wire [31:0] wbd_ext_dat_o;  // data input
+        wire        wbd_ext_ack_o;  // acknowlegement
+        wire        wbd_ext_err_o;  // error
+
+	// User I/O
+	wire [37:0] io_oeb;
+	wire [37:0] io_out;
+	wire [37:0] io_in;
+
+	wire gpio;
+	wire [37:0] mprj_io;
+	wire [7:0] mprj_io_0;
+	reg         test_fail;
+	reg [31:0] read_data;
+	integer    d_risc_id;
+
+
+
+	// External clock is used by default.  Make this artificially fast for the
+	// simulation.  Normally this would be a slow clock and the digital PLL
+	// would be the fast clock.
+
+	always #12.5 clock <= (clock === 1'b0);
+
+	initial begin
+		clock = 0;
+                wbd_ext_cyc_i ='h0;  // strobe/request
+                wbd_ext_stb_i ='h0;  // strobe/request
+                wbd_ext_adr_i ='h0;  // address
+                wbd_ext_we_i  ='h0;  // write
+                wbd_ext_dat_i ='h0;  // data output
+                wbd_ext_sel_i ='h0;  // byte enable
+	end
+
+	`ifdef WFDUMP
+	   initial begin
+	   	$dumpfile("simx.vcd");
+	   	$dumpvars(1, user_sram_exec_tb);
+	   	$dumpvars(1, user_sram_exec_tb.u_top);
+	   	$dumpvars(0, user_sram_exec_tb.u_top.u_riscv_top);
+	   end
+       `endif
+
+	initial begin
+
+		$value$plusargs("risc_core_id=%d", d_risc_id);
+
+		#200; // Wait for reset removal
+	        repeat (10) @(posedge clock);
+		$display("Monitor: Standalone User Risc Boot Test Started");
+
+		// Remove Wb Reset
+		wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+
+	        repeat (2) @(posedge clock);
+		#1;
+		// Remove all the reset
+		if(d_risc_id == 0) begin
+		     $display("STATUS: Working with Risc core 0");
+                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h11F);
+		end else begin
+		     $display("STATUS: Working with Risc core 1");
+                     wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GBL_CFG0,'h21F);
+		end
+
+
+		// Repeat cycles of 1000 clock edges as needed to complete testbench
+		repeat (30) begin
+			repeat (1000) @(posedge clock);
+			// $display("+1000 cycles");
+		end
+
+
+		$display("Monitor: Reading Back the expected value");
+		// User RISC core expect to write these value in global
+		// register, read back and decide on pass fail
+		// 0x30000018  = 0x11223344; 
+                // 0x3000001C  = 0x22334455; 
+                // 0x30000020  = 0x33445566; 
+                // 0x30000024  = 0x44556677; 
+                // 0x30000028 = 0x55667788; 
+                // 0x3000002C = 0x66778899; 
+
+                test_fail = 0;
+		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h11223344);
+		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h22334455);
+		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h33445566);
+		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,read_data,32'h44556677);
+		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,read_data,32'h55667788);
+		wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,read_data,32'h66778899);
+
+
+	   
+	    	$display("###################################################");
+          	if(test_fail == 0) begin
+		   `ifdef GL
+	    	       $display("Monitor: Standalone User Risc Boot (GL) Passed");
+		   `else
+		       $display("Monitor: Standalone User Risc Boot (RTL) Passed");
+		   `endif
+	        end else begin
+		    `ifdef GL
+	    	        $display("Monitor: Standalone User Risc Boot (GL) Failed");
+		    `else
+		        $display("Monitor: Standalone User Risc Boot (RTL) Failed");
+		    `endif
+		 end
+	    	$display("###################################################");
+	    $finish;
+	end
+
+	initial begin
+		wb_rst_i <= 1'b1;
+		#100;
+		wb_rst_i <= 1'b0;	    	// Release reset
+	end
+wire USER_VDD1V8 = 1'b1;
+wire VSS = 1'b0;
+
+user_project_wrapper u_top(
+`ifdef USE_POWER_PINS
+    .vccd1(USER_VDD1V8),	// User area 1 1.8V supply
+    .vssd1(VSS),	// User area 1 digital ground
+`endif
+    .wb_clk_i        (clock),  // System clock
+    .user_clock2     (1'b1),  // Real-time clock
+    .wb_rst_i        (wb_rst_i),  // Regular Reset signal
+
+    .wbs_cyc_i   (wbd_ext_cyc_i),  // strobe/request
+    .wbs_stb_i   (wbd_ext_stb_i),  // strobe/request
+    .wbs_adr_i   (wbd_ext_adr_i),  // address
+    .wbs_we_i    (wbd_ext_we_i),  // write
+    .wbs_dat_i   (wbd_ext_dat_i),  // data output
+    .wbs_sel_i   (wbd_ext_sel_i),  // byte enable
+
+    .wbs_dat_o   (wbd_ext_dat_o),  // data input
+    .wbs_ack_o   (wbd_ext_ack_o),  // acknowlegement
+
+ 
+    // Logic Analyzer Signals
+    .la_data_in      ('1) ,
+    .la_data_out     (),
+    .la_oenb         ('0),
+ 
+
+    // IOs
+    .io_in          (io_in)  ,
+    .io_out         (io_out) ,
+    .io_oeb         (io_oeb) ,
+
+    .user_irq       () 
+
+);
+
+`ifndef GL // Drive Power for Hold Fix Buf
+    // All standard cell need power hook-up for functionality work
+    initial begin
+
+    end
+`endif    
+
+//------------------------------------------------------
+//  Integrate the Serial flash with qurd support to
+//  user core using the gpio pads
+//  ----------------------------------------------------
+
+   wire flash_clk = io_out[24];
+   wire flash_csb = io_out[25];
+   // Creating Pad Delay
+   wire #1 io_oeb_29 = io_oeb[29];
+   wire #1 io_oeb_30 = io_oeb[30];
+   wire #1 io_oeb_31 = io_oeb[31];
+   wire #1 io_oeb_32 = io_oeb[32];
+   tri  #1 flash_io0 = (io_oeb_29== 1'b0) ? io_out[29] : 1'bz;
+   tri  #1 flash_io1 = (io_oeb_30== 1'b0) ? io_out[30] : 1'bz;
+   tri  #1 flash_io2 = (io_oeb_31== 1'b0) ? io_out[31] : 1'bz;
+   tri  #1 flash_io3 = (io_oeb_32== 1'b0) ? io_out[32] : 1'bz;
+
+   assign io_in[29] = flash_io0;
+   assign io_in[30] = flash_io1;
+   assign io_in[31] = flash_io2;
+   assign io_in[32] = flash_io3;
+
+   // Quard flash
+     s25fl256s #(.mem_file_name("user_sram_exec.hex"),
+	         .otp_file_name("none"),
+                 .TimingModel("S25FL512SAGMFI010_F_30pF")) 
+		 u_spi_flash_256mb (
+           // Data Inputs/Outputs
+       .SI      (flash_io0),
+       .SO      (flash_io1),
+       // Controls
+       .SCK     (flash_clk),
+       .CSNeg   (flash_csb),
+       .WPNeg   (flash_io2),
+       .HOLDNeg (flash_io3),
+       .RSTNeg  (!wb_rst_i)
+
+       );
+
+
+
+
+task wb_user_core_write;
+input [31:0] address;
+input [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h1;  // write
+  wbd_ext_dat_i =data;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("DEBUG WB USER ACCESS WRITE Address : %x, Data : %x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read;
+input [31:0] address;
+output [31:0] data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  $display("DEBUG WB USER ACCESS READ Address : %x, Data : %x",address,data);
+  repeat (2) @(posedge clock);
+end
+endtask
+
+task  wb_user_core_read_check;
+input [31:0] address;
+output [31:0] data;
+input [31:0] cmp_data;
+reg    [31:0] data;
+begin
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_adr_i =address;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='0;  // data output
+  wbd_ext_sel_i ='hF;  // byte enable
+  wbd_ext_cyc_i ='h1;  // strobe/request
+  wbd_ext_stb_i ='h1;  // strobe/request
+  wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
+  data  = wbd_ext_dat_o;  
+  repeat (1) @(posedge clock);
+  #1;
+  wbd_ext_cyc_i ='h0;  // strobe/request
+  wbd_ext_stb_i ='h0;  // strobe/request
+  wbd_ext_adr_i ='h0;  // address
+  wbd_ext_we_i  ='h0;  // write
+  wbd_ext_dat_i ='h0;  // data output
+  wbd_ext_sel_i ='h0;  // byte enable
+  if(data !== cmp_data) begin
+     $display("ERROR : WB USER ACCESS READ  Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data);
+     test_fail = 1;
+  end else begin
+     $display("STATUS: WB USER ACCESS READ  Address : 0x%x, Data : 0x%x",address,data);
+  end
+  repeat (2) @(posedge clock);
+end
+endtask
+
+`ifdef GL
+
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
+
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
+
+`endif
+
+/**
+`ifdef GL
+//-----------------------------------------------------------------------------
+// RISC IMEM amd DMEM Monitoring TASK
+//-----------------------------------------------------------------------------
+
+`define RISC_CORE  user_uart_tb.u_top.u_core.u_riscv_top
+
+always@(posedge `RISC_CORE.wb_clk) begin
+    if(`RISC_CORE.wbd_imem_ack_i)
+          $display("RISCV-DEBUG => IMEM ADDRESS: %x Read Data : %x", `RISC_CORE.wbd_imem_adr_o,`RISC_CORE.wbd_imem_dat_i);
+    if(`RISC_CORE.wbd_dmem_ack_i && `RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x Write Data: %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_o);
+    if(`RISC_CORE.wbd_dmem_ack_i && !`RISC_CORE.wbd_dmem_we_o)
+          $display("RISCV-DEBUG => DMEM ADDRESS: %x READ Data : %x Resonse: %x", `RISC_CORE.wbd_dmem_adr_o,`RISC_CORE.wbd_dmem_dat_i);
+end
+
+`endif
+**/
+endmodule
+`include "s25fl256s.sv"
+`default_nettype wire

diff --git a/verilog/dv/user_sspi/Makefile b/verilog/dv/user_sspi/Makefile
index eb764f0..f16f2a7 100644
--- a/verilog/dv/user_sspi/Makefile
+++ b/verilog/dv/user_sspi/Makefile

@@ -55,16 +55,26 @@
    ifeq ($(DUMP),OFF)
 	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
     else  
 	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
    endif
 else  
-	iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
 endif
 
 %.vcd: %.vvp
@@ -74,6 +84,6 @@
 # ---- Clean ----
 
 clean:
-	rm -rf *.vvp *.vcd *.log *.fst
+	rm -f *.elf *.bin *.vvp *.vcd *.log *.dump *.fst
 
 .PHONY: clean hex all

diff --git a/verilog/dv/user_sspi/user_sspi_tb.v b/verilog/dv/user_sspi/user_sspi_tb.v
index e3d52f9..1e81542 100644
--- a/verilog/dv/user_sspi/user_sspi_tb.v
+++ b/verilog/dv/user_sspi/user_sspi_tb.v

@@ -66,7 +66,7 @@
 
 `timescale 1 ns/1 ps
 
-`include "DFFRAM/DFFRAM.v"
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 `include "is62wvs1288.v"
 
 `define TB_GLBL    user_sspi_tb
@@ -567,6 +567,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -596,6 +597,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -618,29 +620,21 @@
 
 `ifdef GL
 
-wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
-wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
-wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
-wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
 
-wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
-wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
-wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
-wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
 
 `endif
 

diff --git a/verilog/dv/user_timer/Makefile b/verilog/dv/user_timer/Makefile
index 6d04ada..077652a 100644
--- a/verilog/dv/user_timer/Makefile
+++ b/verilog/dv/user_timer/Makefile

@@ -55,16 +55,26 @@
    ifeq ($(DUMP),OFF)
 	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
     else  
 	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
    endif
 else  
-	iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
 endif
 
 %.vcd: %.vvp

diff --git a/verilog/dv/user_timer/user_timer_tb.v b/verilog/dv/user_timer/user_timer_tb.v
index b40fd0f..b27d655 100644
--- a/verilog/dv/user_timer/user_timer_tb.v
+++ b/verilog/dv/user_timer/user_timer_tb.v

@@ -66,10 +66,9 @@
 
 `timescale 1 ns / 1 ps
 
-`include "DFFRAM/DFFRAM.v"
-
 `define TB_GLBL    user_timer_tb
 
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 
 
 module user_timer_tb;
@@ -395,6 +394,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -424,6 +424,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -446,21 +447,21 @@
 
 `ifdef GL
 
-wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
-wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
-wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
-wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
 
-wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
-wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
-wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
-wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
 
 `endif
 

diff --git a/verilog/dv/user_uart/Makefile b/verilog/dv/user_uart/Makefile
index 508b1df..0c74848 100644
--- a/verilog/dv/user_uart/Makefile
+++ b/verilog/dv/user_uart/Makefile

@@ -61,16 +61,26 @@
    ifeq ($(DUMP),OFF)
 	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
     else  
 	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
    endif
 else  
-	iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
 endif
 
 %.vcd: %.vvp
@@ -82,4 +92,4 @@
 clean:
 	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
 
-.PHONY: clean hex all
+.PHONY: clean all

diff --git a/verilog/dv/user_uart/user_uart_tb.v b/verilog/dv/user_uart/user_uart_tb.v
index 14f0c7f..f59c3a8 100644
--- a/verilog/dv/user_uart/user_uart_tb.v
+++ b/verilog/dv/user_uart/user_uart_tb.v

@@ -74,7 +74,7 @@
 
 `timescale 1 ns/1 ps
 
-`include "DFFRAM/DFFRAM.v"
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 `include "uart_agent.v"
 
 
@@ -144,8 +144,7 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(1, user_uart_tb);
-	   	$dumpvars(0, user_uart_tb.u_top);
+	   	$dumpvars(0, user_uart_tb);
 	   end
        `endif
 
@@ -200,14 +199,14 @@
          for (i=0; i<40; i=i+1)
          begin
            $display ("\n... UART Agent Writing char %x ...", uart_write_data[i]);
-            user_uart_tb.tb_uart.write_char (uart_write_data[i]);
+            tb_uart.write_char (uart_write_data[i]);
          end
       end
    
       begin
          for (j=0; j<40; j=j+1)
          begin
-           user_uart_tb.tb_uart.read_char_chk(uart_write_data[j]);
+           tb_uart.read_char_chk(uart_write_data[j]);
          end
       end
       join
@@ -388,6 +387,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -404,29 +404,21 @@
 
 `ifdef GL
 
-wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
-wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
-wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
-wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
 
-wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
-wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
-wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
-wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
 
 `endif
 

diff --git a/verilog/dv/user_uart1/Makefile b/verilog/dv/user_uart1/Makefile
index 104d358..7f299a1 100644
--- a/verilog/dv/user_uart1/Makefile
+++ b/verilog/dv/user_uart1/Makefile

@@ -61,16 +61,26 @@
    ifeq ($(DUMP),OFF)
 	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
     else  
 	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
    endif
 else  
-	iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
 endif
 
 %.vcd: %.vvp

diff --git a/verilog/dv/user_uart1/user_uart1_tb.v b/verilog/dv/user_uart1/user_uart1_tb.v
index 47a5406..44587e4 100644
--- a/verilog/dv/user_uart1/user_uart1_tb.v
+++ b/verilog/dv/user_uart1/user_uart1_tb.v

@@ -74,7 +74,7 @@
 
 `timescale 1 ns/1 ps
 
-`include "DFFRAM/DFFRAM.v"
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 `include "uart_agent.v"
 
 
@@ -403,6 +403,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -419,29 +420,21 @@
 
 `ifdef GL
 
-wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
-wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
-wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
-wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
 
-wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
-wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
-wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
-wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
 
 `endif
 

diff --git a/verilog/dv/user_uart_master/Makefile b/verilog/dv/user_uart_master/Makefile
index 340954d..c1eb60e 100644
--- a/verilog/dv/user_uart_master/Makefile
+++ b/verilog/dv/user_uart_master/Makefile

@@ -14,34 +14,28 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-## Caravel Pointers
-CARAVEL_ROOT ?= ../../../caravel
-CARAVEL_PATH ?= $(CARAVEL_ROOT)
-CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel
-CARAVEL_VERILOG_PATH  = $(CARAVEL_PATH)/verilog
-CARAVEL_RTL_PATH = $(CARAVEL_VERILOG_PATH)/rtl
-CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
 
+# ---- Include Partitioned Makefiles ----
 
-## User Project Pointers
-UPRJ_VERILOG_PATH ?= ../../../verilog
-UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
-UPRJ_GL_PATH = $(UPRJ_VERILOG_PATH)/gl
-UPRJ_BEHAVIOURAL_MODELS = ../model
-UPRJ_BEHAVIOURAL_AGENTS = ../agents
-UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/yifive/ycr1c/src/includes
-UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
-UPRJ_INCLUDE_PATH3 = $(UPRJ_RTL_PATH)/i2cm/src/includes
-UPRJ_INCLUDE_PATH4 = $(UPRJ_RTL_PATH)/usb1_host/src/includes
-UPRJ_INCLUDE_PATH5 = $(UPRJ_RTL_PATH)/mbist/include
+CONFIG = caravel_user_project
+ 
+#######################################################################
+## Caravel Verilog for Integration Tests
+#######################################################################
 
+DESIGNS?=../../..
+TOOLS?=/opt/riscv64i/
+
+export USER_PROJECT_VERILOG ?=  $(DESIGNS)/verilog
 ## YIFIVE FIRMWARE
-YIFIVE_FIRMWARE_PATH = $(UPRJ_VERILOG_PATH)/dv/firmware
+YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware
+GCC64_PREFIX?=riscv64-unknown-elf
 
 
 ## Simulation mode: RTL/GL
 SIM?=RTL
 DUMP?=OFF
+RISC_CORE?=0
 
 ### To Enable IVERILOG FST DUMP
 export IVERILOG_DUMPER = fst
@@ -59,38 +53,37 @@
 %.vvp: %_tb.v
 ifeq ($(SIM),RTL)
    ifeq ($(DUMP),OFF)
-	iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-	-I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
+	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
     else  
-	iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
-	-I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) -I $(UPRJ_INCLUDE_PATH3) \
-	-I $(UPRJ_INCLUDE_PATH4) -I $(UPRJ_INCLUDE_PATH5) \
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
    endif
 else  
-	iverilog -g2005-sv -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_GL_PATH) \
-	-I $(UPRJ_BEHAVIOURAL_AGENTS)    \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
 endif
 
 %.vcd: %.vvp
-	vvp $<
-
+	vvp $< +risc_core_id=$(RISC_CORE)
 
 
 # ---- Clean ----
 
 clean:
-	rm -f *.vvp *.vcd *.log 
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
 
 .PHONY: clean all

diff --git a/verilog/dv/user_uart_master/user_uart_master_tb.v b/verilog/dv/user_uart_master/user_uart_master_tb.v
index 3f4f16e..40d7b07 100644
--- a/verilog/dv/user_uart_master/user_uart_master_tb.v
+++ b/verilog/dv/user_uart_master/user_uart_master_tb.v

@@ -64,17 +64,10 @@
 
 `default_nettype wire
 
-`timescale 1 ns / 1 ns
+`timescale 1 ns / 1 ps
 
-`include "uprj_netlists.v"
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
 `include "uart_agent.v"
-`include "user_reg_map.v"
-
-
-
-`define ADDR_SPACE_UART    32'h3001_0000
-`define ADDR_SPACE_PINMUX  32'h3002_0000
-
 
 module user_uart_master_tb;
 

diff --git a/verilog/dv/user_usb/Makefile b/verilog/dv/user_usb/Makefile
index d6b53cd..d8eee80 100644
--- a/verilog/dv/user_usb/Makefile
+++ b/verilog/dv/user_usb/Makefile

@@ -55,25 +55,35 @@
    ifeq ($(DUMP),OFF)
 	iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
     else  
 	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
 	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib  \
 	$< -o $@ 
    endif
 else  
-	iverilog -g2012 -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
-	-f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \
+   ifeq ($(DUMP),OFF)
+	iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
 	$< -o $@ 
+    else  
+	iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \
+	-f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \
+	$< -o $@ 
+   endif
 endif
 
 %.vcd: %.vvp
-	vvp $<
+	vvp $< +risc_core_id=$(RISC_CORE)
 
 
 # ---- Clean ----
 
 clean:
-	rm -f *.vvp *.vcd *.log *.fst
+	rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump
 
 .PHONY: clean hex all

diff --git a/verilog/dv/user_usb/user_usb_tb.v b/verilog/dv/user_usb/user_usb_tb.v
index ff00f62..5974990 100644
--- a/verilog/dv/user_usb/user_usb_tb.v
+++ b/verilog/dv/user_usb/user_usb_tb.v

@@ -43,16 +43,17 @@
 `define TB_GLBL    user_usb_tb
 `define USB_BFM    u_usb_agent
 
-`include "DFFRAM/DFFRAM.v"
 `include "usb_agents.v"
 `include "test_control.v"
 `include "usb1d_defines.v"
 `include "usbd_files.v"
 
+`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+
 module user_usb_tb;
 
 parameter  USB_HPER   = 10.4167; // 48Mhz Half cycle
-parameter  USER2_HPER = 2.6042; // 192Mhz Half cycle
+parameter  USER2_HPER = 2.7777; // 180Mhz Half cycle
 
 	reg clock;
 	reg user_clock2;
@@ -134,7 +135,12 @@
 	`ifdef WFDUMP
 	   initial begin
 	   	$dumpfile("simx.vcd");
-	   	$dumpvars(5, user_usb_tb);
+	   	$dumpvars(0, user_usb_tb);
+	   	//$dumpvars(1, user_usb_tb.u_top);
+	   	//$dumpvars(1, user_usb_tb.u_top.u_uart_i2c_usb_spi);
+	   	//$dumpvars(0, user_usb_tb.u_top.u_uart_i2c_usb_spi.u_usb_host);
+	   	//$dumpvars(0, user_usb_tb.u_top.u_intercon);
+	   	//$dumpvars(0, user_usb_tb.u_top.u_wb_host);
 	   end
        `endif
 
@@ -165,8 +171,9 @@
 	        repeat (10) @(posedge clock);
 		$display("Monitor: Standalone User Risc Boot Test Started");
 
-		// Remove Wb Reset
-		wb_user_core_write('h3080_0000,'h1);
+         
+		// Remove Wb/PinMux Reset
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
 
                 // Enable SPI Multi Functional Ports
                 wb_user_core_write(`ADDR_SPACE_PINMUX+`PINMUX_GPIO_MULTI_FUNC,'h400);
@@ -174,8 +181,10 @@
 	        repeat (2) @(posedge clock);
 		#1;
          
-	        // Set USB clock : 192/4 = 48Mhz	
-                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,{8'h82,4'h0,8'h0,4'h0,8'h01});
+                // Remove Wb/PinMux Reset
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
+	        // Set USB clock : 180/3 = 60Mhz	
+                wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_CLK_CTRL2,{8'h0,8'h61,8'h0,8'h0});
 
                 // Remove the reset
 		// Remove WB and SPI/UART Reset, Keep CORE under Reset
@@ -269,7 +278,7 @@
 // Full Speed Device Indication
 
 pullup(usbd_txdp); 
-//pulldown(usbd_txdn);
+pulldown(usbd_txdn);
 
 usb1d_top u_usb_top(
 
@@ -451,6 +460,7 @@
   wbd_ext_cyc_i ='h1;  // strobe/request
   wbd_ext_stb_i ='h1;  // strobe/request
   wait(wbd_ext_ack_o == 1);
+  repeat (1) @(negedge clock);
   data  = wbd_ext_dat_o;  
   repeat (1) @(posedge clock);
   #1;
@@ -502,29 +512,21 @@
 
 `ifdef GL
 
-wire        wbd_spi_stb_i   = u_top.u_spi_master.wbd_stb_i;
-wire        wbd_spi_ack_o   = u_top.u_spi_master.wbd_ack_o;
-wire        wbd_spi_we_i    = u_top.u_spi_master.wbd_we_i;
-wire [31:0] wbd_spi_adr_i   = u_top.u_spi_master.wbd_adr_i;
-wire [31:0] wbd_spi_dat_i   = u_top.u_spi_master.wbd_dat_i;
-wire [31:0] wbd_spi_dat_o   = u_top.u_spi_master.wbd_dat_o;
-wire [3:0]  wbd_spi_sel_i   = u_top.u_spi_master.wbd_sel_i;
+wire        wbd_spi_stb_i   = u_top.u_qspi_master.wbd_stb_i;
+wire        wbd_spi_ack_o   = u_top.u_qspi_master.wbd_ack_o;
+wire        wbd_spi_we_i    = u_top.u_qspi_master.wbd_we_i;
+wire [31:0] wbd_spi_adr_i   = u_top.u_qspi_master.wbd_adr_i;
+wire [31:0] wbd_spi_dat_i   = u_top.u_qspi_master.wbd_dat_i;
+wire [31:0] wbd_spi_dat_o   = u_top.u_qspi_master.wbd_dat_o;
+wire [3:0]  wbd_spi_sel_i   = u_top.u_qspi_master.wbd_sel_i;
 
-wire        wbd_sdram_stb_i = u_top.u_sdram_ctrl.wb_stb_i;
-wire        wbd_sdram_ack_o = u_top.u_sdram_ctrl.wb_ack_o;
-wire        wbd_sdram_we_i  = u_top.u_sdram_ctrl.wb_we_i;
-wire [31:0] wbd_sdram_adr_i = u_top.u_sdram_ctrl.wb_addr_i;
-wire [31:0] wbd_sdram_dat_i = u_top.u_sdram_ctrl.wb_dat_i;
-wire [31:0] wbd_sdram_dat_o = u_top.u_sdram_ctrl.wb_dat_o;
-wire [3:0]  wbd_sdram_sel_i = u_top.u_sdram_ctrl.wb_sel_i;
-
-wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb.reg_cs;
-wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb.reg_ack;
-wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb.reg_wr;
-wire [7:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb.reg_addr;
-wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb.reg_wdata;
-wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb.reg_rdata;
-wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb.reg_be;
+wire        wbd_uart_stb_i  = u_top.u_uart_i2c_usb_spi.reg_cs;
+wire        wbd_uart_ack_o  = u_top.u_uart_i2c_usb_spi.reg_ack;
+wire        wbd_uart_we_i   = u_top.u_uart_i2c_usb_spi.reg_wr;
+wire [8:0]  wbd_uart_adr_i  = u_top.u_uart_i2c_usb_spi.reg_addr;
+wire [7:0]  wbd_uart_dat_i  = u_top.u_uart_i2c_usb_spi.reg_wdata;
+wire [7:0]  wbd_uart_dat_o  = u_top.u_uart_i2c_usb_spi.reg_rdata;
+wire        wbd_uart_sel_i  = u_top.u_uart_i2c_usb_spi.reg_be;
 
 `endif
 

diff --git a/verilog/dv/wb_port/Makefile b/verilog/dv/wb_port/Makefile
index b05a05f..0a94555 100644
--- a/verilog/dv/wb_port/Makefile
+++ b/verilog/dv/wb_port/Makefile

@@ -51,7 +51,8 @@
 ## Compiler Information 
 #######################################################################
 
-export GCC_PATH?=      $(TOOLS)/bin
+export TOOLS     ?=  /opt/riscv64i 
+export GCC_PATH  ?=  $(TOOLS)/bin
 export GCC_PREFIX?=    riscv64-unknown-linux-gnu
 
 
@@ -153,26 +154,26 @@
 ## RTL
 ifeq ($(SIM),RTL)
    ifeq ($(DUMP),OFF)
-	iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+	iverilog -g2005-sv -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
         -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
         -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
     else  
-	iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+	iverilog -g2005-sv -DWFDUMP -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
         -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
         -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
    endif
-endif 
+endif
 
-## GL
+##GL
 ifeq ($(SIM),GL)
-    ifeq ($(CONFIG),caravel_user_project)
-		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+   ifeq ($(DUMP),OFF)
+	iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
         -f$(VERILOG_PATH)/includes/includes.gl.caravel \
         -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
     else
-		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
-        -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \
-		-f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $<
+	iverilog -Ttyp -DWFDUMP -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#0.1 \
+        -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
     endif
 endif 
 

diff --git a/verilog/dv/wb_port/wb_port.c b/verilog/dv/wb_port/wb_port.c
index f148932..c626610 100644
--- a/verilog/dv/wb_port/wb_port.c
+++ b/verilog/dv/wb_port/wb_port.c

@@ -57,7 +57,7 @@
 	/* Set up the housekeeping SPI to be connected internally so	*/
 	/* that external pin changes don't affect it.			*/
 
-    reg_spi_enable = 1;
+    reg_spi_enable = 0;
     reg_wb_enable = 1;
 	// reg_spimaster_config = 0xa002;	// Enable, prescaler = 2,
                                         // connect to housekeeping SPI

diff --git a/verilog/dv/wb_port/wb_port_tb.v b/verilog/dv/wb_port/wb_port_tb.v
index fdbbf92..ba2cae8 100644
--- a/verilog/dv/wb_port/wb_port_tb.v
+++ b/verilog/dv/wb_port/wb_port_tb.v

@@ -24,7 +24,7 @@
 	reg power1, power2;
 	reg power3, power4;
 
-	wire gpio;
+	tri gpio;
 	wire [37:0] mprj_io;
 	wire [7:0] mprj_io_0;
 	wire [15:0] checkbits;
@@ -43,14 +43,21 @@
 		clock = 0;
 	end
 
+pullup(mprj_io[3]); 
+
 	`ifdef WFDUMP
 	initial begin
 		$dumpfile("simx.vcd");
 		$dumpvars(1, wb_port_tb);
-		//$dumpvars(0, wb_port_tb.uut.soc);
-		//$dumpvars(1, wb_port_tb.uut.mprj);
+		$dumpvars(1, wb_port_tb.uut);
+		$dumpvars(1, wb_port_tb.uut.mgmt_buffers);
+		$dumpvars(1, wb_port_tb.uut.housekeeping);
+		$dumpvars(1, wb_port_tb.uut.pll);
+		$dumpvars(1, wb_port_tb.uut.soc);
+		$dumpvars(1, wb_port_tb.uut.soc.core);
+		$dumpvars(1, wb_port_tb.uut.mprj);
 		$dumpvars(1, wb_port_tb.uut.mprj.u_wb_host);
-		$dumpvars(2, wb_port_tb.uut.mprj.u_pinmux);
+		//$dumpvars(2, wb_port_tb.uut.mprj.u_pinmux);
 	end
        `endif
 

diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project
new file mode 100644
index 0000000..ef76a58
--- /dev/null
+++ b/verilog/includes/includes.gl.caravel_user_project

@@ -0,0 +1,178 @@
+# Caravel user project includes
++define+UNIT_DELAY=#0.1
++incdir+$(USER_PROJECT_VERILOG)/rtl/
++incdir+$(USER_PROJECT_VERILOG)/rtl/i2cm/src/includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/usb1_host/src/includes
++incdir+$(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/includes
++incdir+$(USER_PROJECT_VERILOG)/dv/bfm
++incdir+$(USER_PROJECT_VERILOG)/dv/model
++incdir+$(USER_PROJECT_VERILOG)/dv/agents
+$(USER_PROJECT_VERILOG)/rtl/user_reg_map.v
+
+##################################################
+### USER PROJECT RTL
+##################################################
+#ifdef USER_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_top_wb.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v
+#endif
+
+##################################################
+### YCR INTERFACE
+##################################################
+#ifdef YCR_INTF_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/dcache_top.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/icache_top.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/lib/ycr_async_wbb.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_dmem_wb.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_intf.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/ycr_intf.v
+#endif
+##################################################
+### YCR INTER CONNECT
+##################################################
+#ifdef YCR_ICONNECT_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_iconnect.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_cross_bar.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_router.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_dmem_router.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_tcm.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_timer.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/lib/ycr_arb.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/ycr_iconnect.v
+#endif
+
+
+##################################################
+### YCR CORE
+##################################################
+#ifdef YCR_CORE_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_top.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_core_top.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_dm.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_tapc_synchronizer.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_clk_ctrl.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_scu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_tapc.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_tapc_shift_reg.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_dmi.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ifu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_idu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_exu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mprf.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_csr.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ialu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mul.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_div.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_lsu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_hdu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_tdu.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_ipic.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/ycr_core_top.v
+#endif
+##################################################
+### QSPIM
+##################################################
+#ifdef QSPIM_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_top.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_if.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_regs.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_fifo.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_clkgen.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_ctrl.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_rx.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/qspim/src/qspim_tx.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/qspim_top.v
+#endif
+
+
+##################################################
+### WB_HOST
+##################################################
+#ifdef WB_HOST_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/wb_host/src/wb_host.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart_msg_handler.v
+#else
+$(USER_PROJECT_VERILOG)/gl/wb_host.v
+#endif
+
+##################################################
+### PINMUX
+##################################################
+#ifdef PINMUX_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pinmux_reg.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/gpio_intr.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/pwm.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/pinmux/src/timer.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/pinmux.v
+#endif
+
+##################################################
+### UART
+##################################################
+#ifdef UART_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_core.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_cfg.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_bit_ctrl.v
+#-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_byte_ctrl.v
+#-v $(USER_PROJECT_VERILOG)/rtl/i2cm/src/core/i2cm_top.v
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_core.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc16.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_crc5.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_fifo.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/core/usbh_sie.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_fs_phy.v
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/phy/usb_transceiver.v
+#-v $(USER_PROJECT_VERILOG)/rtl/usb1_host/src/top/usb1_host.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_top.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_ctl.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_if.sv 
+#-v $(USER_PROJECT_VERILOG)/rtl/sspim/src/sspim_cfg.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/uart_i2c_usb_spi_top.v
+#endif
+
+##################################################
+### WISHBONE INTERCONNECT
+##################################################
+#ifdef WB_INTER_RTL
+#-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_slave_port.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_interconnect.sv
+#else
+$(USER_PROJECT_VERILOG)/gl/wb_interconnect.v
+#endif
+
+#-v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_txfsm.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/uart/src/uart_rxfsm.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_sram_mux.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/core/primitives/ycr_reset_cells.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr2c/src/top/ycr_req_retiming.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_wbb.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo2.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo_th.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_skew_adjust.gv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/reset_sync.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/ctech_cells.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_fifo.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_wb.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/async_reg_bus.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/clk_ctl.v
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/registers.v
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/double_sync_low.v
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type1.sv
+#-v $(USER_PROJECT_VERILOG)/rtl/lib/pulse_gen_type2.sv

diff --git a/verilog/includes/includes.gl.lib b/verilog/includes/includes.gl.lib
new file mode 100644
index 0000000..d82a5c2
--- /dev/null
+++ b/verilog/includes/includes.gl.lib

@@ -0,0 +1,11 @@
+###########################################################
+# STD CELLS - they need to be below the defines.v files 
+###########################################################
+-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v
+-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v
+-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
+-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v
+-v $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v
+
+$(USER_PROJECT_VERILOG)/gl/digital_pll.v

diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 882391f..5802940 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project

@@ -59,47 +59,53 @@
 -v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_arb.sv
 -v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_slave_port.sv
 -v $(USER_PROJECT_VERILOG)/rtl/wb_interconnect/src/wb_interconnect.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_hdu.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_tdu.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_ipic.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_csr.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_exu.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_ialu.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_idu.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_ifu.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_lsu.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_mprf.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_mul.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_div.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_top.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/primitives/ycr1_reset_cells.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/primitives/ycr1_cg.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_clk_ctrl.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_tapc_shift_reg.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_tapc.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_tapc_synchronizer.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_core_top.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_dm.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_dmi.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr1_scu.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_imem_router.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_dmem_router.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_dp_memory.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_tcm_router.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_timer.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_dmem_wb.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_imem_wb.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_intf.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_top_wb.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_icache_router.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr1_dcache_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_hdu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_tdu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_ipic.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_csr.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_exu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ialu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_idu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_ifu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_lsu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mprf.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_mul.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_div.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/pipeline/ycr_pipe_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/primitives/ycr_cg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_clk_ctrl.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_tapc_shift_reg.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_tapc.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_tapc_synchronizer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_core_top.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_dm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_dmi.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/core/ycr_scu.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_imem_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_dmem_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_dp_memory.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_tcm.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_timer.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_dmem_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_imem_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_intf.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_sram_mux.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_iconnect.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_cross_bar.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_top_wb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_icache_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_dcache_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/top/ycr_req_retiming.sv
 -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/icache_top.sv
 -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv
 -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv
 -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv
 -v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/cache/src/core/dcache_top.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/lib/ycr1_async_wbb.sv
--v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/lib/ycr1_arb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/lib/ycr_async_wbb.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr1c/src/lib/ycr_arb.sv
+
 -v $(USER_PROJECT_VERILOG)/rtl/lib/sync_fifo.sv
 -v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2wb.sv 
 -v $(USER_PROJECT_VERILOG)/rtl/uart2wb/src/uart2_core.sv 

diff --git a/verilog/includes/includes.rtl.lib b/verilog/includes/includes.rtl.lib
new file mode 100644
index 0000000..5045805
--- /dev/null
+++ b/verilog/includes/includes.rtl.lib

@@ -0,0 +1,3 @@
+-v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll_controller.v
+-v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/digital_pll.v
+-v $(USER_PROJECT_VERILOG)/rtl/digital_pll/src/ring_osc2x13.v

diff --git a/verilog/rtl/digital_pll/src/digital_pll.v b/verilog/rtl/digital_pll/src/digital_pll.v
new file mode 100644
index 0000000..f5400d8
--- /dev/null
+++ b/verilog/rtl/digital_pll/src/digital_pll.v

@@ -0,0 +1,68 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+// Digital PLL (ring oscillator + controller)
+// Technically this is a frequency locked loop, not a phase locked loop.
+
+module digital_pll(
+`ifdef USE_POWER_PINS
+    VPWR,
+    VGND,
+`endif
+    resetb, enable, osc, clockp, div, dco, ext_trim);
+
+`ifdef USE_POWER_PINS
+    input VPWR;
+    input VGND;
+`endif
+
+    input	 resetb;	// Sense negative reset
+    input	 enable;	// Enable PLL
+    input	 osc;		// Input oscillator to match
+    input [4:0]	 div;		// PLL feedback division ratio
+    input 	 dco;		// Run in DCO mode
+    input [25:0] ext_trim;	// External trim for DCO mode
+
+    output [1:0] clockp;	// Two 90 degree clock phases
+
+    wire [25:0]  itrim;		// Internally generated trim bits
+    wire [25:0]  otrim;		// Trim bits applied to the ring oscillator
+    wire	 creset;	// Controller reset
+    wire	 ireset;	// Internal reset (external reset OR disable)
+
+    assign ireset = ~resetb | ~enable;
+
+    // In DCO mode: Hold controller in reset and apply external trim value
+
+    assign itrim = (dco == 1'b0) ? otrim : ext_trim;
+    assign creset = (dco == 1'b0) ? ireset : 1'b1;
+
+    ring_osc2x13 ringosc (
+        .reset(ireset),
+        .trim(itrim),
+        .clockp(clockp)
+    );
+
+    digital_pll_controller pll_control (
+        .reset(creset),
+        .clock(clockp[0]),
+        .osc(osc),
+        .div(div),
+        .trim(otrim)
+    );
+
+endmodule
+`default_nettype wire

diff --git a/verilog/rtl/digital_pll/src/digital_pll_controller.v b/verilog/rtl/digital_pll/src/digital_pll_controller.v
new file mode 100644
index 0000000..ae13d9d
--- /dev/null
+++ b/verilog/rtl/digital_pll/src/digital_pll_controller.v

@@ -0,0 +1,136 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+// (True) digital PLL
+//
+// Output goes to a trimmable ring oscillator (see documentation).
+// Ring oscillator should be trimmable to above and below maximum
+// ranges of the input.
+//
+// Input "osc" comes from a fixed clock source (e.g., crystal oscillator
+// output).
+//
+// Input "div" is the target number of clock cycles per oscillator cycle.
+// e.g., if div == 8 then this is an 8X PLL.
+//
+// Clock "clock" is the PLL output being trimmed.
+// (NOTE:  To be done:  Pass-through enable)
+//
+// Algorithm:
+//
+// 1) Trim is done by thermometer code.  Reset to the highest value
+//    in case the fastest rate clock is too fast for the logic.
+//
+// 2) Count the number of contiguous 1s and 0s in "osc"
+//    periods of the master clock.  If the count maxes out, it does
+//    not roll over.
+//
+// 3) Add the two counts together.
+//
+// 4) If the sum is less than div, then the clock is too slow, so
+//    decrease the trim code.  If the sum is greater than div, the
+//    clock is too fast, so increase the trim code.  If the sum
+//    is equal to div, the the trim code does not change.
+//
+
+module digital_pll_controller(reset, clock, osc, div, trim);
+    input reset;
+    input clock;
+    input osc;
+    input [4:0] div;
+    output [25:0] trim;		// Use ring_osc2x13, with 26 trim bits
+
+    wire [25:0] trim;
+    reg [2:0] oscbuf;
+    reg [2:0] prep;
+
+    reg [4:0] count0;
+    reg [4:0] count1;
+    reg [6:0] tval;	// Includes 2 bits fractional
+    wire [4:0] tint;	// Integer part of the above
+
+    wire [5:0] sum;
+
+    assign sum = count0 + count1;
+ 
+    // Integer to thermometer code (maybe there's an algorithmic way?)
+    assign tint = tval[6:2];
+                                     // |<--second-->|<-- first-->|
+    assign trim = (tint == 5'd0)  ? 26'b0000000000000_0000000000000 :
+          (tint == 5'd1)  ? 26'b0000000000000_0000000000001 :
+          (tint == 5'd2)  ? 26'b0000000000000_0000001000001 :
+          (tint == 5'd3)  ? 26'b0000000000000_0010001000001 :
+          (tint == 5'd4)  ? 26'b0000000000000_0010001001001 :
+          (tint == 5'd5)  ? 26'b0000000000000_0010101001001 :
+          (tint == 5'd6)  ? 26'b0000000000000_1010101001001 :
+          (tint == 5'd7)  ? 26'b0000000000000_1010101101001 :
+          (tint == 5'd8)  ? 26'b0000000000000_1010101101101 :
+          (tint == 5'd9)  ? 26'b0000000000000_1011101101101 :
+          (tint == 5'd10) ? 26'b0000000000000_1011101111101 :
+          (tint == 5'd11) ? 26'b0000000000000_1111101111101 :
+          (tint == 5'd12) ? 26'b0000000000000_1111101111111 :
+          (tint == 5'd13) ? 26'b0000000000000_1111111111111 :
+          (tint == 5'd14) ? 26'b0000000000001_1111111111111 :
+          (tint == 5'd15) ? 26'b0000001000001_1111111111111 :
+          (tint == 5'd16) ? 26'b0010001000001_1111111111111 :
+          (tint == 5'd17) ? 26'b0010001001001_1111111111111 :
+          (tint == 5'd18) ? 26'b0010101001001_1111111111111 :
+          (tint == 5'd19) ? 26'b1010101001001_1111111111111 :
+          (tint == 5'd20) ? 26'b1010101101001_1111111111111 :
+          (tint == 5'd21) ? 26'b1010101101101_1111111111111 :
+          (tint == 5'd22) ? 26'b1011101101101_1111111111111 :
+          (tint == 5'd23) ? 26'b1011101111101_1111111111111 :
+          (tint == 5'd24) ? 26'b1111101111101_1111111111111 :
+          (tint == 5'd25) ? 26'b1111101111111_1111111111111 :
+                    26'b1111111111111_1111111111111;
+   
+    always @(posedge clock or posedge reset) begin
+    if (reset == 1'b1) begin
+        tval <= 7'd0;	// Note:  trim[0] must be zero for startup to work.
+        oscbuf <= 3'd0;
+        prep <= 3'd0;
+        count0 <= 5'd0;
+        count1 <= 5'd0;
+
+    end else begin
+        oscbuf <= {oscbuf[1:0], osc};
+
+        if (oscbuf[2] != oscbuf[1]) begin
+        count1 <= count0;
+        count0 <= 5'b00001;
+        prep <= {prep[1:0], 1'b1};
+
+        if (prep == 3'b111) begin
+            if (sum > div) begin
+		if (tval < 127) begin
+            	    tval <= tval + 1;
+		end
+            end else if (sum < div) begin
+		if (tval > 0) begin
+            	    tval <= tval - 1;
+		end
+            end
+        end
+        end else begin
+        if (count0 != 5'b11111) begin
+                count0 <= count0 + 1;
+        end
+        end
+    end
+    end
+
+endmodule	// digital_pll_controller
+`default_nettype wire

diff --git a/verilog/rtl/digital_pll/src/ring_osc2x13.v b/verilog/rtl/digital_pll/src/ring_osc2x13.v
new file mode 100644
index 0000000..f20110e
--- /dev/null
+++ b/verilog/rtl/digital_pll/src/ring_osc2x13.v

@@ -0,0 +1,250 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+// Tunable ring oscillator---synthesizable (physical) version.
+//
+// NOTE:  This netlist cannot be simulated correctly due to lack
+// of accurate timing in the digital cell verilog models.
+
+module delay_stage(in, trim, out);
+    input in;
+    input [1:0] trim;
+    output out;
+
+    wire d0, d1, d2, ts;
+
+    sky130_fd_sc_hd__clkbuf_2 delaybuf0 (
+	.A(in),
+	.X(ts)
+    );
+
+    sky130_fd_sc_hd__clkbuf_1 delaybuf1 (
+	.A(ts),
+	.X(d0)
+    );
+
+    sky130_fd_sc_hd__einvp_2 delayen1 (
+	.A(d0),
+	.TE(trim[1]),
+	.Z(d1)
+    );
+
+    sky130_fd_sc_hd__einvn_4 delayenb1 (
+	.A(ts),
+	.TE_B(trim[1]),
+	.Z(d1)
+    );
+
+    sky130_fd_sc_hd__clkinv_1 delayint0 (
+	.A(d1),
+	.Y(d2)
+    );
+
+    sky130_fd_sc_hd__einvp_2 delayen0 (
+	.A(d2),
+	.TE(trim[0]),
+	.Z(out)
+    );
+
+    sky130_fd_sc_hd__einvn_8 delayenb0 (
+	.A(ts),
+	.TE_B(trim[0]),
+	.Z(out)
+    );
+
+endmodule
+
+module start_stage(in, trim, reset, out);
+    input in;
+    input [1:0] trim;
+    input reset;
+    output out;
+
+    wire d0, d1, d2, ctrl0, one;
+
+    sky130_fd_sc_hd__clkbuf_1 delaybuf0 (
+	.A(in),
+	.X(d0)
+    );
+
+    sky130_fd_sc_hd__einvp_2 delayen1 (
+	.A(d0),
+	.TE(trim[1]),
+	.Z(d1)
+    );
+
+    sky130_fd_sc_hd__einvn_4 delayenb1 (
+	.A(in),
+	.TE_B(trim[1]),
+	.Z(d1)
+    );
+
+    sky130_fd_sc_hd__clkinv_1 delayint0 (
+	.A(d1),
+	.Y(d2)
+    );
+
+    sky130_fd_sc_hd__einvp_2 delayen0 (
+	.A(d2),
+	.TE(trim[0]),
+	.Z(out)
+    );
+
+    sky130_fd_sc_hd__einvn_8 delayenb0 (
+	.A(in),
+	.TE_B(ctrl0),
+	.Z(out)
+    );
+
+    sky130_fd_sc_hd__einvp_1 reseten0 (
+	.A(one),
+	.TE(reset),
+	.Z(out)
+    );
+
+    sky130_fd_sc_hd__or2_2 ctrlen0 (
+	.A(reset),
+	.B(trim[0]),
+	.X(ctrl0)
+    );
+
+    sky130_fd_sc_hd__conb_1 const1 (
+	.HI(one),
+	.LO()
+    );
+
+endmodule
+
+// Ring oscillator with 13 stages, each with two trim bits delay
+// (see above).  Trim is not binary:  For trim[1:0], lower bit
+// trim[0] is primary trim and must be applied first;  upper
+// bit trim[1] is secondary trim and should only be applied
+// after the primary trim is applied, or it has no effect.
+//
+// Total effective number of inverter stages in this oscillator
+// ranges from 13 at trim 0 to 65 at trim 24.  The intention is
+// to cover a range greater than 2x so that the midrange can be
+// reached over all PVT conditions.
+//
+// Frequency of this ring oscillator under SPICE simulations at
+// nominal PVT is maximum 214 MHz (trim 0), minimum 90 MHz (trim 24).
+
+module ring_osc2x13(reset, trim, clockp);
+    input reset;
+    input [25:0] trim;
+    output[1:0] clockp;
+
+`ifdef FUNCTIONAL	// i.e., behavioral model below
+
+    reg [1:0] clockp;
+    reg hiclock;
+    integer i;
+    real delay;
+    wire [5:0] bcount;
+
+    assign bcount = trim[0] + trim[1] + trim[2]
+		+ trim[3] + trim[4] + trim[5] + trim[6] + trim[7]
+		+ trim[8] + trim[9] + trim[10] + trim[11] + trim[12]
+		+ trim[13] + trim[14] + trim[15] + trim[16] + trim[17]
+		+ trim[18] + trim[19] + trim[20] + trim[21] + trim[22]
+		+ trim[23] + trim[24] + trim[25];
+
+    initial begin
+	hiclock <= 1'b0;
+	delay = 3.0;
+    end
+
+    // Fastest operation is 214 MHz = 4.67ns
+    // Delay per trim is 0.02385
+    // Run "hiclock" at 2x this rate, then use positive and negative
+    // edges to derive the 0 and 90 degree phase clocks.
+
+    always #delay begin
+	hiclock <= (hiclock === 1'b0);
+    end
+
+    always @(trim) begin
+    	// Implement trim as a variable delay, one delay per trim bit
+	delay = 1.168 + 0.012 * $itor(bcount);
+    end
+
+    always @(posedge hiclock or posedge reset) begin
+	if (reset == 1'b1) begin
+	    clockp[0] <= 1'b0;
+	end else begin
+	    clockp[0] <= (clockp[0] === 1'b0);
+	end
+    end
+
+    always @(negedge hiclock or posedge reset) begin
+	if (reset == 1'b1) begin
+	    clockp[1] <= 1'b0;
+	end else begin
+	    clockp[1] <= (clockp[1] === 1'b0);
+	end
+    end
+
+`else 			// !FUNCTIONAL;  i.e., gate level netlist below
+
+    wire [1:0] clockp;
+    wire [12:0] d;
+    wire [1:0] c;
+
+    // Main oscillator loop stages
+ 
+    genvar i;
+    generate
+	for (i = 0; i < 12; i = i + 1) begin : dstage
+	    delay_stage id (
+		.in(d[i]),
+		.trim({trim[i+13], trim[i]}),
+		.out(d[i+1])
+	    );
+	end
+    endgenerate
+
+    // Reset/startup stage
+ 
+    start_stage iss (
+	.in(d[12]),
+	.trim({trim[25], trim[12]}),
+	.reset(reset),
+	.out(d[0])
+    );
+
+    // Buffered outputs a 0 and 90 degrees phase (approximately)
+
+    sky130_fd_sc_hd__clkinv_2 ibufp00 (
+	.A(d[0]),
+	.Y(c[0])
+    );
+    sky130_fd_sc_hd__clkinv_8 ibufp01 (
+	.A(c[0]),
+	.Y(clockp[0])
+    );
+    sky130_fd_sc_hd__clkinv_2 ibufp10 (
+	.A(d[6]),
+	.Y(c[1])
+    );
+    sky130_fd_sc_hd__clkinv_8 ibufp11 (
+	.A(c[1]),
+	.Y(clockp[1])
+    );
+
+`endif // !FUNCTIONAL
+
+endmodule
+`default_nettype wire

diff --git a/verilog/rtl/lib/ctech_cells.sv b/verilog/rtl/lib/ctech_cells.sv
index c9528de..bd34f11 100644
--- a/verilog/rtl/lib/ctech_cells.sv
+++ b/verilog/rtl/lib/ctech_cells.sv

@@ -1,42 +1,72 @@
 
-module ctech_mux2x1 (
-	input  logic A0,
-	input  logic A1,
+module ctech_mux2x1 #(parameter WB = 1) (
+	input  logic [WB-1:0] A0,
+	input  logic [WB-1:0] A1,
 	input  logic S ,
-	output logic X);
+	output logic [WB-1:0] X);
 
 `ifndef SYNTHESIS
 assign X = (S) ? A1 : A0;
 `else 
-sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+    generate
+       if (WB > 1)
+       begin : bus_
+         genvar tcnt;
+         for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_
+             sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S  (S), .X (X[tcnt]));
+         end
+       end else begin
+          sky130_fd_sc_hd__mux2_8 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+       end
+    endgenerate
 `endif
 
 endmodule
 
-module ctech_mux2x1_2 (
-	input  logic A0,
-	input  logic A1,
+module ctech_mux2x1_2 #(parameter WB = 1) (
+	input  logic [WB-1:0] A0,
+	input  logic [WB-1:0] A1,
 	input  logic S ,
-	output logic X);
+	output logic [WB-1:0] X);
 
 `ifndef SYNTHESIS
 assign X = (S) ? A1 : A0;
 `else 
-sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+    generate
+       if (WB > 1)
+       begin : bus_
+         genvar tcnt;
+         for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_
+             sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S  (S), .X (X[tcnt]));
+         end
+       end else begin 
+          sky130_fd_sc_hd__mux2_2 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+       end
+    endgenerate
 `endif
 
 endmodule
 
-module ctech_mux2x1_4 (
-	input  logic A0,
-	input  logic A1,
+module ctech_mux2x1_4 #(parameter WB = 1) (
+	input  logic [WB-1:0] A0,
+	input  logic [WB-1:0] A1,
 	input  logic S ,
-	output logic X);
+	output logic [WB-1:0] X);
 
 `ifndef SYNTHESIS
 assign X = (S) ? A1 : A0;
 `else 
-sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+    generate
+       if (WB > 1)
+       begin : bus_
+         genvar tcnt;
+         for (tcnt = 0; $unsigned(tcnt) < WB; tcnt=tcnt+1) begin : bit_
+             sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0[tcnt]), .A1 (A1[tcnt]), .S  (S), .X (X[tcnt]));
+         end
+       end else begin
+          sky130_fd_sc_hd__mux2_4 u_mux (.A0 (A0), .A1 (A1), .S  (S), .X (X));
+       end
+    endgenerate
 `endif
 
 endmodule

diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv
index 78e63ae..b9949c5 100755
--- a/verilog/rtl/pinmux/src/pinmux.sv
+++ b/verilog/rtl/pinmux/src/pinmux.sv

@@ -131,7 +131,9 @@
                        input logic              uartm_txd  ,       
 
 		       output  logic           pulse1m_mclk,
-	               output  logic [31:0]    pinmux_debug
+	               output  logic [31:0]    pinmux_debug,
+
+		       input   logic           dbg_clk_mon
 
    ); 
 
@@ -503,10 +505,10 @@
 *   Pin-6        PD4/TXD[1]          digital_io[5]
 *   Pin-7        VCC                  -
 *   Pin-8        GND                  -
-*   Pin-9        PB6/XTAL1/TOSC1     digital_io[6]
+*   Pin-9        PB6/XTAL1/TOSC1           digital_io[6]
 *   Pin-10       PB7/XTAL2/TOSC2           digital_io[7]
 *   Pin-11       PD5/SS[3]/OC0B(PWM1)/T1   digital_io[8]
-*   Pin-12       PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9] /analog_io[2]
+*   Pin-12       PD6/SS[2]/OC0A(PWM2)/AIN0 digital_io[9]/analog_io[2]
 *   Pin-13       PD7/A1N1                  digital_io[10]/analog_io[3]
 *   Pin-14       PB0/CLKO/ICP1             digital_io[11]
 *   Pin-15       PB1/SS[1]OC1A(PWM3)       digital_io[12]
@@ -515,7 +517,7 @@
 *   Pin-18       PB4/MISO                  digital_io[15]
 *   Pin-19       PB5/SCK                   digital_io[16]
 *   Pin-20       AVCC                -
-*   Pin-21       AREF                analog_io[10]
+*   Pin-21       AREF                      analog_io[10]
 *   Pin-22       GND                 -
 *   Pin-23       PC0/ADC0            digital_io[18]/analog_io[11]
 *   Pin-24       PC1/ADC1            digital_io[19]/analog_io[12]
@@ -534,7 +536,7 @@
 *                sflash_io1          digital_io[30]
 *                sflash_io2          digital_io[31]
 *                sflash_io3          digital_io[32]
-*                reserved            digital_io[33]
+*                dbg_clk_mon         digital_io[33]
 *                uartm_rxd           digital_io[34]
 *                uartm_txd           digital_io[35]
 *                usb_dp              digital_io[36]
@@ -758,8 +760,8 @@
      digital_io_out[31] = sflash_do[2] ;
      digital_io_out[32] = sflash_do[3] ;
                        
-     // Reserved
-     digital_io_out[33] = 1'b0;
+     // dbg_clk_mon - Pll clock output monitor
+     digital_io_out[33] = dbg_clk_mon;
 
      // UART MASTER I/f
      digital_io_out[34] = 1'b0         ; // RXD
@@ -874,7 +876,7 @@
      digital_io_oen[31] = sflash_oen[2];
      digital_io_oen[32] = sflash_oen[3];
                        
-     // Reserved
+     // dbg_clk_mon
      digital_io_oen[33] = 1'b0  ;
      // UART MASTER
      digital_io_oen[34] = 1'b1; // RXD

diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index c6b33af..7bab960 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv

@@ -716,7 +716,7 @@
 //-----------------------------------------
 // Software Reg-2, Release date: <DAY><MONTH><YEAR>
 // ----------------------------------------
-gen_32b_reg  #(32'h0604_2022) u_reg_23	(
+gen_32b_reg  #(32'h0306_2022) u_reg_23	(
 	      //List of Inputs
 	      .reset_n    (h_reset_n     ),
 	      .clk        (mclk          ),
@@ -729,9 +729,9 @@
 	      );
 
 //-----------------------------------------
-// Software Reg-3: Poject Revison 4.1 = 0004200
+// Software Reg-3: Poject Revison 4.5 = 0004500
 // ----------------------------------------
-gen_32b_reg  #(32'h0004_2000) u_reg_24	(
+gen_32b_reg  #(32'h0004_5000) u_reg_24	(
 	      //List of Inputs
 	      .reset_n    (h_reset_n     ),
 	      .clk        (mclk          ),

diff --git a/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
index d94013b..42a8cec 100644
--- a/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv
+++ b/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv

@@ -287,7 +287,7 @@
      //---------------------------------
      .reg_cs      (reg_spim_cs      ),
      .reg_wr      (reg_wr           ),
-     .reg_addr    (reg_addr         ),
+     .reg_addr    ({2'b0,reg_addr[5:0]} ),
      .reg_wdata   (reg_wdata        ),
      .reg_be      (reg_be           ),
 

diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 21ebfe2..400e4ad 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v

@@ -42,6 +42,9 @@
      `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
 
 
+     `ifndef FULL_CHIP_SIM 
+        `include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"
+     `endif
      `include "pinmux/src/pinmux.sv"
      `include "pinmux/src/pinmux_reg.sv"
      `include "pinmux/src/gpio_intr.sv"
@@ -106,55 +109,53 @@
      `include "wb_interconnect/src/wb_interconnect.sv"
 
 
-     `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_hdu.sv"
-     `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_tdu.sv"
-     `include "yifive/ycr1c/src/core/pipeline/ycr1_ipic.sv"
-     `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_csr.sv"
-     `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_exu.sv"
-     `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_ialu.sv"
-     `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_idu.sv"
-     `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_ifu.sv"
-     `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_lsu.sv"
-     `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_mprf.sv"
-     `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_mul.sv"
-     `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_div.sv"
-     `include "yifive/ycr1c/src/core/pipeline/ycr1_pipe_top.sv"
-     `include "yifive/ycr1c/src/core/primitives/ycr1_reset_cells.sv"
-     `include "yifive/ycr1c/src/core/primitives/ycr1_cg.sv"
-     `include "yifive/ycr1c/src/core/ycr1_clk_ctrl.sv"
-     `include "yifive/ycr1c/src/core/ycr1_tapc_shift_reg.sv"
-     `include "yifive/ycr1c/src/core/ycr1_tapc.sv"
-     `include "yifive/ycr1c/src/core/ycr1_tapc_synchronizer.sv"
-     `include "yifive/ycr1c/src/core/ycr1_core_top.sv"
-     `include "yifive/ycr1c/src/core/ycr1_dm.sv"
-     `include "yifive/ycr1c/src/core/ycr1_dmi.sv"
-     `include "yifive/ycr1c/src/core/ycr1_scu.sv"
-     `include "yifive/ycr1c/src/top/ycr1_imem_router.sv"
-     `include "yifive/ycr1c/src/top/ycr1_dmem_router.sv"
-     `include "yifive/ycr1c/src/top/ycr1_dp_memory.sv"
-     `include "yifive/ycr1c/src/top/ycr1_tcm_router.sv"
-     `include "yifive/ycr1c/src/top/ycr1_timer.sv"
-     `include "yifive/ycr1c/src/top/ycr1_dmem_wb.sv"
-     `include "yifive/ycr1c/src/top/ycr1_imem_wb.sv"
-     `include "yifive/ycr1c/src/top/ycr1_intf.sv"
-     `include "yifive/ycr1c/src/top/ycr1_top_wb.sv"
-     `include "yifive/ycr1c/src/top/ycr1_icache_router.sv"
-     `include "yifive/ycr1c/src/top/ycr1_dcache_router.sv"
+     `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_hdu.sv"
+     `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_tdu.sv"
+     `include "yifive/ycr1c/src/core/pipeline/ycr_ipic.sv"
+     `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_csr.sv"
+     `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_exu.sv"
+     `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_ialu.sv"
+     `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_idu.sv"
+     `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_ifu.sv"
+     `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_lsu.sv"
+     `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_mprf.sv"
+     `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_mul.sv"
+     `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_div.sv"
+     `include "yifive/ycr1c/src/core/pipeline/ycr_pipe_top.sv"
+     `include "yifive/ycr1c/src/core/primitives/ycr_reset_cells.sv"
+     `include "yifive/ycr1c/src/core/primitives/ycr_cg.sv"
+     `include "yifive/ycr1c/src/core/ycr_clk_ctrl.sv"
+     `include "yifive/ycr1c/src/core/ycr_tapc_shift_reg.sv"
+     `include "yifive/ycr1c/src/core/ycr_tapc.sv"
+     `include "yifive/ycr1c/src/core/ycr_tapc_synchronizer.sv"
+     `include "yifive/ycr1c/src/core/ycr_core_top.sv"
+     `include "yifive/ycr1c/src/core/ycr_dm.sv"
+     `include "yifive/ycr1c/src/core/ycr_dmi.sv"
+     `include "yifive/ycr1c/src/core/ycr_scu.sv"
+     `include "yifive/ycr1c/src/top/ycr_imem_router.sv"
+     `include "yifive/ycr1c/src/top/ycr_dmem_router.sv"
+     `include "yifive/ycr1c/src/top/ycr_dp_memory.sv"
+     `include "yifive/ycr1c/src/top/ycr_tcm.sv"
+     `include "yifive/ycr1c/src/top/ycr_timer.sv"
+     `include "yifive/ycr1c/src/top/ycr_dmem_wb.sv"
+     `include "yifive/ycr1c/src/top/ycr_imem_wb.sv"
+     `include "yifive/ycr1c/src/top/ycr_intf.sv"
+     `include "yifive/ycr1c/src/top/ycr_sram_mux.sv"
+     `include "yifive/ycr1c/src/top/ycr_router.sv"
+     `include "yifive/ycr1c/src/top/ycr_iconnect.sv"
+     `include "yifive/ycr1c/src/top/ycr_cross_bar.sv"
+     `include "yifive/ycr1c/src/top/ycr_top_wb.sv"
+     `include "yifive/ycr1c/src/top/ycr_req_retiming.sv"
      `include "yifive/ycr1c/src/cache/src/core/icache_top.sv"
      `include "yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv"
      `include "yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv"
      `include "yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv"
      `include "yifive/ycr1c/src/cache/src/core/dcache_top.sv"
-     `include "yifive/ycr1c/src/lib/ycr1_async_wbb.sv"
-     `include "yifive/ycr1c/src/lib/ycr1_arb.sv"
+     `include "yifive/ycr1c/src/lib/ycr_async_wbb.sv"
+     `include "yifive/ycr1c/src/lib/ycr_arb.sv"
 
      `include "lib/sync_fifo.sv"
 
-     // During Full Chip Sim, DFFRAM file already available in caravel file
-     // list
-     `ifndef FULL_CHIP_SIM 
-        `include "DFFRAM/DFFRAM.v"
-     `endif
 
     `include "uart2wb/src/uart2wb.sv" 
     `include "uart2wb/src/uart2_core.sv" 
@@ -166,4 +167,8 @@
      // standard cell + power pin
      `include "lib/clk_skew_adjust.gv"
      `include "lib/ctech_cells.sv"
+
+     `include "digital_pll/src/digital_pll_controller.v"
+     `include "digital_pll/src/digital_pll.v"
+     `include "digital_pll/src/ring_osc2x13.v"
 `endif

diff --git a/verilog/rtl/usb1_host/src/core/usbh_core.sv b/verilog/rtl/usb1_host/src/core/usbh_core.sv
index adffecb..91073cc 100644
--- a/verilog/rtl/usb1_host/src/core/usbh_core.sv
+++ b/verilog/rtl/usb1_host/src/core/usbh_core.sv

@@ -59,7 +59,7 @@
 // Params
 //-----------------------------------------------------------------
 #(
-     parameter USB_CLK_FREQ     = 48000000
+     parameter USB_CLK_FREQ     = 60000000
 )
 //-----------------------------------------------------------------
 // Ports

diff --git a/verilog/rtl/usb1_host/src/core/usbh_sie.sv b/verilog/rtl/usb1_host/src/core/usbh_sie.sv
index 0d046c0..39d10f9 100644
--- a/verilog/rtl/usb1_host/src/core/usbh_sie.sv
+++ b/verilog/rtl/usb1_host/src/core/usbh_sie.sv

@@ -54,7 +54,7 @@
 // Params
 //-----------------------------------------------------------------
 #(
-     parameter USB_CLK_FREQ     = 48000000
+     parameter USB_CLK_FREQ     = 60000000
 )
 //-----------------------------------------------------------------
 // Ports

diff --git a/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v b/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v
index c7ac174..f83656d 100644
--- a/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v
+++ b/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v

@@ -54,6 +54,13 @@
 //-----------------------------------------------------------------
 
 module usb_fs_phy
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+     parameter USB_CLK_FREQ     = 60000000
+)
+
 (
     // Inputs
      input           clk_i
@@ -87,6 +94,12 @@
 
 
 
+//-------------------------------------------------------------------------
+// For 60Mhz usb clock, data need to sample at once in 4 cycle (60/4 = 12Mhz)
+// For 48Mhz usb clock, data need to sample at once in 3 cycle (48/3 = 12Mhz)
+// ------------------------------------------------------------------------
+localparam SAMPLE_RATE       = (USB_CLK_FREQ == 60000000) ? 3'd4 : 3'd3;
+
 //-----------------------------------------------------------------
 // Wires / Registers
 //-----------------------------------------------------------------
@@ -454,31 +467,36 @@
 //-----------------------------------------------------------------
 // Sample Timer
 //-----------------------------------------------------------------
-reg [1:0] sample_cnt_q;
+reg [2:0] sample_cnt_q;
 reg       adjust_delayed_q;
 
 always @ (posedge clk_i or negedge rstn_i)
-if (!rstn_i)
-begin
-    sample_cnt_q        <= 2'd0;
+if (!rstn_i) begin
+    sample_cnt_q        <= 3'd0;
     adjust_delayed_q    <= 1'b0;
+end else begin
+   // Delayed adjustment
+   if (adjust_delayed_q)
+       adjust_delayed_q    <= 1'b0;
+   else if (bit_edge_w && (sample_cnt_q != 3'd0) && (state_q < STATE_TX_SYNC))
+       sample_cnt_q        <= 3'd0;
+   // Can't adjust sampling point now?
+   else if (bit_edge_w && (sample_cnt_q == 3'd0) && (state_q < STATE_TX_SYNC)) begin
+       // Want to reset sampling point but need to delay adjustment by 1 cycle!
+       adjust_delayed_q    <= 1'b1;
+       if(sample_cnt_q == SAMPLE_RATE) 
+           sample_cnt_q <= 'b0;
+        else
+          sample_cnt_q  <= sample_cnt_q + 'd1;
+   end else begin
+     if(sample_cnt_q == SAMPLE_RATE)
+         sample_cnt_q   <= 'b0;
+     else
+         sample_cnt_q   <= sample_cnt_q + 'd1;
+   end
 end
-// Delayed adjustment
-else if (adjust_delayed_q)
-    adjust_delayed_q    <= 1'b0;
-else if (bit_edge_w && (sample_cnt_q != 2'd0) && (state_q < STATE_TX_SYNC))
-    sample_cnt_q        <= 2'd0;
-// Can't adjust sampling point now?
-else if (bit_edge_w && (sample_cnt_q == 2'd0) && (state_q < STATE_TX_SYNC))
-begin
-    // Want to reset sampling point but need to delay adjustment by 1 cycle!
-    adjust_delayed_q    <= 1'b1;
-    sample_cnt_q        <= sample_cnt_q + 2'd1;
-end
-else
-    sample_cnt_q        <= sample_cnt_q + 2'd1;
 
-assign sample_w = (sample_cnt_q == 2'd0);
+assign sample_w = (sample_cnt_q == 'd0);
 
 //-----------------------------------------------------------------
 // NRZI Receiver

diff --git a/verilog/rtl/usb1_host/src/top/usb1_host.sv b/verilog/rtl/usb1_host/src/top/usb1_host.sv
index 6ee0ff5..3d8f8dd 100644
--- a/verilog/rtl/usb1_host/src/top/usb1_host.sv
+++ b/verilog/rtl/usb1_host/src/top/usb1_host.sv

@@ -37,7 +37,7 @@
 ////   2. usb1_core:  usb1 core                                   ////
 ////   3. usb1_host : usb phy                                     ////
 ////                                                              ////
-////   Assumptiom: usb_clk is 48Mhz                               ////
+////   Assumptiom: usb_clk is 60Mhz                               ////
 ////                                                              ////
 ////  To Do:                                                      ////
 ////    nothing                                                   ////
@@ -49,7 +49,15 @@
 ////                                                              ////
 //////////////////////////////////////////////////////////////////////
 
-module usb1_host (
+module usb1_host 
+//-----------------------------------------------------------------
+// Params
+//-----------------------------------------------------------------
+#(
+     parameter USB_CLK_FREQ     = 60000000
+)
+
+(
     input  logic           usb_clk_i   ,
     input  logic           usb_rstn_i  ,
 
@@ -112,13 +120,35 @@
     logic [31:0]           reg_rdata;
     logic                  reg_ack;
 
+    logic                  wbm_rst_ssn;
+    logic                  usb_rst_ssn;
 
 
+//###################################
+// Wishbone Reset Synchronization
+//###################################
+reset_sync  u_wb_rst (
+	      .scan_mode  (1'b0           ),
+              .dclk       (wbm_clk_i      ), // Destination clock domain
+	      .arst_n     (wbm_rst_n      ), // active low async reset
+              .srst_n     (wbm_rst_ssn    )
+          );
+
+//###################################
+// USB Reset Synchronization
+//###################################
+reset_sync  u_usb_rst (
+	      .scan_mode  (1'b0           ),
+              .dclk       (usb_clk_i      ), // Destination clock domain
+	      .arst_n     (usb_rstn_i     ), // active low async reset
+              .srst_n     (usb_rst_ssn    )
+          );
+
 async_wb  #(.AW (6))
      u_async_wb(
 
     // Master Port
-       .wbm_rst_n        (wbm_rst_n            ),  // Regular Reset signal
+       .wbm_rst_n        (wbm_rst_ssn          ),  // Regular Reset signal
        .wbm_clk_i        (wbm_clk_i            ),  // System clock
        .wbm_cyc_i        (wbm_stb_i            ),  // strobe/request
        .wbm_stb_i        (wbm_stb_i            ),  // strobe/request
@@ -131,7 +161,7 @@
        .wbm_err_o        (wbm_err_o            ),  // error
 
     // Slave Port
-       .wbs_rst_n        (usb_rstn_i           ),  // Regular Reset signal
+       .wbs_rst_n        (usb_rst_ssn          ),  // Regular Reset signal
        .wbs_clk_i        (usb_clk_i            ),  // System clock
        .wbs_cyc_o        (                     ),  // strobe/request
        .wbs_stb_o        (reg_cs               ),  // strobe/request
@@ -145,10 +175,10 @@
 
     );
 
-usbh_core  u_core (
+usbh_core  #(.USB_CLK_FREQ(USB_CLK_FREQ)) u_core (
     // Inputs
     .clk_i               (usb_clk_i           ),
-    .rstn_i              (usb_rstn_i          ),
+    .rstn_i              (usb_rst_ssn         ),
 
     .reg_cs              (reg_cs              ),
     .reg_wr              (reg_wr              ),
@@ -182,10 +212,10 @@
 
 
 
-usb_fs_phy  u_phy(
+usb_fs_phy  #(.USB_CLK_FREQ(USB_CLK_FREQ)) u_phy(
     // Inputs
          .clk_i               (usb_clk_i           ),
-         .rstn_i              (usb_rstn_i          ),
+         .rstn_i              (usb_rst_ssn         ),
          .utmi_data_out_i     (utmi_data_out_o     ),
          .utmi_txvalid_i      (utmi_txvalid_o      ),
          .utmi_op_mode_i      (utmi_op_mode_o      ),

diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 10cc6c4..d022dad 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v

@@ -204,6 +204,14 @@
 ////    4.2  April 6 2022, Dinesh A                               ////
 ////         1. SSPI CS# increased from 1 to 4                    ////
 ////         2. uart port increase to two                         ////
+////    4.3  May 24 2022, Dinesh A                                ////
+////         Re targetted the design to mpw-6 tools set and risc  ////
+////         core logic are timing optimized to 100mhz            ////
+////    4.4  May 29 2022, Dinesh A                                ////
+////         1. Digital PLL integrated and clock debug signal add ////
+////           @digitial io [33] port                             ////
+////    4.5  June 2 2022, Dinesh A                                ////
+////         1. DFFRAM Replaced by SRAM                           ////
 //////////////////////////////////////////////////////////////////////
 ////                                                              ////
 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
@@ -303,22 +311,20 @@
 wire                           wbd_riscv_dcache_lack_o                ; // last burst acknowlegement
 wire                           wbd_riscv_dcache_err_o                 ; // error
 
-// DFFRAM I/F
-
-wire                           dcache_dffram_clk0                     ; // CLK
-wire                           dcache_dffram_cs0                      ; // Chip Select
-wire    [7:0]                  dcache_dffram_addr0                    ; // Address
-wire    [3:0]                  dcache_dffram_wmask0                   ; // Write Mask
-wire    [31:0]                 dcache_dffram_din0                     ; // Write Data
-wire    [31:0]                 dcache_dffram_dout0                    ; // Read Data
-
-wire                           dcache_dffram_clk1                     ; // CLK
-wire                           dcache_dffram_cs1                      ; // Chip Select
-wire    [7:0]                  dcache_dffram_addr1                    ; // Address
-wire    [3:0]                  dcache_dffram_wmask1                   ; // Write Mask
-wire    [31:0]                 dcache_dffram_din1                     ; // Write Data
-wire    [31:0]                 dcache_dffram_dout1                    ; // Read Data
-
+// CACHE SRAM Memory I/F
+wire                           dcache_mem_clk0                        ; // CLK
+wire                           dcache_mem_csb0                        ; // CS#
+wire                           dcache_mem_web0                        ; // WE#
+wire   [8:0]                   dcache_mem_addr0                       ; // Address
+wire   [3:0]                   dcache_mem_wmask0                      ; // WMASK#
+wire   [31:0]                  dcache_mem_din0                        ; // Write Data
+wire   [31:0]                  dcache_mem_dout0                       ; // Read Data
+   
+// SRAM-0 PORT-1, IMEM I/F
+wire                           dcache_mem_clk1                        ; // CLK
+wire                           dcache_mem_csb1                        ; // CS#
+wire  [8:0]                    dcache_mem_addr1                       ; // Address
+wire  [31:0]                   dcache_mem_dout1                       ; // Read Data
 //---------------------------------------------------------------------
 // Wishbone Risc V Icache Memory Interface
 //---------------------------------------------------------------------
@@ -333,21 +339,20 @@
 wire                           wbd_riscv_icache_lack_o                ; // last burst acknowlegement
 wire                           wbd_riscv_icache_err_o                 ; // error
 
-// DFFRAM I/F
-
-wire                           icache_dffram_clk0                     ; // CLK
-wire                           icache_dffram_cs0                      ; // Chip Select
-wire    [7:0]                  icache_dffram_addr0                    ; // Address
-wire    [3:0]                  icache_dffram_wmask0                   ; // Write Mask
-wire    [31:0]                 icache_dffram_din0                     ; // Write Data
-wire    [31:0]                 icache_dffram_dout0                    ; // Read Data
-
-wire                           icache_dffram_clk1                     ; // CLK
-wire                           icache_dffram_cs1                      ; // Chip Select
-wire    [7:0]                  icache_dffram_addr1                    ; // Address
-wire    [3:0]                  icache_dffram_wmask1                   ; // Write Mask
-wire    [31:0]                 icache_dffram_din1                     ; // Write Data
-wire    [31:0]                 icache_dffram_dout1                    ; // Read Data
+// CACHE SRAM Memory I/F
+wire                           icache_mem_clk0                        ; // CLK
+wire                           icache_mem_csb0                        ; // CS#
+wire                           icache_mem_web0                        ; // WE#
+wire   [8:0]                   icache_mem_addr0                       ; // Address
+wire   [3:0]                   icache_mem_wmask0                      ; // WMASK#
+wire   [31:0]                  icache_mem_din0                        ; // Write Data
+// wire   [31:0]               icache_mem_dout0                       ; // Read Data
+   
+// SRAM-0 PORT-1, IMEM I/F
+wire                           icache_mem_clk1                        ; // CLK
+wire                           icache_mem_csb1                        ; // CS#
+wire  [8:0]                    icache_mem_addr1                       ; // Address
+wire  [31:0]                   icache_mem_dout1                       ; // Read Data
 
 //---------------------------------------------------------------------
 // RISC V Wishbone Data Memory Interface
@@ -449,6 +454,7 @@
 wire                           wbd_clk_spi                            ;
 wire                           wbd_clk_pinmux                         ;
 wire                           wbd_int_rst_n                          ;
+wire                           wbd_pll_rst_n                          ;
 
 wire [15:0]                    irq_lines                              ;
 wire                           soft_irq                               ;
@@ -456,7 +462,6 @@
 
 wire [7:0]                     cfg_glb_ctrl                           ;
 wire [31:0]                    cfg_clk_ctrl1                          ;
-wire [31:0]                    cfg_clk_ctrl2                          ;
 wire [3:0]                     cfg_cska_wi                            ; // clock skew adjust for wishbone interconnect
 wire [3:0]                     cfg_cska_wh                            ; // clock skew adjust for web host
 
@@ -494,6 +499,7 @@
 
 wire [31:0]                    spi_debug                              ;
 wire [31:0]                    pinmux_debug                           ;
+wire                           dbg_clk_mon                            ; // clock monitoring port
 wire [63:0]                    riscv_debug                            ;
 
 // SFLASH I/F
@@ -540,23 +546,37 @@
 wire                           pulse1m_mclk                           ;
 wire                           h_reset_n                              ;
 
-`ifndef YCR1_TCM_MEM
+`ifndef SCR1_TCM_MEM
+// SRAM-0 PORT-0 - DMEM I/F
+wire                           sram0_clk0                             ; // CLK
+wire                           sram0_csb0                             ; // CS#
+wire                           sram0_web0                             ; // WE#
+wire   [8:0]                   sram0_addr0                            ; // Address
+wire   [3:0]                   sram0_wmask0                           ; // WMASK#
+wire   [31:0]                  sram0_din0                             ; // Write Data
+wire   [31:0]                  sram0_dout0                            ; // Read Data
 
-// DFFRAM I/F
+// SRAM-0 PORT-1, IMEM I/F
+wire                           sram0_clk1                             ; // CLK
+wire                           sram0_csb1                             ; // CS#
+wire  [8:0]                    sram0_addr1                            ; // Address
+wire  [31:0]                   sram0_dout1                            ; // Read Data
 
-wire                           tcm_dffram_clk0                        ; // CLK
-wire                           tcm_dffram_cs0                         ; // Chip Select
-wire    [7:0]                  tcm_dffram_addr0                       ; // Address
-wire    [3:0]                  tcm_dffram_wmask0                      ; // Write Mask
-wire    [31:0]                 tcm_dffram_din0                        ; // Write Data
-wire    [31:0]                 tcm_dffram_dout0                       ; // Read Data
-   
-wire                           tcm_dffram_clk1                        ; // CLK
-wire                           tcm_dffram_cs1                         ; // Chip Select
-wire    [7:0]                  tcm_dffram_addr1                       ; // Address
-wire    [3:0]                  tcm_dffram_wmask1                      ; // Write Mask
-wire    [31:0]                 tcm_dffram_din1                        ; // Write Data
-wire    [31:0]                 tcm_dffram_dout1                       ; // Read Data
+// SRAM-1 PORT-0 - DMEM I/F
+wire                           sram1_clk0                             ; // CLK
+wire                           sram1_csb0                             ; // CS#
+wire                           sram1_web0                             ; // WE#
+wire   [8:0]                   sram1_addr0                            ; // Address
+wire   [3:0]                   sram1_wmask0                           ; // WMASK#
+wire   [31:0]                  sram1_din0                             ; // Write Data
+wire   [31:0]                  sram1_dout0                            ; // Read Data
+
+// SRAM-1 PORT-1, IMEM I/F
+wire                           sram1_clk1                             ; // CLK
+wire                           sram1_csb1                             ; // CS#
+wire  [8:0]                    sram1_addr1                            ; // Address
+wire  [31:0]                   sram1_dout1                            ; // Read Data
+
 `endif
 
 // SPIM I/F
@@ -575,7 +595,15 @@
 wire                           uartm_rxd                              ;
 wire                           uartm_txd                              ;
 
-
+//----------------------------------------------------------------
+//  Digital PLL I/F
+//  -------------------------------------------------------------
+wire                           cfg_pll_enb                            ; // Enable PLL
+wire [4:0]                     cfg_pll_fed_div                        ; // PLL feedback division ratio
+wire                           cfg_dco_mode                           ; // Run PLL in DCO mode
+wire [25:0]                    cfg_dc_trim                            ; // External trim for DCO mode
+wire                           pll_ref_clk                            ; // Input oscillator to match
+wire [1:0]                     pll_clk_out                            ; // Two 90 degree clock phases
 
 wire [3:0]                     spi_csn                                ;
 
@@ -616,6 +644,7 @@
           .usb_clk                 (usb_clk                 ),
 
           .wbd_int_rst_n           (wbd_int_rst_n           ),
+          .wbd_pll_rst_n           (wbd_pll_rst_n           ),
 
     // Master Port
           .wbm_rst_i               (wb_rst_i                ),  
@@ -649,23 +678,46 @@
           .wbs_err_i               (wbd_int_err_o           ),  
 
           .cfg_clk_ctrl1           (cfg_clk_ctrl1           ),
-          .cfg_clk_ctrl2           (cfg_clk_ctrl2           ),
+
+          .cfg_pll_enb             (cfg_pll_enb             ), 
+          .cfg_pll_fed_div         (cfg_pll_fed_div         ), 
+          .cfg_dco_mode            (cfg_dco_mode            ), 
+          .cfg_dc_trim             (cfg_dc_trim             ),
+          .pll_ref_clk             (pll_ref_clk             ), 
+          .pll_clk_out             (pll_clk_out             ), 
 
           .la_data_in              (la_data_in[17:0]        ),
 
           .uartm_rxd               (uartm_rxd               ),
-          .uartm_txd               (uartm_txd               )
+          .uartm_txd               (uartm_txd               ),
+
+	  .dbg_clk_mon             (dbg_clk_mon             )
 
 
     );
 
 
+// This rtl/gds picked from efabless caravel project 
+digital_pll   u_pll(
+`ifdef USE_POWER_PINS
+    .VPWR                           (vccd1                  ),
+    .VGND                           (vssd1                  ),
+`endif
+    .resetb                         (wbd_pll_rst_n          ), 
+    .enable                         (cfg_pll_enb            ), 
+    .div                            (cfg_pll_fed_div        ), 
+    .dco                            (cfg_dco_mode           ), 
+    .ext_trim                       (cfg_dc_trim            ),
+    .osc                            (pll_ref_clk            ), 
+    .clockp                         (pll_clk_out            ) 
+    );
+
 
 
 //------------------------------------------------------------------------------
 // RISC V Core instance
 //------------------------------------------------------------------------------
-ycr1_top_wb u_riscv_top (
+ycr_top_wb u_riscv_top (
 `ifdef USE_POWER_PINS
           .vccd1                   (vccd1                   ),// User area 1 1.8V supply
           .vssd1                   (vssd1                   ),// User area 1 digital ground
@@ -677,12 +729,13 @@
     // Reset
           .pwrup_rst_n             (wbd_int_rst_n           ),
           .rst_n                   (wbd_int_rst_n           ),
-          .cpu_rst_n               (cpu_core_rst_n[0]       ),
+          .cpu_intf_rst_n          (cpu_intf_rst_n          ),
+          .cpu_core_rst_n          (cpu_core_rst_n[0]       ),
           .riscv_debug             (riscv_debug             ),
+	  .cfg_sram_lphase         (cfg_riscv_sram_lphase   ),
 	  .cfg_cache_ctrl          (cfg_riscv_cache_ctrl    ),
 
     // Clock
-          .core_clk_mclk           (cpu_clk                 ),
           .core_clk                (cpu_clk                 ),
           .rtc_clk                 (rtc_clk                 ),
 
@@ -695,22 +748,36 @@
     //    .test_mode               (1'b0                    ), // Moved inside IP
     //    .test_rst_n              (1'b1                    ), // Moved inside IP
 
-`ifndef YCR1_TCM_MEM
-	// DFFRAM I/F
-          .tcm_dffram_clk0         (tcm_dffram_clk0         ), // CLK
-          .tcm_dffram_cs0          (tcm_dffram_cs0          ), // Chip Select
-          .tcm_dffram_addr0        (tcm_dffram_addr0        ), // Address
-          .tcm_dffram_wmask0       (tcm_dffram_wmask0       ), // Write Mask
-          .tcm_dffram_din0         (tcm_dffram_din0         ), // Write Data
-          .tcm_dffram_dout0        (tcm_dffram_dout0        ), // Read Data
-                                                               
-          .tcm_dffram_clk1         (tcm_dffram_clk1         ), // CLK
-          .tcm_dffram_cs1          (tcm_dffram_cs1          ), // Chip Select
-          .tcm_dffram_addr1        (tcm_dffram_addr1        ), // Address
-          .tcm_dffram_wmask1       (tcm_dffram_wmask1       ), // Write Mask
-          .tcm_dffram_din1         (tcm_dffram_din1         ), // Write Data
-          .tcm_dffram_dout1        (tcm_dffram_dout1        ), // Read Data
+`ifndef SCR1_TCM_MEM
+    // SRAM-0 PORT-0
+          .sram0_clk0         (sram0_clk0                   ),
+          .sram0_csb0         (sram0_csb0                   ),
+          .sram0_web0         (sram0_web0                   ),
+          .sram0_addr0        (sram0_addr0                  ),
+          .sram0_wmask0       (sram0_wmask0                 ),
+          .sram0_din0         (sram0_din0                   ),
+          .sram0_dout0        (sram0_dout0                  ),
+    
+    // SRAM-0 PORT-0
+          .sram0_clk1         (sram0_clk1                   ),
+          .sram0_csb1         (sram0_csb1                   ),
+          .sram0_addr1        (sram0_addr1                  ),
+          .sram0_dout1        (sram0_dout1                  ),
 
+  //  // SRAM-1 PORT-0
+  //      .sram1_clk0         (sram1_clk0                   ),
+  //      .sram1_csb0         (sram1_csb0                   ),
+  //      .sram1_web0         (sram1_web0                   ),
+  //      .sram1_addr0        (sram1_addr0                  ),
+  //      .sram1_wmask0       (sram1_wmask0                 ),
+  //      .sram1_din0         (sram1_din0                   ),
+  //      .sram1_dout0        (sram1_dout0                  ),
+  //  
+  //  // SRAM PORT-0
+  //      .sram1_clk1         (sram1_clk1                   ),
+  //      .sram1_csb1         (sram1_csb1                   ),
+  //      .sram1_addr1        (sram1_addr1                  ),
+  //      .sram1_dout1        (sram1_dout1                  ),
 `endif
     
           .wb_rst_n                (wbd_int_rst_n           ),
@@ -728,20 +795,19 @@
           .wb_icache_lack_i        (wbd_riscv_icache_lack_o ),
           .wb_icache_err_i         (wbd_riscv_icache_err_o  ),
 
-            // DFFRAM I/F
-          .icache_dffram_clk0      (icache_dffram_clk0      ), // CLK
-          .icache_dffram_cs0       (icache_dffram_cs0       ), // Chip Select
-          .icache_dffram_addr0     (icache_dffram_addr0     ), // Address
-          .icache_dffram_wmask0    (icache_dffram_wmask0    ), // Write Mask
-          .icache_dffram_din0      (icache_dffram_din0      ), // Write Data
-          .icache_dffram_dout0     (icache_dffram_dout0     ), // Read Data
-                                                                
-          .icache_dffram_clk1      (icache_dffram_clk1      ), // CLK
-          .icache_dffram_cs1       (icache_dffram_cs1       ), // Chip Select
-          .icache_dffram_addr1     (icache_dffram_addr1     ), // Address
-          .icache_dffram_wmask1    (icache_dffram_wmask1    ), // Write Mask
-          .icache_dffram_din1      (icache_dffram_din1      ), // Write Data
-          .icache_dffram_dout1     (icache_dffram_dout1     ), // Read Data
+          .icache_mem_clk0    (icache_mem_clk0              ), // CLK
+          .icache_mem_csb0    (icache_mem_csb0              ), // CS#
+          .icache_mem_web0    (icache_mem_web0              ), // WE#
+          .icache_mem_addr0   (icache_mem_addr0             ), // Address
+          .icache_mem_wmask0  (icache_mem_wmask0            ), // WMASK#
+          .icache_mem_din0    (icache_mem_din0              ), // Write Data
+//        .icache_mem_dout0   (icache_mem_dout0             ), // Read Data
+                                
+                                
+          .icache_mem_clk1    (icache_mem_clk1              ), // CLK
+          .icache_mem_csb1    (icache_mem_csb1              ), // CS#
+          .icache_mem_addr1   (icache_mem_addr1             ), // Address
+          .icache_mem_dout1   (icache_mem_dout1             ), // Read Data
 
     // Data cache memory interface
           .wb_dcache_stb_o         (wbd_riscv_dcache_stb_i  ),
@@ -756,21 +822,20 @@
           .wb_dcache_lack_i        (wbd_riscv_dcache_lack_o ),
           .wb_dcache_err_i         (wbd_riscv_dcache_err_o  ),
 
+          .dcache_mem_clk0    (dcache_mem_clk0              ), // CLK
+          .dcache_mem_csb0    (dcache_mem_csb0              ), // CS#
+          .dcache_mem_web0    (dcache_mem_web0              ), // WE#
+          .dcache_mem_addr0   (dcache_mem_addr0             ), // Address
+          .dcache_mem_wmask0  (dcache_mem_wmask0            ), // WMASK#
+          .dcache_mem_din0    (dcache_mem_din0              ), // Write Data
+          .dcache_mem_dout0   (dcache_mem_dout0             ), // Read Data
+                                
+                                
+          .dcache_mem_clk1    (dcache_mem_clk1              ), // CLK
+          .dcache_mem_csb1    (dcache_mem_csb1              ), // CS#
+          .dcache_mem_addr1   (dcache_mem_addr1             ), // Address
+          .dcache_mem_dout1   (dcache_mem_dout1             ), // Read Data
 
-     // DFFRAM I/F
-          .dcache_dffram_clk0      (dcache_dffram_clk0      ), // CLK
-          .dcache_dffram_cs0       (dcache_dffram_cs0       ), // Chip Select
-          .dcache_dffram_addr0     (dcache_dffram_addr0     ), // Address
-          .dcache_dffram_wmask0    (dcache_dffram_wmask0    ), // Write Mask
-          .dcache_dffram_din0      (dcache_dffram_din0      ), // Write Data
-          .dcache_dffram_dout0     (dcache_dffram_dout0     ), // Read Data
-                                                         
-          .dcache_dffram_clk1      (dcache_dffram_clk1      ), // CLK
-          .dcache_dffram_cs1       (dcache_dffram_cs1       ), // Chip Select
-          .dcache_dffram_addr1     (dcache_dffram_addr1     ), // Address
-          .dcache_dffram_wmask1    (dcache_dffram_wmask1    ), // Write Mask
-          .dcache_dffram_din1      (dcache_dffram_din1      ), // Write Data
-          .dcache_dffram_dout1     (dcache_dffram_dout1     ), // Read Data
 
     // Data memory interface
           .wbd_dmem_stb_o          (wbd_riscv_dmem_stb_i    ),
@@ -782,90 +847,91 @@
           .wbd_dmem_ack_i          (wbd_riscv_dmem_ack_o    ),
           .wbd_dmem_err_i          (wbd_riscv_dmem_err_o    ) 
 );
-`ifndef YCR1_TCM_MEM
 
-DFFRAM u_tcm_1KB_mem0 (
+`ifndef SCR1_TCM_MEM
+sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb(
 `ifdef USE_POWER_PINS
-          .VPWR                    (vccd1                   ),// area 1 1.8V supply
-          .VGND                    (vssd1                   ),// area 1 digital ground
+          .vccd1              (vccd1                        ),// area 1 1.8V supply
+          .vssd1              (vssd1                        ),// area 1 digital ground
 `endif
-          .CLK                     (tcm_dffram_clk0         ),
-          .WE                      (tcm_dffram_wmask0       ),
-          .EN                      (tcm_dffram_cs0          ),
-          .Di                      (tcm_dffram_din0         ),
-          .Do                      (tcm_dffram_dout0        ),
-          .A                       (tcm_dffram_addr0        )
-);
+// Port 0: RW
+          .clk0               (sram0_clk0                   ),
+          .csb0               (sram0_csb0                   ),
+          .web0               (sram0_web0                   ),
+          .wmask0             (sram0_wmask0                 ),
+          .addr0              (sram0_addr0                  ),
+          .din0               (sram0_din0                   ),
+          .dout0              (sram0_dout0                  ),
+// Port 1: R
+          .clk1               (sram0_clk1                   ),
+          .csb1               (sram0_csb1                   ),
+          .addr1              (sram0_addr1                  ),
+          .dout1              (sram0_dout1                  )
+  );
 
-DFFRAM u_tcm_1KB_mem1 (
+/***
+sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram1_2kb(
 `ifdef USE_POWER_PINS
-          .VPWR                    (vccd1                   ),// area 1 1.8V supply
-          .VGND                    (vssd1                   ),// area 1 digital ground
+          .vccd1              (vccd1                        ),// User area 1 1.8V supply
+          .vssd1              (vssd1                        ),// User area 1 digital ground
 `endif
-          .CLK                     (tcm_dffram_clk1         ),
-          .WE                      (tcm_dffram_wmask1       ),
-          .EN                      (tcm_dffram_cs1          ),
-          .Di                      (tcm_dffram_din1         ),
-          .Do                      (tcm_dffram_dout1        ),
-          .A                       (tcm_dffram_addr1        )
-);
-
+// Port 0: RW
+          .clk0               (sram1_clk0                   ),
+          .csb0               (sram1_csb0                   ),
+          .web0               (sram1_web0                   ),
+          .wmask0             (sram1_wmask0                 ),
+          .addr0              (sram1_addr0                  ),
+          .din0               (sram1_din0                   ),
+          .dout0              (sram1_dout0                  ),
+// Port 1: R
+          .clk1               (sram1_clk1                   ),
+          .csb1               (sram1_csb1                   ),
+          .addr1              (sram1_addr1                  ),
+          .dout1              (sram1_dout1                  )
+  );
+***/
 `endif
 
 
-
-DFFRAM u_icache_1KB_mem0 (
+sky130_sram_2kbyte_1rw1r_32x512_8 u_icache_2kb(
 `ifdef USE_POWER_PINS
-          .VPWR                    (vccd1                   ),// area 1 1.8V supply
-          .VGND                    (vssd1                   ),// area 1 digital ground
+          .vccd1              (vccd1                        ),// User area 1 1.8V supply
+          .vssd1              (vssd1                        ),// User area 1 digital ground
 `endif
-          .CLK                     (icache_dffram_clk0      ),
-          .WE                      (icache_dffram_wmask0    ),
-          .EN                      (icache_dffram_cs0       ),
-          .Di                      (icache_dffram_din0      ),
-          .Do                      (icache_dffram_dout0     ),
-          .A                       (icache_dffram_addr0     )
-);
+// Port 0: RW
+          .clk0               (icache_mem_clk0              ),
+          .csb0               (icache_mem_csb0              ),
+          .web0               (icache_mem_web0              ),
+          .wmask0             (icache_mem_wmask0            ),
+          .addr0              (icache_mem_addr0             ),
+          .din0               (icache_mem_din0              ),
+          .dout0              (                             ),
+// Port 1: R
+          .clk1               (icache_mem_clk1              ),
+          .csb1               (icache_mem_csb1              ),
+          .addr1              (icache_mem_addr1             ),
+          .dout1              (icache_mem_dout1             )
+  );
 
-DFFRAM u_icache_1KB_mem1 (
+sky130_sram_2kbyte_1rw1r_32x512_8 u_dcache_2kb(
 `ifdef USE_POWER_PINS
-          .VPWR                    (vccd1                   ),// area 1 1.8V supply
-          .VGND                    (vssd1                   ),// area 1 digital ground
+          .vccd1              (vccd1                        ),// User area 1 1.8V supply
+          .vssd1              (vssd1                        ),// User area 1 digital ground
 `endif
-          .CLK                     (icache_dffram_clk1      ),
-          .WE                      (icache_dffram_wmask1    ),
-          .EN                      (icache_dffram_cs1       ),
-          .Di                      (icache_dffram_din1      ),
-          .Do                      (icache_dffram_dout1     ),
-          .A                       (icache_dffram_addr1     )
-);
-
-
-DFFRAM u_dcache_1KB_mem0 (
-`ifdef USE_POWER_PINS
-          .VPWR                    (vccd1                   ),// area 1 1.8V supply
-          .VGND                    (vssd1                   ),// area 1 digital ground
-`endif
-          .CLK                     (dcache_dffram_clk0      ),
-          .WE                      (dcache_dffram_wmask0    ),
-          .EN                      (dcache_dffram_cs0       ),
-          .Di                      (dcache_dffram_din0      ),
-          .Do                      (dcache_dffram_dout0     ),
-          .A                       (dcache_dffram_addr0     )
-);
-
-DFFRAM u_dcache_1KB_mem1 (
-`ifdef USE_POWER_PINS
-          .VPWR                    (vccd1                   ),// area 1 1.8V supply
-          .VGND                    (vssd1                   ),// area 1 digital ground
-`endif
-          .CLK                     (dcache_dffram_clk1      ),
-          .WE                      (dcache_dffram_wmask1    ),
-          .EN                      (dcache_dffram_cs1       ),
-          .Di                      (dcache_dffram_din1      ),
-          .Do                      (dcache_dffram_dout1     ),
-          .A                       (dcache_dffram_addr1     )
-);
+// Port 0: RW
+          .clk0               (dcache_mem_clk0              ),
+          .csb0               (dcache_mem_csb0              ),
+          .web0               (dcache_mem_web0              ),
+          .wmask0             (dcache_mem_wmask0            ),
+          .addr0              (dcache_mem_addr0             ),
+          .din0               (dcache_mem_din0              ),
+          .dout0              (dcache_mem_dout0             ),
+// Port 1: R
+          .clk1               (dcache_mem_clk1              ),
+          .csb1               (dcache_mem_csb1              ),
+          .addr1              (dcache_mem_addr1             ),
+          .dout1              (dcache_mem_dout1             )
+  );
 
 
 /*********************************************************
@@ -1208,7 +1274,9 @@
 
 	  .pulse1m_mclk            (pulse1m_mclk            ),
 
-	  .pinmux_debug            (pinmux_debug            )
+	  .pinmux_debug            (pinmux_debug            ),
+
+	  .dbg_clk_mon             (dbg_clk_mon             )
 
 
 

diff --git a/verilog/rtl/user_reg_map.v b/verilog/rtl/user_reg_map.v
index dfe3a99..22a25c0 100644
--- a/verilog/rtl/user_reg_map.v
+++ b/verilog/rtl/user_reg_map.v

@@ -18,6 +18,7 @@
 `define WBHOST_BANK_SEL           8'h04  // reg_1  - Bank Select
 `define WBHOST_CLK_CTRL1          8'h08  // reg_2  - Clock Control-1
 `define WBHOST_CLK_CTRL2          8'h0C  // reg_3  - Clock Control-2
+`define WBHOST_PLL_CTRL           8'h10  // reg_4  - PLL Control
 
 //--------------------------------------------------
 // Pinmux Register

diff --git a/verilog/rtl/wb_host/src/wb_host.sv b/verilog/rtl/wb_host/src/wb_host.sv
index a5738c8..8256742 100644
--- a/verilog/rtl/wb_host/src/wb_host.sv
+++ b/verilog/rtl/wb_host/src/wb_host.sv

@@ -92,6 +92,7 @@
        output logic                usb_clk          ,
        // Global Reset control
        output logic                wbd_int_rst_n    ,
+       output logic                wbd_pll_rst_n    ,
 
     // Master Port
        input   logic               wbm_rst_i        ,  // Regular Reset signal
@@ -125,12 +126,20 @@
        input   logic               wbs_err_i        ,  // error
 
        output logic [31:0]         cfg_clk_ctrl1    ,
-       output logic [31:0]         cfg_clk_ctrl2    ,
+       // Digital PLL I/F
+       output logic                cfg_pll_enb      , // Enable PLL
+       output logic[4:0]           cfg_pll_fed_div  , // PLL feedback division ratio
+       output logic                cfg_dco_mode     , // Run PLL in DCO mode
+       output logic[25:0]          cfg_dc_trim      , // External trim for DCO mode
+       output logic                pll_ref_clk      , // Input oscillator to match
+       input  logic [1:0]          pll_clk_out      , // Two 90 degree clock phases
 
        input  logic [17:0]         la_data_in       ,
 
        input  logic                uartm_rxd        ,
-       output logic                uartm_txd        
+       output logic                uartm_txd        ,
+
+       output logic                dbg_clk_mon
 
     );
 
@@ -143,7 +152,7 @@
 logic               wbs_rst_n;
 
 logic               reg_sel    ;
-logic [1:0]         sw_addr    ;
+logic [2:0]         sw_addr    ;
 logic               sw_rd_en   ;
 logic               sw_wr_en   ;
 logic [31:0]        reg_rdata  ;
@@ -158,12 +167,15 @@
 logic               sw_wr_en_3;
 logic [15:0]        cfg_bank_sel;
 logic [31:0]        reg_0;  // Software_Reg_0
+logic [31:0]        cfg_clk_ctrl2;
 
-logic  [3:0]        cfg_wb_clk_ctrl;
-logic  [3:0]        cfg_cpu_clk_ctrl;
+logic  [31:0]       cfg_pll_ctrl; 
+logic  [7:0]        cfg_wb_clk_ctrl;
+logic  [7:0]        cfg_cpu_clk_ctrl;
 logic  [7:0]        cfg_rtc_clk_ctrl;
 logic  [7:0]        cfg_usb_clk_ctrl;
-logic  [7:0]        cfg_glb_ctrl;
+logic  [31:0]       cfg_glb_ctrl;
+
 
 // uart Master Port
 logic               wbm_uart_cyc_i        ;  // strobe/request
@@ -192,8 +204,39 @@
 logic               wb_ack_int            ; // acknowlegement
 logic               wb_err_int            ; // error
 
+logic [3:0]         cfg_mon_sel           ;
+logic               int_pll_clock         ;
+logic               pll_clk_div16         ;
+logic               pll_clk_div16_buf     ;
+logic [2:0]         cfg_ref_pll_div       ;
 
+
+assign cfg_pll_enb      = cfg_glb_ctrl[15];
+assign cfg_ref_pll_div  = cfg_glb_ctrl[14:12];
+assign cfg_mon_sel      = cfg_glb_ctrl[11:8];
+
+assign cfg_dco_mode     = cfg_pll_ctrl[31];
+assign cfg_pll_fed_div  = cfg_pll_ctrl[30:26];
+assign cfg_dc_trim      = cfg_pll_ctrl[25:0];
+
+//assign   int_pll_clock    = pll_clk_out[0];
+ctech_clk_buf u_clkbuf_pll     (.A (pll_clk_out[0]), . X(int_pll_clock));
+ctech_clk_buf u_clkbuf_pll_div (.A (pll_clk_div16), . X(pll_clk_div16_buf));
+
+
+// Debug clock monitor optin
+assign dbg_clk_mon  = (cfg_mon_sel == 4'b000) ? pll_clk_div16_buf:
+	              (cfg_mon_sel == 4'b001) ? pll_ref_clk  :
+	              (cfg_mon_sel == 4'b010) ? wbs_clk_out  :
+	              (cfg_mon_sel == 4'b011) ? cpu_clk_int  :
+	              (cfg_mon_sel == 4'b100) ? rtc_clk_div  :
+	              (cfg_mon_sel == 4'b101) ? usb_clk_int  : 1'b0;
+
+
+
+// Reset control
 ctech_buf u_buf_wb_rst        (.A(cfg_glb_ctrl[0]),.X(wbd_int_rst_n));
+ctech_buf u_buf_pll_rst       (.A(cfg_glb_ctrl[1]),.X(wbd_pll_rst_n));
 
 //--------------------------------------------------------------------------------
 // Look like wishbone reset removed early than user Power up sequence
@@ -336,7 +379,7 @@
 // ---------------------------------------------------------------------
 assign reg_sel       = wb_req & (wb_adr_i[19] == 1'b1);
 
-assign sw_addr       = wb_adr_i [3:2];
+assign sw_addr       = wb_adr_i [4:2];
 assign sw_rd_en      = reg_sel & !wb_we_i;
 assign sw_wr_en      = reg_sel & wb_we_i;
 
@@ -344,6 +387,8 @@
 assign  sw_wr_en_1 = sw_wr_en && (sw_addr==1);
 assign  sw_wr_en_2 = sw_wr_en && (sw_addr==2);
 assign  sw_wr_en_3 = sw_wr_en && (sw_addr==3);
+assign  sw_wr_en_4 = sw_wr_en && (sw_addr==4);
+assign  sw_wr_en_5 = sw_wr_en && (sw_addr==5);
 
 always @ (posedge wbm_clk_i or negedge wbm_rst_n)
 begin : preg_out_Seq
@@ -369,11 +414,11 @@
 //-------------------------------------
 // Global + Clock Control
 // -------------------------------------
-assign cfg_glb_ctrl         = reg_0[7:0];
-assign cfg_wb_clk_ctrl      = reg_0[11:8];
-assign cfg_rtc_clk_ctrl     = reg_0[19:12];
-assign cfg_cpu_clk_ctrl     = reg_0[23:20];
-assign cfg_usb_clk_ctrl     = reg_0[31:24];
+assign cfg_glb_ctrl         = reg_0[31:0];
+assign cfg_wb_clk_ctrl      = cfg_clk_ctrl2[7:0];
+assign cfg_rtc_clk_ctrl     = cfg_clk_ctrl2[15:8];
+assign cfg_usb_clk_ctrl     = cfg_clk_ctrl2[23:16];
+assign cfg_cpu_clk_ctrl     = cfg_clk_ctrl2[31:24];
 
 
 always @( *)
@@ -381,10 +426,11 @@
   reg_out [31:0] = 8'd0;
 
   case (sw_addr [1:0])
-    2'b00 :   reg_out [31:0] = reg_0;
-    2'b01 :   reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]};     
-    2'b10 :   reg_out [31:0] = cfg_clk_ctrl1 [31:0];    
-    2'b11 :   reg_out [31:0] = cfg_clk_ctrl2 [31:0];     
+    3'b000 :   reg_out [31:0] = reg_0;
+    3'b001 :   reg_out [31:0] = {16'h0,cfg_bank_sel [15:0]};     
+    3'b010 :   reg_out [31:0] = cfg_clk_ctrl1 [31:0];    
+    3'b011 :   reg_out [31:0] = cfg_clk_ctrl2 [31:0];    
+    3'b100 :   reg_out [31:0] = cfg_pll_ctrl [31:0];     
     default : reg_out [31:0] = 'h0;
   endcase
 end
@@ -431,6 +477,15 @@
 	      //List of Outs
 	      .data_out      (cfg_clk_ctrl2[31:0])
           );
+generic_register #(32,0  ) u_pll_ctrl (
+	      .we            ({32{sw_wr_en_4}}  ),		 
+	      .data_in       (wb_dat_i[31:0]   ),
+	      .reset_n       (wbm_rst_n         ),
+	      .clk           (wbm_clk_i         ),
+	      
+	      //List of Outs
+	      .data_out      (cfg_pll_ctrl[31:0])
+          );
 
 
 assign wb_stb_int = wb_req & !reg_sel;
@@ -468,29 +523,51 @@
 
     );
 
+// PLL Ref CLock
+
+clk_ctl #(2) u_pll_ref_clk (
+   // Outputs
+       .clk_o         (pll_ref_clk      ),
+   // Inputs
+       .mclk          (user_clock1      ),
+       .reset_n       (wbm_rst_n        ), 
+       .clk_div_ratio (cfg_ref_pll_div  )
+   );
+
+// PLL DIv16 to debug monitor purpose
+
+clk_ctl #(3) u_pllclk (
+   // Outputs
+       .clk_o         (pll_clk_div16    ),
+   // Inputs
+       .mclk          (int_pll_clock    ),
+       .reset_n       (wbm_rst_n        ), 
+       .clk_div_ratio (4'hF )
+   );
 
 //----------------------------------
 // Generate Internal WishBone Clock
 //----------------------------------
 logic       wb_clk_div;
+logic       wbs_ref_clk_int;
 logic       wbs_ref_clk;
-logic       cfg_wb_clk_src_sel;
-logic       cfg_wb_clk_div;
-logic [1:0] cfg_wb_clk_ratio;
 
-assign    cfg_wb_clk_src_sel   =  cfg_wb_clk_ctrl[3];
-assign    cfg_wb_clk_div       =  cfg_wb_clk_ctrl[2];
-assign    cfg_wb_clk_ratio     =  cfg_wb_clk_ctrl[1:0];
+wire  [1:0]   cfg_wb_clk_src_sel   =  cfg_wb_clk_ctrl[7:6];
+wire          cfg_wb_clk_div       =  cfg_wb_clk_ctrl[5];
+wire  [4:0]   cfg_wb_clk_ratio     =  cfg_wb_clk_ctrl[4:0];
 
 
-//assign wbs_ref_clk = (cfg_wb_clk_src_sel) ? user_clock2 : user_clock1;
-ctech_mux2x1 u_wbs_ref_sel (.A0 (user_clock1), .A1 (user_clock2), .S  (cfg_wb_clk_src_sel), .X  (wbs_ref_clk));
+assign wbs_ref_clk_int = (cfg_wb_clk_src_sel ==2'b00) ? user_clock1 :
+                         (cfg_wb_clk_src_sel ==2'b01) ? user_clock2 :	
+	                 int_pll_clock;
+
+ctech_clk_buf u_wbs_ref_clkbuf (.A (wbs_ref_clk_int), . X(wbs_ref_clk));
 
 //assign wbs_clk_out  = (cfg_wb_clk_div)  ? wb_clk_div : wbm_clk_i;
 ctech_mux2x1 u_wbs_clk_sel (.A0 (wbs_ref_clk), .A1 (wb_clk_div), .S  (cfg_wb_clk_div), .X  (wbs_clk_out));
 
 
-clk_ctl #(1) u_wbclk (
+clk_ctl #(4) u_wbclk (
    // Outputs
        .clk_o         (wb_clk_div      ),
    // Inputs
@@ -504,22 +581,26 @@
 // Generate CORE Clock Generation
 //----------------------------------
 wire   cpu_clk_div;
+wire   cpu_ref_clk_int;
 wire   cpu_ref_clk;
 wire   cpu_clk_int;
 
-wire       cfg_cpu_clk_src_sel   = cfg_cpu_clk_ctrl[3];
-wire       cfg_cpu_clk_div       = cfg_cpu_clk_ctrl[2];
-wire [1:0] cfg_cpu_clk_ratio     = cfg_cpu_clk_ctrl[1:0];
+wire [1:0] cfg_cpu_clk_src_sel   = cfg_cpu_clk_ctrl[7:6];
+wire       cfg_cpu_clk_div       = cfg_cpu_clk_ctrl[5];
+wire [4:0] cfg_cpu_clk_ratio     = cfg_cpu_clk_ctrl[4:0];
 
-//assign cpu_ref_clk = (cfg_cpu_clk_src_sel) ? user_clock2 : user_clock1;
+assign cpu_ref_clk_int = (cfg_cpu_clk_src_sel ==2'b00) ? user_clock1 :
+                         (cfg_cpu_clk_src_sel ==2'b01) ? user_clock2 :	
+	                 int_pll_clock;
+
+ctech_clk_buf u_cpu_ref_clkbuf (.A (cpu_ref_clk_int), . X(cpu_ref_clk));
+
 //assign cpu_clk_int = (cfg_cpu_clk_div)     ? cpu_clk_div : cpu_ref_clk;
-
-ctech_mux2x1 u_cpu_ref_sel (.A0 (user_clock1), .A1 (user_clock2), .S  (cfg_cpu_clk_src_sel), .X  (cpu_ref_clk));
 ctech_mux2x1 u_cpu_clk_sel (.A0 (cpu_ref_clk), .A1 (cpu_clk_div), .S  (cfg_cpu_clk_div),     .X  (cpu_clk_int));
 
 ctech_clk_buf u_clkbuf_cpu (.A (cpu_clk_int), . X(cpu_clk));
 
-clk_ctl #(1) u_cpuclk (
+clk_ctl #(4) u_cpuclk (
    // Outputs
        .clk_o         (cpu_clk_div      ),
    // Inputs
@@ -551,20 +632,25 @@
 // Generate USB Clock Generation
 //----------------------------------
 wire   usb_clk_div;
+wire   usb_ref_clk_int;
 wire   usb_ref_clk;
 wire   usb_clk_int;
 
-wire       cfg_usb_clk_div       = cfg_usb_clk_ctrl[7];
-wire [6:0] cfg_usb_clk_ratio     = cfg_usb_clk_ctrl[6:0];
+wire [1:0] cfg_usb_clk_sel_sel   = cfg_usb_clk_ctrl[7:6];
+wire       cfg_usb_clk_div       = cfg_usb_clk_ctrl[5];
+wire [4:0] cfg_usb_clk_ratio     = cfg_usb_clk_ctrl[4:0];
 
-assign usb_ref_clk = user_clock2 ;
+assign usb_ref_clk_int = (cfg_usb_clk_sel_sel ==2'b00) ? user_clock1 :
+                         (cfg_usb_clk_sel_sel ==2'b01) ? user_clock2 :	
+	                 int_pll_clock;
+ctech_clk_buf u_usb_ref_clkbuf (.A (usb_ref_clk_int), . X(usb_ref_clk));
 //assign usb_clk_int = (cfg_usb_clk_div)     ? usb_clk_div : usb_ref_clk;
 ctech_mux2x1 u_usb_clk_sel (.A0 (usb_ref_clk), .A1 (usb_clk_div), .S  (cfg_usb_clk_div), .X  (usb_clk_int));
 
 
 ctech_clk_buf u_clkbuf_usb (.A (usb_clk_int), . X(usb_clk));
 
-clk_ctl #(6) u_usbclk (
+clk_ctl #(4) u_usbclk (
    // Outputs
        .clk_o         (usb_clk_div      ),
    // Inputs