MPW-4 submission with 8KB WishBone and 4KB TCM Memory
diff --git a/openlane/mbist/base.sdc b/openlane/mbist/base.sdc new file mode 100644 index 0000000..1f050a1 --- /dev/null +++ b/openlane/mbist/base.sdc
@@ -0,0 +1,129 @@ +############################################################################### +# Created by write_sdc +# Sun Nov 14 09:33:23 2021 +############################################################################### +current_design mbist_top +############################################################################### +# Timing Constraints +############################################################################### +create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}] +create_clock -name wb_clk2_i -period 10.0000 [get_ports {wb_clk2_i}] +create_generated_clock -name bist_mem_clk_a -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks wb_clk2_i] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a] +create_generated_clock -name bist_mem_clk_b -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks wb_clk2_i] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b] + +set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {wb_clk_i wb_clk2_i bist_mem_clk_a bist_mem_clk_b}] + +set_clock_transition 0.1500 [all_clocks] +set_clock_uncertainty -setup 0.2500 [all_clocks] + +set_clock_uncertainty -hold 0.2500 [all_clocks] + +set ::env(SYNTH_TIMING_DERATE) 0.05 +puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" +set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] +set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] + +set_input_delay -max 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}] +set_input_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}] + +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}] +set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}] + +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}] +set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}] + +set_false_path -from [get_ports {bist_en}] +set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}] +set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}] +set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}] +set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}] + +set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_en}] +set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}] +set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}] +set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}] +set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}] + +## Functional Inputs +set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[*]}] +set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}] +set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}] +set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}] +set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbd_mbist1_dat_o[*]}] +set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[*]}] + +set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[*]}] +set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}] +set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}] +set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}] +set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbd_mbist1_dat_o[*]}] +set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[*]}] + +set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[*]}] +set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}] +set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_err_o}] + +set_output_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[*]}] +set_output_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}] +set_output_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_err_o}] + +## Towards MEMORY from MBIST CLOCK +## PORT-A +set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}] + + +set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}] +set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}] + +set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}] +set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}] + + + +## PORT-B +set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}] +set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}] +set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}] +set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}] +set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}] + +set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}] +set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}] +set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}] +set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}] +set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}] + + +# Set max delay for clock skew + +set_max_delay 3.5 -from [get_ports {wbd_clk_int}] +set_max_delay 2 -to [get_ports {wbd_clk_mbist}] +set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_mbist + +############################################################################### +# Environment +############################################################################### +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] +set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] +puts "\[INFO\]: Setting load to: $cap_load" +set_load $cap_load [all_outputs] + +set_timing_derate -early 0.9500 +set_timing_derate -late 1.0500 +############################################################################### +# Design Rules +############################################################################### +set_max_fanout 4.0000 [current_design]
diff --git a/openlane/mbist/config.tcl b/openlane/mbist/config.tcl new file mode 100755 index 0000000..78cd955 --- /dev/null +++ b/openlane/mbist/config.tcl
@@ -0,0 +1,123 @@ +# SPDX-FileCopyrightText: 2021 , Dinesh Annayya +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 +# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> + +# Global +# ------ + +set script_dir [file dirname [file normalize [info script]]] +# Name + +set ::env(DESIGN_NAME) mbist_top + +set ::env(DESIGN_IS_CORE) "0" + +# Timing configuration +set ::env(CLOCK_PERIOD) "10" +#set ::env(CLOCK_PORT) "u_cts_wb_clk_b1.u_buf/X \ +# u_cts_wb_clk_b2.u_buf/X \ +# " +set ::env(CLOCK_PORT) { wb_clk_i mem_no\[3\].u_mem_sel.u_mem_clk_sel.u_mux/X mem_no\[2\].u_mem_sel.u_mem_clk_sel.u_mux/X mem_no\[1\].u_mem_sel.u_mem_clk_sel.u_mux/X mem_no\[0\].u_mem_sel.u_mem_clk_sel.u_mux/X } + +set ::env(SYNTH_MAX_FANOUT) 4 + +## CTS BUFFER +set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" +set ::env(CTS_SINK_CLUSTERING_SIZE) "16" +set ::env(CLOCK_BUFFER_FANOUT) "8" + + +# Sources +# ------- + +# Local sources + no2usb sources +set ::env(VERILOG_FILES) "\ + $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ + $script_dir/../../verilog/rtl/mbist/src/core/mbist_addr_gen.sv \ + $script_dir/../../verilog/rtl/mbist/src/core/mbist_fsm.sv \ + $script_dir/../../verilog/rtl/mbist/src/core/mbist_op_sel.sv \ + $script_dir/../../verilog/rtl/mbist/src/core/mbist_repair_addr.sv \ + $script_dir/../../verilog/rtl/mbist/src/core/mbist_sti_sel.sv \ + $script_dir/../../verilog/rtl/mbist/src/core/mbist_pat_sel.sv \ + $script_dir/../../verilog/rtl/mbist/src/core/mbist_mux.sv \ + $script_dir/../../verilog/rtl/mbist/src/core/mbist_data_cmp.sv \ + $script_dir/../../verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv \ + $script_dir/../../verilog/rtl/mbist/src/top/mbist_top.sv \ + $script_dir/../../verilog/rtl/lib/ctech_cells.sv \ + $script_dir/../../verilog/rtl/lib/reset_sync.sv \ + $script_dir/../../verilog/rtl/lib/ser_shift.sv \ + " + +set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/mbist/include ] +set ::env(SYNTH_DEFINES) [list SYNTHESIS ] + + +set ::env(SYNTH_PARAMS) "BIST_ADDR_WD 9,\ + BIST_DATA_WD 32,\ + BIST_ADDR_START 9'h000,\ + BIST_ADDR_END 9'h1FB,\ + BIST_REPAIR_ADDR_START 9'h1FC,\ + BIST_RAD_WD_I 9,\ + BIST_RAD_WD_O 9\ + " + +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 +set ::env(SDC_FILE) "$script_dir/base.sdc" +set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" + +set ::env(LEC_ENABLE) 0 + +set ::env(VDD_PIN) [list {vccd1}] +set ::env(GND_PIN) [list {vssd1}] + + +# Floorplanning +# ------------- + +set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg + +set ::env(FP_SIZING) absolute +set ::env(DIE_AREA) "0 0 1500 200" + + +# If you're going to use multiple power domains, then keep this disabled. +set ::env(RUN_CVC) 1 + +#set ::env(PDN_CFG) $script_dir/pdn.tcl + + +set ::env(PL_TIME_DRIVEN) 1 +set ::env(PL_TARGET_DENSITY) "0.30" + + + +set ::env(FP_IO_VEXTEND) 4 +set ::env(FP_IO_HEXTEND) 4 + +set ::env(FP_PDN_VPITCH) 140 +set ::env(FP_PDN_HPITCH) 140 +set ::env(FP_PDN_VWIDTH) 5 +set ::env(FP_PDN_HWIDTH) 5 + +set ::env(GLB_RT_MAXLAYER) 5 +set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 + +set ::env(DIODE_INSERTION_STRATEGY) 4 + + +set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" +set ::env(QUIT_ON_MAGIC_DRC) "1" +set ::env(QUIT_ON_LVS_ERROR) "0" +set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/mbist/interactive.tcl b/openlane/mbist/interactive.tcl new file mode 100644 index 0000000..f59586f --- /dev/null +++ b/openlane/mbist/interactive.tcl
@@ -0,0 +1,219 @@ +#!/usr/bin/tclsh +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# Copyright 2020 Efabless Corporation +# Copyright 2020 Sylvain Munaut +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +package require openlane; + + +proc run_placement_step {args} { + # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def] + # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0] + # set_def $pdndef + if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } { + set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF) + } + + run_placement +} + +proc run_cts_step {args} { + # set_def $::env(opendp_result_file_tag).def + if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } { + set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF) + } + + run_cts + run_resizer_timing +} + +proc run_routing_step {args} { + # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def] + # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0] + # set_def $resizerdef + if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } { + set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF) + } + run_routing +} + +proc run_diode_insertion_2_5_step {args} { + # set_def $::env(tritonRoute_result_file_tag).def + if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } { + set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF) + } + if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } { + run_antenna_check + heal_antenna_violators; # modifies the routed DEF + } + +} + +proc run_power_pins_insertion_step {args} { + # set_def $::env(tritonRoute_result_file_tag).def + if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } { + set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF) + } + if { $::env(LVS_INSERT_POWER_PINS) } { + write_powered_verilog + set_netlist $::env(lvs_result_file_tag).powered.v + } + +} + +proc run_lvs_step {{ lvs_enabled 1 }} { + # set_def $::env(tritonRoute_result_file_tag).def + if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } { + set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF) + } + if { $lvs_enabled } { + run_magic_spice_export + run_lvs; # requires run_magic_spice_export + } + +} + +proc run_drc_step {{ drc_enabled 1 }} { + if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } { + set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF) + } + if { $drc_enabled } { + run_magic_drc + run_klayout_drc + } +} + +proc run_antenna_check_step {{ antenna_check_enabled 1 }} { + if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } { + set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF) + } + if { $antenna_check_enabled } { + run_antenna_check + } +} + +proc run_flow {args} { + set script_dir [file dirname [file normalize [info script]]] + + set options { + {-design required} + {-save_path optional} + {-no_lvs optional} + {-no_drc optional} + {-no_antennacheck optional} + } + set flags {-save} + parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume + + prep {*}$args + + set LVS_ENABLED 1 + set DRC_ENABLED 1 + set ANTENNACHECK_ENABLED 1 + + set steps [dict create "synthesis" {run_synthesis "" } \ + "floorplan" {run_floorplan ""} \ + "placement" {run_placement_step ""} \ + "cts" {run_cts_step ""} \ + "routing" {run_routing_step ""}\ + "diode_insertion" {run_diode_insertion_2_5_step ""} \ + "power_pins_insertion" {run_power_pins_insertion_step ""} \ + "gds_magic" {run_magic ""} \ + "gds_drc_klayout" {run_klayout ""} \ + "gds_xor_klayout" {run_klayout_gds_xor ""} \ + "lvs" "run_lvs_step $LVS_ENABLED" \ + "drc" "run_drc_step $DRC_ENABLED" \ + "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \ + "cvc" {run_lef_cvc} + ] + + set_if_unset arg_values(-to) "cvc"; + + if { [info exists ::env(CURRENT_STEP) ] } { + puts "\[INFO\]:Picking up where last execution left off" + puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)] + } else { + set ::env(CURRENT_STEP) "synthesis"; + } + set_if_unset arg_values(-from) $::env(CURRENT_STEP); + set exe 0; + dict for {step_name step_exe} $steps { + if { [ string equal $arg_values(-from) $step_name ] } { + set exe 1; + } + + if { $exe } { + # For when it fails + set ::env(CURRENT_STEP) $step_name + [lindex $step_exe 0] [lindex $step_exe 1] ; + } + + if { [ string equal $arg_values(-to) $step_name ] } { + set exe 0: + break; + } + + } + + # for when it resumes + set steps_as_list [dict keys $steps] + set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1] + set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx] + + if { [info exists flags_map(-save) ] } { + if { ! [info exists arg_values(-save_path)] } { + set arg_values(-save_path) "" + } + save_views -lef_path $::env(magic_result_file_tag).lef \ + -def_path $::env(CURRENT_DEF) \ + -gds_path $::env(magic_result_file_tag).gds \ + -mag_path $::env(magic_result_file_tag).mag \ + -maglef_path $::env(magic_result_file_tag).lef.mag \ + -spice_path $::env(magic_result_file_tag).spice \ + -spef_path $::env(CURRENT_SPEF) \ + -verilog_path $::env(CURRENT_NETLIST) \ + -save_path $arg_values(-save_path) \ + -tag $::env(RUN_TAG) + } + + + calc_total_runtime + save_state + generate_final_summary_report + + check_timing_violations + + puts_success "Flow Completed Without Fatal Errors." + +} + +run_flow {*}$argv
diff --git a/openlane/mbist/pin_order.cfg b/openlane/mbist/pin_order.cfg new file mode 100644 index 0000000..0416192 --- /dev/null +++ b/openlane/mbist/pin_order.cfg
@@ -0,0 +1,527 @@ +#BUS_SORT + +#MANUAL_PLACE + + +#S +rst_n 0000 0 + + + +#E +cfg_cska_mbist\[3\] 0000 0 4 +cfg_cska_mbist\[2\] +cfg_cska_mbist\[1\] +cfg_cska_mbist\[0\] +wb_clk2_i +wb_clk_i +wbd_clk_mbist +wbd_clk_int + +wb_cyc_i 0025 0 2 +wb_stb_i +wb_we_i +wb_cs_i\[1\] +wb_cs_i\[0\] +wb_adr_i\[8\] +wb_adr_i\[7\] +wb_adr_i\[6\] +wb_adr_i\[5\] +wb_adr_i\[4\] +wb_adr_i\[3\] +wb_adr_i\[2\] +wb_adr_i\[1\] +wb_adr_i\[0\] +wb_dat_i\[31\] +wb_dat_i\[30\] +wb_dat_i\[29\] +wb_dat_i\[28\] +wb_dat_i\[27\] +wb_dat_i\[26\] +wb_dat_i\[25\] +wb_dat_i\[24\] +wb_dat_i\[23\] +wb_dat_i\[22\] +wb_dat_i\[21\] +wb_dat_i\[20\] +wb_dat_i\[19\] +wb_dat_i\[18\] +wb_dat_i\[17\] +wb_dat_i\[16\] +wb_dat_i\[15\] +wb_dat_i\[14\] +wb_dat_i\[13\] +wb_dat_i\[12\] +wb_dat_i\[11\] +wb_dat_i\[10\] +wb_dat_i\[9\] +wb_dat_i\[8\] +wb_dat_i\[7\] +wb_dat_i\[6\] +wb_dat_i\[5\] +wb_dat_i\[4\] +wb_dat_i\[3\] +wb_dat_i\[2\] +wb_dat_i\[1\] +wb_dat_i\[0\] +wb_sel_i\[3\] +wb_sel_i\[2\] +wb_sel_i\[1\] +wb_sel_i\[0\] +wb_dat_o\[31\] +wb_dat_o\[30\] +wb_dat_o\[29\] +wb_dat_o\[28\] +wb_dat_o\[27\] +wb_dat_o\[26\] +wb_dat_o\[25\] +wb_dat_o\[24\] +wb_dat_o\[23\] +wb_dat_o\[22\] +wb_dat_o\[21\] +wb_dat_o\[20\] +wb_dat_o\[19\] +wb_dat_o\[18\] +wb_dat_o\[17\] +wb_dat_o\[16\] +wb_dat_o\[15\] +wb_dat_o\[14\] +wb_dat_o\[13\] +wb_dat_o\[12\] +wb_dat_o\[11\] +wb_dat_o\[10\] +wb_dat_o\[9\] +wb_dat_o\[8\] +wb_dat_o\[7\] +wb_dat_o\[6\] +wb_dat_o\[5\] +wb_dat_o\[4\] +wb_dat_o\[3\] +wb_dat_o\[2\] +wb_dat_o\[1\] +wb_dat_o\[0\] +wb_ack_o +wb_err_o + + +bist_error_cnt3\[3\] 0150 0 2 +bist_error_cnt3\[2\] +bist_error_cnt3\[1\] +bist_error_cnt3\[0\] +bist_correct\[3\] +bist_error\[3\] +bist_error_cnt2\[3\] +bist_error_cnt2\[2\] +bist_error_cnt2\[1\] +bist_error_cnt2\[0\] +bist_correct\[2\] +bist_error\[2\] +bist_error_cnt1\[3\] +bist_error_cnt1\[2\] +bist_error_cnt1\[1\] +bist_error_cnt1\[0\] +bist_correct\[1\] +bist_error\[1\] +bist_error_cnt0\[3\] +bist_error_cnt0\[2\] +bist_error_cnt0\[1\] +bist_error_cnt0\[0\] +bist_correct\[0\] +bist_error\[0\] +bist_done +bist_sdo +bist_shift +bist_sdi +bist_load +bist_run +bist_en + +#S +mem_clk_a\[0\] 250 0 2 +mem_cen_a\[0\] +mem_web_a\[0\] +mem_addr_a0\[0\] +mem_addr_a0\[1\] +mem_addr_a0\[2\] +mem_addr_a0\[3\] +mem_addr_a0\[4\] +mem_addr_a0\[5\] +mem_addr_a0\[6\] +mem_addr_a0\[7\] +mem_addr_a0\[8\] +mem_mask_a0\[0\] +mem_mask_a0\[1\] +mem_mask_a0\[2\] +mem_mask_a0\[3\] +mem_din_a0\[0\] +mem_din_a0\[1\] +mem_din_a0\[2\] +mem_din_a0\[3\] +mem_din_a0\[4\] +mem_din_a0\[5\] +mem_din_a0\[6\] +mem_din_a0\[7\] +mem_din_a0\[8\] +mem_din_a0\[9\] +mem_din_a0\[10\] +mem_din_a0\[11\] +mem_din_a0\[12\] +mem_din_a0\[13\] +mem_din_a0\[14\] +mem_din_a0\[15\] +mem_din_a0\[16\] +mem_din_a0\[17\] +mem_din_a0\[18\] +mem_din_a0\[19\] +mem_din_a0\[20\] +mem_din_a0\[21\] +mem_din_a0\[22\] +mem_din_a0\[23\] +mem_din_a0\[24\] +mem_din_a0\[25\] +mem_din_a0\[26\] +mem_din_a0\[27\] +mem_din_a0\[28\] +mem_din_a0\[29\] +mem_din_a0\[30\] +mem_din_a0\[31\] + + +mem_dout_a0\[0\] 350 0 2 +mem_dout_a0\[1\] +mem_dout_a0\[2\] +mem_dout_a0\[3\] +mem_dout_a0\[4\] +mem_dout_a0\[5\] +mem_dout_a0\[6\] +mem_dout_a0\[7\] +mem_dout_a0\[8\] +mem_dout_a0\[9\] +mem_dout_a0\[10\] +mem_dout_a0\[11\] +mem_dout_a0\[12\] +mem_dout_a0\[13\] +mem_dout_a0\[14\] +mem_dout_a0\[15\] +mem_dout_a0\[16\] +mem_dout_a0\[17\] +mem_dout_a0\[18\] +mem_dout_a0\[19\] +mem_dout_a0\[20\] +mem_dout_a0\[21\] +mem_dout_a0\[22\] +mem_dout_a0\[23\] +mem_dout_a0\[24\] +mem_dout_a0\[25\] +mem_dout_a0\[26\] +mem_dout_a0\[27\] +mem_dout_a0\[28\] +mem_dout_a0\[29\] +mem_dout_a0\[30\] +mem_dout_a0\[31\] + + +mem_clk_b\[0\] 0450 0 2 +mem_cen_b\[0\] +mem_addr_b0\[8\] +mem_addr_b0\[7\] +mem_addr_b0\[6\] +mem_addr_b0\[5\] +mem_addr_b0\[4\] +mem_addr_b0\[3\] +mem_addr_b0\[2\] +mem_addr_b0\[1\] +mem_addr_b0\[0\] + + +mem_clk_a\[1\] 1000 0 2 +mem_cen_a\[1\] +mem_web_a\[1\] +mem_addr_a1\[0\] +mem_addr_a1\[1\] +mem_addr_a1\[2\] +mem_addr_a1\[3\] +mem_addr_a1\[4\] +mem_addr_a1\[5\] +mem_addr_a1\[6\] +mem_addr_a1\[7\] +mem_addr_a1\[8\] +mem_mask_a1\[0\] +mem_mask_a1\[1\] +mem_mask_a1\[2\] +mem_mask_a1\[3\] +mem_din_a1\[0\] +mem_din_a1\[1\] +mem_din_a1\[2\] +mem_din_a1\[3\] +mem_din_a1\[4\] +mem_din_a1\[5\] +mem_din_a1\[6\] +mem_din_a1\[7\] +mem_din_a1\[8\] +mem_din_a1\[9\] +mem_din_a1\[10\] +mem_din_a1\[11\] +mem_din_a1\[12\] +mem_din_a1\[13\] +mem_din_a1\[14\] +mem_din_a1\[15\] +mem_din_a1\[16\] +mem_din_a1\[17\] +mem_din_a1\[18\] +mem_din_a1\[19\] +mem_din_a1\[20\] +mem_din_a1\[21\] +mem_din_a1\[22\] +mem_din_a1\[23\] +mem_din_a1\[24\] +mem_din_a1\[25\] +mem_din_a1\[26\] +mem_din_a1\[27\] +mem_din_a1\[28\] +mem_din_a1\[29\] +mem_din_a1\[30\] +mem_din_a1\[31\] + + +mem_dout_a1\[0\] 1100 0 2 +mem_dout_a1\[1\] +mem_dout_a1\[2\] +mem_dout_a1\[3\] +mem_dout_a1\[4\] +mem_dout_a1\[5\] +mem_dout_a1\[6\] +mem_dout_a1\[7\] +mem_dout_a1\[8\] +mem_dout_a1\[9\] +mem_dout_a1\[10\] +mem_dout_a1\[11\] +mem_dout_a1\[12\] +mem_dout_a1\[13\] +mem_dout_a1\[14\] +mem_dout_a1\[15\] +mem_dout_a1\[16\] +mem_dout_a1\[17\] +mem_dout_a1\[18\] +mem_dout_a1\[19\] +mem_dout_a1\[20\] +mem_dout_a1\[21\] +mem_dout_a1\[22\] +mem_dout_a1\[23\] +mem_dout_a1\[24\] +mem_dout_a1\[25\] +mem_dout_a1\[26\] +mem_dout_a1\[27\] +mem_dout_a1\[28\] +mem_dout_a1\[29\] +mem_dout_a1\[30\] +mem_dout_a1\[31\] + + +mem_clk_b\[1\] 1200 0 2 +mem_cen_b\[1\] +mem_addr_b1\[8\] +mem_addr_b1\[7\] +mem_addr_b1\[6\] +mem_addr_b1\[5\] +mem_addr_b1\[4\] +mem_addr_b1\[3\] +mem_addr_b1\[2\] +mem_addr_b1\[1\] +mem_addr_b1\[0\] + + +#N +mem_clk_a\[2\] 250 0 2 +mem_cen_a\[2\] +mem_web_a\[2\] +mem_addr_a2\[0\] +mem_addr_a2\[1\] +mem_addr_a2\[2\] +mem_addr_a2\[3\] +mem_addr_a2\[4\] +mem_addr_a2\[5\] +mem_addr_a2\[6\] +mem_addr_a2\[7\] +mem_addr_a2\[8\] +mem_mask_a2\[0\] +mem_mask_a2\[1\] +mem_mask_a2\[2\] +mem_mask_a2\[3\] +mem_din_a2\[0\] +mem_din_a2\[1\] +mem_din_a2\[2\] +mem_din_a2\[3\] +mem_din_a2\[4\] +mem_din_a2\[5\] +mem_din_a2\[6\] +mem_din_a2\[7\] +mem_din_a2\[8\] +mem_din_a2\[9\] +mem_din_a2\[10\] +mem_din_a2\[11\] +mem_din_a2\[12\] +mem_din_a2\[13\] +mem_din_a2\[14\] +mem_din_a2\[15\] +mem_din_a2\[16\] +mem_din_a2\[17\] +mem_din_a2\[18\] +mem_din_a2\[19\] +mem_din_a2\[20\] +mem_din_a2\[21\] +mem_din_a2\[22\] +mem_din_a2\[23\] +mem_din_a2\[24\] +mem_din_a2\[25\] +mem_din_a2\[26\] +mem_din_a2\[27\] +mem_din_a2\[28\] +mem_din_a2\[29\] +mem_din_a2\[30\] +mem_din_a2\[31\] + + +mem_dout_a2\[0\] 0350 0 2 +mem_dout_a2\[1\] +mem_dout_a2\[2\] +mem_dout_a2\[3\] +mem_dout_a2\[4\] +mem_dout_a2\[5\] +mem_dout_a2\[6\] +mem_dout_a2\[7\] +mem_dout_a2\[8\] +mem_dout_a2\[9\] +mem_dout_a2\[10\] +mem_dout_a2\[11\] +mem_dout_a2\[12\] +mem_dout_a2\[13\] +mem_dout_a2\[14\] +mem_dout_a2\[15\] +mem_dout_a2\[16\] +mem_dout_a2\[17\] +mem_dout_a2\[18\] +mem_dout_a2\[19\] +mem_dout_a2\[20\] +mem_dout_a2\[21\] +mem_dout_a2\[22\] +mem_dout_a2\[23\] +mem_dout_a2\[24\] +mem_dout_a2\[25\] +mem_dout_a2\[26\] +mem_dout_a2\[27\] +mem_dout_a2\[28\] +mem_dout_a2\[29\] +mem_dout_a2\[30\] +mem_dout_a2\[31\] + + +mem_clk_b\[2\] 0450 0 2 +mem_cen_b\[2\] +mem_addr_b2\[8\] +mem_addr_b2\[7\] +mem_addr_b2\[6\] +mem_addr_b2\[5\] +mem_addr_b2\[4\] +mem_addr_b2\[3\] +mem_addr_b2\[2\] +mem_addr_b2\[1\] +mem_addr_b2\[0\] + + +mem_clk_a\[3\] 1000 0 2 +mem_cen_a\[3\] +mem_web_a\[3\] +mem_addr_a3\[0\] +mem_addr_a3\[1\] +mem_addr_a3\[2\] +mem_addr_a3\[3\] +mem_addr_a3\[4\] +mem_addr_a3\[5\] +mem_addr_a3\[6\] +mem_addr_a3\[7\] +mem_addr_a3\[8\] +mem_mask_a3\[0\] +mem_mask_a3\[1\] +mem_mask_a3\[2\] +mem_mask_a3\[3\] +mem_din_a3\[0\] +mem_din_a3\[1\] +mem_din_a3\[2\] +mem_din_a3\[3\] +mem_din_a3\[4\] +mem_din_a3\[5\] +mem_din_a3\[6\] +mem_din_a3\[7\] +mem_din_a3\[8\] +mem_din_a3\[9\] +mem_din_a3\[10\] +mem_din_a3\[11\] +mem_din_a3\[12\] +mem_din_a3\[13\] +mem_din_a3\[14\] +mem_din_a3\[15\] +mem_din_a3\[16\] +mem_din_a3\[17\] +mem_din_a3\[18\] +mem_din_a3\[19\] +mem_din_a3\[20\] +mem_din_a3\[21\] +mem_din_a3\[22\] +mem_din_a3\[23\] +mem_din_a3\[24\] +mem_din_a3\[25\] +mem_din_a3\[26\] +mem_din_a3\[27\] +mem_din_a3\[28\] +mem_din_a3\[29\] +mem_din_a3\[30\] +mem_din_a3\[31\] + + +mem_dout_a3\[0\] 1100 0 2 +mem_dout_a3\[1\] +mem_dout_a3\[2\] +mem_dout_a3\[3\] +mem_dout_a3\[4\] +mem_dout_a3\[5\] +mem_dout_a3\[6\] +mem_dout_a3\[7\] +mem_dout_a3\[8\] +mem_dout_a3\[9\] +mem_dout_a3\[10\] +mem_dout_a3\[11\] +mem_dout_a3\[12\] +mem_dout_a3\[13\] +mem_dout_a3\[14\] +mem_dout_a3\[15\] +mem_dout_a3\[16\] +mem_dout_a3\[17\] +mem_dout_a3\[18\] +mem_dout_a3\[19\] +mem_dout_a3\[20\] +mem_dout_a3\[21\] +mem_dout_a3\[22\] +mem_dout_a3\[23\] +mem_dout_a3\[24\] +mem_dout_a3\[25\] +mem_dout_a3\[26\] +mem_dout_a3\[27\] +mem_dout_a3\[28\] +mem_dout_a3\[29\] +mem_dout_a3\[30\] +mem_dout_a3\[31\] + + +mem_clk_b\[3\] 1200 0 2 +mem_cen_b\[3\] +mem_addr_b3\[8\] +mem_addr_b3\[7\] +mem_addr_b3\[6\] +mem_addr_b3\[5\] +mem_addr_b3\[4\] +mem_addr_b3\[3\] +mem_addr_b3\[2\] +mem_addr_b3\[1\] +mem_addr_b3\[0\] +
diff --git a/openlane/mbist/sta.tcl b/openlane/mbist/sta.tcl new file mode 100644 index 0000000..57a6c35 --- /dev/null +++ b/openlane/mbist/sta.tcl
@@ -0,0 +1,88 @@ +# SPDX-FileCopyrightText: 2021 , Dinesh Annayya +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 +# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> + + +set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib" +set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib" +set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib" +set ::env(DESIGN_NAME) "mbist_top" +set ::env(BASE_SDC_FILE) "base.sdc" +set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8" +set ::env(SYNTH_DRIVING_CELL_PIN) "Y" +set ::env(SYNTH_CAP_LOAD) "17.65" +set ::env(WIRE_RC_LAYER) "met1" + +#To disable empty filler cell black box get created +#set link_make_black_boxes 0 + + +set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um +define_corners wc bc tt +read_liberty -corner bc $::env(LIB_FASTEST) +read_liberty -corner wc $::env(LIB_SLOWEST) +read_liberty -corner tt $::env(LIB_TYPICAL) + + +read_verilog ../user_project_wrapper/netlist/mbist.v +link_design $::env(DESIGN_NAME) + + +read_spef ../../spef/mbist_top.spef + + +read_sdc -echo $::env(BASE_SDC_FILE) + +# check for missing constraints +check_setup -verbose > unconstraints.rpt + +set_operating_conditions -analysis_type single +# Propgate the clock +set_propagated_clock [all_clocks] + +report_tns +report_wns +#report_power +echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_ss_max.rpt +report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc >> timing_ss_max.rpt +report_checks -group_count 100 -path_delay max -path_group bist_clk -corner wc >> timing_ss_max.rpt +report_checks -group_count 100 -path_delay max -path_group mem_clk_a -corner wc >> timing_ss_max.rpt +report_checks -group_count 100 -path_delay max -path_group mem_clk_b -corner wc >> timing_ss_max.rpt +report_checks -path_delay max -corner wc >> timing_ss_max.rpt + +echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_ff_min.rpt +report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc >> timing_ff_min.rpt +report_checks -group_count 100 -path_delay min -path_group bist_clk -corner bc >> timing_ff_min.rpt +report_checks -group_count 100 -path_delay min -path_group mem_clk_a -corner bc >> timing_ff_min.rpt +report_checks -group_count 100 -path_delay min -path_group mem_clk_b -corner bc >> timing_ff_min.rpt +report_checks -path_delay min -corner bc >> timing_ff_min.rpt + +echo "################ CORNER : TT (MAX) TIMING Report ###################" > timing_tt_max.rpt +report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_max.rpt +report_checks -group_count 100 -path_delay max -path_group bist_clk -corner tt >> timing_tt_max.rpt +report_checks -group_count 100 -path_delay max -path_group mem_clk_a -corner tt >> timing_tt_max.rpt +report_checks -group_count 100 -path_delay max -path_group mem_clk_b -corner tt >> timing_tt_max.rpt +report_checks -path_delay min -corner tt >> timing_tt_min.rpt + +echo "################ CORNER : TT (MIN) TIMING Report ###################" > timing_tt_min.rpt +report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_min.rpt +report_checks -group_count 100 -path_delay min -path_group bist_clk -corner tt >> timing_tt_min.rpt +report_checks -group_count 100 -path_delay min -path_group mem_clk_a -corner tt >> timing_tt_min.rpt +report_checks -group_count 100 -path_delay min -path_group mem_clk_b -corner tt >> timing_tt_min.rpt +report_checks -path_delay min -corner tt >> timing_tt_min.rpt + +report_checks -path_delay min + +#exit
diff --git a/openlane/pinmux/base.sdc b/openlane/pinmux/base.sdc index b6a4983..cbbfba5 100644 --- a/openlane/pinmux/base.sdc +++ b/openlane/pinmux/base.sdc
@@ -36,24 +36,24 @@ set_input_delay 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {h_reset_n}] -set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}] -set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}] -set_input_delay -max 6.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}] +set_input_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}] +set_input_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}] +set_input_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}] +set_input_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}] +set_input_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}] -set_input_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}] +set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_addr[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_be[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_cs}] +set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wdata[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_wr}] -set_output_delay -max 4.5000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}] -set_output_delay -max 4.5000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}] +set_output_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}] +set_output_delay -max 4.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}] -set_output_delay -min 1.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_ack}] +set_output_delay -min 2.0000 -clock [get_clocks {mclk}] -add_delay [get_ports {reg_rdata[*]}] ############################################################################### # Environment ###############################################################################
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl index 99ecdb7..ce6c000 100755 --- a/openlane/pinmux/config.tcl +++ b/openlane/pinmux/config.tcl
@@ -31,6 +31,11 @@ set ::env(SYNTH_MAX_FANOUT) 4 +## CTS BUFFER +set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" +set ::env(CTS_SINK_CLUSTERING_SIZE) "16" +set ::env(CLOCK_BUFFER_FANOUT) "8" + # Sources # ------- @@ -74,7 +79,7 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.35" +set ::env(PL_TARGET_DENSITY) "0.30" set ::env(CELL_PAD) "4"
diff --git a/openlane/pinmux/pin_order.cfg b/openlane/pinmux/pin_order.cfg index 3a35f08..05643c9 100644 --- a/openlane/pinmux/pin_order.cfg +++ b/openlane/pinmux/pin_order.cfg
@@ -66,13 +66,6 @@ bist_error_cnt3\[0\] bist_correct\[3\] bist_error\[3\] -bist_done\[3\] -bist_sdo\[3\] -bist_shift\[3\] -bist_sdi\[3\] -bist_load\[3\] -bist_run\[3\] -bist_en\[3\] bist_error_cnt2\[3\] bist_error_cnt2\[2\] @@ -80,13 +73,6 @@ bist_error_cnt2\[0\] bist_correct\[2\] bist_error\[2\] -bist_done\[2\] -bist_sdo\[2\] -bist_shift\[2\] -bist_sdi\[2\] -bist_load\[2\] -bist_run\[2\] -bist_en\[2\] bist_error_cnt1\[3\] bist_error_cnt1\[2\] @@ -94,13 +80,6 @@ bist_error_cnt1\[0\] bist_correct\[1\] bist_error\[1\] -bist_done\[1\] -bist_sdo\[1\] -bist_shift\[1\] -bist_sdi\[1\] -bist_load\[1\] -bist_run\[1\] -bist_en\[1\] bist_error_cnt0\[3\] bist_error_cnt0\[2\] @@ -108,13 +87,13 @@ bist_error_cnt0\[0\] bist_correct\[0\] bist_error\[0\] -bist_done\[0\] -bist_sdo\[0\] -bist_shift\[0\] -bist_sdi\[0\] -bist_load\[0\] -bist_run\[0\] -bist_en\[0\] +bist_done +bist_sdo +bist_shift +bist_sdi +bist_load +bist_run +bist_en soft_irq irq_lines\[15\]
diff --git a/openlane/qspim/config.tcl b/openlane/qspim/config.tcl index 4b3958f..a29839a 100755 --- a/openlane/qspim/config.tcl +++ b/openlane/qspim/config.tcl
@@ -31,6 +31,11 @@ set ::env(SYNTH_MAX_FANOUT) 4 +## CTS BUFFER +set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" +set ::env(CTS_SINK_CLUSTERING_SIZE) "16" +set ::env(CLOCK_BUFFER_FANOUT) "8" + # Sources # -------
diff --git a/openlane/syntacore/config.tcl b/openlane/syntacore/config.tcl index 5f94296..57a674a 100755 --- a/openlane/syntacore/config.tcl +++ b/openlane/syntacore/config.tcl
@@ -30,6 +30,11 @@ set ::env(SYNTH_MAX_FANOUT) 4 +## CTS BUFFER +set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" +set ::env(CTS_SINK_CLUSTERING_SIZE) "16" +set ::env(CLOCK_BUFFER_FANOUT) "8" + # Sources # ------- @@ -70,6 +75,7 @@ set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes ] set ::env(SYNTH_READ_BLACKBOX_LIB) 1 +set ::env(SYNTH_DEFINES) [list SYNTHESIS ] set ::env(SDC_FILE) "$script_dir/base.sdc" set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" @@ -88,7 +94,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) [list 0.0 0.0 1500.0 500.0] +set ::env(DIE_AREA) [list 0.0 0.0 1520.0 520.0] # If you're going to use multiple power domains, then keep this disabled. @@ -98,7 +104,7 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.33" +set ::env(PL_TARGET_DENSITY) "0.32" # helps in anteena fix set ::env(USE_ARC_ANTENNA_CHECK) "0"
diff --git a/openlane/syntacore/pin_order.cfg b/openlane/syntacore/pin_order.cfg index cf28a0a..d9738fe 100644 --- a/openlane/syntacore/pin_order.cfg +++ b/openlane/syntacore/pin_order.cfg
@@ -63,7 +63,7 @@ wb_clk -wbd_imem_stb_o 0150 0 +wbd_imem_stb_o 0200 0 wbd_imem_we_o wbd_imem_adr_o\[31\] wbd_imem_adr_o\[30\] @@ -274,131 +274,267 @@ wbd_dmem_err_i +#N +sram0_clk0 250 0 2 +sram0_csb0 +sram0_web0 +sram0_addr0\[0\] +sram0_addr0\[1\] +sram0_addr0\[2\] +sram0_addr0\[3\] +sram0_addr0\[4\] +sram0_addr0\[5\] +sram0_addr0\[6\] +sram0_addr0\[7\] +sram0_addr0\[8\] +sram0_wmask0\[0\] +sram0_wmask0\[1\] +sram0_wmask0\[2\] +sram0_wmask0\[3\] +sram0_din0\[0\] +sram0_din0\[1\] +sram0_din0\[2\] +sram0_din0\[3\] +sram0_din0\[4\] +sram0_din0\[5\] +sram0_din0\[6\] +sram0_din0\[7\] +sram0_din0\[8\] +sram0_din0\[9\] +sram0_din0\[10\] +sram0_din0\[11\] +sram0_din0\[12\] +sram0_din0\[13\] +sram0_din0\[14\] +sram0_din0\[15\] +sram0_din0\[16\] +sram0_din0\[17\] +sram0_din0\[18\] +sram0_din0\[19\] +sram0_din0\[20\] +sram0_din0\[21\] +sram0_din0\[22\] +sram0_din0\[23\] +sram0_din0\[24\] +sram0_din0\[25\] +sram0_din0\[26\] +sram0_din0\[27\] +sram0_din0\[28\] +sram0_din0\[29\] +sram0_din0\[30\] +sram0_din0\[31\] + + +sram0_dout0\[0\] 0350 0 2 +sram0_dout0\[1\] +sram0_dout0\[2\] +sram0_dout0\[3\] +sram0_dout0\[4\] +sram0_dout0\[5\] +sram0_dout0\[6\] +sram0_dout0\[7\] +sram0_dout0\[8\] +sram0_dout0\[9\] +sram0_dout0\[10\] +sram0_dout0\[11\] +sram0_dout0\[12\] +sram0_dout0\[13\] +sram0_dout0\[14\] +sram0_dout0\[15\] +sram0_dout0\[16\] +sram0_dout0\[17\] +sram0_dout0\[18\] +sram0_dout0\[19\] +sram0_dout0\[20\] +sram0_dout0\[21\] +sram0_dout0\[22\] +sram0_dout0\[23\] +sram0_dout0\[24\] +sram0_dout0\[25\] +sram0_dout0\[26\] +sram0_dout0\[27\] +sram0_dout0\[28\] +sram0_dout0\[29\] +sram0_dout0\[30\] +sram0_dout0\[31\] + + +sram0_clk1 0450 0 2 +sram0_csb1 +sram0_addr1\[8\] +sram0_addr1\[7\] +sram0_addr1\[6\] +sram0_addr1\[5\] +sram0_addr1\[4\] +sram0_addr1\[3\] +sram0_addr1\[2\] +sram0_addr1\[1\] +sram0_addr1\[0\] + +sram0_dout1\[0\] 0550 0 2 +sram0_dout1\[1\] +sram0_dout1\[2\] +sram0_dout1\[3\] +sram0_dout1\[4\] +sram0_dout1\[5\] +sram0_dout1\[6\] +sram0_dout1\[7\] +sram0_dout1\[8\] +sram0_dout1\[9\] +sram0_dout1\[10\] +sram0_dout1\[11\] +sram0_dout1\[12\] +sram0_dout1\[13\] +sram0_dout1\[14\] +sram0_dout1\[15\] +sram0_dout1\[16\] +sram0_dout1\[17\] +sram0_dout1\[18\] +sram0_dout1\[19\] +sram0_dout1\[20\] +sram0_dout1\[21\] +sram0_dout1\[22\] +sram0_dout1\[23\] +sram0_dout1\[24\] +sram0_dout1\[25\] +sram0_dout1\[26\] +sram0_dout1\[27\] +sram0_dout1\[28\] +sram0_dout1\[29\] +sram0_dout1\[30\] +sram0_dout1\[31\] + + +sram1_clk0 1000 0 2 +sram1_csb0 +sram1_web0 +sram1_addr0\[0\] +sram1_addr0\[1\] +sram1_addr0\[2\] +sram1_addr0\[3\] +sram1_addr0\[4\] +sram1_addr0\[5\] +sram1_addr0\[6\] +sram1_addr0\[7\] +sram1_addr0\[8\] +sram1_wmask0\[0\] +sram1_wmask0\[1\] +sram1_wmask0\[2\] +sram1_wmask0\[3\] +sram1_din0\[0\] +sram1_din0\[1\] +sram1_din0\[2\] +sram1_din0\[3\] +sram1_din0\[4\] +sram1_din0\[5\] +sram1_din0\[6\] +sram1_din0\[7\] +sram1_din0\[8\] +sram1_din0\[9\] +sram1_din0\[10\] +sram1_din0\[11\] +sram1_din0\[12\] +sram1_din0\[13\] +sram1_din0\[14\] +sram1_din0\[15\] +sram1_din0\[16\] +sram1_din0\[17\] +sram1_din0\[18\] +sram1_din0\[19\] +sram1_din0\[20\] +sram1_din0\[21\] +sram1_din0\[22\] +sram1_din0\[23\] +sram1_din0\[24\] +sram1_din0\[25\] +sram1_din0\[26\] +sram1_din0\[27\] +sram1_din0\[28\] +sram1_din0\[29\] +sram1_din0\[30\] +sram1_din0\[31\] + + +sram1_dout0\[0\] 1100 0 2 +sram1_dout0\[1\] +sram1_dout0\[2\] +sram1_dout0\[3\] +sram1_dout0\[4\] +sram1_dout0\[5\] +sram1_dout0\[6\] +sram1_dout0\[7\] +sram1_dout0\[8\] +sram1_dout0\[9\] +sram1_dout0\[10\] +sram1_dout0\[11\] +sram1_dout0\[12\] +sram1_dout0\[13\] +sram1_dout0\[14\] +sram1_dout0\[15\] +sram1_dout0\[16\] +sram1_dout0\[17\] +sram1_dout0\[18\] +sram1_dout0\[19\] +sram1_dout0\[20\] +sram1_dout0\[21\] +sram1_dout0\[22\] +sram1_dout0\[23\] +sram1_dout0\[24\] +sram1_dout0\[25\] +sram1_dout0\[26\] +sram1_dout0\[27\] +sram1_dout0\[28\] +sram1_dout0\[29\] +sram1_dout0\[30\] +sram1_dout0\[31\] + + +sram1_clk1 1200 0 2 +sram1_csb1 +sram1_addr1\[8\] +sram1_addr1\[7\] +sram1_addr1\[6\] +sram1_addr1\[5\] +sram1_addr1\[4\] +sram1_addr1\[3\] +sram1_addr1\[2\] +sram1_addr1\[1\] +sram1_addr1\[0\] + +sram1_dout1\[0\] 1300 0 2 +sram1_dout1\[1\] +sram1_dout1\[2\] +sram1_dout1\[3\] +sram1_dout1\[4\] +sram1_dout1\[5\] +sram1_dout1\[6\] +sram1_dout1\[7\] +sram1_dout1\[8\] +sram1_dout1\[9\] +sram1_dout1\[10\] +sram1_dout1\[11\] +sram1_dout1\[12\] +sram1_dout1\[13\] +sram1_dout1\[14\] +sram1_dout1\[15\] +sram1_dout1\[16\] +sram1_dout1\[17\] +sram1_dout1\[18\] +sram1_dout1\[19\] +sram1_dout1\[20\] +sram1_dout1\[21\] +sram1_dout1\[22\] +sram1_dout1\[23\] +sram1_dout1\[24\] +sram1_dout1\[25\] +sram1_dout1\[26\] +sram1_dout1\[27\] +sram1_dout1\[28\] +sram1_dout1\[29\] +sram1_dout1\[30\] +sram1_dout1\[31\] + #S -sram_dout0\[31\] 000 0 4 -sram_dout0\[30\] -sram_dout0\[29\] -sram_dout0\[28\] -sram_dout0\[27\] -sram_dout0\[26\] -sram_dout0\[25\] -sram_dout0\[24\] -sram_dout0\[23\] -sram_dout0\[22\] -sram_dout0\[21\] -sram_dout0\[20\] -sram_dout0\[19\] -sram_dout0\[18\] -sram_dout0\[17\] -sram_dout0\[16\] -sram_dout0\[15\] -sram_dout0\[14\] -sram_dout0\[13\] -sram_dout0\[12\] -sram_dout0\[11\] -sram_dout0\[10\] -sram_dout0\[9\] -sram_dout0\[8\] -sram_dout0\[7\] -sram_dout0\[6\] -sram_dout0\[5\] -sram_dout0\[4\] -sram_dout0\[3\] -sram_dout0\[2\] -sram_dout0\[1\] -sram_dout0\[0\] - -sram_din0\[31\] 200 0 4 -sram_din0\[30\] -sram_din0\[29\] -sram_din0\[28\] -sram_din0\[27\] -sram_din0\[26\] -sram_din0\[25\] -sram_din0\[24\] -sram_din0\[23\] -sram_din0\[22\] -sram_din0\[21\] -sram_din0\[20\] -sram_din0\[19\] -sram_din0\[18\] -sram_din0\[17\] -sram_din0\[16\] -sram_din0\[15\] -sram_din0\[14\] -sram_din0\[13\] -sram_din0\[12\] -sram_din0\[11\] -sram_din0\[10\] -sram_din0\[9\] -sram_din0\[8\] -sram_din0\[7\] -sram_din0\[6\] -sram_din0\[5\] -sram_din0\[4\] -sram_din0\[3\] -sram_din0\[2\] -sram_din0\[1\] -sram_din0\[0\] -sram_wmask0\[3\] -sram_wmask0\[2\] -sram_wmask0\[1\] -sram_wmask0\[0\] -sram_web0 -sram_csb0 -sram_addr0\[8\] -sram_addr0\[7\] -sram_addr0\[6\] -sram_addr0\[5\] -sram_addr0\[4\] -sram_addr0\[3\] -sram_addr0\[2\] -sram_addr0\[1\] -sram_addr0\[0\] - -sram_csb1 400 0 4 -sram_addr1\[8\] -sram_addr1\[7\] -sram_addr1\[6\] -sram_addr1\[5\] -sram_addr1\[4\] -sram_addr1\[3\] -sram_addr1\[2\] -sram_addr1\[1\] -sram_addr1\[0\] -sram_dout1\[0\] -sram_dout1\[1\] -sram_dout1\[2\] -sram_dout1\[3\] -sram_dout1\[4\] -sram_dout1\[5\] -sram_dout1\[6\] -sram_dout1\[7\] -sram_dout1\[8\] -sram_dout1\[9\] -sram_dout1\[10\] -sram_dout1\[11\] -sram_dout1\[12\] -sram_dout1\[13\] -sram_dout1\[14\] -sram_dout1\[15\] -sram_dout1\[16\] -sram_dout1\[17\] -sram_dout1\[18\] -sram_dout1\[19\] -sram_dout1\[20\] -sram_dout1\[21\] -sram_dout1\[22\] -sram_dout1\[23\] -sram_dout1\[24\] -sram_dout1\[25\] -sram_dout1\[26\] -sram_dout1\[27\] -sram_dout1\[28\] -sram_dout1\[29\] -sram_dout1\[30\] -sram_dout1\[31\] - riscv_debug\[0\] 1000 0 2 riscv_debug\[1\] riscv_debug\[2\] @@ -465,7 +601,7 @@ riscv_debug\[63\] -wb_rst_n 1200 0 2 +wb_rst_n 1450 0 2 pwrup_rst_n rst_n core_clk
diff --git a/openlane/uart_i2cm_usb_spi/base.sdc b/openlane/uart_i2cm_usb_spi/base.sdc index 8623b71..bee06d8 100644 --- a/openlane/uart_i2cm_usb_spi/base.sdc +++ b/openlane/uart_i2cm_usb_spi/base.sdc
@@ -7,33 +7,18 @@ # Timing Constraints ############################################################################### create_clock -name app_clk -period 10.0000 [get_ports {app_clk}] -create_clock -name line_clk -period 100.0000 [get_pins {u_uart_core.u_lineclk_buf.u_buf/X}] +create_clock -name line_clk -period 100.0000 [get_pins {u_uart_core.u_lineclk_buf.u_mux/X}] create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}] -set_clock_uncertainty -rise_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -hold 0.2500 -set_clock_uncertainty -rise_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -setup 0.2500 -set_clock_uncertainty -rise_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -hold 0.2500 -set_clock_uncertainty -rise_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -setup 0.2500 -set_clock_uncertainty -fall_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -hold 0.2500 -set_clock_uncertainty -fall_from [get_clocks {app_clk}] -rise_to [get_clocks {app_clk}] -setup 0.2500 -set_clock_uncertainty -fall_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -hold 0.2500 -set_clock_uncertainty -fall_from [get_clocks {app_clk}] -fall_to [get_clocks {app_clk}] -setup 0.2500 -set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -hold 0.2500 -set_clock_uncertainty -rise_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -setup 0.2500 -set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -hold 0.2500 -set_clock_uncertainty -rise_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -setup 0.2500 -set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -hold 0.2500 -set_clock_uncertainty -fall_from [get_clocks {line_clk}] -rise_to [get_clocks {line_clk}] -setup 0.2500 -set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -hold 0.2500 -set_clock_uncertainty -fall_from [get_clocks {line_clk}] -fall_to [get_clocks {line_clk}] -setup 0.2500 +set_clock_transition 0.1500 [all_clocks] +set_clock_uncertainty -setup 0.2500 [all_clocks] +set_clock_uncertainty -hold 0.2500 [all_clocks] -set ::env(SYNTH_TIMING_DERATE) 0.05 -puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" -set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] -set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] + set_clock_groups -name async_clock -asynchronous \ -group [get_clocks {app_clk}]\ + -group [get_clocks {usb_clk}]\ -group [get_clocks {line_clk}] -comment {Async Clock group} ### ClkSkew Adjust @@ -43,15 +28,15 @@ set_case_analysis 0 [get_ports {cfg_cska_uart[3]}] -set_max_delay 3.5 -from [get_ports {wbd_clk_int}] -set_max_delay 2 -to [get_ports {wbd_clk_uart}] -set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_uart +set_max_delay 5 -from [get_ports {wbd_clk_int}] +set_max_delay 5 -to [get_ports {wbd_clk_uart}] +set_max_delay 5 -from wbd_clk_int -to wbd_clk_uart -set_input_delay 2.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {i2c_rstn}] -set_input_delay 2.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {uart_rstn}] -set_input_delay 2.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {usb_rstn}] +set_input_delay 3.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {i2c_rstn}] +set_input_delay 3.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {uart_rstn}] +set_input_delay 3.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {usb_rstn}] set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_addr[*]}] @@ -80,15 +65,11 @@ set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] puts "\[INFO\]: Setting load to: $cap_load" set_load $cap_load [all_outputs] -############################################################################### -# Design Rules -############################################################################### -#disable clock gating check at static clock select pins -set_false_path -through [get_pins u_cpu_ref_sel.u_mux/S] -set_false_path -through [get_pins u_cpu_clk_sel.u_mux/S] -set_false_path -through [get_pins u_wbs_clk_sel.u_mux/S] -set_false_path -through [get_pins u_usb_clk_sel.u_mux/S] +set ::env(SYNTH_TIMING_DERATE) 0.05 +puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" +set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] +set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] ############################################################################### # Design Rules
diff --git a/openlane/uart_i2cm_usb_spi/config.tcl b/openlane/uart_i2cm_usb_spi/config.tcl index 852ba18..fa19eff 100644 --- a/openlane/uart_i2cm_usb_spi/config.tcl +++ b/openlane/uart_i2cm_usb_spi/config.tcl
@@ -27,10 +27,15 @@ # Timing configuration set ::env(CLOCK_PERIOD) "10" -set ::env(CLOCK_PORT) "app_clk usb_clk u_uart_core.line_clk_16x" +set ::env(CLOCK_PORT) "app_clk usb_clk u_uart_core.u_lineclk_buf.u_mux/X" set ::env(SYNTH_MAX_FANOUT) 4 +## CTS BUFFER +set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" +set ::env(CTS_SINK_CLUSTERING_SIZE) "16" +set ::env(CLOCK_BUFFER_FANOUT) "8" + # Sources # -------
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index d85c42a..97e8153 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -65,7 +65,7 @@ $proj_dir/../../verilog/gl/qspim.v \ $proj_dir/../../verilog/gl/wb_interconnect.v \ $proj_dir/../../verilog/gl/pinmux.v \ - $proj_dir/../../verilog/gl/mbist1.v \ + $proj_dir/../../verilog/gl/mbist.v \ $proj_dir/../../verilog/gl/uart_i2cm_usb_spi.v \ $proj_dir/../../verilog/gl/wb_host.v \ $proj_dir/../../verilog/gl/syntacore.v \ @@ -78,7 +78,7 @@ $lef_root/wb_interconnect.lef \ $lef_root/uart_i2cm_usb_spi.lef \ $lef_root/wb_host.lef \ - $lef_root/mbist1.lef \ + $lef_root/mbist.lef \ $lef_root/syntacore.lef \ $lef_root/sky130_sram_2kbyte_1rw1r_32x512_8.lef \ " @@ -89,7 +89,7 @@ $gds_root/wb_interconnect.gds \ $gds_root/uart_i2cm_usb_spi.gds \ $gds_root/wb_host.gds \ - $gds_root/mbist1.gds \ + $gds_root/mbist.gds \ $gds_root/syntacore.gds \ $gds_root/sky130_sram_2kbyte_1rw1r_32x512_8.gds \ " @@ -114,44 +114,39 @@ set ::env(VDD_PIN) "vccd1 vccd2 vdda1 vdda2" set ::env(GND_PIN) "vssd1 vssd2 vssa1 vssa2" -set ::env(GLB_RT_OBS) " - li1 200 165 883.1 581.54,\ - met1 200 165 883.1 581.54,\ - met2 200 165 883.1 581.54,\ - met3 200 165 883.1 581.54,\ - met4 200 195 883.1 581.54,\ - li1 200 1325 883.1 1741.54,\ - met1 200 1325 883.1 1741.54,\ - met2 200 1325 883.1 1741.54,\ - met3 200 1325 883.1 1741.54,\ - li1 200 1850 883.1 2266.54,\ - met1 200 1850 883.1 2266.54,\ - met2 200 1850 883.1 2266.54,\ - met3 200 1850 883.1 2266.54,\ - li1 200 2400 883.1 2816.54,\ - met1 200 2400 883.1 2816.54,\ - met2 200 2400 883.1 2816.54,\ - met3 200 2400 883.1 2816.54,\ - li1 200 2950 883.1 3366.54,\ - met1 200 2950 883.1 3366.54,\ - met2 200 2950 883.1 3366.54,\ - met3 200 2950 883.1 3366.54,\ - met5 0 0 2920 3520" +set ::env(GLB_RT_OBS) " li1 150 1300 833.1 1716.54,\ + met1 150 1300 833.1 1716.54,\ + met3 150 1300 833.1 1716.54,\ + li1 950 1300 1633.1 1716.54,\ + met1 950 1300 1633.1 1716.54,\ + met2 950 1300 1633.1 1716.54,\ + met3 950 1300 1633.1 1716.54,\ + li1 150 1900 833.1 2316.54,\ + met1 150 1900 833.1 2316.54,\ + met3 150 1900 833.1 2316.54,\ + li1 950 1900 1633.1 2316.54,\ + met1 950 1900 1633.1 2316.54,\ + met3 950 1900 1633.1 2316.54,\ + li1 150 2900 833.1 3316.54,\ + met1 150 2900 833.1 3316.54,\ + met3 150 2900 833.1 3316.54,\ + li1 950 2900 1633.1 3316.54,\ + met1 950 2900 1633.1 3316.54,\ + met3 950 2900 1633.1 3316.54,\ + met5 0 0 2920 3520" set ::env(FP_PDN_MACRO_HOOKS) "\ u_intercon vccd1 vssd1 \ u_pinmux vccd1 vssd1 \ u_qspi_master vccd1 vssd1 \ u_riscv_top vccd1 vssd1 \ - u_sram_2kb vccd1 vssd1 \ - u_mbist1 vccd1 vssd1 \ - u_mbist2 vccd1 vssd1 \ - u_mbist3 vccd1 vssd1 \ - u_mbist4 vccd1 vssd1 \ + u_tsram0_2kb vccd1 vssd1 \ + u_tsram1_2kb vccd1 vssd1 \ + u_mbist vccd1 vssd1 \ + u_sram0_2kb vccd1 vssd1 \ u_sram1_2kb vccd1 vssd1 \ u_sram2_2kb vccd1 vssd1 \ u_sram3_2kb vccd1 vssd1 \ - u_sram4_2kb vccd1 vssd1 \ u_uart_i2c_usb_spi vccd1 vssd1 \ u_wb_host vccd1 vssd1 \ "
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index e8c75d9..b98e50c 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,19 +1,14 @@ -u_qspi_master 2200 700 N -u_uart_i2c_usb_spi 2200 1400 N -u_pinmux 2200 2300 N -u_riscv_top 200 700 N -u_sram_2kb 200 165 N +u_qspi_master 2200 600 N +u_uart_i2c_usb_spi 2200 1300 N +u_pinmux 2200 2200 N +u_riscv_top 150 600 N +u_tsram0_2kb 150 1300 N +u_tsram1_2kb 950 1300 N -u_mbist1 1100 1325 N -u_sram1_2kb 200 1325 N - -u_mbist2 1100 1850 N -u_sram2_2kb 200 1850 N - -u_mbist3 1100 2400 N -u_sram3_2kb 200 2400 N - -u_mbist4 1100 2950 N -u_sram4_2kb 200 2950 N -u_intercon 1850 700 N -u_wb_host 1750 200 N +u_mbist 150 2500 N +u_sram0_2kb 150 1900 N +u_sram1_2kb 950 1900 FS +u_sram2_2kb 150 2900 N +u_sram3_2kb 950 2900 N +u_intercon 1850 600 N +u_wb_host 1850 300 N
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl index a3cd647..3ad1047 100755 --- a/openlane/wb_host/config.tcl +++ b/openlane/wb_host/config.tcl
@@ -30,6 +30,11 @@ set ::env(SYNTH_MAX_FANOUT) 4 +## CTS BUFFER +set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" +set ::env(CTS_SINK_CLUSTERING_SIZE) "16" +set ::env(CLOCK_BUFFER_FANOUT) "8" + # Sources # ------- @@ -60,7 +65,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 350 250" +set ::env(DIE_AREA) "0 0 450 200" # If you're going to use multiple power domains, then keep this disabled.
diff --git a/openlane/wb_host/pin_order.cfg b/openlane/wb_host/pin_order.cfg index 27bcf92..ed4f0bd 100644 --- a/openlane/wb_host/pin_order.cfg +++ b/openlane/wb_host/pin_order.cfg
@@ -28,6 +28,9 @@ cfg_clk_ctrl2\[17\] cfg_clk_ctrl2\[16\] +cpu_clk 0100 0 2 +rtc_clk +cpu_rst_n @@ -145,11 +148,7 @@ #N -cpu_clk 0000 0 2 -rtc_clk -cpu_rst_n - -wbd_int_rst_n 0100 0 2 +wbd_int_rst_n 0000 0 2 cfg_clk_ctrl2\[31\] cfg_clk_ctrl2\[30\] cfg_clk_ctrl2\[29\] @@ -209,7 +208,7 @@ -wbs_stb_o 0160 0 2 +wbs_stb_o 060 0 2 wbs_we_o wbs_adr_o\[31\] wbs_adr_o\[30\]
diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc index 37358bb..68e7dde 100644 --- a/openlane/wb_interconnect/base.sdc +++ b/openlane/wb_interconnect/base.sdc
@@ -29,2058 +29,118 @@ # Set max delay for clock skew -set_max_delay 3.5 -from [get_ports {wbd_clk_int}] +set_max_delay 4.0 -from [get_ports {wbd_clk_int}] set_max_delay 2 -to [get_ports {wbd_clk_wi}] -set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_wi +set_max_delay 4.0 -from wbd_clk_int -to wbd_clk_wi ## set_input_delay -max 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {rst_n}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[0]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[10]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[11]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[12]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[13]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[14]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[15]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[16]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[17]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[18]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[19]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[1]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[20]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[21]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[22]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[23]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[24]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[25]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[26]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[27]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[28]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[29]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[2]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[30]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[31]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[3]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[4]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[5]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[6]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[7]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[8]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[9]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[0]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[10]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[11]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[12]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[13]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[14]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[15]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[16]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[17]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[18]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[19]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[1]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[20]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[21]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[22]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[23]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[24]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[25]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[26]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[27]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[28]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[29]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[2]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[30]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[31]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[3]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[4]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[5]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[6]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[7]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[8]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[9]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[0]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[1]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[2]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[3]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[0]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[10]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[11]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[12]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[13]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[14]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[15]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[16]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[17]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[18]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[19]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[1]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[20]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[21]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[22]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[23]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[24]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[25]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[26]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[27]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[28]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[29]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[2]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[30]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[31]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[3]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[4]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[5]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[6]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[7]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[8]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[9]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[0]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[10]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[11]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[12]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[13]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[14]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[15]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[16]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[17]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[18]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[19]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[1]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[20]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[21]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[22]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[23]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[24]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[25]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[26]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[27]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[28]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[29]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[2]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[30]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[31]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[3]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[4]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[5]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[6]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[7]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[8]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[9]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[0]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[1]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[2]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[3]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[0]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[10]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[11]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[12]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[13]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[14]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[15]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[16]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[17]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[18]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[19]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[1]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[20]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[21]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[22]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[23]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[24]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[25]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[26]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[27]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[28]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[29]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[2]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[30]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[31]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[3]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[4]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[5]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[6]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[7]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[8]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[9]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[0]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[10]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[11]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[12]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[13]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[14]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[15]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[16]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[17]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[18]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[19]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[1]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[20]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[21]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[22]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[23]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[24]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[25]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[26]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[27]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[28]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[29]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[2]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[30]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[31]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[3]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[4]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[5]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[6]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[7]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[8]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[9]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[0]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[1]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[2]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[3]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_ack_i}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[0]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[10]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[11]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[12]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[13]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[14]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[15]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[16]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[17]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[18]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[19]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[1]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[20]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[21]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[22]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[23]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[24]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[25]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[26]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[27]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[28]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[29]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[2]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[30]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[31]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[3]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[4]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[5]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[6]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[7]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[8]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[9]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_ack_i}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[0]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[10]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[11]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[12]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[13]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[14]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[15]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[16]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[17]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[18]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[19]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[1]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[20]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[21]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[22]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[23]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[24]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[25]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[26]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[27]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[28]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[29]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[2]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[30]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[31]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[3]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[4]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[5]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[6]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[7]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[8]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[9]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_ack_i}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[0]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[10]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[11]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[12]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[13]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[14]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[15]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[16]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[17]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[18]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[19]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[1]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[20]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[21]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[22]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[23]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[24]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[25]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[26]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[27]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[28]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[29]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[2]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[30]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[31]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[3]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[4]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[5]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[6]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[7]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[8]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[9]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_ack_i}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[0]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[10]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[11]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[12]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[13]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[14]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[15]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[16]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[17]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[18]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[19]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[1]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[20]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[21]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[22]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[23]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[24]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[25]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[26]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[27]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[28]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[29]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[2]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[30]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[31]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[3]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[4]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[5]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[6]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[7]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[8]}] -set_input_delay -max 6.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[9]}] +set_input_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[*]}] +set_input_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[*]}] +set_input_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[*]}] +set_input_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[*]}] +set_input_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_ack_i}] +set_input_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[*]}] +set_input_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_ack_i}] +set_input_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[*]}] +set_input_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_ack_i}] +set_input_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[*]}] +set_input_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_ack_i}] +set_input_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[*]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_ack_i}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_ack_i}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_ack_i}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[9]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_ack_i}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[0]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[10]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[11]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[12]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[13]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[14]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[15]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[16]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[17]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[18]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[19]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[1]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[20]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[21]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[22]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[23]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[24]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[25]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[26]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[27]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[28]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[29]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[2]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[30]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[31]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[3]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[4]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[5]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[6]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[7]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[8]}] -set_input_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[9]}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_adr_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_sel_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_adr_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_sel_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_adr_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_sel_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_i[*]}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_ack_i}] +set_input_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_i[*]}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_ack_o}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[10]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[11]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[12]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[13]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[14]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[15]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[16]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[17]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[18]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[19]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[20]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[21]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[22]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[23]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[24]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[25]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[26]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[27]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[28]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[29]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[30]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[31]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[3]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[4]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[5]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[6]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[7]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[8]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[9]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[*]}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_err_o}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_ack_o}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[10]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[11]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[12]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[13]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[14]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[15]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[16]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[17]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[18]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[19]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[20]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[21]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[22]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[23]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[24]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[25]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[26]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[27]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[28]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[29]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[30]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[31]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[3]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[4]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[5]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[6]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[7]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[8]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[9]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[*]}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_err_o}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_ack_o}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[10]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[11]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[12]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[13]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[14]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[15]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[16]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[17]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[18]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[19]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[20]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[21]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[22]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[23]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[24]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[25]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[26]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[27]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[28]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[29]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[30]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[31]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[3]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[4]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[5]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[6]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[7]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[8]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[9]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[*]}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_err_o}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[10]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[11]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[12]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[13]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[14]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[15]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[16]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[17]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[18]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[19]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[20]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[21]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[22]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[23]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[24]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[25]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[26]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[27]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[28]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[29]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[30]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[31]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[3]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[4]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[5]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[6]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[7]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[8]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[9]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[*]}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_cyc_o}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[10]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[11]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[12]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[13]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[14]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[15]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[16]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[17]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[18]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[19]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[20]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[21]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[22]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[23]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[24]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[25]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[26]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[27]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[28]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[29]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[30]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[31]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[3]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[4]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[5]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[6]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[7]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[8]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[9]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[3]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[*]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[*]}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_stb_o}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_we_o}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[10]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[11]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[12]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[13]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[14]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[15]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[16]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[17]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[18]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[19]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[20]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[21]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[22]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[23]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[24]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[25]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[26]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[27]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[28]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[29]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[30]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[31]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[3]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[4]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[5]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[6]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[7]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[8]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[9]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[*]}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_cyc_o}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[10]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[11]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[12]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[13]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[14]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[15]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[16]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[17]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[18]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[19]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[20]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[21]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[22]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[23]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[24]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[25]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[26]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[27]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[28]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[29]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[30]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[31]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[3]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[4]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[5]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[6]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[7]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[8]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[9]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[3]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[*]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[*]}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_stb_o}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_we_o}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[3]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[4]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[5]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[6]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[7]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[*]}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_cyc_o}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[10]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[11]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[12]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[13]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[14]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[15]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[16]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[17]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[18]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[19]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[20]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[21]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[22]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[23]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[24]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[25]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[26]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[27]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[28]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[29]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[30]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[31]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[3]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[4]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[5]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[6]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[7]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[8]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[9]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[3]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[*]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[*]}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_stb_o}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_we_o}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[3]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[4]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[5]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[6]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[7]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[*]}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_cyc_o}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[10]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[11]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[12]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[13]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[14]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[15]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[16]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[17]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[18]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[19]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[20]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[21]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[22]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[23]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[24]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[25]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[26]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[27]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[28]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[29]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[30]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[31]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[3]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[4]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[5]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[6]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[7]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[8]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[9]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[0]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[1]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[2]}] -set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[3]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[*]}] +set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[*]}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_stb_o}] set_output_delay -max 4.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_we_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_ack_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[10]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[11]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[12]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[13]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[14]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[15]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[16]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[17]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[18]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[19]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[20]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[21]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[22]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[23]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[24]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[25]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[26]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[27]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[28]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[29]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[30]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[31]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[4]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[5]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[6]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[7]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[8]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[9]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_err_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_ack_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[10]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[11]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[12]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[13]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[14]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[15]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[16]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[17]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[18]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[19]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[20]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[21]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[22]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[23]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[24]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[25]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[26]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[27]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[28]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[29]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[30]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[31]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[4]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[5]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[6]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[7]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[8]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[9]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_err_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_ack_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[10]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[11]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[12]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[13]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[14]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[15]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[16]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[17]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[18]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[19]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[20]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[21]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[22]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[23]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[24]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[25]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[26]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[27]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[28]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[29]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[30]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[31]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[4]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[5]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[6]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[7]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[8]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[9]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_err_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[10]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[11]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[12]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[13]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[14]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[15]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[16]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[17]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[18]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[19]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[20]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[21]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[22]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[23]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[24]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[25]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[26]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[27]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[28]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[29]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[30]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[31]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[4]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[5]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[6]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[7]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[8]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[9]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_cyc_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[10]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[11]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[12]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[13]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[14]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[15]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[16]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[17]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[18]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[19]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[20]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[21]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[22]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[23]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[24]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[25]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[26]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[27]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[28]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[29]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[30]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[31]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[4]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[5]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[6]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[7]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[8]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[9]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_stb_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_we_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[10]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[11]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[12]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[13]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[14]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[15]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[16]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[17]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[18]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[19]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[20]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[21]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[22]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[23]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[24]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[25]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[26]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[27]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[28]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[29]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[30]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[31]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[4]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[5]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[6]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[7]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[8]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[9]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_cyc_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[10]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[11]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[12]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[13]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[14]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[15]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[16]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[17]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[18]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[19]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[20]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[21]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[22]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[23]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[24]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[25]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[26]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[27]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[28]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[29]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[30]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[31]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[4]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[5]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[6]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[7]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[8]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[9]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_stb_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_we_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[4]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[5]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[6]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[7]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_cyc_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[10]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[11]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[12]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[13]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[14]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[15]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[16]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[17]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[18]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[19]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[20]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[21]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[22]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[23]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[24]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[25]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[26]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[27]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[28]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[29]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[30]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[31]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[4]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[5]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[6]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[7]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[8]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[9]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_stb_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_we_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[4]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[5]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[6]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[7]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_cyc_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[10]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[11]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[12]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[13]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[14]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[15]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[16]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[17]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[18]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[19]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[20]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[21]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[22]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[23]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[24]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[25]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[26]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[27]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[28]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[29]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[30]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[31]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[4]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[5]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[6]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[7]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[8]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[9]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[0]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[1]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[2]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[3]}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_stb_o}] -set_output_delay -min 1.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_we_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_ack_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_dat_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m0_wbd_err_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_ack_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_dat_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m1_wbd_err_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_ack_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_dat_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {m2_wbd_err_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_adr_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_cyc_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_dat_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_sel_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_stb_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s0_wbd_we_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_adr_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_cyc_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_dat_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_sel_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_stb_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s1_wbd_we_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_adr_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_cyc_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_dat_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_sel_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_stb_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s2_wbd_we_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_adr_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_cyc_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_dat_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_sel_o[*]}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_stb_o}] +set_output_delay -min 2.0000 -clock [get_clocks {clk_i}] -add_delay [get_ports {s3_wbd_we_o}] ############################################################################### # Environment ############################################################################### -set_load -pin_load 0.0334 [get_ports {m0_wbd_ack_o}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_err_o}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_ack_o}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_err_o}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_ack_o}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_err_o}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_cyc_o}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_stb_o}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_we_o}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_cyc_o}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_stb_o}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_we_o}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_cyc_o}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_stb_o}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_we_o}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_cyc_o}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_stb_o}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_we_o}] -set_load -pin_load 0.0334 [get_ports {wbd_clk_wi}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[31]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[30]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[29]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[28]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[27]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[26]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[25]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[24]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[23]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[22]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[21]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[20]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[19]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[18]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[17]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[16]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[15]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[14]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[13]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[12]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[11]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[10]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[9]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[8]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[7]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[6]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[5]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[4]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[3]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[2]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[1]}] -set_load -pin_load 0.0334 [get_ports {m0_wbd_dat_o[0]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[31]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[30]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[29]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[28]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[27]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[26]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[25]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[24]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[23]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[22]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[21]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[20]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[19]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[18]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[17]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[16]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[15]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[14]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[13]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[12]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[11]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[10]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[9]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[8]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[7]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[6]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[5]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[4]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[3]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[2]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[1]}] -set_load -pin_load 0.0334 [get_ports {m1_wbd_dat_o[0]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[31]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[30]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[29]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[28]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[27]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[26]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[25]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[24]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[23]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[22]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[21]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[20]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[19]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[18]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[17]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[16]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[15]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[14]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[13]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[12]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[11]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[10]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[9]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[8]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[7]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[6]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[5]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[4]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[3]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[2]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[1]}] -set_load -pin_load 0.0334 [get_ports {m2_wbd_dat_o[0]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[31]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[30]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[29]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[28]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[27]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[26]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[25]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[24]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[23]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[22]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[21]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[20]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[19]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[18]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[17]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[16]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[15]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[14]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[13]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[12]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[11]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[10]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[9]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[8]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[7]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[6]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[5]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[4]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[3]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[2]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[1]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_adr_o[0]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[31]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[30]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[29]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[28]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[27]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[26]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[25]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[24]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[23]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[22]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[21]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[20]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[19]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[18]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[17]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[16]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[15]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[14]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[13]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[12]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[11]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[10]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[9]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[8]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[7]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[6]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[5]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[4]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[3]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[2]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[1]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_dat_o[0]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[3]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[2]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[1]}] -set_load -pin_load 0.0334 [get_ports {s0_wbd_sel_o[0]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[31]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[30]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[29]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[28]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[27]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[26]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[25]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[24]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[23]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[22]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[21]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[20]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[19]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[18]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[17]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[16]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[15]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[14]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[13]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[12]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[11]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[10]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[9]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[8]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[7]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[6]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[5]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[4]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[3]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[2]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[1]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_adr_o[0]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[31]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[30]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[29]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[28]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[27]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[26]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[25]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[24]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[23]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[22]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[21]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[20]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[19]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[18]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[17]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[16]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[15]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[14]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[13]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[12]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[11]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[10]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[9]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[8]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[7]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[6]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[5]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[4]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[3]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[2]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[1]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_dat_o[0]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[3]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[2]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[1]}] -set_load -pin_load 0.0334 [get_ports {s1_wbd_sel_o[0]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[7]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[6]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[5]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[4]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[3]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[2]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[1]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_adr_o[0]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[31]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[30]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[29]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[28]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[27]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[26]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[25]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[24]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[23]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[22]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[21]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[20]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[19]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[18]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[17]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[16]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[15]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[14]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[13]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[12]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[11]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[10]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[9]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[8]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[7]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[6]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[5]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[4]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[3]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[2]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[1]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_dat_o[0]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[3]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[2]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[1]}] -set_load -pin_load 0.0334 [get_ports {s2_wbd_sel_o[0]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[7]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[6]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[5]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[4]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[3]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[2]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[1]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_adr_o[0]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[31]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[30]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[29]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[28]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[27]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[26]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[25]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[24]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[23]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[22]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[21]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[20]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[19]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[18]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[17]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[16]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[15]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[14]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[13]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[12]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[11]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[10]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[9]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[8]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[7]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[6]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[5]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[4]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[3]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[2]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[1]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_dat_o[0]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[3]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[2]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[1]}] -set_load -pin_load 0.0334 [get_ports {s3_wbd_sel_o[0]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clk_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_cyc_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_stb_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_we_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_cyc_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_stb_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_we_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_cyc_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_stb_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_we_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_ack_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_ack_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_ack_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_ack_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wbd_clk_int}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[3]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[2]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[1]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {cfg_cska_wi[0]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[31]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[30]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[29]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[28]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[27]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[26]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[25]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[24]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[23]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[22]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[21]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[20]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[19]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[18]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[17]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[16]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[15]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[14]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[13]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[12]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_adr_i[11]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} 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[get_ports {m0_wbd_dat_i[16]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[15]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[14]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[13]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[12]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[11]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m0_wbd_dat_i[10]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} 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[get_ports {m1_wbd_adr_i[19]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[18]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[17]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[16]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[15]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[14]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[13]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} 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-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[5]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[4]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[3]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[2]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[1]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_adr_i[0]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 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[get_ports {m1_wbd_dat_i[18]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[17]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[16]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[15]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[14]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[13]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m1_wbd_dat_i[12]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} 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[get_ports {m2_wbd_adr_i[21]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[20]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[19]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[18]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[17]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[16]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_adr_i[15]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} 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[get_ports {m2_wbd_dat_i[20]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[19]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[18]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[17]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[16]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[15]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {m2_wbd_dat_i[14]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} 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[get_ports {s0_wbd_dat_i[23]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[22]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[21]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[20]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[19]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[18]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[17]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} 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-set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[9]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[8]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[7]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[6]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[5]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[4]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[3]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[2]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[1]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s0_wbd_dat_i[0]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[31]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[30]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[29]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[28]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[27]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[26]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[25]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[24]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[23]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[22]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[21]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[20]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[19]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[18]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[17]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[16]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[15]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[14]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[13]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[12]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[11]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[10]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[9]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[8]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[7]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[6]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[5]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[4]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[3]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[2]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[1]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s1_wbd_dat_i[0]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[31]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[30]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[29]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[28]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[27]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[26]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[25]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[24]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[23]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[22]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[21]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[20]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[19]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[18]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[17]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[16]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[15]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[14]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[13]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[12]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[11]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[10]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[9]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[8]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[7]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[6]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[5]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[4]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[3]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[2]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[1]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s2_wbd_dat_i[0]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[31]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[30]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[29]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[28]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[27]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[26]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[25]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[24]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[23]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[22]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[21]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[20]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[19]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[18]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[17]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[16]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[15]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[14]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[13]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[12]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[11]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[10]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[9]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[8]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[7]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[6]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[5]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[4]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[3]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[2]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[1]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {s3_wbd_dat_i[0]}] +set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] +set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] +puts "\[INFO\]: Setting load to: $cap_load" +set_load $cap_load [all_outputs] ############################################################################### # Design Rules ###############################################################################
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index fc3e712..7861baf 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -31,6 +31,11 @@ set ::env(SYNTH_MAX_FANOUT) 4 +## CTS BUFFER +set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" +set ::env(CTS_SINK_CLUSTERING_SIZE) "16" +set ::env(CLOCK_BUFFER_FANOUT) "8" + # Sources # ------- @@ -46,7 +51,7 @@ set ::env(SYNTH_DEFINES) [list SYNTHESIS ] set ::env(SYNTH_PARAMS) "CH_CLK_WD 8,\ - CH_DATA_WD 137 \ + CH_DATA_WD 116 \ " set ::env(SYNTH_READ_BLACKBOX_LIB) 1 @@ -65,7 +70,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 160 2500" +set ::env(DIE_AREA) "0 0 160 2200" # If you're going to use multiple power domains, then keep this disabled. @@ -100,6 +105,12 @@ set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" -set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0" +set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "1" set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1" +set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "1000" +set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "1.5" +set ::env(PL_RESIZER_MAX_CAP_MARGIN) "5" + +## FANOUT Reduced to take care of long routes +set ::env(SYNTH_MAX_FANOUT) "2"
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index d2855e3..295c0ef 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -61,7 +61,7 @@ clk_i -m0_wbd_stb_i 050 0 2 +m0_wbd_stb_i 060 0 2 m0_wbd_we_i m0_wbd_adr_i\[31\] m0_wbd_adr_i\[30\] @@ -227,7 +227,7 @@ ch_clk_out\[0\] -m1_wbd_stb_i 0150 0 2 +m1_wbd_stb_i 0200 0 2 m1_wbd_we_i m1_wbd_adr_i\[31\] m1_wbd_adr_i\[30\] @@ -440,15 +440,17 @@ m2_wbd_cyc_i -ch_data_out\[23\] 600 0 2 +ch_data_out\[23\] 1900 0 2 ch_data_out\[22\] ch_data_out\[21\] ch_data_out\[20\] ch_clk_out\[4\] -s3_wbd_cyc_o 625 0 2 +s3_wbd_cyc_o 1925 0 2 s3_wbd_stb_o s3_wbd_we_o +s3_wbd_adr_o\[12\] +s3_wbd_adr_o\[11\] s3_wbd_adr_o\[10\] s3_wbd_adr_o\[9\] s3_wbd_adr_o\[8\] @@ -530,113 +532,12 @@ s3_wbd_dat_i\[0\] s3_wbd_ack_i -ch_data_in\[97\] 750 0 2 -ch_data_in\[96\] -ch_data_in\[95\] -ch_data_in\[94\] -ch_data_in\[93\] -ch_data_in\[92\] -ch_data_in\[91\] -ch_data_in\[90\] - -ch_data_out\[89\] -ch_data_out\[88\] -ch_data_out\[87\] -ch_data_out\[86\] -ch_data_out\[85\] - - -ch_data_out\[27\] 1150 0 2 -ch_data_out\[26\] -ch_data_out\[25\] -ch_data_out\[24\] -ch_clk_out\[5\] - -s4_wbd_cyc_o 1175 0 2 -s4_wbd_stb_o -s4_wbd_we_o -s4_wbd_adr_o\[10\] -s4_wbd_adr_o\[9\] -s4_wbd_adr_o\[8\] -s4_wbd_adr_o\[7\] -s4_wbd_adr_o\[6\] -s4_wbd_adr_o\[5\] -s4_wbd_adr_o\[4\] -s4_wbd_adr_o\[3\] -s4_wbd_adr_o\[2\] -s4_wbd_adr_o\[1\] -s4_wbd_adr_o\[0\] -s4_wbd_dat_o\[31\] -s4_wbd_dat_o\[30\] -s4_wbd_dat_o\[29\] -s4_wbd_dat_o\[28\] -s4_wbd_dat_o\[27\] -s4_wbd_dat_o\[26\] -s4_wbd_dat_o\[25\] -s4_wbd_dat_o\[24\] -s4_wbd_dat_o\[23\] -s4_wbd_dat_o\[22\] -s4_wbd_dat_o\[21\] -s4_wbd_dat_o\[20\] -s4_wbd_dat_o\[19\] -s4_wbd_dat_o\[18\] -s4_wbd_dat_o\[17\] -s4_wbd_dat_o\[16\] -s4_wbd_dat_o\[15\] -s4_wbd_dat_o\[14\] -s4_wbd_dat_o\[13\] -s4_wbd_dat_o\[12\] -s4_wbd_dat_o\[11\] -s4_wbd_dat_o\[10\] -s4_wbd_dat_o\[9\] -s4_wbd_dat_o\[8\] -s4_wbd_dat_o\[7\] -s4_wbd_dat_o\[6\] -s4_wbd_dat_o\[5\] -s4_wbd_dat_o\[4\] -s4_wbd_dat_o\[3\] -s4_wbd_dat_o\[2\] -s4_wbd_dat_o\[1\] -s4_wbd_dat_o\[0\] -s4_wbd_sel_o\[3\] -s4_wbd_sel_o\[2\] -s4_wbd_sel_o\[1\] -s4_wbd_sel_o\[0\] -s4_wbd_dat_i\[31\] -s4_wbd_dat_i\[30\] -s4_wbd_dat_i\[29\] -s4_wbd_dat_i\[28\] -s4_wbd_dat_i\[27\] -s4_wbd_dat_i\[26\] -s4_wbd_dat_i\[25\] -s4_wbd_dat_i\[24\] -s4_wbd_dat_i\[23\] -s4_wbd_dat_i\[22\] -s4_wbd_dat_i\[21\] -s4_wbd_dat_i\[20\] -s4_wbd_dat_i\[19\] -s4_wbd_dat_i\[18\] -s4_wbd_dat_i\[17\] -s4_wbd_dat_i\[16\] -s4_wbd_dat_i\[15\] -s4_wbd_dat_i\[14\] -s4_wbd_dat_i\[13\] -s4_wbd_dat_i\[12\] -s4_wbd_dat_i\[11\] -s4_wbd_dat_i\[10\] -s4_wbd_dat_i\[9\] -s4_wbd_dat_i\[8\] -s4_wbd_dat_i\[7\] -s4_wbd_dat_i\[6\] -s4_wbd_dat_i\[5\] -s4_wbd_dat_i\[4\] -s4_wbd_dat_i\[3\] -s4_wbd_dat_i\[2\] -s4_wbd_dat_i\[1\] -s4_wbd_dat_i\[0\] -s4_wbd_ack_i - -ch_data_in\[110\] 1300 0 2 +ch_data_in\[115\] 2050 0 2 +ch_data_in\[114\] +ch_data_in\[113\] +ch_data_in\[112\] +ch_data_in\[111\] +ch_data_in\[110\] ch_data_in\[109\] ch_data_in\[108\] ch_data_in\[107\] @@ -644,223 +545,42 @@ ch_data_in\[105\] ch_data_in\[104\] ch_data_in\[103\] - -ch_data_out\[102\] -ch_data_out\[101\] -ch_data_out\[100\] -ch_data_out\[99\] -ch_data_out\[98\] +ch_data_in\[102\] +ch_data_in\[101\] +ch_data_in\[100\] +ch_data_in\[99\] +ch_data_in\[98\] +ch_data_in\[97\] +ch_data_in\[96\] +ch_data_in\[95\] +ch_data_in\[94\] +ch_data_in\[93\] +ch_data_in\[92\] +ch_data_in\[91\] +ch_data_in\[90\] +ch_data_out\[89\] +ch_data_out\[88\] +ch_data_out\[87\] +ch_data_out\[86\] +ch_data_out\[85\] -ch_data_out\[31\] 1700 0 2 -ch_data_out\[30\] -ch_data_out\[29\] + +ch_clk_out\[5\] 2150 0 2 +ch_clk_out\[6\] +ch_clk_out\[7\] +ch_data_out\[24\] +ch_data_out\[25\] +ch_data_out\[26\] +ch_data_out\[27\] ch_data_out\[28\] -ch_clk_out\[6\] - -s5_wbd_cyc_o 1725 0 2 -s5_wbd_stb_o -s5_wbd_we_o -s5_wbd_adr_o\[10\] -s5_wbd_adr_o\[9\] -s5_wbd_adr_o\[8\] -s5_wbd_adr_o\[7\] -s5_wbd_adr_o\[6\] -s5_wbd_adr_o\[5\] -s5_wbd_adr_o\[4\] -s5_wbd_adr_o\[3\] -s5_wbd_adr_o\[2\] -s5_wbd_adr_o\[1\] -s5_wbd_adr_o\[0\] -s5_wbd_dat_o\[31\] -s5_wbd_dat_o\[30\] -s5_wbd_dat_o\[29\] -s5_wbd_dat_o\[28\] -s5_wbd_dat_o\[27\] -s5_wbd_dat_o\[26\] -s5_wbd_dat_o\[25\] -s5_wbd_dat_o\[24\] -s5_wbd_dat_o\[23\] -s5_wbd_dat_o\[22\] -s5_wbd_dat_o\[21\] -s5_wbd_dat_o\[20\] -s5_wbd_dat_o\[19\] -s5_wbd_dat_o\[18\] -s5_wbd_dat_o\[17\] -s5_wbd_dat_o\[16\] -s5_wbd_dat_o\[15\] -s5_wbd_dat_o\[14\] -s5_wbd_dat_o\[13\] -s5_wbd_dat_o\[12\] -s5_wbd_dat_o\[11\] -s5_wbd_dat_o\[10\] -s5_wbd_dat_o\[9\] -s5_wbd_dat_o\[8\] -s5_wbd_dat_o\[7\] -s5_wbd_dat_o\[6\] -s5_wbd_dat_o\[5\] -s5_wbd_dat_o\[4\] -s5_wbd_dat_o\[3\] -s5_wbd_dat_o\[2\] -s5_wbd_dat_o\[1\] -s5_wbd_dat_o\[0\] -s5_wbd_sel_o\[3\] -s5_wbd_sel_o\[2\] -s5_wbd_sel_o\[1\] -s5_wbd_sel_o\[0\] -s5_wbd_dat_i\[31\] -s5_wbd_dat_i\[30\] -s5_wbd_dat_i\[29\] -s5_wbd_dat_i\[28\] -s5_wbd_dat_i\[27\] -s5_wbd_dat_i\[26\] -s5_wbd_dat_i\[25\] -s5_wbd_dat_i\[24\] -s5_wbd_dat_i\[23\] -s5_wbd_dat_i\[22\] -s5_wbd_dat_i\[21\] -s5_wbd_dat_i\[20\] -s5_wbd_dat_i\[19\] -s5_wbd_dat_i\[18\] -s5_wbd_dat_i\[17\] -s5_wbd_dat_i\[16\] -s5_wbd_dat_i\[15\] -s5_wbd_dat_i\[14\] -s5_wbd_dat_i\[13\] -s5_wbd_dat_i\[12\] -s5_wbd_dat_i\[11\] -s5_wbd_dat_i\[10\] -s5_wbd_dat_i\[9\] -s5_wbd_dat_i\[8\] -s5_wbd_dat_i\[7\] -s5_wbd_dat_i\[6\] -s5_wbd_dat_i\[5\] -s5_wbd_dat_i\[4\] -s5_wbd_dat_i\[3\] -s5_wbd_dat_i\[2\] -s5_wbd_dat_i\[1\] -s5_wbd_dat_i\[0\] -s5_wbd_ack_i - -ch_data_in\[123\] 1850 0 2 -ch_data_in\[122\] -ch_data_in\[121\] -ch_data_in\[120\] -ch_data_in\[119\] -ch_data_in\[118\] -ch_data_in\[117\] -ch_data_in\[116\] - -ch_data_out\[115\] -ch_data_out\[114\] -ch_data_out\[113\] -ch_data_out\[112\] -ch_data_out\[111\] - -ch_data_out\[35\] 2250 0 2 -ch_data_out\[34\] -ch_data_out\[33\] +ch_data_out\[29\] +ch_data_out\[30\] +ch_data_out\[31\] ch_data_out\[32\] -ch_clk_out\[7\] - -s6_wbd_cyc_o 2275 0 2 -s6_wbd_stb_o -s6_wbd_we_o -s6_wbd_adr_o\[10\] -s6_wbd_adr_o\[9\] -s6_wbd_adr_o\[8\] -s6_wbd_adr_o\[7\] -s6_wbd_adr_o\[6\] -s6_wbd_adr_o\[5\] -s6_wbd_adr_o\[4\] -s6_wbd_adr_o\[3\] -s6_wbd_adr_o\[2\] -s6_wbd_adr_o\[1\] -s6_wbd_adr_o\[0\] -s6_wbd_dat_o\[31\] -s6_wbd_dat_o\[30\] -s6_wbd_dat_o\[29\] -s6_wbd_dat_o\[28\] -s6_wbd_dat_o\[27\] -s6_wbd_dat_o\[26\] -s6_wbd_dat_o\[25\] -s6_wbd_dat_o\[24\] -s6_wbd_dat_o\[23\] -s6_wbd_dat_o\[22\] -s6_wbd_dat_o\[21\] -s6_wbd_dat_o\[20\] -s6_wbd_dat_o\[19\] -s6_wbd_dat_o\[18\] -s6_wbd_dat_o\[17\] -s6_wbd_dat_o\[16\] -s6_wbd_dat_o\[15\] -s6_wbd_dat_o\[14\] -s6_wbd_dat_o\[13\] -s6_wbd_dat_o\[12\] -s6_wbd_dat_o\[11\] -s6_wbd_dat_o\[10\] -s6_wbd_dat_o\[9\] -s6_wbd_dat_o\[8\] -s6_wbd_dat_o\[7\] -s6_wbd_dat_o\[6\] -s6_wbd_dat_o\[5\] -s6_wbd_dat_o\[4\] -s6_wbd_dat_o\[3\] -s6_wbd_dat_o\[2\] -s6_wbd_dat_o\[1\] -s6_wbd_dat_o\[0\] -s6_wbd_sel_o\[3\] -s6_wbd_sel_o\[2\] -s6_wbd_sel_o\[1\] -s6_wbd_sel_o\[0\] -s6_wbd_dat_i\[31\] -s6_wbd_dat_i\[30\] -s6_wbd_dat_i\[29\] -s6_wbd_dat_i\[28\] -s6_wbd_dat_i\[27\] -s6_wbd_dat_i\[26\] -s6_wbd_dat_i\[25\] -s6_wbd_dat_i\[24\] -s6_wbd_dat_i\[23\] -s6_wbd_dat_i\[22\] -s6_wbd_dat_i\[21\] -s6_wbd_dat_i\[20\] -s6_wbd_dat_i\[19\] -s6_wbd_dat_i\[18\] -s6_wbd_dat_i\[17\] -s6_wbd_dat_i\[16\] -s6_wbd_dat_i\[15\] -s6_wbd_dat_i\[14\] -s6_wbd_dat_i\[13\] -s6_wbd_dat_i\[12\] -s6_wbd_dat_i\[11\] -s6_wbd_dat_i\[10\] -s6_wbd_dat_i\[9\] -s6_wbd_dat_i\[8\] -s6_wbd_dat_i\[7\] -s6_wbd_dat_i\[6\] -s6_wbd_dat_i\[5\] -s6_wbd_dat_i\[4\] -s6_wbd_dat_i\[3\] -s6_wbd_dat_i\[2\] -s6_wbd_dat_i\[1\] -s6_wbd_dat_i\[0\] -s6_wbd_ack_i - -ch_data_in\[136\] 2400 0 2 -ch_data_in\[135\] -ch_data_in\[134\] -ch_data_in\[133\] -ch_data_in\[132\] -ch_data_in\[131\] -ch_data_in\[130\] -ch_data_in\[129\] - -ch_data_out\[128\] -ch_data_out\[127\] -ch_data_out\[126\] -ch_data_out\[125\] -ch_data_out\[124\] +ch_data_out\[33\] +ch_data_out\[34\] +ch_data_out\[35\] #E ch_data_out\[19\] 0000 0 2 @@ -1066,35 +786,12 @@ s1_wbd_ack_i s1_wbd_cyc_o -ch_data_out\[136\] 1600 0 2 -ch_data_out\[135\] -ch_data_out\[134\] -ch_data_out\[133\] -ch_data_out\[132\] -ch_data_out\[131\] -ch_data_out\[130\] -ch_data_out\[129\] -ch_data_in\[128\] -ch_data_in\[127\] -ch_data_in\[126\] -ch_data_in\[125\] -ch_data_in\[124\] - -ch_data_out\[123\] -ch_data_out\[122\] -ch_data_out\[121\] -ch_data_out\[120\] -ch_data_out\[119\] -ch_data_out\[118\] -ch_data_out\[117\] -ch_data_out\[116\] -ch_data_in\[115\] -ch_data_in\[114\] -ch_data_in\[113\] -ch_data_in\[112\] -ch_data_in\[111\] - -ch_data_out\[110\] +ch_data_out\[115\] 1600 0 2 +ch_data_out\[114\] +ch_data_out\[113\] +ch_data_out\[112\] +ch_data_out\[111\] +ch_data_out\[110\] ch_data_out\[109\] ch_data_out\[108\] ch_data_out\[107\] @@ -1102,14 +799,12 @@ ch_data_out\[105\] ch_data_out\[104\] ch_data_out\[103\] -ch_data_in\[102\] -ch_data_in\[101\] -ch_data_in\[100\] -ch_data_in\[99\] -ch_data_in\[98\] - - -ch_data_out\[97\] +ch_data_out\[102\] +ch_data_out\[101\] +ch_data_out\[100\] +ch_data_out\[99\] +ch_data_out\[98\] +ch_data_out\[97\] ch_data_out\[96\] ch_data_out\[95\] ch_data_out\[94\]
diff --git a/signoff/mbist1/OPENLANE_VERSION b/signoff/mbist/OPENLANE_VERSION similarity index 100% rename from signoff/mbist1/OPENLANE_VERSION rename to signoff/mbist/OPENLANE_VERSION
diff --git a/signoff/mbist1/PDK_SOURCES b/signoff/mbist/PDK_SOURCES similarity index 100% rename from signoff/mbist1/PDK_SOURCES rename to signoff/mbist/PDK_SOURCES
diff --git a/signoff/mbist1/final_summary_report.csv b/signoff/mbist/final_summary_report.csv similarity index 72% rename from signoff/mbist1/final_summary_report.csv rename to signoff/mbist/final_summary_report.csv index d452efb..78824ce 100644 --- a/signoff/mbist1/final_summary_report.csv +++ b/signoff/mbist/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/mbist1,mbist_top1,mbist1,flow_completed,0h4m36s,-1,45345.454545454544,0.055,22672.727272727272,28.31,565.84,1247,0,0,0,0,0,0,0,1,0,0,-1,79820,14384,-1.26,-1.78,-1,-1.47,-1,-20.05,-28.82,-1,-32.82,-1,50155361.0,15.2,37.82,27.67,8.7,0.06,-1,1182,2538,325,1649,0,0,0,1156,0,0,0,0,0,0,0,4,231,261,16,186,665,0,851,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/mbist,mbist_top,mbist,flow_completed,0h11m2s,-1,20833.333333333336,0.3,10416.666666666668,13.1,663.13,3125,0,0,0,0,0,0,0,10,0,0,-1,458568,43437,-0.67,-6.26,-1,-1.39,-1,-0.67,-3033.14,-1,-1.39,-1,372704250.0,1.47,48.85,12.24,20.92,0.0,-1,2382,6613,753,4936,0,0,0,2339,0,0,0,0,0,0,0,4,849,672,17,130,3852,0,3982,90.9090909090909,11,10,AREA 0,4,50,1,140,140,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv index bc9656d..c09928a 100644 --- a/signoff/pinmux/final_summary_report.csv +++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h24m22s,-1,46327.27272727273,0.2475,23163.636363636364,27.14,711.29,5733,0,0,0,0,0,0,-1,1,0,-1,-1,426122,64960,0.0,-0.15,-1,0.0,-1,0.0,-4.48,-1,0.0,-1,294610837.0,2.99,41.93,31.98,13.81,0.52,-1,3584,8628,542,5585,0,0,0,4221,0,0,0,0,0,0,0,4,1345,1351,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.35,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h16m18s,-1,46004.0404040404,0.2475,23002.0202020202,27.03,702.81,5693,0,0,0,0,0,0,-1,1,0,-1,-1,421015,60601,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,309034294.0,6.6,42.63,33.16,10.43,0.49,-1,3568,8567,541,5539,0,0,0,4197,0,0,0,0,0,0,0,4,1341,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim/final_summary_report.csv b/signoff/qspim/final_summary_report.csv index b8e1b13..b75a144 100644 --- a/signoff/qspim/final_summary_report.csv +++ b/signoff/qspim/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h8m51s,-1,64727.27272727273,0.22,32363.636363636364,37.61,693.52,7120,0,0,0,0,0,0,-1,1,0,-1,-1,300881,62676,0.0,-4.31,-1,0.0,-1,0.0,-1599.52,-1,0.0,-1,205184440.0,6.18,33.84,32.42,0.61,1.6,-1,5860,8812,519,3470,0,0,0,6886,0,0,0,0,0,0,0,4,1764,2182,20,388,2940,0,3328,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h8m52s,-1,64727.27272727273,0.22,32363.636363636364,37.61,695.07,7120,0,0,0,0,0,0,-1,1,0,-1,-1,299102,62398,0.0,-4.31,-1,0.0,-1,0.0,-1599.52,-1,0.0,-1,205184440.0,6.62,33.96,32.07,0.54,1.34,-1,5860,8812,519,3470,0,0,0,6886,0,0,0,0,0,0,0,4,1764,2182,20,388,2940,0,3328,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/syntacore/final_summary_report.csv b/signoff/syntacore/final_summary_report.csv index 7f9e60e..d573af1 100644 --- a/signoff/syntacore/final_summary_report.csv +++ b/signoff/syntacore/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,1h33m29s,-1,55728.0,0.75,27864.0,32.5,1199.69,20898,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1799741,253072,-2.04,-16.74,-1,-0.12,-1,-2459.49,-21364.73,-1,-0.15,-1,1416553880.0,6.55,67.08,25.24,36.63,0.0,-1,18304,29655,1036,12280,0,0,0,21716,0,0,0,0,0,0,0,4,5144,5849,49,350,10177,0,10527,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.33,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/syntacore,scr1_top_wb,syntacore,flow_completed,0h35m5s,-1,53092.1052631579,0.7904,26546.05263157895,30.7,1184.14,20982,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1620249,234724,-2.04,-17.66,-1,-0.03,-1,-2476.75,-21882.2,-1,-0.03,-1,1288559929.0,1.19,62.41,23.31,23.29,0.0,-1,18371,29934,1071,12527,0,0,0,21750,0,0,0,0,0,0,0,4,5144,5851,49,366,10822,0,11188,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.32,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/uart_i2cm_usb_spi/final_summary_report.csv b/signoff/uart_i2cm_usb_spi/final_summary_report.csv index b018192..82f2b7b 100644 --- a/signoff/uart_i2cm_usb_spi/final_summary_report.csv +++ b/signoff/uart_i2cm_usb_spi/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow_completed,0h14m3s,-1,64045.71428571429,0.35,32022.857142857145,37.57,832.49,11208,0,0,0,0,0,0,-1,1,0,-1,-1,436470,97856,-4.53,-4.87,-1,-4.61,-1,-141.45,-152.51,-1,-139.04,-1,264189380.0,3.96,30.67,29.3,0.93,0.27,-1,8571,12978,1539,5889,0,0,0,9747,0,0,0,0,0,0,0,4,2731,2697,26,498,4643,0,5141,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.45,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/uart_i2cm_usb_spi,uart_i2c_usb_spi_top,uart_i2cm_usb_spi,flow_completed,0h13m36s,-1,63977.14285714286,0.35,31988.57142857143,37.54,836.07,11196,0,0,0,0,0,0,-1,1,0,-1,-1,434083,97891,-4.52,-4.86,-1,-4.69,-1,-141.37,-151.91,-1,-139.26,-1,264395920.0,0.39,30.63,28.98,0.99,0.4,-1,8563,12970,1541,5891,0,0,0,9737,0,0,0,0,0,0,0,4,2730,2694,26,498,4643,0,5141,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.45,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index 2973df2..b98995d 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h37m54s,-1,2.9187422166874217,10.2784,1.4593711083437109,-1,535.66,15,0,0,0,0,0,0,-1,0,0,-1,-1,1475745,10933,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.52,4.51,3.23,0.65,0.54,-1,298,2697,298,2697,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h39m20s,-1,2.529576587795766,10.2784,1.264788293897883,-1,530.09,13,0,0,0,0,0,0,-1,0,0,-1,-1,1195465,7994,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.36,3.25,3.57,0.37,0.62,-1,269,2530,269,2530,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/final_summary_report.csv b/signoff/wb_host/final_summary_report.csv index 64e4de6..8a3c4ac 100644 --- a/signoff/wb_host/final_summary_report.csv +++ b/signoff/wb_host/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h6m16s,-1,63908.571428571435,0.0875,31954.285714285717,39.91,592.74,2796,0,0,0,0,0,0,0,1,0,0,-1,142732,25079,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,103335902.0,2.56,41.03,34.71,4.26,0.62,-1,1403,3046,726,2367,0,0,0,1466,0,0,0,0,0,0,0,4,783,970,13,166,1105,0,1271,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.41,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/wb_host,wb_host,wb_host,flow_completed,0h7m17s,-1,62133.33333333334,0.09,31066.66666666667,39.23,583.55,2796,0,0,0,0,0,0,0,0,0,0,-1,156439,26510,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,117576375.0,0.0,47.59,28.13,12.61,0.16,-1,1403,3046,726,2367,0,0,0,1466,0,0,0,0,0,0,0,4,783,970,13,130,1105,0,1235,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.41,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv index ff1a200..de2a952 100644 --- a/signoff/wb_interconnect/final_summary_report.csv +++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h6m50s,-1,9035.0,0.4,4517.5,3.86,674.82,1807,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,690765,27420,0.0,0.0,-1,-0.07,-1,0.0,0.0,-1,-0.14,-1,611850677.0,26.99,15.84,53.48,1.44,22.81,-1,1268,3988,208,2928,0,0,0,1682,0,0,0,0,0,0,0,4,540,639,7,1822,5021,0,6843,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.5,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h8m25s,-1,10670.454545454546,0.35200000000000004,5335.227272727273,4.18,656.2,1878,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,595153,26667,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,524917517.0,43.3,14.09,52.85,1.35,22.33,-1,948,3082,178,2312,0,0,0,1249,0,0,0,0,0,0,0,4,439,494,10,1600,4411,0,6011,90.9090909090909,11,10,AREA 0,2,50,1,100,100,0.5,0.0,sky130_fd_sc_hd,4,4
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl index 695b0fa..92b3b08 100644 --- a/sta/scripts/caravel_timing.tcl +++ b/sta/scripts/caravel_timing.tcl
@@ -1,26 +1,26 @@ set ::env(USER_ROOT) "/home/dinesha/workarea/opencore/git/riscduino" set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-4/caravel_openframe" - set ::env(PDK_ROOT) "/opt/pdk_mpw4" + set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw4" - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core.v read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/DFFRAM.v read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core_wrapper.v @@ -49,7 +49,7 @@ read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v - read_verilog $::env(USER_ROOT)/verilog/gl/mbist1.v + read_verilog $::env(USER_ROOT)/verilog/gl/mbist.v read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v @@ -144,10 +144,7 @@ read_spef -path gpio_defaults_block_37 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef ## User Project Spef - read_spef -path mprj/u_mbist1 $::env(USER_ROOT)/spef/mbist_top1.spef - read_spef -path mprj/u_mbist2 $::env(USER_ROOT)/spef/mbist_top1.spef - read_spef -path mprj/u_mbist3 $::env(USER_ROOT)/spef/mbist_top1.spef - read_spef -path mprj/u_mbist4 $::env(USER_ROOT)/spef/mbist_top1.spef + read_spef -path mprj/u_mbist $::env(USER_ROOT)/spef/mbist_top.spef read_spef -path mprj/u_riscv_top $::env(USER_ROOT)/spef/scr1_top_wb.spef read_spef -path mprj/u_pinmux $::env(USER_ROOT)/spef/pinmux.spef
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index 10f37d4..cda6027 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -14,68 +14,60 @@ #create_clock [get_pins clocking/pll_clk90 ] -name "pll_clk90" -period 25 create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clock] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i] -create_clock -name wbs_clk_i -period 15.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}] -create_clock -name cpu_clk -period 20.0000 [get_pins {mprj/u_wb_host/cpu_clk}] -create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_wb_host/rtc_clk}] -create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_wb_host/usb_clk}] -create_clock -name line_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart_core.u_lineclk_buf.u_buf/X}] +create_clock -name wbs_clk_i -period 15.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}] +create_clock -name cpu_ref_clk -period 10.0000 [get_pins {mprj/u_wb_host/u_cpu_ref_sel.u_mux/X}] +create_clock -name cpu_clk -period 20.0000 [get_pins {mprj/u_wb_host/cpu_clk}] +create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_wb_host/rtc_clk}] +create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_wb_host/usb_clk}] +create_clock -name line_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart_core.u_lineclk_buf.u_mux/X}] +create_generated_clock -name mem_clk0 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/mem_no[0].u_mem_sel.u_mem_clk_sel.u_mux/X] +create_generated_clock -name mem_clk1 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/mem_no[1].u_mem_sel.u_mem_clk_sel.u_mux/X] +create_generated_clock -name mem_clk2 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/mem_no[2].u_mem_sel.u_mem_clk_sel.u_mux/X] +create_generated_clock -name mem_clk3 -add -source [get_pins {mprj/u_wb_host/wbs_clk_out}] -master_clock [get_clocks wbs_clk_i] -divide_by 1 -comment {memory Clock} [get_pins mprj/u_mbist/mem_no[3].u_mem_sel.u_mem_clk_sel.u_mux/X] ## Case analysis set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}] -set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}] +set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}] set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}] set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}] set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}] -set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}] -set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[2]}] -set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[3]}] +set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}] +set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[2]}] +set_case_analysis 1 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[3]}] set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[0]}] set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[1]}] set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}] set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}] -set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] -set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}] +set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}] +set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}] -set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[0]}] -set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[1]}] -set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[2]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[3]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[0]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[1]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[2]}] +set_case_analysis 1 [get_pins {mprj/u_riscv_top/cfg_cska_riscv[3]}] + set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}] set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}] set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[2]}] set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[3]}] -set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}] +set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[0]}] +set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}] set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[2]}] -set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[1]}] -set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}] +set_case_analysis 1 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}] -set_case_analysis 1 [get_pins {mprj/u_mbist1/cfg_cska_mbist[0]}] -set_case_analysis 1 [get_pins {mprj/u_mbist1/cfg_cska_mbist[1]}] -set_case_analysis 1 [get_pins {mprj/u_mbist1/cfg_cska_mbist[2]}] -set_case_analysis 0 [get_pins {mprj/u_mbist1/cfg_cska_mbist[3]}] +set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[0]}] +set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[1]}] +set_case_analysis 0 [get_pins {mprj/u_mbist/cfg_cska_mbist[2]}] +set_case_analysis 1 [get_pins {mprj/u_mbist/cfg_cska_mbist[3]}] -set_case_analysis 1 [get_pins {mprj/u_mbist2/cfg_cska_mbist[0]}] -set_case_analysis 1 [get_pins {mprj/u_mbist2/cfg_cska_mbist[1]}] -set_case_analysis 1 [get_pins {mprj/u_mbist2/cfg_cska_mbist[2]}] -set_case_analysis 0 [get_pins {mprj/u_mbist2/cfg_cska_mbist[3]}] - -set_case_analysis 1 [get_pins {mprj/u_mbist3/cfg_cska_mbist[0]}] -set_case_analysis 1 [get_pins {mprj/u_mbist3/cfg_cska_mbist[1]}] -set_case_analysis 1 [get_pins {mprj/u_mbist3/cfg_cska_mbist[2]}] -set_case_analysis 0 [get_pins {mprj/u_mbist3/cfg_cska_mbist[3]}] - -set_case_analysis 1 [get_pins {mprj/u_mbist4/cfg_cska_mbist[0]}] -set_case_analysis 1 [get_pins {mprj/u_mbist4/cfg_cska_mbist[1]}] -set_case_analysis 1 [get_pins {mprj/u_mbist4/cfg_cska_mbist[2]}] -set_case_analysis 0 [get_pins {mprj/u_mbist4/cfg_cska_mbist[3]}] #disable clock gating check at static clock select pins set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.u_mux/S] @@ -83,10 +75,11 @@ set_propagated_clock [all_clocks] set_clock_groups -name async_clock -asynchronous \ - -group [get_clocks {clock wb_clk}]\ + -group [get_clocks {clock wb_clk mem_clk0 mem_clk1 mem_clk2 mem_clk3}]\ -group [get_clocks {user_clk2}]\ -group [get_clocks {wbs_clk_i}]\ -group [get_clocks {cpu_clk}]\ + -group [get_clocks {cpu_ref_clk}]\ -group [get_clocks {rtc_clk}]\ -group [get_clocks {usb_clk}]\ -group [get_clocks {line_clk}]\ @@ -154,6 +147,9 @@ set_false_path -from [get_ports mprj_io[*]] set_false_path -from [get_ports gpio] +## User Project static signals +set_false_path -through [get_pins mprj/u_pinmux/bist_en] + # TODO set this as parameter set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] puts "\[INFO\]: Setting load to: $cap_load"
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index f645004..49482e0 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -242,8 +242,8 @@ wb_user_core_write('h3080_0000,'h1); wb_user_core_read_check(32'h30020058,read_data,32'h8273_8343); - wb_user_core_read_check(32'h3002005C,read_data,32'h1112_2021); - wb_user_core_read_check(32'h30020060,read_data,32'h0001_9000); + wb_user_core_read_check(32'h3002005C,read_data,32'h2012_2021); + wb_user_core_read_check(32'h30020060,read_data,32'h0002_2000); end
diff --git a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v index 8378213..5fe3ae9 100644 --- a/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v +++ b/verilog/dv/user_mbist_test1/user_mbist_test1_tb.v
@@ -42,14 +42,10 @@ `define WB_MAP `30080_0000 `define GLBL_FUNC_MAP 'h3002_0000 -`define MBIST1_FUNC_MAP 'h3003_0000 -`define MBIST2_FUNC_MAP 'h3004_0000 -`define MBIST3_FUNC_MAP 'h3005_0000 -`define MBIST4_FUNC_MAP 'h3006_0000 -`define MBIST5_FUNC_MAP 'h3007_0000 -`define MBIST6_FUNC_MAP 'h3008_0000 -`define MBIST7_FUNC_MAP 'h3009_0000 -`define MBIST8_FUNC_MAP 'h300A_0000 +`define MBIST1_FUNC_MAP 'h3003_0000 // 0x3003_0000 to 0x3003_07FF +`define MBIST2_FUNC_MAP 'h3003_0800 // 0x3003_0800 to 0x3003_0FFF +`define MBIST3_FUNC_MAP 'h3003_1000 // 0x3003_1000 to 0x3003_17FF +`define MBIST4_FUNC_MAP 'h3003_1800 // 0x3003_1800 to 0x3003_1FFF `define GLBL_BIST_CTRL1 'h3002_0070 `define GLBL_BIST_STAT1 'h3002_0074 @@ -59,7 +55,7 @@ `define WB_GLBL_CTRL 'h3080_0000 -`define NO_SRAM 2 // 8 +`define NO_SRAM 4 // 8 @@ -115,7 +111,9 @@ `ifdef WFDUMP initial begin $dumpfile("simx.vcd"); - $dumpvars(5, user_mbist_test1_tb); + $dumpvars(2, user_mbist_test1_tb); + $dumpvars(0, user_mbist_test1_tb.u_top.u_mbist); + $dumpvars(0, user_mbist_test1_tb.u_top.u_intercon); $dumpoff; end `endif @@ -144,16 +142,81 @@ // [2] - Bist Correct - 0 // [3] - Reserved - 0 // [7:4] - Bist Error Cnt - 4'h0 - insert_fault(0,0,64'h01010101_01010101); + insert_fault(0,0,0,0,0,32'h01010101); if(test_fail == 0) begin $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Passed"); end else begin $display("Monitor: Step-1: BIST Test without any Memory Error insertion test Failed"); end - $dumpon; $display("###################################################"); - $display(" MBIST Test with Single Address Failure"); + + $display("#########################################################"); + $display(" MBIST Test with With Single Address Failure for MEM-0"); + $display("#########################################################"); + + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h1 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(1,0,0,0,0,32'h01010115); + + if(test_fail == 0) begin + $display("Monitor: Step-2.1: BIST Test with Single Address Failure at MEM0 Error insertion test Passed"); + end else begin + $display("Monitor: Step-2.1: BIST Test with Single Address Failure at MEM0 Error insertion test Failed"); + end + $display("##########################################################"); + $display(" MBIST Test with With Single Address Failure for MEM-0/1"); + $display("##########################################################"); + + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h1 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(1,1,0,0,0,32'h01011515); + + if(test_fail == 0) begin + $display("Monitor: Step-2.2: BIST Test with Single Address Failure at MEM0/1 Error insertion test Passed"); + end else begin + $display("Monitor: Step-2.2: BIST Test with Single Address Failure at MEM0/1 Error insertion test Failed"); + end + $display("##########################################################"); + $display(" MBIST Test with With Single Address Failure for MEM-0/1/2"); + $display("##########################################################"); + + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h1 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(1,1,1,0,0,32'h01151515); + + if(test_fail == 0) begin + $display("Monitor: Step-2.3: BIST Test with Single Address Failure at MEM0/1/2 Error insertion test Passed"); + end else begin + $display("Monitor: Step-2.3: BIST Test with Single Address Failure at MEM0/1/2 Error insertion test Failed"); + end + + $display("###################################################"); + $display(" MBIST Test with Single Address Failure to All Memory"); $display("###################################################"); // Check Is there is any BIST Error // [0] - Bist Done - 1 @@ -163,17 +226,84 @@ // [7:4] - Bist Error Cnt - 4'h1 //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 faultaddr[0] = 9'h10; - insert_fault(1,1,64'h15151515_15151515); + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(1,1,1,1,1,32'h15151515); if(test_fail == 0) begin - $display("Monitor: Step-2: BIST Test with One Memory Error insertion test Passed"); + $display("Monitor: Step-2.4: BIST Test with One Memory Error insertion test Passed"); end else begin - $display("Monitor: Step-2: BIST Test with One Memory Error insertion test Failed"); - end + $display("Monitor: Step-2.4: BIST Test with One Memory Error insertion test Failed"); + end $display("###################################################"); - $dumpoff; + + $display("#########################################################"); + $display(" MBIST Test with With Two Address Failure for MEM-0"); + $display("#########################################################"); + + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h2 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(2,0,0,0,0,32'h01010125); + + if(test_fail == 0) begin + $display("Monitor: Step-3.1: BIST Test with Two Address Failure at MEM0 Error insertion test Passed"); + end else begin + $display("Monitor: Step-3.1: BIST Test with Two Address Failure at MEM0 Error insertion test Failed"); + end + $display("##########################################################"); + $display(" MBIST Test with With Two Address Failure for MEM-0/1"); + $display("##########################################################"); + + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h2 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(2,2,0,0,0,32'h01012525); + + if(test_fail == 0) begin + $display("Monitor: Step-3.2: BIST Test with Two Address Failure at MEM0/1 Error insertion test Passed"); + end else begin + $display("Monitor: Step-3.2: BIST Test with Two Address Failure at MEM0/1 Error insertion test Failed"); + end + $display("##########################################################"); + $display(" MBIST Test with With Two Address Failure for MEM-0/1/2"); + $display("##########################################################"); + + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h2 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(2,2,2,0,0,32'h01252525); + + if(test_fail == 0) begin + $display("Monitor: Step-3.3: BIST Test with Two Address Failure at MEM0/1/2 Error insertion test Passed"); + end else begin + $display("Monitor: Step-3.3: BIST Test with Two Address Failure at MEM0/1/2 Error insertion test Failed"); + end + $display("###################################################"); - $display(" MBIST Test with Two Address Failure"); + $display(" MBIST Test with Two Address Failure to All Memory"); $display("###################################################"); // Check Is there is any BIST Error // [0] - Bist Done - 1 @@ -181,19 +311,23 @@ // [2] - Bist Correct - 1 // [3] - Reserved - 0 // [7:4] - Bist Error Cnt - 4'h2 - //if(read_data[6:0] != 7'b0010101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x2 + //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 faultaddr[0] = 9'h10; faultaddr[1] = 9'h20; - insert_fault(2,0,64'h25252525_25252525); + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(2,2,2,2,1,32'h25252525); if(test_fail == 0) begin - $display("Monitor: Step-3: BIST Test with Two Memory Error insertion test Passed"); + $display("Monitor: Step-3.4: BIST Test with Two Memory Error insertion test Passed"); end else begin - $display("Monitor: Step-3: BIST Test with Two Memory Error insertion test Failed"); - end + $display("Monitor: Step-3.4: BIST Test with Two Memory Error insertion test Failed"); + end $display("###################################################"); - $display(" MBIST Test with Three Address Failure"); - $display("###################################################"); + + $display("#########################################################"); + $display(" MBIST Test with With Three Address Failure for MEM-0"); + $display("#########################################################"); // Check Is there is any BIST Error // [0] - Bist Done - 1 @@ -201,41 +335,171 @@ // [2] - Bist Correct - 1 // [3] - Reserved - 0 // [7:4] - Bist Error Cnt - 4'h3 - //if(read_data[6:0] != 7'b0011101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x3 faultaddr[0] = 9'h10; faultaddr[1] = 9'h20; faultaddr[2] = 9'h30; - insert_fault(3,1,64'h35353535_35353535); + faultaddr[3] = 9'h40; + insert_fault(3,0,0,0,0,32'h01010135); if(test_fail == 0) begin - $display("Monitor: Step-4: BIST Test with Three Memory Error insertion test Passed"); + $display("Monitor: Step-4.1: BIST Test with Three Address Failure at MEM0 Error insertion test Passed"); end else begin - $display("Monitor: Step-4: BIST Test with Three Memory Error insertion test Failed"); - end - $dumpoff; + $display("Monitor: Step-4.1: BIST Test with Three Address Failure at MEM0 Error insertion test Failed"); + end + $display("##########################################################"); + $display(" MBIST Test with With Three Address Failure for MEM-0/1"); + $display("##########################################################"); + + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h3 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(3,3,0,0,0,32'h01013535); + + if(test_fail == 0) begin + $display("Monitor: Step-4.2: BIST Test with Three Address Failure at MEM0/1 Error insertion test Passed"); + end else begin + $display("Monitor: Step-4.2: BIST Test with Three Address Failure at MEM0/1 Error insertion test Failed"); + end + $display("##########################################################"); + $display(" MBIST Test with With Three Address Failure for MEM-0/1/2"); + $display("##########################################################"); + + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h3 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(3,3,3,0,0,32'h01353535); + + if(test_fail == 0) begin + $display("Monitor: Step-4.3: BIST Test with Three Address Failure at MEM0/1/2 Error insertion test Passed"); + end else begin + $display("Monitor: Step-4.3: BIST Test with Three Address Failure at MEM0/1/2 Error insertion test Failed"); + end + $display("###################################################"); - $display(" MBIST Test with Fours Address Failure"); + $display(" MBIST Test with Three Address Failure to All Memory"); $display("###################################################"); + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h3 + //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(3,3,3,3,1,32'h35353535); + + if(test_fail == 0) begin + $display("Monitor: Step-4.4: BIST Test with Three Memory Error insertion test Passed"); + end else begin + $display("Monitor: Step-4.4: BIST Test with Three Memory Error insertion test Failed"); + end + $display("###################################################"); + + $display("#########################################################"); + $display(" MBIST Test with With Four Address Failure for MEM-0"); + $display("#########################################################"); + // Check Is there is any BIST Error // [0] - Bist Done - 1 // [1] - Bist Error - 0 // [2] - Bist Correct - 1 // [3] - Reserved - 0 // [7:4] - Bist Error Cnt - 4'h4 - //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 faultaddr[0] = 9'h10; faultaddr[1] = 9'h20; faultaddr[2] = 9'h30; faultaddr[3] = 9'h40; - insert_fault(4,0,64'h45454545_45454545); + insert_fault(4,0,0,0,0,32'h01010145); if(test_fail == 0) begin - $display("Monitor: Step-5: BIST Test with Four Memory Error insertion test Passed"); + $display("Monitor: Step-4.1: BIST Test with Four Address Failure at MEM0 Error insertion test Passed"); end else begin - $display("Monitor: Step-5: BIST Test with Four Memory Error insertion test Failed"); + $display("Monitor: Step-4.1: BIST Test with Four Address Failure at MEM0 Error insertion test Failed"); + end + $display("##########################################################"); + $display(" MBIST Test with With Four Address Failure for MEM-0/1"); + $display("##########################################################"); + + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h4 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(4,4,0,0,0,32'h01014545); + + if(test_fail == 0) begin + $display("Monitor: Step-4.2: BIST Test with Four Address Failure at MEM0/1 Error insertion test Passed"); + end else begin + $display("Monitor: Step-4.2: BIST Test with Four Address Failure at MEM0/1 Error insertion test Failed"); + end + $display("##########################################################"); + $display(" MBIST Test with With Four Address Failure for MEM-0/1/2"); + $display("##########################################################"); + + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h3 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(4,4,4,0,0,32'h01454545); + + if(test_fail == 0) begin + $display("Monitor: Step-4.3: BIST Test with Four Address Failure at MEM0/1/2 Error insertion test Passed"); + end else begin + $display("Monitor: Step-4.3: BIST Test with Four Address Failure at MEM0/1/2 Error insertion test Failed"); end - $dumpon; + $display("###################################################"); + $display(" MBIST Test with Four Address Failure to All Memory"); + $display("###################################################"); + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 0 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h3 + //if(read_data[6:0] != 7'b0001101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x1 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + insert_fault(4,4,4,4,1,32'h45454545); + + if(test_fail == 0) begin + $display("Monitor: Step-4.4: BIST Test with Four Memory Error insertion test Passed"); + end else begin + $display("Monitor: Step-4.4: BIST Test with Four Memory Error insertion test Failed"); + end + $display("###################################################"); + + $display("###################################################"); $display(" MBIST Test with Fours Address(Continous Starting Addrsess) Failure"); $display("###################################################"); @@ -250,12 +514,12 @@ faultaddr[1] = 9'h1; faultaddr[2] = 9'h2; faultaddr[3] = 9'h3; - insert_fault(4,0,64'h45454545_45454545); + insert_fault(4,4,4,4,0,32'h45454545); if(test_fail == 0) begin - $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Passed"); + $display("Monitor: Step-5.1: BIST Test with Four Memory Error insertion test Passed"); end else begin - $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Failed"); + $display("Monitor: Step-5.1: BIST Test with Four Memory Error insertion test Failed"); end $display("###################################################"); @@ -272,15 +536,16 @@ faultaddr[1] = 9'hF1; faultaddr[2] = 9'hF2; faultaddr[3] = 9'hF3; - insert_fault(4,0,64'h45454545_45454545); + insert_fault(4,4,4,4,0,32'h45454545); if(test_fail == 0) begin - $display("Monitor: Step-5.3: BIST Test with Four Memory Error insertion test Passed"); + $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Passed"); end else begin - $display("Monitor: Step-5.3: BIST Test with Four Memory Error insertion test Failed"); + $display("Monitor: Step-5.2: BIST Test with Four Memory Error insertion test Failed"); end - $display("###################################################"); - $display(" MBIST Test with Five Address Failure"); + + $display("###################################################"); + $display(" MBIST Test with Five Address Failure for MEM0"); $display("###################################################"); // Check Is there is any BIST Error // [0] - Bist Done - 1 @@ -294,19 +559,87 @@ faultaddr[2] = 9'h30; faultaddr[3] = 9'h40; faultaddr[4] = 9'h50; - insert_fault(5,1,64'h47474747_47474747); + insert_fault(5,0,0,0,1,32'h01010147); if(test_fail == 0) begin - $display("Monitor: Step-5: BIST Test with Five Memory Error insertion test Passed"); + $display("Monitor: Step-6.1: BIST Test with Five Memory Error insertion for MEM0 test Passed"); end else begin - $display("Monitor: Step-5: BIST Test with Five Memory Error insertion test Failed"); + $display("Monitor: Step-6.1: BIST Test with Five Memory Error insertion for MEM0 test Failed"); + end + + $display("###################################################"); + $display(" MBIST Test with Five Address Failure for MEM0/1"); + $display("###################################################"); + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 1 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h4 + //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + faultaddr[4] = 9'h50; + insert_fault(5,5,0,0,1,32'h01014747); + + if(test_fail == 0) begin + $display("Monitor: Step-6.2: BIST Test with Five Memory Error insertion for MEM0/1 test Passed"); + end else begin + $display("Monitor: Step-6.2: BIST Test with Five Memory Error insertion for MEM0/1 test Failed"); + end + + $display("###################################################"); + $display(" MBIST Test with Five Address Failure for MEM0/1/2"); + $display("###################################################"); + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 1 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h4 + //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + faultaddr[4] = 9'h50; + insert_fault(5,5,5,0,1,32'h01474747); + + if(test_fail == 0) begin + $display("Monitor: Step-6.3: BIST Test with Five Memory Error insertion for MEM0/1/2 test Passed"); + end else begin + $display("Monitor: Step-6.3: BIST Test with Five Memory Error insertion for MEM0/1/2 test Failed"); + end + + $display("###################################################"); + $display(" MBIST Test with Five Address Failure for All Memory"); + $display("###################################################"); + // Check Is there is any BIST Error + // [0] - Bist Done - 1 + // [1] - Bist Error - 1 + // [2] - Bist Correct - 1 + // [3] - Reserved - 0 + // [7:4] - Bist Error Cnt - 4'h4 + //if(read_data[6:0] != 7'b0100101) test_fail = 1; // Bist correct = 1 and Bist Err Cnt - 0x4 + faultaddr[0] = 9'h10; + faultaddr[1] = 9'h20; + faultaddr[2] = 9'h30; + faultaddr[3] = 9'h40; + faultaddr[4] = 9'h50; + insert_fault(5,5,5,5,1,32'h47474747); + + if(test_fail == 0) begin + $display("Monitor: Step-6.4: BIST Test with Five Memory Error insertion test Passed"); + end else begin + $display("Monitor: Step-6.4: BIST Test with Five Memory Error insertion test Failed"); end $dumpon; $display("###################################################"); $display(" MBIST Test with Functional Access, continuation of previous MBIST Signature"); $display("###################################################"); - $dumpon; fork begin // Remove the Bist Enable and Bist Run @@ -401,9 +734,9 @@ join_any disable fork; //disable pending fork activity if(test_fail == 0) begin - $display("Monitor: Step-5: BIST Test with Functional access test Passed"); + $display("Monitor: Step-7: BIST Test with Functional access test Passed"); end else begin - $display("Monitor: Step-5: BIST Test with Functional access test failed"); + $display("Monitor: Step-7: BIST Test with Functional access test failed"); end $display("###################################################"); @@ -463,16 +796,24 @@ // ----------------------------------- task insert_fault; -input [3:0] num_fault; +input [3:0] num0_fault; +input [3:0] num1_fault; +input [3:0] num2_fault; +input [3:0] num3_fault; input fault_type; // 0 -> struck at 0 and 1 -> struck at 1 -input [63:0] mbist_signature; +input [31:0] mbist_signature; reg [31:0] datain; reg [8:0] fail_addr1; reg [8:0] fail_addr2; reg [8:0] fail_addr3; reg [8:0] fail_addr4; +reg [3:0] num_fault[0:3]; integer j; begin + num_fault[0] = num0_fault; + num_fault[1] = num1_fault; + num_fault[2] = num2_fault; + num_fault[3] = num3_fault; repeat (2) @(posedge clock); fork begin @@ -481,7 +822,7 @@ // Remove WB and BIST RESET wb_user_core_write(`WB_GLBL_CTRL,'h001); // Set the Bist Enable and Bist Run - wb_user_core_write(`GLBL_BIST_CTRL1,'h00003333); + wb_user_core_write(`GLBL_BIST_CTRL1,'h00000003); // Remove WB and BIST RESET wb_user_core_write(`WB_GLBL_CTRL,'h081); // Check for MBIST Done @@ -491,6 +832,9 @@ end // wait for some time for all the BIST to complete repeat (1000) @(posedge clock); + // Toggle the Bist Load for update the shift data + wb_user_core_write(`GLBL_BIST_CTRL1,'h00000004); + wb_user_core_write(`GLBL_BIST_CTRL1,'h00000000); // Check Is there is any BIST Error // [0] - Bist Done // [1] - Bist Error @@ -506,82 +850,82 @@ repeat (1) @(posedge clock); #1; - if(u_top.u_sram1_2kb.web0 == 1'b0 && - ((num_fault > 0 && u_top.u_sram1_2kb.addr0 == faultaddr[0]) || - (num_fault > 1 && u_top.u_sram1_2kb.addr0 == faultaddr[1]) || - (num_fault > 2 && u_top.u_sram1_2kb.addr0 == faultaddr[2]) || - (num_fault > 3 && u_top.u_sram1_2kb.addr0 == faultaddr[3]) || - (num_fault > 4 && u_top.u_sram1_2kb.addr0 == faultaddr[4]) || - (num_fault > 5 && u_top.u_sram1_2kb.addr0 == faultaddr[5]) || - (num_fault > 6 && u_top.u_sram1_2kb.addr0 == faultaddr[6]) || - (num_fault > 7 && u_top.u_sram1_2kb.addr0 == faultaddr[7]))) + if(u_top.u_sram0_2kb.web0 == 1'b0 && + ((num_fault[0] > 0 && u_top.u_sram0_2kb.addr0 == faultaddr[0]) || + (num_fault[0] > 1 && u_top.u_sram0_2kb.addr0 == faultaddr[1]) || + (num_fault[0] > 2 && u_top.u_sram0_2kb.addr0 == faultaddr[2]) || + (num_fault[0] > 3 && u_top.u_sram0_2kb.addr0 == faultaddr[3]) || + (num_fault[0] > 4 && u_top.u_sram0_2kb.addr0 == faultaddr[4]) || + (num_fault[0] > 5 && u_top.u_sram0_2kb.addr0 == faultaddr[5]) || + (num_fault[0] > 6 && u_top.u_sram0_2kb.addr0 == faultaddr[6]) || + (num_fault[0] > 7 && u_top.u_sram0_2kb.addr0 == faultaddr[7]))) begin if(fault_type == 0) // Struck at 0 - force u_top.u_sram1_2kb.din0 = u_top.mem1_din_b & 32'hFFFF_FFFE; + force u_top.u_sram0_2kb.din0 = u_top.mem0_din_a & 32'hFFFF_FFFE; else - force u_top.u_sram1_2kb.din0 = u_top.mem1_din_b | 32'h1; + force u_top.u_sram0_2kb.din0 = u_top.mem0_din_a | 32'h1; + -> error_insert; + end else begin + release u_top.u_sram0_2kb.din0; + end + + if(u_top.u_sram1_2kb.web0 == 1'b0 && + ((num_fault[1] > 0 && u_top.u_sram1_2kb.addr0 == faultaddr[0]+1) || + (num_fault[1] > 1 && u_top.u_sram1_2kb.addr0 == faultaddr[1]+1) || + (num_fault[1] > 2 && u_top.u_sram1_2kb.addr0 == faultaddr[2]+1) || + (num_fault[1] > 3 && u_top.u_sram1_2kb.addr0 == faultaddr[3]+1) || + (num_fault[1] > 4 && u_top.u_sram1_2kb.addr0 == faultaddr[4]+1) || + (num_fault[1] > 5 && u_top.u_sram1_2kb.addr0 == faultaddr[5]+1) || + (num_fault[1] > 6 && u_top.u_sram1_2kb.addr0 == faultaddr[6]+1) || + (num_fault[1] > 7 && u_top.u_sram1_2kb.addr0 == faultaddr[7]+1))) + begin + if(fault_type == 0) // Struck at 0 + force u_top.u_sram1_2kb.din0 = u_top.mem1_din_a & 32'hFFFF_FFFE; + else + force u_top.u_sram1_2kb.din0 = u_top.mem1_din_a | 32'h1; -> error_insert; end else begin release u_top.u_sram1_2kb.din0; end if(u_top.u_sram2_2kb.web0 == 1'b0 && - ((num_fault > 0 && u_top.u_sram2_2kb.addr0 == faultaddr[0]+1) || - (num_fault > 1 && u_top.u_sram2_2kb.addr0 == faultaddr[1]+1) || - (num_fault > 2 && u_top.u_sram2_2kb.addr0 == faultaddr[2]+1) || - (num_fault > 3 && u_top.u_sram2_2kb.addr0 == faultaddr[3]+1) || - (num_fault > 4 && u_top.u_sram2_2kb.addr0 == faultaddr[4]+1) || - (num_fault > 5 && u_top.u_sram2_2kb.addr0 == faultaddr[5]+1) || - (num_fault > 6 && u_top.u_sram2_2kb.addr0 == faultaddr[6]+1) || - (num_fault > 7 && u_top.u_sram2_2kb.addr0 == faultaddr[7]+1))) + ((num_fault[2] > 0 && u_top.u_sram2_2kb.addr0 == faultaddr[0]+2) || + (num_fault[2] > 1 && u_top.u_sram2_2kb.addr0 == faultaddr[1]+2) || + (num_fault[2] > 2 && u_top.u_sram2_2kb.addr0 == faultaddr[2]+2) || + (num_fault[2] > 3 && u_top.u_sram2_2kb.addr0 == faultaddr[3]+2) || + (num_fault[2] > 4 && u_top.u_sram2_2kb.addr0 == faultaddr[4]+2) || + (num_fault[2] > 5 && u_top.u_sram2_2kb.addr0 == faultaddr[5]+2) || + (num_fault[2] > 6 && u_top.u_sram2_2kb.addr0 == faultaddr[6]+2) || + (num_fault[2] > 7 && u_top.u_sram2_2kb.addr0 == faultaddr[7]+2))) begin if(fault_type == 0) // Struck at 0 - force u_top.u_sram2_2kb.din0 = u_top.mem2_din_b & 32'hFFFF_FFFE; + force u_top.u_sram2_2kb.din0 = u_top.mem2_din_a & 32'hFFFF_FFFE; else - force u_top.u_sram2_2kb.din0 = u_top.mem2_din_b | 32'h1; + force u_top.u_sram2_2kb.din0 = u_top.mem2_din_a | 32'h1; -> error_insert; end else begin release u_top.u_sram2_2kb.din0; end if(u_top.u_sram3_2kb.web0 == 1'b0 && - ((num_fault > 0 && u_top.u_sram3_2kb.addr0 == faultaddr[0]+2) || - (num_fault > 1 && u_top.u_sram3_2kb.addr0 == faultaddr[1]+2) || - (num_fault > 2 && u_top.u_sram3_2kb.addr0 == faultaddr[2]+2) || - (num_fault > 3 && u_top.u_sram3_2kb.addr0 == faultaddr[3]+2) || - (num_fault > 4 && u_top.u_sram3_2kb.addr0 == faultaddr[4]+2) || - (num_fault > 5 && u_top.u_sram3_2kb.addr0 == faultaddr[5]+2) || - (num_fault > 6 && u_top.u_sram3_2kb.addr0 == faultaddr[6]+2) || - (num_fault > 7 && u_top.u_sram3_2kb.addr0 == faultaddr[7]+2))) + ((num_fault[3] > 0 && u_top.u_sram3_2kb.addr0 == faultaddr[0]+3) || + (num_fault[3] > 1 && u_top.u_sram3_2kb.addr0 == faultaddr[1]+3) || + (num_fault[3] > 2 && u_top.u_sram3_2kb.addr0 == faultaddr[2]+3) || + (num_fault[3] > 3 && u_top.u_sram3_2kb.addr0 == faultaddr[3]+3) || + (num_fault[3] > 4 && u_top.u_sram3_2kb.addr0 == faultaddr[4]+3) || + (num_fault[3] > 5 && u_top.u_sram3_2kb.addr0 == faultaddr[5]+3) || + (num_fault[3] > 6 && u_top.u_sram3_2kb.addr0 == faultaddr[6]+3) || + (num_fault[3] > 7 && u_top.u_sram3_2kb.addr0 == faultaddr[7]+3))) begin if(fault_type == 0) // Struck at 0 - force u_top.u_sram3_2kb.din0 = u_top.mem3_din_b & 32'hFFFF_FFFE; + force u_top.u_sram3_2kb.din0 = u_top.mem3_din_a & 32'hFFFF_FFFE; else - force u_top.u_sram3_2kb.din0 = u_top.mem3_din_b | 32'h1; + force u_top.u_sram3_2kb.din0 = u_top.mem3_din_a | 32'h1; -> error_insert; end else begin release u_top.u_sram3_2kb.din0; end - if(u_top.u_sram4_2kb.web0 == 1'b0 && - ((num_fault > 0 && u_top.u_sram4_2kb.addr0 == faultaddr[0]+3) || - (num_fault > 1 && u_top.u_sram4_2kb.addr0 == faultaddr[1]+3) || - (num_fault > 2 && u_top.u_sram4_2kb.addr0 == faultaddr[2]+3) || - (num_fault > 3 && u_top.u_sram4_2kb.addr0 == faultaddr[3]+3) || - (num_fault > 4 && u_top.u_sram4_2kb.addr0 == faultaddr[4]+3) || - (num_fault > 5 && u_top.u_sram4_2kb.addr0 == faultaddr[5]+3) || - (num_fault > 6 && u_top.u_sram4_2kb.addr0 == faultaddr[6]+3) || - (num_fault > 7 && u_top.u_sram4_2kb.addr0 == faultaddr[7]+3))) - begin - if(fault_type == 0) // Struck at 0 - force u_top.u_sram4_2kb.din0 = u_top.mem4_din_b & 32'hFFFF_FFFE; - else - force u_top.u_sram4_2kb.din0 = u_top.mem4_din_b | 32'h1; - -> error_insert; - end else begin - release u_top.u_sram4_2kb.din0; - end - //if(u_top.u_sram5_1kb.web0 == 1'b0 && // ((num_fault > 0 && u_top.u_sram5_1kb.addr0 == faultaddr[0]+4) || // (num_fault > 1 && u_top.u_sram5_1kb.addr0 == faultaddr[1]+4) || @@ -670,25 +1014,28 @@ disable fork; //disable pending fork activity // Read Back the Failure Address and cross-check all the 8 MBIST - for(j=0; j < `NO_SRAM; j=j+1) begin - fail_addr1 = faultaddr[0]+j; - fail_addr2 = faultaddr[1]+j; - fail_addr3 = faultaddr[2]+j; - fail_addr4 = faultaddr[3]+j; + // Read Signature is comming is reverse order, MBIST4 => MBIST3 => MBIST2 + for(j=`NO_SRAM; j > 0; j=j-1) begin + fail_addr1 = faultaddr[0]+j-1; + fail_addr2 = faultaddr[1]+j-1; + fail_addr3 = faultaddr[2]+j-1; + fail_addr4 = faultaddr[3]+j-1; - // Select the Serial SDI/SDO interface - wb_user_core_write(`GLBL_BIST_CTRL1,j << 28); - if(num_fault == 1) - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{16'h0,7'h0,fail_addr1},32'h0000_FFFF); - if(num_fault == 2) - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF); - if(num_fault == 3) begin - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF); - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{16'h0,7'h0,fail_addr3},32'h0000_FFFF); - end - if(num_fault >= 4) begin - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr2,7'h0,fail_addr1},32'hFFFF_FFFF); - wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,faultaddr[3]+j,7'h0,fail_addr3},32'hFFFF_FFFF); + if(num_fault[j-1] == 1) begin + wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{32'h0},32'hFFFF_FFFF); + wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr1,16'h0},32'hFFFF_FFFF); + end else if(num_fault[j-1] == 2) begin + wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{32'h0},32'hFFFF_FFFF); + wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr1,7'h0,fail_addr2},32'hFFFF_FFFF); + end else if(num_fault[j-1] == 3) begin + wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr3,16'h0},32'hFFFF_FFFF); + wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr1,7'h0,fail_addr2},32'hFFFF_FFFF); + end else if(num_fault[j-1] >= 4) begin + wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr3,7'h0,fail_addr4},32'hFFFF_FFFF); + wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,{7'h0,fail_addr1,7'h0,fail_addr2},32'hFFFF_FFFF); + end else begin + wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,32'h0,32'hFFFF_FFFF); + wb_user_core_read_check(`GLBL_BIST_SRDATA,read_data,32'h0,32'hFFFF_FFFF); end end end
diff --git a/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v b/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v index 278e07f..e748da4 100644 --- a/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v +++ b/verilog/dv/user_risc_soft_boot/user_risc_soft_boot_tb.v
@@ -155,13 +155,13 @@ tem_mem_32b[i] = {tem_mem[(i*4)+3],tem_mem[(i*4)+2],tem_mem[(i*4)+1],tem_mem[(i*4)]}; $writememh("sram_bank0.hex",tem_mem_32b,0,511); - $readmemh("sram_bank0.hex",u_top.u_sram1_2kb.mem,0,511); + $readmemh("sram_bank0.hex",u_top.u_sram0_2kb.mem,0,511); for(i =512; i < 1023; i = i+1) tem_mem_32b[i-512] = {tem_mem[(i*4)+3],tem_mem[(i*4)+2],tem_mem[(i*4)+1],tem_mem[(i*4)]}; $writememh("sram_bank1.hex",tem_mem_32b,0,511); - $readmemh("sram_bank1.hex",u_top.u_sram2_2kb.mem,0,511); + $readmemh("sram_bank1.hex",u_top.u_sram1_2kb.mem,0,511); // Enable the SRAM Remap to boot region wb_user_core_write('h3080_000C,{4'b1111,28'h0}); @@ -189,23 +189,12 @@ // 0x3000002C = 0x66778899; test_fail = 0; - wb_user_core_read(32'h30020058,read_data); - if(read_data != 32'h11223344) test_fail = 1; - - wb_user_core_read(32'h3002005C,read_data); - if(read_data != 32'h22334455) test_fail = 1; - - wb_user_core_read(32'h30020060,read_data); - if(read_data != 32'h33445566) test_fail = 1; - - wb_user_core_read(32'h30020064,read_data); - if(read_data!= 32'h44556677) test_fail = 1; - - wb_user_core_read(32'h30020068,read_data); - if(read_data!= 32'h55667788) test_fail = 1; - - wb_user_core_read(32'h3002006C,read_data) ; - if(read_data != 32'h66778899) test_fail = 1; + wb_user_core_read_check(32'h30020058,read_data,32'h11223344); + wb_user_core_read_check(32'h3002005C,read_data,32'h22334455); + wb_user_core_read_check(32'h30020060,read_data,32'h33445566); + wb_user_core_read_check(32'h30020064,read_data,32'h44556677); + wb_user_core_read_check(32'h30020068,read_data,32'h55667788); + wb_user_core_read_check(32'h3002006C,read_data,32'h66778899) ; $display("###################################################"); @@ -332,6 +321,40 @@ end endtask +task wb_user_core_read_check; +input [31:0] address; +output [31:0] data; +input [31:0] cmp_data; +reg [31:0] data; +begin + repeat (1) @(posedge clock); + #1; + wbd_ext_adr_i =address; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='0; // data output + wbd_ext_sel_i ='hF; // byte enable + wbd_ext_cyc_i ='h1; // strobe/request + wbd_ext_stb_i ='h1; // strobe/request + wait(wbd_ext_ack_o == 1); + data = wbd_ext_dat_o; + repeat (1) @(posedge clock); + #1; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + if(data !== cmp_data) begin + $display("ERROR : WB USER ACCESS READ Address : 0x%x, Exd: 0x%x Rxd: 0x%x ",address,cmp_data,data); + test_fail = 1; + end else begin + $display("STATUS: WB USER ACCESS READ Address : 0x%x, Data : 0x%x",address,data); + end + repeat (2) @(posedge clock); +end +endtask + `ifdef GL wire wbd_spi_stb_i = u_top.u_spi_master.wbd_stb_i;
diff --git a/verilog/rtl/lib/ser_shift.sv b/verilog/rtl/lib/ser_shift.sv new file mode 100644 index 0000000..21ef9dc --- /dev/null +++ b/verilog/rtl/lib/ser_shift.sv
@@ -0,0 +1,76 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +//// //// +//// ser_shift //// +//// //// +//// This file is part of the mbist_ctrl cores project //// +//// https://github.com/dineshannayya/riscdunio.git //// +//// //// +//// Description //// +//// This block manages the parallel to serial conversion //// +//// This block usefull for Bist SDI/SDO access //// +//// asserts Reg Ack //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.0 - 16th Dec 2021, Dinesh A //// +//// Initial integration //// +//// //// +////////////////////////////////////////////////////////////////////// + +module ser_shift + #(parameter WD = 32) + ( + + // Master Port + input logic rst_n , // Regular Reset signal + input logic clk , // System clock + input logic load , // load request + input logic shift , // shift + input logic [WD-1:0] load_data , // load data + input logic sdi , // sdi + output logic sdo // sdo + + + ); + +logic [WD-1:0] shift_reg; + +always@(negedge rst_n or posedge clk) +begin + if(rst_n == 0) begin + shift_reg <= 'h0; + end else if(load) begin + shift_reg <= load_data; + end else if(shift) begin + shift_reg <= {sdi,shift_reg[WD-1:1]}; + end +end + +assign sdo = shift_reg[0]; + + + +endmodule
diff --git a/verilog/rtl/mbist/run_iverilog b/verilog/rtl/mbist/run_iverilog index a88ada5..f5f5020 100755 --- a/verilog/rtl/mbist/run_iverilog +++ b/verilog/rtl/mbist/run_iverilog
@@ -1,5 +1,5 @@ -iverilog -g2005-sv \ -src/top/mbist_top1.sv \ +iverilog -g2005-sv -DFUNCTIONAL -D UNIT_DELAY=#0.1 \ +src/top/mbist_top.sv \ src/core/mbist_addr_gen.sv \ src/core/mbist_fsm.sv \ src/core/mbist_op_sel.sv \ @@ -12,7 +12,6 @@ -I include/ \ ../lib/ctech_cells.sv \ ../lib/reset_sync.sv \ +../clk_skew_adjust/src/clk_skew_adjust.gv \ $PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v \ -$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v \ ---timescale 1ns/100ps \ ---bbox-unsup +$PDK_ROOT/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
diff --git a/verilog/rtl/mbist/src/core/mbist_addr_gen.sv b/verilog/rtl/mbist/src/core/mbist_addr_gen.sv index 584a2b6..ffcf42c 100644 --- a/verilog/rtl/mbist/src/core/mbist_addr_gen.sv +++ b/verilog/rtl/mbist/src/core/mbist_addr_gen.sv
@@ -55,8 +55,8 @@ input logic rst_n, // asynchronous reset input logic run, // stop or start state machine input logic updown, // count up or down - input logic scan_shift, // shift scan input - input logic scan_load, // load scan input + input logic bist_shift, // shift scan input + input logic bist_load, // load scan input input logic sdi // scan data input ); @@ -78,7 +78,7 @@ always @(posedge clk or negedge rst_n) begin if(!rst_n) bist_addr <= BIST_ADDR_START ; - else if(scan_load) bist_addr <= start_addr; + else if(bist_load) bist_addr <= start_addr; else bist_addr <= next_addr; end @@ -100,17 +100,16 @@ always @(posedge clk or negedge rst_n) begin if(!rst_n) start_addr <= BIST_ADDR_START ; - else if(scan_shift) start_addr <= {sdi, start_addr[BIST_ADDR_WD-1:1]}; + else if(bist_shift) start_addr <= {sdi, start_addr[BIST_ADDR_WD-1:1]}; end /* Start register */ always @(posedge clk or negedge rst_n) begin if(!rst_n) end_addr <= BIST_ADDR_END ; - else if(scan_shift) end_addr <= {start_addr[0], end_addr[BIST_ADDR_WD-1:1]}; + else if(bist_shift) end_addr <= {start_addr[0], end_addr[BIST_ADDR_WD-1:1]}; end - assign sdo = end_addr[0]; endmodule
diff --git a/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv b/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv index b631626..5e22d3e 100644 --- a/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv +++ b/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv
@@ -61,12 +61,15 @@ //// //// ////////////////////////////////////////////////////////////////////// module mbist_mem_wrapper #( + parameter BIST_NO_SRAM=4, parameter BIST_ADDR_WD=10, parameter BIST_DATA_WD=32) ( input logic rst_n , // WB I/F + input logic [(BIST_NO_SRAM+1)/2-1:0] sram_id , input logic wb_clk_i , // System clock input logic wb_cyc_i , // strobe/request + input logic [(BIST_NO_SRAM+1)/2-1:0] wb_cs_i , // Chip Select input logic wb_stb_i , // strobe/request input logic [BIST_ADDR_WD-1:0] wb_adr_i , // address input logic wb_we_i , // write @@ -75,35 +78,26 @@ output logic [BIST_DATA_WD-1:0] wb_dat_o , // data input output logic wb_ack_o , // acknowlegement output logic wb_err_o , // error - // MEM A PORT - output logic func_clk_a , - output logic func_cen_a , - output logic [BIST_ADDR_WD-1:0] func_addr_a , - input logic [BIST_DATA_WD-1:0] func_dout_a , - - // Functional B Port - output logic func_clk_b , - output logic func_cen_b , - output logic func_web_b , - output logic [BIST_DATA_WD/8-1:0] func_mask_b , - output logic [BIST_ADDR_WD-1:0] func_addr_b , - output logic [BIST_DATA_WD-1:0] func_din_b + // MEM PORT + output logic func_clk , + output logic func_cen , + output logic func_web , + output logic [BIST_DATA_WD/8-1:0] func_mask , + output logic [BIST_ADDR_WD-1:0] func_addr , + input logic [BIST_DATA_WD-1:0] func_dout , + output logic [BIST_DATA_WD-1:0] func_din ); // Memory Write PORT -assign func_clk_b = wb_clk_i; -assign func_cen_b = !wb_stb_i; -assign func_web_b = !wb_we_i; -assign func_mask_b = wb_sel_i; -assign func_addr_b = wb_adr_i; -assign func_din_b = wb_dat_i; - -assign func_clk_a = wb_clk_i; -assign func_cen_a = (wb_stb_i == 1'b1 && wb_we_i == 1'b0 && wb_ack_o ==0) ? 1'b0 : 1'b1; -assign func_addr_a = wb_adr_i; -assign wb_dat_o = func_dout_a; +assign func_clk = wb_clk_i; +assign func_cen = (wb_cs_i == sram_id) ? !wb_stb_i : 1'b1; +assign func_web = (wb_cs_i == sram_id) ? !wb_we_i : 1'b1; +assign func_mask = wb_sel_i; +assign func_addr = wb_adr_i; +assign func_din = wb_dat_i; +assign wb_dat_o = func_dout; assign wb_err_o = 1'b0; @@ -112,7 +106,7 @@ if ( rst_n == 1'b0 ) begin wb_ack_o<= 'h0; end else begin - wb_ack_o <= (wb_stb_i == 1'b1) & (wb_ack_o == 0); + wb_ack_o <= (wb_cs_i == sram_id) & (wb_stb_i == 1'b1) & (wb_ack_o == 0); end end
diff --git a/verilog/rtl/mbist/src/core/mbist_mux.sv b/verilog/rtl/mbist/src/core/mbist_mux.sv index 754ea63..0341b16 100755 --- a/verilog/rtl/mbist/src/core/mbist_mux.sv +++ b/verilog/rtl/mbist/src/core/mbist_mux.sv
@@ -61,73 +61,57 @@ input logic [BIST_ADDR_WD-1:0] bist_error_addr, output logic bist_correct, input logic bist_sdi, + input logic bist_load, input logic bist_shift, output logic bist_sdo, - // FUNCTIONAL CTRL SIGNAL - input logic func_clk_a, - input logic func_cen_a, - input logic [BIST_ADDR_WD-1:0] func_addr_a, - // Common for func and Mbist i/f - output logic [BIST_DATA_WD-1:0] func_dout_a, - - input logic func_clk_b, - input logic func_cen_b, - input logic func_web_b, - input logic [BIST_DATA_WD/8-1:0] func_mask_b, - input logic [BIST_ADDR_WD-1:0] func_addr_b, - input logic [BIST_DATA_WD-1:0] func_din_b, + input logic func_clk, + input logic func_cen, + input logic func_web, + input logic [BIST_DATA_WD/8-1:0] func_mask, + input logic [BIST_ADDR_WD-1:0] func_addr, + input logic [BIST_DATA_WD-1:0] func_din, + output logic [BIST_DATA_WD-1:0] func_dout, // towards memory - output logic mem_clk_a, - output logic mem_cen_a, - output logic [BIST_ADDR_WD-1:0] mem_addr_a, - input logic [BIST_DATA_WD-1:0] mem_dout_a, - output logic mem_clk_b, - output logic mem_cen_b, - output logic mem_web_b, - output logic [BIST_DATA_WD/8-1:0] mem_mask_b, - output logic [BIST_ADDR_WD-1:0] mem_addr_b, - output logic [BIST_DATA_WD-1:0] mem_din_b + output logic mem_clk, + output logic mem_cen, + output logic mem_web, + output logic [BIST_DATA_WD/8-1:0] mem_mask, + output logic [BIST_ADDR_WD-1:0] mem_addr, + output logic [BIST_DATA_WD-1:0] mem_din, + input logic [BIST_DATA_WD-1:0] mem_dout ); parameter BIST_MASK_WD = BIST_DATA_WD/8; -wire [BIST_ADDR_WD-1:0] addr_a; -wire [BIST_ADDR_WD-1:0] addr_b; -wire mem_clk_a_cts; // used for internal clock tree -wire mem_clk_b_cts; // usef for internal clock tree +wire [BIST_ADDR_WD-1:0] addr; -assign addr_a = (bist_en) ? bist_addr : func_addr_a; -assign addr_b = (bist_en) ? bist_addr : func_addr_b; +assign addr = (bist_en) ? bist_addr : func_addr; -assign mem_cen_a = (bist_en) ? !bist_rd : func_cen_a; -assign mem_cen_b = (bist_en) ? !bist_wr : func_cen_b; - -assign mem_web_b = (bist_en) ? !bist_wr : func_web_b; -assign mem_mask_b = (bist_en) ? {{BIST_MASK_WD}{1'b1}} : func_mask_b; +assign mem_cen = (bist_en) ? !(bist_rd | bist_wr) : func_cen; +assign mem_web = (bist_en) ? !bist_wr : func_web; +assign mem_mask = (bist_en) ? {{BIST_MASK_WD}{1'b1}} : func_mask; //assign mem_clk_a = (bist_en) ? bist_clk : func_clk_a; //assign mem_clk_b = (bist_en) ? bist_clk : func_clk_b; -ctech_mux2x1 u_mem_clk_a_sel (.A0 (func_clk_a),.A1 (bist_clk),.S (bist_en), .X (mem_clk_a)); -ctech_mux2x1 u_mem_clk_b_sel (.A0 (func_clk_b),.A1 (bist_clk),.S (bist_en), .X (mem_clk_b)); +ctech_mux2x1 u_mem_clk_sel (.A0 (func_clk),.A1 (bist_clk),.S (bist_en), .X (mem_clk)); -ctech_clk_buf u_cts_mem_clk_a (.A (mem_clk_a), . X(mem_clk_a_cts)); -ctech_clk_buf u_cts_mem_clk_b (.A (mem_clk_b), . X(mem_clk_b_cts)); +//ctech_clk_buf u_mem_clk (.A (mem_clk_cts), . X(mem_clk)); -assign mem_din_b = (bist_en) ? bist_wdata : func_din_b; +assign mem_din = (bist_en) ? bist_wdata : func_din; // During scan, SRAM data is unknown, feed data in back to avoid unknow // propagation -assign func_dout_a = (scan_mode) ? mem_din_b : mem_dout_a; +assign func_dout = (scan_mode) ? mem_din : mem_dout; mbist_repair_addr #(.BIST_ADDR_WD (BIST_ADDR_WD), @@ -137,41 +121,21 @@ .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START), .BIST_RAD_WD_I (BIST_RAD_WD_I), .BIST_RAD_WD_O (BIST_RAD_WD_O)) - u_repair_A( - .AddressOut (mem_addr_a ), + u_repair( + .AddressOut (mem_addr ), .Correct (bist_correct ), .sdo (bist_sdo ), - .AddressIn (addr_a ), - .clk (mem_clk_a_cts ), + .AddressIn (addr ), + .clk (mem_clk ), .rst_n (rst_n ), .Error (bist_error ), .ErrorAddr (bist_error_addr ), - .scan_shift (bist_shift ), + .bist_load (bist_load ), + .bist_shift (bist_shift ), .sdi (bist_sdi ) ); -mbist_repair_addr - #(.BIST_ADDR_WD (BIST_ADDR_WD), - .BIST_DATA_WD (BIST_DATA_WD), - .BIST_ADDR_START (BIST_ADDR_START), - .BIST_ADDR_END (BIST_ADDR_END), - .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START), - .BIST_RAD_WD_I (BIST_RAD_WD_I), - .BIST_RAD_WD_O (BIST_RAD_WD_O)) - u_repair_B( - .AddressOut (mem_addr_b ), - .Correct ( ), // Both Bist Correct are same - .sdo ( ), - - .AddressIn (addr_b ), - .clk (mem_clk_b_cts ), - .rst_n (rst_n ), - .Error (bist_error ), - .ErrorAddr (bist_error_addr ), - .scan_shift (1'b0 ), // Both Repair hold same address - .sdi (1'b0 ) -);
diff --git a/verilog/rtl/mbist/src/core/mbist_repair_addr.sv b/verilog/rtl/mbist/src/core/mbist_repair_addr.sv index 70eb7c1..983f661 100644 --- a/verilog/rtl/mbist/src/core/mbist_repair_addr.sv +++ b/verilog/rtl/mbist/src/core/mbist_repair_addr.sv
@@ -60,18 +60,14 @@ input logic rst_n, input logic Error, input logic [BIST_RAD_WD_I-1:0] ErrorAddr, - input logic scan_shift, // shift scan input + input logic bist_load, + input logic bist_shift, // shift scan input input logic sdi // scan data input ); logic [3:0] ErrorCnt; // Assumed Maximum Error correction is less than 16 -logic [15:0] shift_reg; -logic [15:0] shift_load; -logic [7:0] shift_cnt; -logic scan_shift_d; -logic shift_pos_edge; logic [BIST_RAD_WD_I-1:0] RepairMem [0:BIST_ERR_LIMIT-1]; integer i; @@ -110,39 +106,39 @@ /******************************************** * Serial shifting the Repair address * *******************************************/ - -always@(posedge clk or negedge rst_n) -begin - if(!rst_n) begin - shift_reg <= '0; - shift_cnt <= '0; - scan_shift_d <= 1'b0; - end else begin - if(scan_shift && (shift_cnt[7:4] < BIST_ERR_LIMIT)) begin - shift_cnt <= shift_cnt+1; - end - scan_shift_d <= scan_shift; - shift_reg <= shift_load; +integer j; +logic [0:BIST_ERR_LIMIT-1] sdi_in; +logic [0:BIST_ERR_LIMIT-1] sdo_out; +// Daisy chain the Serial In/OUT +always_comb begin + for(j =0; j < BIST_ERR_LIMIT; j=j+1) begin + sdi_in[j] =(j==0) ? sdi : sdo_out[j-1]; end end -// Detect scan_shift pos edge -assign shift_pos_edge = (scan_shift_d ==0) && (scan_shift); +assign sdo = sdo_out[BIST_ERR_LIMIT-1]; -always_comb -begin - shift_load = shift_reg; - // Block the data reloading every pos edge of shift - if(scan_shift && ((shift_cnt[7:4]+1) < BIST_ERR_LIMIT) && (shift_cnt[3:0] == 4'b1111)) - shift_load = {RepairMem[shift_cnt[7:4]+1]}; - else if(scan_shift) - shift_load = {sdi,shift_reg[15:1]}; - else - shift_load = {RepairMem[shift_cnt[7:4]]}; - +genvar no; +generate +for (no = 0; $unsigned(no) < BIST_ERR_LIMIT; no=no+1) begin : num + + ser_shift + #(.WD(16)) u_shift( + + // Master Port + .rst_n (rst_n ), + .clk (clk ), + .load (bist_load ), + .shift (bist_shift ), + .load_data (RepairMem[no] ), + .sdi (sdi_in[no] ), + .sdo (sdo_out[no] ) + + + ); end +endgenerate -assign sdo = shift_reg[0]; endmodule
diff --git a/verilog/rtl/mbist/src/top/mbist_top.sv b/verilog/rtl/mbist/src/top/mbist_top.sv new file mode 100644 index 0000000..a1094cf --- /dev/null +++ b/verilog/rtl/mbist/src/top/mbist_top.sv
@@ -0,0 +1,576 @@ +////////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Dinesh Annayya <dinesha@opencores.org> +// +////////////////////////////////////////////////////////////////////// +//// //// +//// MBIST TOP //// +//// //// +//// This file is part of the mbist_ctrl cores project //// +//// https://github.com/dineshannayya/mbist_ctrl.git //// +//// //// +//// Description //// +//// This block integrate mbist controller with row //// +//// redendency feature //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.0 - 11th Oct 2021, Dinesh A //// +//// Initial integration //// +//// 0.1 - 26th Oct 2021, Dinesh A //// +//// Fixed Error Address are serial shifted through //// +//// sdi/sdo //// +//// 0.2 - 15 Dec 2021, Dinesh A //// +//// Added support for common MBIST for 4 SRAM //// +//// 0.3 - 29th Dec 2021, Dinesh A //// +//// yosys synthesis issue for two dimension variable //// +//// changed the variable defination from logic to wire //// +//// //// +////////////////////////////////////////////////////////////////////// + +`include "mbist_def.svh" +module mbist_top + #( + parameter BIST_NO_SRAM = 4, + parameter BIST_ADDR_WD = 9, + parameter BIST_DATA_WD = 32, + parameter BIST_ADDR_START = 9'h000, + parameter BIST_ADDR_END = 9'h1FB, + parameter BIST_REPAIR_ADDR_START = 9'h1FC, + parameter BIST_RAD_WD_I = BIST_ADDR_WD, + parameter BIST_RAD_WD_O = BIST_ADDR_WD) ( + +`ifdef USE_POWER_PINS + inout vccd1, // User area 1 1.8V supply + inout vssd1, // User area 1 digital ground +`endif + + // Clock Skew Adjust + input wire wbd_clk_int, + output wire wbd_clk_mbist, + input wire [3:0] cfg_cska_mbist, // clock skew adjust for web host + + input logic rst_n, + + // MBIST I/F + input wire bist_en, + input wire bist_run, + input wire bist_shift, + input wire bist_load, + input wire bist_sdi, + + output wire [3:0] bist_error_cnt0, + output wire [3:0] bist_error_cnt1, + output wire [3:0] bist_error_cnt2, + output wire [3:0] bist_error_cnt3, + output wire [BIST_NO_SRAM-1:0] bist_correct , + output wire [BIST_NO_SRAM-1:0] bist_error , + output wire bist_done, + output wire bist_sdo, + + + // WB I/F + input wire wb_clk_i, // System clock + input wire wb_clk2_i, // System clock2 is no cts + input wire wb_cyc_i, // strobe/request + input wire wb_stb_i, // strobe/request + input wire [(BIST_NO_SRAM+1)/2-1:0] wb_cs_i, + input wire [BIST_ADDR_WD-1:0] wb_adr_i, // address + input wire wb_we_i , // write + input wire [BIST_DATA_WD-1:0] wb_dat_i, // data output + input wire [BIST_DATA_WD/8-1:0] wb_sel_i, // byte enable + output wire [BIST_DATA_WD-1:0] wb_dat_o, // data input + output wire wb_ack_o, // acknowlegement + output wire wb_err_o, // error + + // towards memory + // PORT-A + output wire [BIST_NO_SRAM-1:0] mem_clk_a, + output wire [BIST_ADDR_WD-1:0] mem_addr_a0, + output wire [BIST_ADDR_WD-1:0] mem_addr_a1, + output wire [BIST_ADDR_WD-1:0] mem_addr_a2, + output wire [BIST_ADDR_WD-1:0] mem_addr_a3, + output wire [BIST_NO_SRAM-1:0] mem_cen_a, + output wire [BIST_NO_SRAM-1:0] mem_web_a, + output wire [BIST_DATA_WD/8-1:0] mem_mask_a0, + output wire [BIST_DATA_WD/8-1:0] mem_mask_a1, + output wire [BIST_DATA_WD/8-1:0] mem_mask_a2, + output wire [BIST_DATA_WD/8-1:0] mem_mask_a3, + output wire [BIST_DATA_WD-1:0] mem_din_a0, + output wire [BIST_DATA_WD-1:0] mem_din_a1, + output wire [BIST_DATA_WD-1:0] mem_din_a2, + output wire [BIST_DATA_WD-1:0] mem_din_a3, + + input wire [BIST_DATA_WD-1:0] mem_dout_a0, + input wire [BIST_DATA_WD-1:0] mem_dout_a1, + input wire [BIST_DATA_WD-1:0] mem_dout_a2, + input wire [BIST_DATA_WD-1:0] mem_dout_a3, + + + // PORT-B + output wire [BIST_NO_SRAM-1:0] mem_clk_b, + output wire [BIST_NO_SRAM-1:0] mem_cen_b, + output wire [BIST_ADDR_WD-1:0] mem_addr_b0, + output wire [BIST_ADDR_WD-1:0] mem_addr_b1, + output wire [BIST_ADDR_WD-1:0] mem_addr_b2, + output wire [BIST_ADDR_WD-1:0] mem_addr_b3 + + + + +); + +parameter NO_SRAM_WD = (BIST_NO_SRAM+1)/2; + +// FUNCTIONAL PORT +wire func_clk[0:BIST_NO_SRAM-1]; +wire func_cen[0:BIST_NO_SRAM-1]; +wire func_web[0:BIST_NO_SRAM-1]; +wire [BIST_DATA_WD/8-1:0]func_mask[0:BIST_NO_SRAM-1]; +wire [BIST_ADDR_WD-1:0]func_addr[0:BIST_NO_SRAM-1]; +wire [BIST_DATA_WD-1:0]func_dout[0:BIST_NO_SRAM-1]; +wire [BIST_DATA_WD-1:0]func_din[0:BIST_NO_SRAM-1]; + +//---------------------------------------------------- +// Local variable defination +// --------------------------------------------------- +// +wire srst_n ; // sync reset w.r.t bist_clk +wire cmd_phase ; // Command Phase +wire cmp_phase ; // Compare Phase +wire run_op ; // Run next Operation +wire run_addr ; // Run Next Address +wire run_sti ; // Run Next Stimulus +wire run_pat ; // Run Next Pattern +wire op_updown ; // Adress updown direction +wire last_addr ; // last address indication +wire last_sti ; // last stimulus +wire last_op ; // last operation +wire last_pat ; // last pattern +wire [BIST_DATA_WD-1:0] pat_data ; // Selected Data Pattern +wire [BIST_STI_WD-1:0] stimulus ; // current stimulus +wire compare ; // compare data +wire op_repeatflag; +wire op_reverse; +wire op_read ; +wire op_write ; +wire op_invert ; + + +wire bist_error_correct[0:BIST_NO_SRAM-1] ; +wire [BIST_ADDR_WD-1:0]bist_error_addr[0:BIST_NO_SRAM-1] ; // bist address + +wire [BIST_ADDR_WD-1:0]bist_addr ; // bist address +wire [BIST_DATA_WD-1:0] bist_wdata ; // bist write data +wire bist_wr ; +wire bist_rd ; +wire [BIST_DATA_WD-1:0] wb_dat[0:BIST_NO_SRAM-1]; // data input +wire wb_ack[0:BIST_NO_SRAM-1]; // acknowlegement +wire wb_err[0:BIST_NO_SRAM-1]; // error + +//-------------------------------------------------------- +// As yosys does not support two dimensional var, +// converting it single dimension +// ------------------------------------------------------- +wire [3:0] bist_error_cnt_i [0:BIST_NO_SRAM-1]; + +assign bist_error_cnt0 = bist_error_cnt_i[0]; +assign bist_error_cnt1 = bist_error_cnt_i[1]; +assign bist_error_cnt2 = bist_error_cnt_i[2]; +assign bist_error_cnt3 = bist_error_cnt_i[3]; + + +// Towards MEMORY PORT - A +wire [BIST_ADDR_WD-1:0] mem_addr_a_i[0:BIST_NO_SRAM-1]; +wire [BIST_DATA_WD/8-1:0] mem_mask_a_i[0:BIST_NO_SRAM-1]; +wire [BIST_DATA_WD-1:0] mem_dout_a_i[0:BIST_NO_SRAM-1]; +wire [BIST_DATA_WD-1:0] mem_din_a_i[0:BIST_NO_SRAM-1]; + +assign mem_addr_a0 = mem_addr_a_i[0]; +assign mem_addr_a1 = mem_addr_a_i[1]; +assign mem_addr_a2 = mem_addr_a_i[2]; +assign mem_addr_a3 = mem_addr_a_i[3]; + +assign mem_din_a0 = mem_din_a_i[0]; +assign mem_din_a1 = mem_din_a_i[1]; +assign mem_din_a2 = mem_din_a_i[2]; +assign mem_din_a3 = mem_din_a_i[3]; + +assign mem_mask_a0= mem_mask_a_i[0]; +assign mem_mask_a1= mem_mask_a_i[1]; +assign mem_mask_a2= mem_mask_a_i[2]; +assign mem_mask_a3= mem_mask_a_i[3]; + +// FROM MEMORY +assign mem_dout_a_i[0] = mem_dout_a0; +assign mem_dout_a_i[1] = mem_dout_a1; +assign mem_dout_a_i[2] = mem_dout_a2; +assign mem_dout_a_i[3] = mem_dout_a3; + +// Towards MEMORY PORT - A +assign mem_clk_b = 'b0; +assign mem_cen_b = 'b0; +assign mem_addr_b0 = 'b0; +assign mem_addr_b1 = 'b0; +assign mem_addr_b2 = 'b0; +assign mem_addr_b3 = 'b0; + +//--------------------------------------------------- +// Manage the SDI => SDO Diasy chain +// -------------------------------------------------- +//--------------------------------- +// SDI => SDO diasy chain +// bist_sdi => bist_addr_sdo => bist_sti_sdo => bist_op_sdo => bist_pat_sdo => bist_sdo +// --------------------------------- +wire bist_addr_sdo ; +wire bist_sti_sdo ; +wire bist_op_sdo ; +wire bist_pat_sdo ; + +wire bist_ms_sdi[0:BIST_NO_SRAM-1]; +wire bist_ms_sdo[0:BIST_NO_SRAM-1]; + +// Adjust the SDI => SDO Daisy chain +assign bist_ms_sdi[0] = bist_pat_sdo; +assign bist_ms_sdi[1] = bist_ms_sdo[0]; +assign bist_ms_sdi[2] = bist_ms_sdo[1]; +assign bist_ms_sdi[3] = bist_ms_sdo[2]; +assign bist_sdo = bist_ms_sdo[3]; + +// Pick the correct read path +assign wb_dat_o = wb_dat[wb_cs_i]; +assign wb_ack_o = wb_ack[wb_cs_i]; +assign wb_err_o = wb_err[wb_cs_i]; + +assign bist_wr = (cmd_phase && op_write); +assign bist_rd = (cmd_phase && op_read); + +assign compare = (cmp_phase && op_read); +assign bist_wdata = (op_invert) ? ~pat_data : pat_data; + +// Clock Tree branching to avoid clock latency towards SRAM path +wire wb_clk_b1,wb_clk_b2; +//ctech_clk_buf u_cts_wb_clk_b1 (.A (wb_clk_i), . X(wb_clk_b1)); +//ctech_clk_buf u_cts_wb_clk_b2 (.A (wb_clk_i), . X(wb_clk_b2)); + +// wb_host clock skew control +clk_skew_adjust u_skew_mbist + ( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground +`endif + .clk_in (wbd_clk_int ), + .sel (cfg_cska_mbist ), + .clk_out (wbd_clk_mbist ) + ); + +reset_sync u_reset_sync ( + .scan_mode (1'b0 ), + .dclk (wb_clk_i ), // Destination clock domain + .arst_n (rst_n ), // active low async reset + .srst_n (srst_n ) + ); + + +integer i; +reg bist_error_and; +reg bist_error_correct_or; + +always_comb begin + bist_error_and =0; + bist_error_correct_or = 0; + for(i=0; i <BIST_NO_SRAM; i = i+1) begin + bist_error_and = bist_error_and & bist_error[i]; + bist_error_correct_or = bist_error_correct_or | bist_error_correct[i]; + end +end + + +// bist main control FSM + +mbist_fsm + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + u_fsm ( + + .cmd_phase (cmd_phase ), + .cmp_phase (cmp_phase ), + .run_op (run_op ), + .run_addr (run_addr ), + .run_sti (run_sti ), + .run_pat (run_pat ), + .bist_done (bist_done ), + + + .clk (wb_clk_i ), + .rst_n (srst_n ), + .bist_run (bist_run ), + .last_op (last_op ), + .last_addr (last_addr ), + .last_sti (last_sti ), + .last_pat (last_pat ), + .op_reverse (op_reverse ), + .bist_error (bist_error_and ) +); + + +// bist address generation +mbist_addr_gen + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + u_addr_gen( + .last_addr (last_addr ), + .bist_addr (bist_addr ), + .sdo (bist_addr_sdo ), + + .clk (wb_clk_i ), + .rst_n (srst_n ), + .run (run_addr ), + .updown (op_updown ), + .bist_shift (bist_shift ), + .bist_load (bist_load ), + .sdi (bist_sdi ) + +); + + +// BIST current stimulus selection +mbist_sti_sel + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + u_sti_sel( + + .sdo (bist_sti_sdo ), + .last_stimulus (last_sti ), + .stimulus (stimulus ), + + .clk (wb_clk_i ), + .rst_n (srst_n ), + .scan_shift (bist_shift ), + .sdi (bist_addr_sdo ), + .run (run_sti ) + +); + + +// Bist Operation selection +mbist_op_sel + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + u_op_sel ( + + .op_read (op_read ), + .op_write (op_write ), + .op_invert (op_invert ), + .op_updown (op_updown ), + .op_reverse (op_reverse ), + .op_repeatflag (op_repeatflag ), + .sdo (bist_op_sdo ), + .last_op (last_op ), + + .clk (wb_clk_i ), + .rst_n (srst_n ), + .scan_shift (bist_shift ), + .sdi (bist_sti_sdo ), + .re_init (bist_error_correct_or ), + .run (run_op ), + .stimulus (stimulus ) + + ); + + + +mbist_pat_sel + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + u_pat_sel ( + .pat_last (last_pat ), + .pat_data (pat_data ), + .sdo (bist_pat_sdo ), + .clk (wb_clk_i ), + .rst_n (srst_n ), + .run (run_pat ), + .scan_shift (bist_shift ), + .sdi (bist_op_sdo ) + + ); + + + + + +genvar sram_no; +generate +for (sram_no = 0; $unsigned(sram_no) < BIST_NO_SRAM; sram_no=sram_no+1) begin : mem_no + + +mbist_data_cmp + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + + + u_cmp ( + .error (bist_error[sram_no] ), + .error_correct (bist_error_correct[sram_no] ), + .correct ( ), // same signal available at bist mux + .error_addr (bist_error_addr[sram_no] ), + .error_cnt (bist_error_cnt_i[sram_no] ), + .clk (wb_clk_i ), + .rst_n (srst_n ), + .addr_inc_phase (run_addr ), + .compare (compare ), + .read_invert (op_invert ), + .comp_data (pat_data ), + .rxd_data (func_dout[sram_no] ), + .addr (bist_addr ) + + ); + + // WB To Memory Signal Mapping + mbist_mem_wrapper #( + .BIST_NO_SRAM (BIST_NO_SRAM ), + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ) + ) u_mem_wrapper_( + .rst_n (srst_n ), + // WB I/F + .sram_id (NO_SRAM_WD'(sram_no) ), + .wb_clk_i (wb_clk2_i ), // System clock + .wb_cyc_i (wb_cyc_i ), // strobe/request + .wb_cs_i (wb_cs_i ), // Chip Select + .wb_stb_i (wb_stb_i ), // strobe/request + .wb_adr_i (wb_adr_i ), // address + .wb_we_i (wb_we_i ), // write + .wb_dat_i (wb_dat_i ), // data output + .wb_sel_i (wb_sel_i ), // byte enable + .wb_dat_o (wb_dat[sram_no] ), // data input + .wb_ack_o (wb_ack[sram_no] ), // acknowlegement + .wb_err_o (wb_err[sram_no] ), // error + // MEM A PORT + .func_clk (func_clk[sram_no] ), + .func_cen (func_cen[sram_no] ), + .func_web (func_web[sram_no] ), + .func_mask (func_mask[sram_no] ), + .func_addr (func_addr[sram_no] ), + .func_din (func_din[sram_no] ), + .func_dout (func_dout[sram_no] ) + ); + + +mbist_mux + #( + .BIST_ADDR_WD (BIST_ADDR_WD ), + .BIST_DATA_WD (BIST_DATA_WD ), + .BIST_ADDR_START (BIST_ADDR_START ), + .BIST_ADDR_END (BIST_ADDR_END ), + .BIST_REPAIR_ADDR_START (BIST_REPAIR_ADDR_START ), + .BIST_RAD_WD_I (BIST_RAD_WD_I ), + .BIST_RAD_WD_O (BIST_RAD_WD_O ) + ) + u_mem_sel ( + + .scan_mode (1'b0 ), + + .rst_n (srst_n ), + // MBIST CTRL SIGNAL + .bist_en (bist_en ), + .bist_addr (bist_addr ), + .bist_wdata (bist_wdata ), + .bist_clk (wb_clk2_i ), + .bist_wr (bist_wr ), + .bist_rd (bist_rd ), + .bist_error (bist_error_correct[sram_no]), + .bist_error_addr (bist_error_addr[sram_no] ), + .bist_correct (bist_correct[sram_no] ), + .bist_sdi (bist_ms_sdi[sram_no] ), + .bist_load (bist_load ), + .bist_shift (bist_shift ), + .bist_sdo (bist_ms_sdo[sram_no] ), + + // FUNCTIONAL CTRL SIGNAL + .func_clk (func_clk[sram_no] ), + .func_cen (func_cen[sram_no] ), + .func_web (func_web[sram_no] ), + .func_mask (func_mask[sram_no] ), + .func_addr (func_addr[sram_no] ), + .func_din (func_din[sram_no] ), + .func_dout (func_dout[sram_no] ), + + + // towards memory + // Memory Out Port + .mem_clk (mem_clk_a[sram_no] ), + .mem_cen (mem_cen_a[sram_no] ), + .mem_web (mem_web_a[sram_no] ), + .mem_mask (mem_mask_a_i[sram_no] ), + .mem_addr (mem_addr_a_i[sram_no] ), + .mem_din (mem_din_a_i[sram_no] ), + .mem_dout (mem_dout_a_i[sram_no] ) + + ); +end +endgenerate + +endmodule +
diff --git a/verilog/rtl/pinmux/src/pinmux.sv b/verilog/rtl/pinmux/src/pinmux.sv index 518ceaa..3588254 100755 --- a/verilog/rtl/pinmux/src/pinmux.sv +++ b/verilog/rtl/pinmux/src/pinmux.sv
@@ -79,15 +79,15 @@ output logic [31:0] pinmux_debug, // BIST I/F - output logic [3:0] bist_en, - output logic [3:0] bist_run, - output logic [3:0] bist_load, + output logic bist_en, + output logic bist_run, + output logic bist_load, - output logic [3:0] bist_sdi, - output logic [3:0] bist_shift, - input logic [3:0] bist_sdo, + output logic bist_sdi, + output logic bist_shift, + input logic bist_sdo, - input logic [3:0] bist_done, + input logic bist_done, input logic [3:0] bist_error, input logic [3:0] bist_correct, input logic [3:0] bist_error_cnt0,
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv index 4ed5fbc..06e259e 100644 --- a/verilog/rtl/pinmux/src/pinmux_reg.sv +++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -64,21 +64,21 @@ output logic [31:0] gpio_prev_indata, // prv data from GPIO I/P pins // BIST I/F - output logic [3:0] bist_en, - output logic [3:0] bist_run, - output logic [3:0] bist_load, + output logic bist_en, + output logic bist_run, + output logic bist_load, - output logic [3:0] bist_sdi, - output logic [3:0] bist_shift, - input logic [3:0] bist_sdo, + output logic bist_sdi, + output logic bist_shift, + input logic bist_sdo, - input logic [3:0] bist_done, - input logic [3:0] bist_error, - input logic [3:0] bist_correct, - input logic [3:0] bist_error_cnt0, - input logic [3:0] bist_error_cnt1, - input logic [3:0] bist_error_cnt2, - input logic [3:0] bist_error_cnt3 + input logic bist_done, + input logic [3:0] bist_error, + input logic [3:0] bist_correct, + input logic [3:0] bist_error_cnt0, + input logic [3:0] bist_error_cnt1, + input logic [3:0] bist_error_cnt2, + input logic [3:0] bist_error_cnt3 ); @@ -668,7 +668,7 @@ //----------------------------------------- // Software Reg-2, Release date: <DAY><MONTH><YEAR> // ---------------------------------------- -gen_32b_reg #(32'h1312_2021) u_reg_23 ( +gen_32b_reg #(32'h2012_2021) u_reg_23 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -681,9 +681,9 @@ ); //----------------------------------------- -// Software Reg-3: Poject Revison 2.0 = 0002000 +// Software Reg-3: Poject Revison 2.1 = 0002200 // ---------------------------------------- -gen_32b_reg #(32'h0002_0000) u_reg_24 ( +gen_32b_reg #(32'h0002_2000) u_reg_24 ( //List of Inputs .reset_n (h_reset_n ), .clk (mclk ), @@ -759,23 +759,11 @@ ); -wire [3:0] bist_serial_sel = cfg_bist_ctrl_1[31:28]; -assign bist_en[0] = cfg_bist_ctrl_1[0]; -assign bist_run[0] = cfg_bist_ctrl_1[1]; -assign bist_load[0] = cfg_bist_ctrl_1[2]; +assign bist_en = cfg_bist_ctrl_1[0]; +assign bist_run = cfg_bist_ctrl_1[1]; +assign bist_load = cfg_bist_ctrl_1[2]; -assign bist_en[1] = cfg_bist_ctrl_1[4]; -assign bist_run[1] = cfg_bist_ctrl_1[5]; -assign bist_load[1] = cfg_bist_ctrl_1[6]; - -assign bist_en[2] = cfg_bist_ctrl_1[8]; -assign bist_run[2] = cfg_bist_ctrl_1[9]; -assign bist_load[2] = cfg_bist_ctrl_1[10]; - -assign bist_en[3] = cfg_bist_ctrl_1[12]; -assign bist_run[3] = cfg_bist_ctrl_1[13]; -assign bist_load[3] = cfg_bist_ctrl_1[14]; //----------------------------------------------------------------------- // reg-29 @@ -783,10 +771,10 @@ logic [31:0] cfg_bist_status_1; assign cfg_bist_status_1 = { 16'h0, - bist_error_cnt3, 1'b0, bist_correct[3], bist_error[3], bist_done[3], - bist_error_cnt2, 1'b0, bist_correct[2], bist_error[2], bist_done[2], - bist_error_cnt1, 1'b0, bist_correct[1], bist_error[1], bist_done[1], - bist_error_cnt0, 1'b0, bist_correct[0], bist_error[0], bist_done[0] + bist_error_cnt3, 1'b0, bist_correct[3], bist_error[3], bist_done, + bist_error_cnt2, 1'b0, bist_correct[2], bist_error[2], bist_done, + bist_error_cnt1, 1'b0, bist_correct[1], bist_error[1], bist_done, + bist_error_cnt0, 1'b0, bist_correct[0], bist_error[0], bist_done }; //----------------------------------------------------------------------- @@ -798,21 +786,9 @@ logic bist_sdo_int; logic [31:0] serail_dout; -assign bist_sdo_int = (bist_serial_sel == 4'b0000) ? bist_sdo[0] : - (bist_serial_sel == 4'b0001) ? bist_sdo[1] : - (bist_serial_sel == 4'b0010) ? bist_sdo[2] : - (bist_serial_sel == 4'b0011) ? bist_sdo[3] : - 1'b0; - -assign bist_shift[0] = (bist_serial_sel == 4'b0000) ? bist_shift_int : 1'b0; -assign bist_shift[1] = (bist_serial_sel == 4'b0001) ? bist_shift_int : 1'b0; -assign bist_shift[2] = (bist_serial_sel == 4'b0010) ? bist_shift_int : 1'b0; -assign bist_shift[3] = (bist_serial_sel == 4'b0011) ? bist_shift_int : 1'b0; - -assign bist_sdi[0] = (bist_serial_sel == 4'b0000) ? bist_sdi_int : 1'b0; -assign bist_sdi[1] = (bist_serial_sel == 4'b0001) ? bist_sdi_int : 1'b0; -assign bist_sdi[2] = (bist_serial_sel == 4'b0010) ? bist_sdi_int : 1'b0; -assign bist_sdi[3] = (bist_serial_sel == 4'b0011) ? bist_sdi_int : 1'b0; +assign bist_sdo_int = bist_sdo; +assign bist_shift = bist_shift_int; +assign bist_sdi = bist_sdi_int ; ser_inf_32b u_ser_intf (
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv index dfe2904..b1a5a05 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_intf.sv
@@ -73,87 +73,104 @@ module scr1_intf ( // Control - input logic pwrup_rst_n, // Power-Up Reset - input logic rst_n, // Regular Reset signal - input logic cpu_rst_n, // CPU Reset (Core Reset) - input logic core_clk, // Core clock - input logic rtc_clk, // Real-time clock - output logic [63:0] riscv_debug, + input logic pwrup_rst_n, // Power-Up Reset + input logic rst_n, // Regular Reset signal + input logic cpu_rst_n, // CPU Reset (Core Reset) + input logic core_clk, // Core clock + input logic rtc_clk, // Real-time clock + output logic [63:0] riscv_debug, `ifdef SCR1_DBG_EN // -- JTAG I/F - input logic trst_n, + input logic trst_n, `endif // SCR1_DBG_EN `ifndef SCR1_TCM_MEM - // SRAM PORT-0 - output logic sram_csb0, - output logic sram_web0, - output logic [8:0] sram_addr0, - output logic [3:0] sram_wmask0, - output logic [31:0] sram_din0, - input logic [31:0] sram_dout0, + // SRAM-0 PORT-0 + output logic sram0_clk0, + output logic sram0_csb0, + output logic sram0_web0, + output logic [8:0] sram0_addr0, + output logic [3:0] sram0_wmask0, + output logic [31:0] sram0_din0, + input logic [31:0] sram0_dout0, - // SRAM PORT-1 - output logic sram_csb1, - output logic [8:0] sram_addr1, - input logic [31:0] sram_dout1, + // SRAM-0 PORT-1 + output logic sram0_clk1, + output logic sram0_csb1, + output logic [8:0] sram0_addr1, + input logic [31:0] sram0_dout1, + + // SRAM-1 PORT-0 + output logic sram1_clk0, + output logic sram1_csb0, + output logic sram1_web0, + output logic [8:0] sram1_addr0, + output logic [3:0] sram1_wmask0, + output logic [31:0] sram1_din0, + input logic [31:0] sram1_dout0, + + // SRAM-1 PORT-1 + output logic sram1_clk1, + output logic sram1_csb1, + output logic [8:0] sram1_addr1, + input logic [31:0] sram1_dout1, `endif - input logic wb_rst_n, // Wish bone reset - input logic wb_clk, // wish bone clock + input logic wb_rst_n, // Wish bone reset + input logic wb_clk, // wish bone clock // Instruction Memory Interface - output logic wbd_imem_stb_o, // strobe/request - output logic [SCR1_WB_WIDTH-1:0] wbd_imem_adr_o, // address - output logic wbd_imem_we_o, // write - output logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_o, // data output - output logic [3:0] wbd_imem_sel_o, // byte enable - input logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_i, // data input - input logic wbd_imem_ack_i, // acknowlegement - input logic wbd_imem_err_i, // error + output logic wbd_imem_stb_o, // strobe/request + output logic [SCR1_WB_WIDTH-1:0] wbd_imem_adr_o, // address + output logic wbd_imem_we_o, // write + output logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_o, // data output + output logic [3:0] wbd_imem_sel_o, // byte enable + input logic [SCR1_WB_WIDTH-1:0] wbd_imem_dat_i, // data input + input logic wbd_imem_ack_i, // acknowlegement + input logic wbd_imem_err_i, // error // Data Memory Interface - output logic wbd_dmem_stb_o, // strobe/request - output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_adr_o, // address - output logic wbd_dmem_we_o, // write - output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_o, // data output - output logic [3:0] wbd_dmem_sel_o, // byte enable - input logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_i, // data input - input logic wbd_dmem_ack_i, // acknowlegement - input logic wbd_dmem_err_i, // error + output logic wbd_dmem_stb_o, // strobe/request + output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_adr_o, // address + output logic wbd_dmem_we_o, // write + output logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_o, // data output + output logic [3:0] wbd_dmem_sel_o, // byte enable + input logic [SCR1_WB_WIDTH-1:0] wbd_dmem_dat_i, // data input + input logic wbd_dmem_ack_i, // acknowlegement + input logic wbd_dmem_err_i, // error // Common - output logic pwrup_rst_n_sync, // Power-Up reset - output logic rst_n_sync, // Regular reset - output logic cpu_rst_n_sync, // CPU reset - output logic test_mode, // DFT Test Mode - output logic test_rst_n, // DFT Test Reset - input logic core_rst_n_local, // Core reset - input logic [48:0] core_debug , + output logic pwrup_rst_n_sync, // Power-Up reset + output logic rst_n_sync, // Regular reset + output logic cpu_rst_n_sync, // CPU reset + output logic test_mode, // DFT Test Mode + output logic test_rst_n, // DFT Test Reset + input logic core_rst_n_local, // Core reset + input logic [48:0] core_debug , `ifdef SCR1_DBG_EN // Debug Interface - output logic tapc_trst_n, // Test Reset (TRSTn) + output logic tapc_trst_n, // Test Reset (TRSTn) `endif // Memory-mapped external timer - output logic [63:0] timer_val, // Machine timer value - output logic timer_irq, + output logic [63:0] timer_val, // Machine timer value + output logic timer_irq, // Instruction Memory Interface - output logic core_imem_req_ack, // IMEM request acknowledge - input logic core_imem_req, // IMEM request - input logic core_imem_cmd, // IMEM command - input logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr, // IMEM address - output logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata, // IMEM read data - output logic [1:0] core_imem_resp, // IMEM response + output logic core_imem_req_ack, // IMEM request acknowledge + input logic core_imem_req, // IMEM request + input logic core_imem_cmd, // IMEM command + input logic [`SCR1_IMEM_AWIDTH-1:0] core_imem_addr, // IMEM address + output logic [`SCR1_IMEM_DWIDTH-1:0] core_imem_rdata, // IMEM read data + output logic [1:0] core_imem_resp, // IMEM response // Data Memory Interface - output logic core_dmem_req_ack, // DMEM request acknowledge - input logic core_dmem_req, // DMEM request - input logic core_dmem_cmd, // DMEM command - input logic[1:0] core_dmem_width, // DMEM data width - input logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr, // DMEM address - input logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata, // DMEM write data - output logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata, // DMEM read data - output logic [1:0] core_dmem_resp // DMEM response + output logic core_dmem_req_ack, // DMEM request acknowledge + input logic core_dmem_req, // DMEM request + input logic core_dmem_cmd, // DMEM command + input logic[1:0] core_dmem_width, // DMEM data width + input logic [`SCR1_DMEM_AWIDTH-1:0] core_dmem_addr, // DMEM address + input logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_wdata, // DMEM write data + output logic [`SCR1_DMEM_DWIDTH-1:0] core_dmem_rdata, // DMEM read data + output logic [1:0] core_dmem_resp // DMEM response ); //------------------------------------------------------------------------------- @@ -285,18 +302,36 @@ .rst_n (core_rst_n_local), `ifndef SCR1_TCM_MEM - // SRAM PORT-0 - .sram_csb0 (sram_csb0), - .sram_web0 (sram_web0), - .sram_addr0 (sram_addr0), - .sram_wmask0 (sram_wmask0), - .sram_din0 (sram_din0), - .sram_dout0 (sram_dout0), + // SRAM-0 PORT-0 + .sram0_clk0 (sram0_clk0), + .sram0_csb0 (sram0_csb0), + .sram0_web0 (sram0_web0), + .sram0_addr0 (sram0_addr0), + .sram0_wmask0 (sram0_wmask0), + .sram0_din0 (sram0_din0), + .sram0_dout0 (sram0_dout0), - // SRAM PORT-0 - .sram_csb1 (sram_csb1), - .sram_addr1 (sram_addr1), - .sram_dout1 (sram_dout1), + // SRAM-0 PORT-1 + .sram0_clk1 (sram0_clk1), + .sram0_csb1 (sram0_csb1), + .sram0_addr1 (sram0_addr1), + .sram0_dout1 (sram0_dout1), + + // SRAM-1 PORT-0 + .sram1_clk0 (sram1_clk0), + .sram1_csb0 (sram1_csb0), + .sram1_web0 (sram1_web0), + .sram1_addr0 (sram1_addr0), + .sram1_wmask0 (sram1_wmask0), + .sram1_din0 (sram1_din0), + .sram1_dout0 (sram1_dout0), + + // SRAM-1 PORT-1 + .sram1_clk1 (sram1_clk1), + .sram1_csb1 (sram1_csb1), + .sram1_addr1 (sram1_addr1), + .sram1_dout1 (sram1_dout1), + `endif
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv index 48e6930..2524fd3 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
@@ -33,18 +33,36 @@ input logic rst_n, `ifndef SCR1_TCM_MEM - // SRAM PORT-0 - output logic sram_csb0, - output logic sram_web0, - output logic [8:0] sram_addr0, - output logic [3:0] sram_wmask0, - output logic [31:0] sram_din0, - input logic [31:0] sram_dout0, + // SRAM0 PORT-0 + output logic sram0_clk0, + output logic sram0_csb0, + output logic sram0_web0, + output logic [8:0] sram0_addr0, + output logic [3:0] sram0_wmask0, + output logic [31:0] sram0_din0, + input logic [31:0] sram0_dout0, - // SRAM PORT-1 - output logic sram_csb1, - output logic [8:0] sram_addr1, - input logic [31:0] sram_dout1, + // SRAM-0 PORT-1 + output logic sram0_clk1, + output logic sram0_csb1, + output logic [8:0] sram0_addr1, + input logic [31:0] sram0_dout1, + + // SRAM1 PORT-0 + output logic sram1_clk0, + output logic sram1_csb0, + output logic sram1_web0, + output logic [8:0] sram1_addr0, + output logic [3:0] sram1_wmask0, + output logic [31:0] sram1_din0, + input logic [31:0] sram1_dout0, + + // SRAM-1 PORT-1 + output logic sram1_clk1, + output logic sram1_csb1, + output logic [8:0] sram1_addr1, + input logic [31:0] sram1_dout1, + `endif // Core instruction interface @@ -105,18 +123,38 @@ // Memory data composing //------------------------------------------------------------------------------- `ifndef SCR1_TCM_MEM -// connect the TCM memory to SRAM -assign sram_csb1 =!imem_req; -assign sram_addr1 = imem_addr[10:2]; -assign imem_rdata = sram_dout1; +// connect the TCM memory to SRAM-0 +assign sram0_clk1 = clk; +assign sram0_csb1 =!(imem_req & imem_addr[11] == 1'b0); +assign sram0_addr1 = imem_addr[10:2]; -// SRAM Port 0 Control Generation -assign sram_csb0 = !(dmem_req & ((dmem_cmd == SCR1_MEM_CMD_RD) | (dmem_cmd == SCR1_MEM_CMD_WR))); -assign sram_web0 = !(dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR)); -assign sram_addr0 = dmem_addr[10:2]; -assign sram_wmask0 = dmem_byteen; -assign sram_din0 = dmem_writedata; -assign dmem_rdata_local = sram_dout0; +// connect the TCM memory to SRAM-1 +assign sram1_clk1 = clk; +assign sram1_csb1 =!(imem_req & imem_addr[11] == 1'b1); +assign sram1_addr1 = imem_addr[10:2]; + +// IMEM Read Data Selection Based on Address bit[11] +assign imem_rdata = (imem_addr[11] == 1'b0) ? sram0_dout1: sram1_dout1; + +// SRAM-0 Port 0 Control Generation +assign sram0_clk0 = clk; +assign sram0_csb0 = !(dmem_req & (imem_addr[11] == 1'b0) & ((dmem_cmd == SCR1_MEM_CMD_RD) | (dmem_cmd == SCR1_MEM_CMD_WR))); +assign sram0_web0 = !(dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR)); +assign sram0_addr0 = dmem_addr[10:2]; +assign sram0_wmask0 = dmem_byteen; +assign sram0_din0 = dmem_writedata; + +// SRAM-1 Port 0 Control Generation +assign sram1_clk0 = clk; +assign sram1_csb0 = !(dmem_req & (imem_addr[11] == 1'b1) & ((dmem_cmd == SCR1_MEM_CMD_RD) | (dmem_cmd == SCR1_MEM_CMD_WR))); +assign sram1_web0 = !(dmem_req & (dmem_cmd == SCR1_MEM_CMD_WR)); +assign sram1_addr0 = dmem_addr[10:2]; +assign sram1_wmask0 = dmem_byteen; +assign sram1_din0 = dmem_writedata; + + +// DMEM Read Data Selection Based on Address bit[11] +assign dmem_rdata_local = (dmem_addr[11] == 1'b0) ? sram0_dout0: sram1_dout0; `endif
diff --git a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv index 6c67693..60e055c 100644 --- a/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv +++ b/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
@@ -141,18 +141,35 @@ `endif // SCR1_DBG_EN `ifndef SCR1_TCM_MEM - // SRAM PORT-0 - output logic sram_csb0, - output logic sram_web0, - output logic [8:0] sram_addr0, - output logic [3:0] sram_wmask0, - output logic [31:0] sram_din0, - input logic [31:0] sram_dout0, + // SRAM-0 PORT-0 + output logic sram0_clk0, + output logic sram0_csb0, + output logic sram0_web0, + output logic [8:0] sram0_addr0, + output logic [3:0] sram0_wmask0, + output logic [31:0] sram0_din0, + input logic [31:0] sram0_dout0, - // SRAM PORT-1 - output logic sram_csb1, - output logic [8:0] sram_addr1, - input logic [31:0] sram_dout1, + // SRAM-0 PORT-1 + output logic sram0_clk1, + output logic sram0_csb1, + output logic [8:0] sram0_addr1, + input logic [31:0] sram0_dout1, + + // SRAM-1 PORT-0 + output logic sram1_clk0, + output logic sram1_csb0, + output logic sram1_web0, + output logic [8:0] sram1_addr0, + output logic [3:0] sram1_wmask0, + output logic [31:0] sram1_din0, + input logic [31:0] sram1_dout0, + + // SRAM-1 PORT-1 + output logic sram1_clk1, + output logic sram1_csb1, + output logic [8:0] sram1_addr1, + input logic [31:0] sram1_dout1, `endif @@ -297,18 +314,35 @@ `endif // SCR1_DBG_EN `ifndef SCR1_TCM_MEM - // SRAM PORT-0 - .sram_csb0 (sram_csb0), - .sram_web0 (sram_web0), - .sram_addr0 (sram_addr0), - .sram_wmask0 (sram_wmask0), - .sram_din0 (sram_din0), - .sram_dout0 (sram_dout0), + // SRAM-0 PORT-0 + .sram0_clk0 (sram0_clk0), + .sram0_csb0 (sram0_csb0), + .sram0_web0 (sram0_web0), + .sram0_addr0 (sram0_addr0), + .sram0_wmask0 (sram0_wmask0), + .sram0_din0 (sram0_din0), + .sram0_dout0 (sram0_dout0), - // SRAM PORT-0 - .sram_csb1 (sram_csb1), - .sram_addr1 (sram_addr1), - .sram_dout1 (sram_dout1), + // SRAM-0 PORT-1 + .sram0_clk1 (sram0_clk1), + .sram0_csb1 (sram0_csb1), + .sram0_addr1 (sram0_addr1), + .sram0_dout1 (sram0_dout1), + + // SRAM-1 PORT-0 + .sram1_clk0 (sram1_clk0), + .sram1_csb0 (sram1_csb0), + .sram1_web0 (sram1_web0), + .sram1_addr0 (sram1_addr0), + .sram1_wmask0 (sram1_wmask0), + .sram1_din0 (sram1_din0), + .sram1_dout0 (sram1_dout0), + + // SRAM-1 PORT-1 + .sram1_clk1 (sram1_clk1), + .sram1_csb1 (sram1_csb1), + .sram1_addr1 (sram1_addr1), + .sram1_dout1 (sram1_dout1), `endif .wb_rst_n (wb_rst_n), // Wish bone reset
diff --git a/verilog/rtl/uart/src/uart_core.sv b/verilog/rtl/uart/src/uart_core.sv index b3eefab..948cd35 100644 --- a/verilog/rtl/uart/src/uart_core.sv +++ b/verilog/rtl/uart/src/uart_core.sv
@@ -192,7 +192,10 @@ wire line_clk_16x_in; -ctech_clk_buf u_lineclk_buf (.A(line_clk_16x_in), .X(line_clk_16x)); +// OpenSource CTS tool does not work with buffer as source point +// changed buf to max with select tied=0 +//ctech_clk_buf u_lineclk_buf (.A(line_clk_16x_in), .X(line_clk_16x)); +ctech_mux2x1 u_lineclk_buf (.A0(line_clk_16x_in), .A1(1'b0), .S(1'b0), .X(line_clk_16x)); clk_ctl #(11) u_clk_ctl ( // Outputs
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v index b140722..18389aa 100644 --- a/verilog/rtl/uprj_netlists.v +++ b/verilog/rtl/uprj_netlists.v
@@ -99,6 +99,7 @@ `include "lib/registers.v" `include "lib/clk_ctl.v" `include "lib/ser_inf_32b.sv" + `include "lib/ser_shift.sv" `include "digital_core/src/glbl_cfg.sv" `include "wb_host/src/wb_host.sv" @@ -154,7 +155,7 @@ `include "mbist/src/core/mbist_data_cmp.sv" `include "mbist/src/core/mbist_mem_wrapper.sv" - `include "mbist/src/top/mbist_top1.sv" + `include "mbist/src/top/mbist_top.sv" `include "user_project_wrapper.v" // we are using netlist file for clk_skew_adjust as it has
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index bb64ea6..916a1fd 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -129,8 +129,16 @@ //// 1.9 Dec 11, 2021, Dinesh A //// //// 2 x 2K SRAM added into Wishbone Interface //// //// Temporary ADC block removed //// -//// 0.0 Dec 14, 2021, Dinesh A //// +//// 2.0 Dec 14, 2021, Dinesh A //// //// Added two more 2K SRAM added into Wishbone Interface //// +//// 2.1 Dec 16, 2021, Dinesh A //// +//// 1.4 MBIST controller changed to single one //// +//// 2.Added one more SRAM to TCM memory //// +//// 3.WishBone Interconnect chang to take care mbist changes//// +//// 4.Pinmux change to take care of mbist changes //// +//// 2.2 Dec 20, 2021, Dinesh A //// +//// 1. MBIST design issue fix for yosys //// +//// 2. Full chip Timing and Transition clean-up //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2000 Authors and OPENCORES.ORG //// @@ -208,6 +216,7 @@ // Local Parameter Declaration // -------------------------------------------------- +parameter BIST_NO_SRAM= 4; // NO of MBIST MEMORY parameter SDR_DW = 8; // SDR Data Width parameter SDR_BW = 1; // SDR Byte Width parameter WB_WIDTH = 32; // WB ADDRESS/DARA WIDTH @@ -305,54 +314,16 @@ //--------------------------------------------------------------------- // MBIST1 //--------------------------------------------------------------------- -wire wbd_mbist1_stb_o; // strobe/request -wire [BIST1_ADDR_WD-1:0] wbd_mbist1_adr_o; // address -wire wbd_mbist1_we_o; // write -wire [WB_WIDTH-1:0] wbd_mbist1_dat_o; // data output -wire [3:0] wbd_mbist1_sel_o; // byte enable -wire wbd_mbist1_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist1_dat_i; // data input -wire wbd_mbist1_ack_i; // acknowlegement -wire wbd_mbist1_err_i; // error +wire wbd_mbist_stb_o; // strobe/request +wire [12:0] wbd_mbist_adr_o; // address +wire wbd_mbist_we_o; // write +wire [WB_WIDTH-1:0] wbd_mbist_dat_o; // data output +wire [3:0] wbd_mbist_sel_o; // byte enable +wire wbd_mbist_cyc_o ; +wire [WB_WIDTH-1:0] wbd_mbist_dat_i; // data input +wire wbd_mbist_ack_i; // acknowlegement +wire wbd_mbist_err_i; // error -//--------------------------------------------------------------------- -// MBIST2 -//--------------------------------------------------------------------- -wire wbd_mbist2_stb_o; // strobe/request -wire [BIST1_ADDR_WD-1:0] wbd_mbist2_adr_o; // address -wire wbd_mbist2_we_o; // write -wire [WB_WIDTH-1:0] wbd_mbist2_dat_o; // data output -wire [3:0] wbd_mbist2_sel_o; // byte enable -wire wbd_mbist2_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist2_dat_i; // data input -wire wbd_mbist2_ack_i; // acknowlegement -wire wbd_mbist2_err_i; // error - -//--------------------------------------------------------------------- -// MBIST2 -//--------------------------------------------------------------------- -wire wbd_mbist3_stb_o; // strobe/request -wire [BIST1_ADDR_WD-1:0] wbd_mbist3_adr_o; // address -wire wbd_mbist3_we_o; // write -wire [WB_WIDTH-1:0] wbd_mbist3_dat_o; // data output -wire [3:0] wbd_mbist3_sel_o; // byte enable -wire wbd_mbist3_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist3_dat_i; // data input -wire wbd_mbist3_ack_i; // acknowlegement -wire wbd_mbist3_err_i; // error - -//--------------------------------------------------------------------- -// MBIST2 -//--------------------------------------------------------------------- -wire wbd_mbist4_stb_o; // strobe/request -wire [BIST1_ADDR_WD-1:0] wbd_mbist4_adr_o; // address -wire wbd_mbist4_we_o; // write -wire [WB_WIDTH-1:0] wbd_mbist4_dat_o; // data output -wire [3:0] wbd_mbist4_sel_o; // byte enable -wire wbd_mbist4_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist4_dat_i; // data input -wire wbd_mbist4_ack_i; // acknowlegement -wire wbd_mbist4_err_i; // error //---------------------------------------------------- // CPU Configuration //---------------------------------------------------- @@ -427,7 +398,7 @@ wire wbd_clk_spi_skew ; // clock for spi with clock skew wire wbd_clk_glbl_skew ; // clock for global reg with clock skew wire wbd_clk_wh_skew ; // clock for global reg -wire wbd_clk_mbist1_skew; // clock for global reg +wire wbd_clk_mbist_skew; // clock for global reg wire wbd_clk_mbist2_skew; // clock for global reg wire wbd_clk_mbist3_skew; // clock for global reg wire wbd_clk_mbist4_skew; // clock for global reg @@ -483,18 +454,36 @@ wire h_reset_n ; `ifndef SCR1_TCM_MEM -// SRAM PORT-0 - DMEM I/F -wire sram_csb0 ; // CS# -wire sram_web0 ; // WE# -wire [8:0] sram_addr0 ; // Address -wire [3:0] sram_wmask0 ; // WMASK# -wire [31:0] sram_din0 ; // Write Data -wire [31:0] sram_dout0 ; // Read Data +// SRAM-0 PORT-0 - DMEM I/F +wire sram0_clk0 ; // CLK +wire sram0_csb0 ; // CS# +wire sram0_web0 ; // WE# +wire [8:0] sram0_addr0 ; // Address +wire [3:0] sram0_wmask0 ; // WMASK# +wire [31:0] sram0_din0 ; // Write Data +wire [31:0] sram0_dout0 ; // Read Data -// SRAM PORT-1, IMEM I/F -wire sram_csb1 ; // CS# -wire [8:0] sram_addr1 ; // Address -wire [31:0] sram_dout1 ; // Read Data +// SRAM-0 PORT-1, IMEM I/F +wire sram0_clk1 ; // CLK +wire sram0_csb1 ; // CS# +wire [8:0] sram0_addr1 ; // Address +wire [31:0] sram0_dout1 ; // Read Data + +// SRAM-1 PORT-0 - DMEM I/F +wire sram1_clk0 ; // CLK +wire sram1_csb0 ; // CS# +wire sram1_web0 ; // WE# +wire [8:0] sram1_addr0 ; // Address +wire [3:0] sram1_wmask0 ; // WMASK# +wire [31:0] sram1_din0 ; // Write Data +wire [31:0] sram1_dout0 ; // Read Data + +// SRAM-1 PORT-1, IMEM I/F +wire sram1_clk1 ; // CLK +wire sram1_csb1 ; // CS# +wire [8:0] sram1_addr1 ; // Address +wire [31:0] sram1_dout1 ; // Read Data + `endif // SPIM I/F @@ -510,15 +499,15 @@ //---------------------------------------------------------- // BIST I/F // --------------------------------------------------------- -wire [3:0] bist_en ; -wire [3:0] bist_run ; -wire [3:0] bist_load ; +wire bist_en ; +wire bist_run ; +wire bist_load ; -wire [3:0] bist_sdi ; -wire [3:0] bist_shift ; -wire [3:0] bist_sdo ; +wire bist_sdi ; +wire bist_shift ; +wire bist_sdo ; -wire [3:0] bist_done ; +wire bist_done ; wire [3:0] bist_error ; wire [3:0] bist_correct ; wire [3:0] bist_error_cnt0 ; @@ -527,15 +516,15 @@ wire [3:0] bist_error_cnt3 ; // With Repeater Buffer -wire [3:0] bist_en_rp ; -wire [3:0] bist_run_rp ; -wire [3:0] bist_load_rp ; +wire bist_en_rp ; +wire bist_run_rp ; +wire bist_load_rp ; -wire [3:0] bist_sdi_rp ; -wire [3:0] bist_shift_rp ; -wire [3:0] bist_sdo_rp ; +wire bist_sdi_rp ; +wire bist_shift_rp ; +wire bist_sdo_rp ; -wire [3:0] bist_done_rp ; +wire bist_done_rp ; wire [3:0] bist_error_rp ; wire [3:0] bist_correct_rp ; wire [3:0] bist_error_cnt0_rp ; @@ -545,63 +534,34 @@ // towards memory MBIST1 // PORT-A -wire mem1_clk_a; +wire [BIST_NO_SRAM-1:0] mem_clk_a; +wire [BIST1_ADDR_WD-1:2] mem0_addr_a; wire [BIST1_ADDR_WD-1:2] mem1_addr_a; -wire mem1_cen_a; -wire [BIST_DATA_WD-1:0] mem1_din_b; - -// PORT-B -wire mem1_clk_b; -wire mem1_cen_b; -wire mem1_web_b; -wire [BIST_DATA_WD/8-1:0] mem1_mask_b; -wire [BIST1_ADDR_WD-1:2] mem1_addr_b; -wire [BIST_DATA_WD-1:0] mem1_dout_a; - -// towards memory MBIST2 -// PORT-A -wire mem2_clk_a; wire [BIST1_ADDR_WD-1:2] mem2_addr_a; -wire mem2_cen_a; -wire [BIST_DATA_WD-1:0] mem2_din_b; - -// PORT-B -wire mem2_clk_b; -wire mem2_cen_b; -wire mem2_web_b; -wire [BIST_DATA_WD/8-1:0] mem2_mask_b; -wire [BIST1_ADDR_WD-1:2] mem2_addr_b; -wire [BIST_DATA_WD-1:0] mem2_dout_a; - -// towards memory MBIST3 -// PORT-A -wire mem3_clk_a; wire [BIST1_ADDR_WD-1:2] mem3_addr_a; -wire mem3_cen_a; -wire [BIST_DATA_WD-1:0] mem3_din_b; +wire [BIST_NO_SRAM-1:0] mem_cen_a; +wire [BIST_NO_SRAM-1:0] mem_web_a; +wire [BIST_DATA_WD/8-1:0] mem0_mask_a; +wire [BIST_DATA_WD/8-1:0] mem1_mask_a; +wire [BIST_DATA_WD/8-1:0] mem2_mask_a; +wire [BIST_DATA_WD/8-1:0] mem3_mask_a; +wire [BIST_DATA_WD-1:0] mem0_din_a; +wire [BIST_DATA_WD-1:0] mem1_din_a; +wire [BIST_DATA_WD-1:0] mem2_din_a; +wire [BIST_DATA_WD-1:0] mem3_din_a; +wire [BIST_DATA_WD-1:0] mem0_dout_a; +wire [BIST_DATA_WD-1:0] mem1_dout_a; +wire [BIST_DATA_WD-1:0] mem2_dout_a; +wire [BIST_DATA_WD-1:0] mem3_dout_a; // PORT-B -wire mem3_clk_b; -wire mem3_cen_b; -wire mem3_web_b; -wire [BIST_DATA_WD/8-1:0] mem3_mask_b; +wire [BIST_NO_SRAM-1:0] mem_clk_b; +wire [BIST_NO_SRAM-1:0] mem_cen_b; +wire [BIST1_ADDR_WD-1:2] mem0_addr_b; +wire [BIST1_ADDR_WD-1:2] mem1_addr_b; +wire [BIST1_ADDR_WD-1:2] mem2_addr_b; wire [BIST1_ADDR_WD-1:2] mem3_addr_b; -wire [BIST_DATA_WD-1:0] mem3_dout_a; -// towards memory MBIST4 -// PORT-A -wire mem4_clk_a; -wire [BIST1_ADDR_WD-1:2] mem4_addr_a; -wire mem4_cen_a; -wire [BIST_DATA_WD-1:0] mem4_din_b; - -// PORT-B -wire mem4_clk_b; -wire mem4_cen_b; -wire mem4_web_b; -wire [BIST_DATA_WD/8-1:0] mem4_mask_b; -wire [BIST1_ADDR_WD-1:2] mem4_addr_b; -wire [BIST_DATA_WD-1:0] mem4_dout_a; ///////////////////////////////////////////////////////// // Clock Skew Ctrl @@ -724,18 +684,35 @@ // .test_rst_n (1'b1 ), // Moved inside IP `ifndef SCR1_TCM_MEM - // SRAM PORT-0 - .sram_csb0 (sram_csb0 ), - .sram_web0 (sram_web0 ), - .sram_addr0 (sram_addr0 ), - .sram_wmask0 (sram_wmask0 ), - .sram_din0 (sram_din0 ), - .sram_dout0 (sram_dout0 ), + // SRAM-0 PORT-0 + .sram0_clk0 (sram0_clk0 ), + .sram0_csb0 (sram0_csb0 ), + .sram0_web0 (sram0_web0 ), + .sram0_addr0 (sram0_addr0 ), + .sram0_wmask0 (sram0_wmask0 ), + .sram0_din0 (sram0_din0 ), + .sram0_dout0 (sram0_dout0 ), + + // SRAM-0 PORT-0 + .sram0_clk1 (sram0_clk1 ), + .sram0_csb1 (sram0_csb1 ), + .sram0_addr1 (sram0_addr1 ), + .sram0_dout1 (sram0_dout1 ), + + // SRAM-1 PORT-0 + .sram1_clk0 (sram1_clk0 ), + .sram1_csb0 (sram1_csb0 ), + .sram1_web0 (sram1_web0 ), + .sram1_addr0 (sram1_addr0 ), + .sram1_wmask0 (sram1_wmask0 ), + .sram1_din0 (sram1_din0 ), + .sram1_dout0 (sram1_dout0 ), // SRAM PORT-0 - .sram_csb1 (sram_csb1 ), - .sram_addr1 (sram_addr1 ), - .sram_dout1 (sram_dout1 ), + .sram1_clk1 (sram1_clk1 ), + .sram1_csb1 (sram1_csb1 ), + .sram1_addr1 (sram1_addr1 ), + .sram1_dout1 (sram1_dout1 ), `endif .wb_rst_n (wbd_int_rst_n ), @@ -762,24 +739,44 @@ ); `ifndef SCR1_TCM_MEM -sky130_sram_2kbyte_1rw1r_32x512_8 u_sram_2kb( +sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb( `ifdef USE_POWER_PINS .vccd1 (vccd1),// User area 1 1.8V supply .vssd1 (vssd1),// User area 1 digital ground `endif // Port 0: RW - .clk0 (cpu_clk), - .csb0 (sram_csb0), - .web0 (sram_web0), - .wmask0 (sram_wmask0), - .addr0 (sram_addr0), - .din0 (sram_din0), - .dout0 (sram_dout0), + .clk0 (sram0_clk0), + .csb0 (sram0_csb0), + .web0 (sram0_web0), + .wmask0 (sram0_wmask0), + .addr0 (sram0_addr0), + .din0 (sram0_din0), + .dout0 (sram0_dout0), // Port 1: R - .clk1 (cpu_clk), - .csb1 (sram_csb1), - .addr1 (sram_addr1), - .dout1 (sram_dout1) + .clk1 (sram0_clk1), + .csb1 (sram0_csb1), + .addr1 (sram0_addr1), + .dout1 (sram0_dout1) + ); + +sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram1_2kb( +`ifdef USE_POWER_PINS + .vccd1 (vccd1),// User area 1 1.8V supply + .vssd1 (vssd1),// User area 1 digital ground +`endif +// Port 0: RW + .clk0 (sram1_clk0), + .csb0 (sram1_csb0), + .web0 (sram1_web0), + .wmask0 (sram1_wmask0), + .addr0 (sram1_addr0), + .din0 (sram1_din0), + .dout0 (sram1_dout0), +// Port 1: R + .clk1 (sram1_clk1), + .csb1 (sram1_csb1), + .addr1 (sram1_addr1), + .dout1 (sram1_dout1) ); `endif @@ -837,7 +834,7 @@ wb_interconnect #( `ifndef SYNTHESIS .CH_CLK_WD(8), - .CH_DATA_WD(137) + .CH_DATA_WD(116) `endif ) u_intercon ( `ifdef USE_POWER_PINS @@ -866,46 +863,25 @@ bist_error_cnt3[3:0], bist_correct[3], bist_error[3], - bist_done[3], - bist_sdo[3], - bist_shift[3], - bist_sdi[3], - bist_load[3], - bist_run[3], - bist_en[3], bist_error_cnt2[3:0], bist_correct[2], bist_error[2], - bist_done[2], - bist_sdo[2], - bist_shift[2], - bist_sdi[2], - bist_load[2], - bist_run[2], - bist_en[2], bist_error_cnt1[3:0], bist_correct[1], bist_error[1], - bist_done[1], - bist_sdo[1], - bist_shift[1], - bist_sdi[1], - bist_load[1], - bist_run[1], - bist_en[1], bist_error_cnt0[3:0], bist_correct[0], bist_error[0], - bist_done[0], - bist_sdo[0], - bist_shift[0], - bist_sdi[0], - bist_load[0], - bist_run[0], - bist_en[0], + bist_done, + bist_sdo, + bist_shift, + bist_sdi, + bist_load, + bist_run, + bist_en, soft_irq, @@ -926,46 +902,25 @@ bist_error_cnt3_rp[3:0], bist_correct_rp[3], bist_error_rp[3], - bist_done_rp[3], - bist_sdo_rp[3], - bist_shift_rp[3], - bist_sdi_rp[3], - bist_load_rp[3], - bist_run_rp[3], - bist_en_rp[3], bist_error_cnt2_rp[3:0], bist_correct_rp[2], bist_error_rp[2], - bist_done_rp[2], - bist_sdo_rp[2], - bist_shift_rp[2], - bist_sdi_rp[2], - bist_load_rp[2], - bist_run_rp[2], - bist_en_rp[2], bist_error_cnt1_rp[3:0], bist_correct_rp[1], bist_error_rp[1], - bist_done_rp[1], - bist_sdo_rp[1], - bist_shift_rp[1], - bist_sdi_rp[1], - bist_load_rp[1], - bist_run_rp[1], - bist_en_rp[1], bist_error_cnt0_rp[3:0], bist_correct_rp[0], bist_error_rp[0], - bist_done_rp[0], - bist_sdo_rp[0], - bist_shift_rp[0], - bist_sdi_rp[0], - bist_load_rp[0], - bist_run_rp[0], - bist_en_rp[0], + bist_done_rp, + bist_sdo_rp, + bist_shift_rp, + bist_sdi_rp, + bist_load_rp, + bist_run_rp, + bist_en_rp, soft_irq_rp, irq_lines_rp[15:0], @@ -1059,47 +1014,15 @@ // Slave 3 Interface // .s3_wbd_err_i (1'b0 ), - Moved inside IP - .s3_wbd_dat_i (wbd_mbist1_dat_i ), - .s3_wbd_ack_i (wbd_mbist1_ack_i ), - .s3_wbd_dat_o (wbd_mbist1_dat_o ), - .s3_wbd_adr_o (wbd_mbist1_adr_o ), - .s3_wbd_sel_o (wbd_mbist1_sel_o ), - .s3_wbd_we_o (wbd_mbist1_we_o ), - .s3_wbd_cyc_o (wbd_mbist1_cyc_o ), - .s3_wbd_stb_o (wbd_mbist1_stb_o ), + .s3_wbd_dat_i (wbd_mbist_dat_i ), + .s3_wbd_ack_i (wbd_mbist_ack_i ), + .s3_wbd_dat_o (wbd_mbist_dat_o ), + .s3_wbd_adr_o (wbd_mbist_adr_o ), + .s3_wbd_sel_o (wbd_mbist_sel_o ), + .s3_wbd_we_o (wbd_mbist_we_o ), + .s3_wbd_cyc_o (wbd_mbist_cyc_o ), + .s3_wbd_stb_o (wbd_mbist_stb_o ) - // Slave 4 Interface - // .s4_wbd_err_i (1'b0 ), - Moved inside IP - .s4_wbd_dat_i (wbd_mbist2_dat_i ), - .s4_wbd_ack_i (wbd_mbist2_ack_i ), - .s4_wbd_dat_o (wbd_mbist2_dat_o ), - .s4_wbd_adr_o (wbd_mbist2_adr_o ), - .s4_wbd_sel_o (wbd_mbist2_sel_o ), - .s4_wbd_we_o (wbd_mbist2_we_o ), - .s4_wbd_cyc_o (wbd_mbist2_cyc_o ), - .s4_wbd_stb_o (wbd_mbist2_stb_o ), - - // Slave 5 Interface - // .s5_wbd_err_i (1'b0 ), - Moved inside IP - .s5_wbd_dat_i (wbd_mbist3_dat_i ), - .s5_wbd_ack_i (wbd_mbist3_ack_i ), - .s5_wbd_dat_o (wbd_mbist3_dat_o ), - .s5_wbd_adr_o (wbd_mbist3_adr_o ), - .s5_wbd_sel_o (wbd_mbist3_sel_o ), - .s5_wbd_we_o (wbd_mbist3_we_o ), - .s5_wbd_cyc_o (wbd_mbist3_cyc_o ), - .s5_wbd_stb_o (wbd_mbist3_stb_o ), - - // Slave 6 Interface - // .s6_wbd_err_i (1'b0 ), - Moved inside IP - .s6_wbd_dat_i (wbd_mbist4_dat_i ), - .s6_wbd_ack_i (wbd_mbist4_ack_i ), - .s6_wbd_dat_o (wbd_mbist4_dat_o ), - .s6_wbd_adr_o (wbd_mbist4_adr_o ), - .s6_wbd_sel_o (wbd_mbist4_sel_o ), - .s6_wbd_we_o (wbd_mbist4_we_o ), - .s6_wbd_cyc_o (wbd_mbist4_cyc_o ), - .s6_wbd_stb_o (wbd_mbist4_stb_o ) ); @@ -1260,8 +1183,9 @@ ); //------------- MBIST1 - 512x32 ---- -mbist_top1 #( +mbist_top #( `ifndef SYNTHESIS + .BIST_NO_SRAM (4 ), .BIST_ADDR_WD (BIST1_ADDR_WD-2 ), .BIST_DATA_WD (BIST_DATA_WD ), .BIST_ADDR_START (9'h000 ), @@ -1271,7 +1195,7 @@ .BIST_RAD_WD_O (BIST1_ADDR_WD-2 ) `endif ) - u_mbist1 ( + u_mbist ( `ifdef USE_POWER_PINS .vccd1 (vccd1 ),// User area 1 1.8V supply @@ -1281,228 +1205,132 @@ // Clock Skew adjust .wbd_clk_int (wbd_clk_mbist1_rp ), .cfg_cska_mbist (cfg_cska_mbist1_rp ), - .wbd_clk_mbist (wbd_clk_mbist1_skew ), + .wbd_clk_mbist (wbd_clk_mbist_skew ), // WB I/F - .wb_clk_i (wbd_clk_mbist1_skew ), - .wb_cyc_i (wbd_mbist1_cyc_o), - .wb_stb_i (wbd_mbist1_stb_o), - .wb_adr_i (wbd_mbist1_adr_o[BIST1_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist1_we_o ), - .wb_dat_i (wbd_mbist1_dat_o), - .wb_sel_i (wbd_mbist1_sel_o), - .wb_dat_o (wbd_mbist1_dat_i), - .wb_ack_o (wbd_mbist1_ack_i), + .wb_clk2_i (wbd_clk_mbist_skew ), + .wb_clk_i (wbd_clk_mbist_skew ), + .wb_cyc_i (wbd_mbist_cyc_o), + .wb_stb_i (wbd_mbist_stb_o), + .wb_cs_i (wbd_mbist_adr_o[12:11]), + .wb_adr_i (wbd_mbist_adr_o[BIST1_ADDR_WD-1:2]), + .wb_we_i (wbd_mbist_we_o ), + .wb_dat_i (wbd_mbist_dat_o), + .wb_sel_i (wbd_mbist_sel_o), + .wb_dat_o (wbd_mbist_dat_i), + .wb_ack_o (wbd_mbist_ack_i), .wb_err_o ( ), .rst_n (bist_rst_n ), - .bist_en (bist_en_rp[0] ), - .bist_run (bist_run_rp[0] ), - .bist_shift (bist_shift_rp[0] ), - .bist_load (bist_load_rp[0] ), - .bist_sdi (bist_sdi_rp[0] ), + .bist_en (bist_en_rp ), + .bist_run (bist_run_rp ), + .bist_shift (bist_shift_rp ), + .bist_load (bist_load_rp ), + .bist_sdi (bist_sdi_rp ), - .bist_error_cnt (bist_error_cnt0 ), - .bist_correct (bist_correct[0] ), - .bist_error (bist_error[0] ), - .bist_done (bist_done[0] ), - .bist_sdo (bist_sdo[0] ), + .bist_error_cnt3 (bist_error_cnt3 ), + .bist_error_cnt2 (bist_error_cnt2 ), + .bist_error_cnt1 (bist_error_cnt1 ), + .bist_error_cnt0 (bist_error_cnt0 ), + .bist_correct (bist_correct ), + .bist_error (bist_error ), + .bist_done (bist_done ), + .bist_sdo (bist_sdo ), // towards memory // PORT-A - .mem_clk_a (mem1_clk_a ), - .mem_addr_a (mem1_addr_a ), - .mem_cen_a (mem1_cen_a ), - .mem_dout_a (mem1_dout_a ), + .mem_clk_a (mem_clk_a ), + .mem_addr_a0 (mem0_addr_a ), + .mem_addr_a1 (mem1_addr_a ), + .mem_addr_a2 (mem2_addr_a ), + .mem_addr_a3 (mem3_addr_a ), + .mem_cen_a (mem_cen_a ), + .mem_web_a (mem_web_a ), + .mem_mask_a0 (mem0_mask_a ), + .mem_mask_a1 (mem1_mask_a ), + .mem_mask_a2 (mem2_mask_a ), + .mem_mask_a3 (mem3_mask_a ), + .mem_din_a0 (mem0_din_a ), + .mem_din_a1 (mem1_din_a ), + .mem_din_a2 (mem2_din_a ), + .mem_din_a3 (mem3_din_a ), + .mem_dout_a0 (mem0_dout_a ), + .mem_dout_a1 (mem1_dout_a ), + .mem_dout_a2 (mem2_dout_a ), + .mem_dout_a3 (mem3_dout_a ), // PORT-B - .mem_clk_b (mem1_clk_b ), - .mem_cen_b (mem1_cen_b ), - .mem_web_b (mem1_web_b ), - .mem_mask_b (mem1_mask_b ), - .mem_addr_b (mem1_addr_b ), - .mem_din_b (mem1_din_b ) + .mem_clk_b (mem_clk_b ), + .mem_cen_b (mem_cen_b ), + .mem_addr_b0 (mem0_addr_b ), + .mem_addr_b1 (mem1_addr_b ), + .mem_addr_b2 (mem2_addr_b ), + .mem_addr_b3 (mem3_addr_b ) ); +sky130_sram_2kbyte_1rw1r_32x512_8 u_sram0_2kb( +`ifdef USE_POWER_PINS + .vccd1 (vccd1),// User area 1 1.8V supply + .vssd1 (vssd1),// User area 1 digital ground +`endif +// Port 0: RW + .clk0 (mem_clk_a[0]), + .csb0 (mem_cen_a[0]), + .web0 (mem_web_a[0]), + .wmask0 (mem0_mask_a), + .addr0 (mem0_addr_a), + .din0 (mem0_din_a), + .dout0 (mem0_dout_a), +// Port 1: R + .clk1 (mem_clk_b[0]), + .csb1 (mem_cen_b[0]), + .addr1 (mem0_addr_b), + .dout1 () + ); + sky130_sram_2kbyte_1rw1r_32x512_8 u_sram1_2kb( `ifdef USE_POWER_PINS .vccd1 (vccd1),// User area 1 1.8V supply .vssd1 (vssd1),// User area 1 digital ground `endif // Port 0: RW - .clk0 (mem1_clk_b), - .csb0 (mem1_cen_b), - .web0 (mem1_web_b), - .wmask0 (mem1_mask_b), - .addr0 (mem1_addr_b), - .din0 (mem1_din_b), - .dout0 (), + .clk0 (mem_clk_a[1]), + .csb0 (mem_cen_a[1]), + .web0 (mem_web_a[1]), + .wmask0 (mem1_mask_a), + .addr0 (mem1_addr_a), + .din0 (mem1_din_a), + .dout0 (mem1_dout_a), // Port 1: R - .clk1 (mem1_clk_a), - .csb1 (mem1_cen_a), - .addr1 (mem1_addr_a), - .dout1 (mem1_dout_a) + .clk1 (mem_clk_b[1]), + .csb1 (mem_cen_b[1]), + .addr1 (mem1_addr_b), + .dout1 () ); -//------------- MBIST2 - 512x32 ---- - -mbist_top1 #( - `ifndef SYNTHESIS - .BIST_ADDR_WD (BIST1_ADDR_WD-2 ), - .BIST_DATA_WD (BIST_DATA_WD ), - .BIST_ADDR_START (9'h000 ), - .BIST_ADDR_END (9'h1FB ), - .BIST_REPAIR_ADDR_START (9'h1FC ), - .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST1_ADDR_WD-2 ) - `endif - ) - u_mbist2 ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - - // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist2_rp), - .cfg_cska_mbist (cfg_cska_mbist2_rp), - .wbd_clk_mbist (wbd_clk_mbist2_skew), - - // WB I/F - .wb_clk_i (wbd_clk_mbist2_skew), - .wb_cyc_i (wbd_mbist2_cyc_o), - .wb_stb_i (wbd_mbist2_stb_o), - .wb_adr_i (wbd_mbist2_adr_o[BIST1_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist2_we_o ), - .wb_dat_i (wbd_mbist2_dat_o), - .wb_sel_i (wbd_mbist2_sel_o), - .wb_dat_o (wbd_mbist2_dat_i), - .wb_ack_o (wbd_mbist2_ack_i), - .wb_err_o ( ), - - .rst_n (bist_rst_n ), - - - .bist_en (bist_en_rp[1] ), - .bist_run (bist_run_rp[1] ), - .bist_shift (bist_shift_rp[1] ), - .bist_load (bist_load_rp[1] ), - .bist_sdi (bist_sdi_rp[1] ), - - .bist_error_cnt (bist_error_cnt1 ), - .bist_correct (bist_correct[1] ), - .bist_error (bist_error[1] ), - .bist_done (bist_done[1] ), - .bist_sdo (bist_sdo[1] ), - - // towards memory - // PORT-A - .mem_clk_a (mem2_clk_a ), - .mem_addr_a (mem2_addr_a ), - .mem_cen_a (mem2_cen_a ), - .mem_dout_a (mem2_dout_a ), - // PORT-B - .mem_clk_b (mem2_clk_b ), - .mem_cen_b (mem2_cen_b ), - .mem_web_b (mem2_web_b ), - .mem_mask_b (mem2_mask_b ), - .mem_addr_b (mem2_addr_b ), - .mem_din_b (mem2_din_b ) - - -); - sky130_sram_2kbyte_1rw1r_32x512_8 u_sram2_2kb( `ifdef USE_POWER_PINS .vccd1 (vccd1),// User area 1 1.8V supply .vssd1 (vssd1),// User area 1 digital ground `endif // Port 0: RW - .clk0 (mem2_clk_b), - .csb0 (mem2_cen_b), - .web0 (mem2_web_b), - .wmask0 (mem2_mask_b), - .addr0 (mem2_addr_b), - .din0 (mem2_din_b), - .dout0 (), + .clk0 (mem_clk_a[2]), + .csb0 (mem_cen_a[2]), + .web0 (mem_web_a[2]), + .wmask0 (mem2_mask_a), + .addr0 (mem2_addr_a), + .din0 (mem2_din_a), + .dout0 (mem2_dout_a), // Port 1: R - .clk1 (mem2_clk_a), - .csb1 (mem2_cen_a), - .addr1 (mem2_addr_a), - .dout1 (mem2_dout_a) + .clk1 (mem_clk_b[2]), + .csb1 (mem_cen_b[2]), + .addr1 (mem2_addr_b), + .dout1 () ); - -//------------- MBIST3 - 512x32 ---- - -mbist_top1 #( - `ifndef SYNTHESIS - .BIST_ADDR_WD (BIST1_ADDR_WD-2 ), - .BIST_DATA_WD (BIST_DATA_WD ), - .BIST_ADDR_START (9'h000 ), - .BIST_ADDR_END (9'h1FB ), - .BIST_REPAIR_ADDR_START (9'h1FC ), - .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST1_ADDR_WD-2 ) - `endif - ) - u_mbist3 ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - - // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist3_rp), - .cfg_cska_mbist (cfg_cska_mbist3_rp), - .wbd_clk_mbist (wbd_clk_mbist3_skew), - - // WB I/F - .wb_clk_i (wbd_clk_mbist3_skew), - .wb_cyc_i (wbd_mbist3_cyc_o), - .wb_stb_i (wbd_mbist3_stb_o), - .wb_adr_i (wbd_mbist3_adr_o[BIST1_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist3_we_o ), - .wb_dat_i (wbd_mbist3_dat_o), - .wb_sel_i (wbd_mbist3_sel_o), - .wb_dat_o (wbd_mbist3_dat_i), - .wb_ack_o (wbd_mbist3_ack_i), - .wb_err_o ( ), - - .rst_n (bist_rst_n ), - - - .bist_en (bist_en_rp[2] ), - .bist_run (bist_run_rp[2] ), - .bist_shift (bist_shift_rp[2] ), - .bist_load (bist_load_rp[2] ), - .bist_sdi (bist_sdi_rp[2] ), - - .bist_error_cnt (bist_error_cnt2 ), - .bist_correct (bist_correct[2] ), - .bist_error (bist_error[2] ), - .bist_done (bist_done[2] ), - .bist_sdo (bist_sdo[2] ), - - // towards memory - // PORT-A - .mem_clk_a (mem3_clk_a ), - .mem_addr_a (mem3_addr_a ), - .mem_cen_a (mem3_cen_a ), - .mem_dout_a (mem3_dout_a ), - // PORT-B - .mem_clk_b (mem3_clk_b ), - .mem_cen_b (mem3_cen_b ), - .mem_web_b (mem3_web_b ), - .mem_mask_b (mem3_mask_b ), - .mem_addr_b (mem3_addr_b ), - .mem_din_b (mem3_din_b ) - - -); sky130_sram_2kbyte_1rw1r_32x512_8 u_sram3_2kb( `ifdef USE_POWER_PINS @@ -1510,106 +1338,18 @@ .vssd1 (vssd1),// User area 1 digital ground `endif // Port 0: RW - .clk0 (mem3_clk_b), - .csb0 (mem3_cen_b), - .web0 (mem3_web_b), - .wmask0 (mem3_mask_b), - .addr0 (mem3_addr_b), - .din0 (mem3_din_b), - .dout0 (), + .clk0 (mem_clk_a[3]), + .csb0 (mem_cen_a[3]), + .web0 (mem_web_a[3]), + .wmask0 (mem3_mask_a), + .addr0 (mem3_addr_a), + .din0 (mem3_din_a), + .dout0 (mem3_dout_a), // Port 1: R - .clk1 (mem3_clk_a), - .csb1 (mem3_cen_a), - .addr1 (mem3_addr_a), - .dout1 (mem3_dout_a) - ); - -//------------- MBIST4 - 512x32 ---- - -mbist_top1 #( - `ifndef SYNTHESIS - .BIST_ADDR_WD (BIST1_ADDR_WD-2 ), - .BIST_DATA_WD (BIST_DATA_WD ), - .BIST_ADDR_START (9'h000 ), - .BIST_ADDR_END (9'h1FB ), - .BIST_REPAIR_ADDR_START (9'h1FC ), - .BIST_RAD_WD_I (BIST1_ADDR_WD-2 ), - .BIST_RAD_WD_O (BIST1_ADDR_WD-2 ) - `endif - ) - u_mbist4 ( -`ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground -`endif - - // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist4_rp), - .cfg_cska_mbist (cfg_cska_mbist4_rp), - .wbd_clk_mbist (wbd_clk_mbist4_skew), - - // WB I/F - .wb_clk_i (wbd_clk_mbist4_skew), - .wb_cyc_i (wbd_mbist4_cyc_o), - .wb_stb_i (wbd_mbist4_stb_o), - .wb_adr_i (wbd_mbist4_adr_o[BIST1_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist4_we_o ), - .wb_dat_i (wbd_mbist4_dat_o), - .wb_sel_i (wbd_mbist4_sel_o), - .wb_dat_o (wbd_mbist4_dat_i), - .wb_ack_o (wbd_mbist4_ack_i), - .wb_err_o ( ), - - .rst_n (bist_rst_n ), - - - .bist_en (bist_en_rp[3] ), - .bist_run (bist_run_rp[3] ), - .bist_shift (bist_shift_rp[3] ), - .bist_load (bist_load_rp[3] ), - .bist_sdi (bist_sdi_rp[3] ), - - .bist_error_cnt (bist_error_cnt3 ), - .bist_correct (bist_correct[3] ), - .bist_error (bist_error[3] ), - .bist_done (bist_done[3] ), - .bist_sdo (bist_sdo[3] ), - - // towards memory - // PORT-A - .mem_clk_a (mem4_clk_a ), - .mem_addr_a (mem4_addr_a ), - .mem_cen_a (mem4_cen_a ), - .mem_dout_a (mem4_dout_a ), - // PORT-B - .mem_clk_b (mem4_clk_b ), - .mem_cen_b (mem4_cen_b ), - .mem_web_b (mem4_web_b ), - .mem_mask_b (mem4_mask_b ), - .mem_addr_b (mem4_addr_b ), - .mem_din_b (mem4_din_b ) - - -); - -sky130_sram_2kbyte_1rw1r_32x512_8 u_sram4_2kb( -`ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground -`endif -// Port 0: RW - .clk0 (mem4_clk_b), - .csb0 (mem4_cen_b), - .web0 (mem4_web_b), - .wmask0 (mem4_mask_b), - .addr0 (mem4_addr_b), - .din0 (mem4_din_b), - .dout0 (), -// Port 1: R - .clk1 (mem4_clk_a), - .csb1 (mem4_cen_a), - .addr1 (mem4_addr_a), - .dout1 (mem4_dout_a) + .clk1 (mem_clk_b[3]), + .csb1 (mem_cen_b[3]), + .addr1 (mem3_addr_b), + .dout1 () ); /***
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index ebd1fcd..51e4beb 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -64,6 +64,8 @@ //// removed //// //// Memory remap added to move the RISC Program memory //// //// to SRAM Memory //// +//// 0.9 - 15 Dec 2021, Dinesh A //// +//// Consolidated 4 MBIST port into one 8KB Port //// //// //// ////////////////////////////////////////////////////////////////////// //// //// @@ -194,47 +196,11 @@ input logic s3_wbd_ack_i, // input logic s3_wbd_err_i, output logic [31:0] s3_wbd_dat_o, - output logic [10:0] s3_wbd_adr_o, + output logic [12:0] s3_wbd_adr_o, output logic [3:0] s3_wbd_sel_o, output logic s3_wbd_we_o, output logic s3_wbd_cyc_o, - output logic s3_wbd_stb_o, - - // Slave 4 Interface - // MBIST2 - input logic [31:0] s4_wbd_dat_i, - input logic s4_wbd_ack_i, - // input logic s4_wbd_err_i, - output logic [31:0] s4_wbd_dat_o, - output logic [10:0] s4_wbd_adr_o, - output logic [3:0] s4_wbd_sel_o, - output logic s4_wbd_we_o, - output logic s4_wbd_cyc_o, - output logic s4_wbd_stb_o, - - // Slave 5 Interface - // MBIST3 - input logic [31:0] s5_wbd_dat_i, - input logic s5_wbd_ack_i, - // input logic s5_wbd_err_i, - output logic [31:0] s5_wbd_dat_o, - output logic [10:0] s5_wbd_adr_o, - output logic [3:0] s5_wbd_sel_o, - output logic s5_wbd_we_o, - output logic s5_wbd_cyc_o, - output logic s5_wbd_stb_o, - - // Slave 6 Interface - // MBIST4 - input logic [31:0] s6_wbd_dat_i, - input logic s6_wbd_ack_i, - // input logic s6_wbd_err_i, - output logic [31:0] s6_wbd_dat_o, - output logic [10:0] s6_wbd_adr_o, - output logic [3:0] s6_wbd_sel_o, - output logic s6_wbd_we_o, - output logic s6_wbd_cyc_o, - output logic s6_wbd_stb_o + output logic s3_wbd_stb_o ); //////////////////////////////////////////////////////////////////// @@ -246,10 +212,7 @@ parameter TARGET_SPI_REG = 4'b0000; parameter TARGET_UART = 4'b0001; parameter TARGET_PINMUX = 4'b0010; -parameter TARGET_MBIST1 = 4'b0011; -parameter TARGET_MBIST2 = 4'b0100; -parameter TARGET_MBIST3 = 4'b0101; -parameter TARGET_MBIST4 = 4'b0110; +parameter TARGET_MBIST = 4'b0011; // WishBone Wr Interface typedef struct packed { @@ -285,18 +248,12 @@ type_wb_wr_intf s1_wb_wr; type_wb_wr_intf s2_wb_wr; type_wb_wr_intf s3_wb_wr; -type_wb_wr_intf s4_wb_wr; -type_wb_wr_intf s5_wb_wr; -type_wb_wr_intf s6_wb_wr; // Slave Read Interface type_wb_rd_intf s0_wb_rd; type_wb_rd_intf s1_wb_rd; type_wb_rd_intf s2_wb_rd; type_wb_rd_intf s3_wb_rd; -type_wb_rd_intf s4_wb_rd; -type_wb_rd_intf s5_wb_rd; -type_wb_rd_intf s6_wb_rd; type_wb_wr_intf m_bus_wr; // Multiplexed Master I/F @@ -330,10 +287,7 @@ // 0x1001_0080 to 0x1001_00BF - USB // 0x1001_00C0 to 0x1001_00FF - SSPIM // 0x1002_0000 to 0x1002_00FF - PINMUX -// 0x1003_0000 to 0x1003_07FF - MBIST1 -// 0x1004_0000 to 0x1004_07FF - MBIST2 -// 0x1005_0000 to 0x1005_07FF - MBIST3 -// 0x1006_0000 to 0x1006_07FF - MBIST4 +// 0x1003_0000 to 0x1003_1FFF - MBIST // 0x3080_0000 to 0x3080_00FF - WB HOST (This decoding happens at wb_host block) // --------------------------------------------------------------------------- // @@ -341,10 +295,7 @@ (m0_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG : // SPI REG (m0_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : // UART/I2C/USB/SPI (m0_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : // PINMUX - (m0_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST1 : // MBIST1 - (m0_wbd_adr_i[31:16] == 16'h1004 ) ? TARGET_MBIST2 : // MBIST2 - (m0_wbd_adr_i[31:16] == 16'h1005 ) ? TARGET_MBIST3 : // MBIST3 - (m0_wbd_adr_i[31:16] == 16'h1006 ) ? TARGET_MBIST4 : // MBIST4 + (m0_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST : // MBIST 4'b0000; //------------------------------ @@ -356,38 +307,29 @@ // 0x1001_0080 to 0x1001_00BF - USB // 0x1001_00C0 to 0x1001_00FF - SSPIM // 0x1002_0000 to 0x1002_00FF - PINMUX -// 0x1003_0000 to 0x1003_07FF - MBIST1 -// 0x1004_0000 to 0x1004_07FF - MBIST2 -// 0x1005_0000 to 0x1005_07FF - MBIST3 -// 0x1006_0000 to 0x1006_07FF - MBIST4 +// 0x1003_0000 to 0x1003_1FFF - MBIST //----------------------------- // -wire [3:0] m1_wbd_tid_i = (boot_remap[0] && m1_wbd_adr_i[31:11] == 21'h0) ? TARGET_MBIST1: - (boot_remap[1] && m1_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST2: - (boot_remap[2] && m1_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST3: - (boot_remap[3] && m1_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST4: +wire [3:0] m1_wbd_tid_i = (boot_remap[0] && m1_wbd_adr_i[31:11] == 21'h0) ? TARGET_MBIST: + (boot_remap[1] && m1_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST: + (boot_remap[2] && m1_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST: + (boot_remap[3] && m1_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST: (m1_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : (m1_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG : (m1_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : (m1_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : - (m1_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST1 : - (m1_wbd_adr_i[31:16] == 16'h1004 ) ? TARGET_MBIST2 : - (m1_wbd_adr_i[31:16] == 16'h1005 ) ? TARGET_MBIST3 : - (m1_wbd_adr_i[31:16] == 16'h1006 ) ? TARGET_MBIST4 : + (m1_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST : 4'b0000; -wire [3:0] m2_wbd_tid_i = (boot_remap[0] && m2_wbd_adr_i[31:11] == 21'h0) ? TARGET_MBIST1: - (boot_remap[1] && m2_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST2: - (boot_remap[2] && m2_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST3: - (boot_remap[3] && m2_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST4: +wire [3:0] m2_wbd_tid_i = (boot_remap[0] && m2_wbd_adr_i[31:11] == 21'h0) ? TARGET_MBIST: + (boot_remap[1] && m2_wbd_adr_i[31:11] == 21'h1) ? TARGET_MBIST: + (boot_remap[2] && m2_wbd_adr_i[31:11] == 21'h2) ? TARGET_MBIST: + (boot_remap[3] && m2_wbd_adr_i[31:11] == 21'h3) ? TARGET_MBIST: (m2_wbd_adr_i[31:28] == 4'b0000 ) ? TARGET_SPI_MEM : (m2_wbd_adr_i[31:16] == 16'h1000 ) ? TARGET_SPI_REG : (m2_wbd_adr_i[31:16] == 16'h1001 ) ? TARGET_UART : (m2_wbd_adr_i[31:16] == 16'h1002 ) ? TARGET_PINMUX : - (m2_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST1 : - (m2_wbd_adr_i[31:16] == 16'h1004 ) ? TARGET_MBIST2 : - (m2_wbd_adr_i[31:16] == 16'h1005 ) ? TARGET_MBIST3 : - (m2_wbd_adr_i[31:16] == 16'h1006 ) ? TARGET_MBIST4 : + (m2_wbd_adr_i[31:16] == 16'h1003 ) ? TARGET_MBIST : 4'b0000; //---------------------------------------- // Master Mapping @@ -454,32 +396,12 @@ assign s2_wbd_stb_o = s2_wb_wr.wbd_stb ; assign s3_wbd_dat_o = s3_wb_wr.wbd_dat[31:0] ; - assign s3_wbd_adr_o = s3_wb_wr.wbd_adr[10:0] ; // MBIST Need 11 bit + assign s3_wbd_adr_o = s3_wb_wr.wbd_adr[12:0] ; // MBIST Need 13 bit assign s3_wbd_sel_o = s3_wb_wr.wbd_sel[3:0] ; assign s3_wbd_we_o = s3_wb_wr.wbd_we ; assign s3_wbd_cyc_o = s3_wb_wr.wbd_cyc ; assign s3_wbd_stb_o = s3_wb_wr.wbd_stb ; - assign s4_wbd_dat_o = s4_wb_wr.wbd_dat[31:0] ; - assign s4_wbd_adr_o = s4_wb_wr.wbd_adr[10:0] ; // MBIST Need 11 bit - assign s4_wbd_sel_o = s4_wb_wr.wbd_sel[3:0] ; - assign s4_wbd_we_o = s4_wb_wr.wbd_we ; - assign s4_wbd_cyc_o = s4_wb_wr.wbd_cyc ; - assign s4_wbd_stb_o = s4_wb_wr.wbd_stb ; - - assign s5_wbd_dat_o = s5_wb_wr.wbd_dat[31:0] ; - assign s5_wbd_adr_o = s5_wb_wr.wbd_adr[10:0] ; // MBIST Need 11 bit - assign s5_wbd_sel_o = s5_wb_wr.wbd_sel[3:0] ; - assign s5_wbd_we_o = s5_wb_wr.wbd_we ; - assign s5_wbd_cyc_o = s5_wb_wr.wbd_cyc ; - assign s5_wbd_stb_o = s5_wb_wr.wbd_stb ; - - assign s6_wbd_dat_o = s6_wb_wr.wbd_dat[31:0] ; - assign s6_wbd_adr_o = s6_wb_wr.wbd_adr[10:0] ; // MBIST Need 11 bit - assign s6_wbd_sel_o = s6_wb_wr.wbd_sel[3:0] ; - assign s6_wbd_we_o = s6_wb_wr.wbd_we ; - assign s6_wbd_cyc_o = s6_wb_wr.wbd_cyc ; - assign s6_wbd_stb_o = s6_wb_wr.wbd_stb ; assign s0_wb_rd.wbd_dat = s0_wbd_dat_i ; assign s0_wb_rd.wbd_ack = s0_wbd_ack_i ; @@ -497,17 +419,6 @@ assign s3_wb_rd.wbd_ack = s3_wbd_ack_i ; assign s3_wb_rd.wbd_err = 1'b0; // s3_wbd_err_i ; - unused - assign s4_wb_rd.wbd_dat = s4_wbd_dat_i ; - assign s4_wb_rd.wbd_ack = s4_wbd_ack_i ; - assign s4_wb_rd.wbd_err = 1'b0; // s4_wbd_err_i ; - unused - - assign s5_wb_rd.wbd_dat = s5_wbd_dat_i ; - assign s5_wb_rd.wbd_ack = s5_wbd_ack_i ; - assign s5_wb_rd.wbd_err = 1'b0; // s5_wbd_err_i ; - unused - - assign s6_wb_rd.wbd_dat = s6_wbd_dat_i ; - assign s6_wb_rd.wbd_ack = s6_wbd_ack_i ; - assign s6_wb_rd.wbd_err = 1'b0; // s6_wbd_err_i ; - unused // // arbitor // @@ -542,9 +453,6 @@ 4'h1: s_bus_rd = s1_wb_rd; 4'h2: s_bus_rd = s2_wb_rd; 4'h3: s_bus_rd = s3_wb_rd; - 4'h4: s_bus_rd = s4_wb_rd; - 4'h5: s_bus_rd = s5_wb_rd; - 4'h6: s_bus_rd = s6_wb_rd; default: s_bus_rd = s0_wb_rd; endcase end @@ -555,9 +463,6 @@ assign s1_wb_wr = (s_wbd_tid == 3'b001) ? s_bus_wr : 'h0; assign s2_wb_wr = (s_wbd_tid == 3'b010) ? s_bus_wr : 'h0; assign s3_wb_wr = (s_wbd_tid == 3'b011) ? s_bus_wr : 'h0; -assign s4_wb_wr = (s_wbd_tid == 3'b100) ? s_bus_wr : 'h0; -assign s5_wb_wr = (s_wbd_tid == 3'b101) ? s_bus_wr : 'h0; -assign s6_wb_wr = (s_wbd_tid == 3'b110) ? s_bus_wr : 'h0; // Connect Slave to Master assign m0_wb_rd = (gnt == 2'b00) ? m_bus_rd : 'h0;