#BUS_SORT | |
#MANUAL_PLACE | |
#E | |
core_clk 0000 0 | |
rtc_clk | |
cpu_rst_n | |
#W | |
wb_clk 0000 0 | |
wb_rst_n | |
pwrup_rst_n | |
rst_n | |
#N | |
wbd_imem_stb_o 0000 0 | |
wbd_imem_we_o | |
wbd_imem_adr_o\[31\] | |
wbd_imem_adr_o\[30\] | |
wbd_imem_adr_o\[29\] | |
wbd_imem_adr_o\[28\] | |
wbd_imem_adr_o\[27\] | |
wbd_imem_adr_o\[26\] | |
wbd_imem_adr_o\[25\] | |
wbd_imem_adr_o\[24\] | |
wbd_imem_adr_o\[23\] | |
wbd_imem_adr_o\[22\] | |
wbd_imem_adr_o\[21\] | |
wbd_imem_adr_o\[20\] | |
wbd_imem_adr_o\[19\] | |
wbd_imem_adr_o\[18\] | |
wbd_imem_adr_o\[17\] | |
wbd_imem_adr_o\[16\] | |
wbd_imem_adr_o\[15\] | |
wbd_imem_adr_o\[14\] | |
wbd_imem_adr_o\[13\] | |
wbd_imem_adr_o\[12\] | |
wbd_imem_adr_o\[11\] | |
wbd_imem_adr_o\[10\] | |
wbd_imem_adr_o\[9\] | |
wbd_imem_adr_o\[8\] | |
wbd_imem_adr_o\[7\] | |
wbd_imem_adr_o\[6\] | |
wbd_imem_adr_o\[5\] | |
wbd_imem_adr_o\[4\] | |
wbd_imem_adr_o\[3\] | |
wbd_imem_adr_o\[2\] | |
wbd_imem_adr_o\[1\] | |
wbd_imem_adr_o\[0\] | |
wbd_imem_sel_o\[3\] | |
wbd_imem_sel_o\[2\] | |
wbd_imem_sel_o\[1\] | |
wbd_imem_sel_o\[0\] | |
wbd_imem_dat_o\[31\] | |
wbd_imem_dat_o\[30\] | |
wbd_imem_dat_o\[29\] | |
wbd_imem_dat_o\[28\] | |
wbd_imem_dat_o\[27\] | |
wbd_imem_dat_o\[26\] | |
wbd_imem_dat_o\[25\] | |
wbd_imem_dat_o\[24\] | |
wbd_imem_dat_o\[23\] | |
wbd_imem_dat_o\[22\] | |
wbd_imem_dat_o\[21\] | |
wbd_imem_dat_o\[20\] | |
wbd_imem_dat_o\[19\] | |
wbd_imem_dat_o\[18\] | |
wbd_imem_dat_o\[17\] | |
wbd_imem_dat_o\[16\] | |
wbd_imem_dat_o\[15\] | |
wbd_imem_dat_o\[14\] | |
wbd_imem_dat_o\[13\] | |
wbd_imem_dat_o\[12\] | |
wbd_imem_dat_o\[11\] | |
wbd_imem_dat_o\[10\] | |
wbd_imem_dat_o\[9\] | |
wbd_imem_dat_o\[8\] | |
wbd_imem_dat_o\[7\] | |
wbd_imem_dat_o\[6\] | |
wbd_imem_dat_o\[5\] | |
wbd_imem_dat_o\[4\] | |
wbd_imem_dat_o\[3\] | |
wbd_imem_dat_o\[2\] | |
wbd_imem_dat_o\[1\] | |
wbd_imem_dat_o\[0\] | |
wbd_imem_dat_i\[31\] | |
wbd_imem_dat_i\[30\] | |
wbd_imem_dat_i\[29\] | |
wbd_imem_dat_i\[28\] | |
wbd_imem_dat_i\[27\] | |
wbd_imem_dat_i\[26\] | |
wbd_imem_dat_i\[25\] | |
wbd_imem_dat_i\[24\] | |
wbd_imem_dat_i\[23\] | |
wbd_imem_dat_i\[22\] | |
wbd_imem_dat_i\[21\] | |
wbd_imem_dat_i\[20\] | |
wbd_imem_dat_i\[19\] | |
wbd_imem_dat_i\[18\] | |
wbd_imem_dat_i\[17\] | |
wbd_imem_dat_i\[16\] | |
wbd_imem_dat_i\[15\] | |
wbd_imem_dat_i\[14\] | |
wbd_imem_dat_i\[13\] | |
wbd_imem_dat_i\[12\] | |
wbd_imem_dat_i\[11\] | |
wbd_imem_dat_i\[10\] | |
wbd_imem_dat_i\[9\] | |
wbd_imem_dat_i\[8\] | |
wbd_imem_dat_i\[7\] | |
wbd_imem_dat_i\[6\] | |
wbd_imem_dat_i\[5\] | |
wbd_imem_dat_i\[4\] | |
wbd_imem_dat_i\[3\] | |
wbd_imem_dat_i\[2\] | |
wbd_imem_dat_i\[1\] | |
wbd_imem_dat_i\[0\] | |
wbd_imem_ack_i | |
wbd_imem_err_i | |
wbd_dmem_stb_o 0500 0 2 | |
wbd_dmem_we_o | |
wbd_dmem_adr_o\[31\] | |
wbd_dmem_adr_o\[30\] | |
wbd_dmem_adr_o\[29\] | |
wbd_dmem_adr_o\[28\] | |
wbd_dmem_adr_o\[27\] | |
wbd_dmem_adr_o\[26\] | |
wbd_dmem_adr_o\[25\] | |
wbd_dmem_adr_o\[24\] | |
wbd_dmem_adr_o\[23\] | |
wbd_dmem_adr_o\[22\] | |
wbd_dmem_adr_o\[21\] | |
wbd_dmem_adr_o\[20\] | |
wbd_dmem_adr_o\[19\] | |
wbd_dmem_adr_o\[18\] | |
wbd_dmem_adr_o\[17\] | |
wbd_dmem_adr_o\[16\] | |
wbd_dmem_adr_o\[15\] | |
wbd_dmem_adr_o\[14\] | |
wbd_dmem_adr_o\[13\] | |
wbd_dmem_adr_o\[12\] | |
wbd_dmem_adr_o\[11\] | |
wbd_dmem_adr_o\[10\] | |
wbd_dmem_adr_o\[9\] | |
wbd_dmem_adr_o\[8\] | |
wbd_dmem_adr_o\[7\] | |
wbd_dmem_adr_o\[6\] | |
wbd_dmem_adr_o\[5\] | |
wbd_dmem_adr_o\[4\] | |
wbd_dmem_adr_o\[3\] | |
wbd_dmem_adr_o\[2\] | |
wbd_dmem_adr_o\[1\] | |
wbd_dmem_adr_o\[0\] | |
wbd_dmem_sel_o\[3\] | |
wbd_dmem_sel_o\[2\] | |
wbd_dmem_sel_o\[1\] | |
wbd_dmem_sel_o\[0\] | |
wbd_dmem_dat_o\[31\] | |
wbd_dmem_dat_o\[30\] | |
wbd_dmem_dat_o\[29\] | |
wbd_dmem_dat_o\[28\] | |
wbd_dmem_dat_o\[27\] | |
wbd_dmem_dat_o\[26\] | |
wbd_dmem_dat_o\[25\] | |
wbd_dmem_dat_o\[24\] | |
wbd_dmem_dat_o\[23\] | |
wbd_dmem_dat_o\[22\] | |
wbd_dmem_dat_o\[21\] | |
wbd_dmem_dat_o\[20\] | |
wbd_dmem_dat_o\[19\] | |
wbd_dmem_dat_o\[18\] | |
wbd_dmem_dat_o\[17\] | |
wbd_dmem_dat_o\[16\] | |
wbd_dmem_dat_o\[15\] | |
wbd_dmem_dat_o\[14\] | |
wbd_dmem_dat_o\[13\] | |
wbd_dmem_dat_o\[12\] | |
wbd_dmem_dat_o\[11\] | |
wbd_dmem_dat_o\[10\] | |
wbd_dmem_dat_o\[9\] | |
wbd_dmem_dat_o\[8\] | |
wbd_dmem_dat_o\[7\] | |
wbd_dmem_dat_o\[6\] | |
wbd_dmem_dat_o\[5\] | |
wbd_dmem_dat_o\[4\] | |
wbd_dmem_dat_o\[3\] | |
wbd_dmem_dat_o\[2\] | |
wbd_dmem_dat_o\[1\] | |
wbd_dmem_dat_o\[0\] | |
wbd_dmem_dat_i\[31\] | |
wbd_dmem_dat_i\[30\] | |
wbd_dmem_dat_i\[29\] | |
wbd_dmem_dat_i\[28\] | |
wbd_dmem_dat_i\[27\] | |
wbd_dmem_dat_i\[26\] | |
wbd_dmem_dat_i\[25\] | |
wbd_dmem_dat_i\[24\] | |
wbd_dmem_dat_i\[23\] | |
wbd_dmem_dat_i\[22\] | |
wbd_dmem_dat_i\[21\] | |
wbd_dmem_dat_i\[20\] | |
wbd_dmem_dat_i\[19\] | |
wbd_dmem_dat_i\[18\] | |
wbd_dmem_dat_i\[17\] | |
wbd_dmem_dat_i\[16\] | |
wbd_dmem_dat_i\[15\] | |
wbd_dmem_dat_i\[14\] | |
wbd_dmem_dat_i\[13\] | |
wbd_dmem_dat_i\[12\] | |
wbd_dmem_dat_i\[11\] | |
wbd_dmem_dat_i\[10\] | |
wbd_dmem_dat_i\[9\] | |
wbd_dmem_dat_i\[8\] | |
wbd_dmem_dat_i\[7\] | |
wbd_dmem_dat_i\[6\] | |
wbd_dmem_dat_i\[5\] | |
wbd_dmem_dat_i\[4\] | |
wbd_dmem_dat_i\[3\] | |
wbd_dmem_dat_i\[2\] | |
wbd_dmem_dat_i\[1\] | |
wbd_dmem_dat_i\[0\] | |
wbd_dmem_ack_i | |
wbd_dmem_err_i | |
irq_lines\[15\] 1200 0 2 | |
irq_lines\[14\] | |
irq_lines\[13\] | |
irq_lines\[12\] | |
irq_lines\[11\] | |
irq_lines\[10\] | |
irq_lines\[9\] | |
irq_lines\[8\] | |
irq_lines\[7\] | |
irq_lines\[6\] | |
irq_lines\[5\] | |
irq_lines\[4\] | |
irq_lines\[3\] | |
irq_lines\[2\] | |
irq_lines\[1\] | |
irq_lines\[0\] | |
soft_irq | |
fuse_mhartid\[31\] | |
fuse_mhartid\[30\] | |
fuse_mhartid\[29\] | |
fuse_mhartid\[28\] | |
fuse_mhartid\[27\] | |
fuse_mhartid\[26\] | |
fuse_mhartid\[25\] | |
fuse_mhartid\[24\] | |
fuse_mhartid\[23\] | |
fuse_mhartid\[22\] | |
fuse_mhartid\[21\] | |
fuse_mhartid\[20\] | |
fuse_mhartid\[19\] | |
fuse_mhartid\[18\] | |
fuse_mhartid\[17\] | |
fuse_mhartid\[16\] | |
fuse_mhartid\[15\] | |
fuse_mhartid\[14\] | |
fuse_mhartid\[13\] | |
fuse_mhartid\[12\] | |
fuse_mhartid\[11\] | |
fuse_mhartid\[10\] | |
fuse_mhartid\[9\] | |
fuse_mhartid\[8\] | |
fuse_mhartid\[7\] | |
fuse_mhartid\[6\] | |
fuse_mhartid\[5\] | |
fuse_mhartid\[4\] | |
fuse_mhartid\[3\] | |
fuse_mhartid\[2\] | |
fuse_mhartid\[1\] | |
fuse_mhartid\[0\] | |
#S | |
riscv_debug\[0\] 500 0 4 | |
riscv_debug\[1\] | |
riscv_debug\[2\] | |
riscv_debug\[3\] | |
riscv_debug\[4\] | |
riscv_debug\[5\] | |
riscv_debug\[6\] | |
riscv_debug\[7\] | |
riscv_debug\[8\] | |
riscv_debug\[9\] | |
riscv_debug\[10\] | |
riscv_debug\[11\] | |
riscv_debug\[12\] | |
riscv_debug\[13\] | |
riscv_debug\[14\] | |
riscv_debug\[15\] | |
riscv_debug\[16\] | |
riscv_debug\[17\] | |
riscv_debug\[18\] | |
riscv_debug\[19\] | |
riscv_debug\[20\] | |
riscv_debug\[21\] | |
riscv_debug\[22\] | |
riscv_debug\[23\] | |
riscv_debug\[24\] | |
riscv_debug\[25\] | |
riscv_debug\[26\] | |
riscv_debug\[27\] | |
riscv_debug\[28\] | |
riscv_debug\[29\] | |
riscv_debug\[30\] | |
riscv_debug\[31\] | |
riscv_debug\[32\] | |
riscv_debug\[33\] | |
riscv_debug\[34\] | |
riscv_debug\[35\] | |
riscv_debug\[36\] | |
riscv_debug\[37\] | |
riscv_debug\[38\] | |
riscv_debug\[39\] | |
riscv_debug\[40\] | |
riscv_debug\[41\] | |
riscv_debug\[42\] | |
riscv_debug\[43\] | |
riscv_debug\[44\] | |
riscv_debug\[45\] | |
riscv_debug\[46\] | |
riscv_debug\[47\] | |
riscv_debug\[48\] | |
riscv_debug\[49\] | |
riscv_debug\[50\] | |
riscv_debug\[51\] | |
riscv_debug\[52\] | |
riscv_debug\[53\] | |
riscv_debug\[54\] | |
riscv_debug\[55\] | |
riscv_debug\[56\] | |
riscv_debug\[57\] | |
riscv_debug\[58\] | |
riscv_debug\[59\] | |
riscv_debug\[60\] | |
riscv_debug\[61\] | |
riscv_debug\[62\] | |
riscv_debug\[63\] | |