#BUS_SORT | |
#MANUAL_PLACE | |
#N | |
reset_n 0000 0 | |
user_irq\[2\] | |
user_irq\[1\] | |
user_irq\[0\] | |
#W | |
sdr_init_done 0000 0 | |
cfg_sdr_width\[1] | |
cfg_sdr_width\[0] | |
cfg_colbits\[1\] | |
cfg_colbits\[0\] | |
cfg_sdr_tras_d\[3\] | |
cfg_sdr_tras_d\[2\] | |
cfg_sdr_tras_d\[1\] | |
cfg_sdr_tras_d\[0\] | |
cfg_sdr_trp_d\[3\] | |
cfg_sdr_trp_d\[2\] | |
cfg_sdr_trp_d\[1\] | |
cfg_sdr_trp_d\[0\] | |
cfg_sdr_trcd_d\[3\] | |
cfg_sdr_trcd_d\[2\] | |
cfg_sdr_trcd_d\[1\] | |
cfg_sdr_trcd_d\[0\] | |
cfg_sdr_en | |
cfg_req_depth\[1\] | |
cfg_req_depth\[0\] | |
cfg_sdr_mode_reg\[12\] | |
cfg_sdr_mode_reg\[11\] | |
cfg_sdr_mode_reg\[10\] | |
cfg_sdr_mode_reg\[9\] | |
cfg_sdr_mode_reg\[8\] | |
cfg_sdr_mode_reg\[7\] | |
cfg_sdr_mode_reg\[6\] | |
cfg_sdr_mode_reg\[5\] | |
cfg_sdr_mode_reg\[4\] | |
cfg_sdr_mode_reg\[3\] | |
cfg_sdr_mode_reg\[2\] | |
cfg_sdr_mode_reg\[1\] | |
cfg_sdr_mode_reg\[0\] | |
cfg_sdr_cas\[2\] | |
cfg_sdr_cas\[1\] | |
cfg_sdr_cas\[0\] | |
cfg_sdr_trcar_d\[3\] | |
cfg_sdr_trcar_d\[2\] | |
cfg_sdr_trcar_d\[1\] | |
cfg_sdr_trcar_d\[0\] | |
cfg_sdr_twr_d\[3\] | |
cfg_sdr_twr_d\[2\] | |
cfg_sdr_twr_d\[1\] | |
cfg_sdr_twr_d\[0\] | |
cfg_sdr_rfsh\[11\] | |
cfg_sdr_rfsh\[10\] | |
cfg_sdr_rfsh\[9\] | |
cfg_sdr_rfsh\[8\] | |
cfg_sdr_rfsh\[7\] | |
cfg_sdr_rfsh\[6\] | |
cfg_sdr_rfsh\[5\] | |
cfg_sdr_rfsh\[4\] | |
cfg_sdr_rfsh\[3\] | |
cfg_sdr_rfsh\[2\] | |
cfg_sdr_rfsh\[1\] | |
cfg_sdr_rfsh\[0\] | |
cfg_sdr_rfmax\[2\] | |
cfg_sdr_rfmax\[1\] | |
cfg_sdr_rfmax\[0\] | |
mclk 0150 0 | |
#S | |
reg_cs 0000 0 | |
reg_wr | |
reg_addr\[7\] | |
reg_addr\[6\] | |
reg_addr\[5\] | |
reg_addr\[4\] | |
reg_addr\[3\] | |
reg_addr\[2\] | |
reg_addr\[1\] | |
reg_addr\[0\] | |
reg_be\[3\] | |
reg_be\[2\] | |
reg_be\[1\] | |
reg_be\[0\] | |
reg_wdata\[31\] | |
reg_wdata\[30\] | |
reg_wdata\[29\] | |
reg_wdata\[28\] | |
reg_wdata\[27\] | |
reg_wdata\[26\] | |
reg_wdata\[25\] | |
reg_wdata\[24\] | |
reg_wdata\[23\] | |
reg_wdata\[22\] | |
reg_wdata\[21\] | |
reg_wdata\[20\] | |
reg_wdata\[19\] | |
reg_wdata\[18\] | |
reg_wdata\[17\] | |
reg_wdata\[16\] | |
reg_wdata\[15\] | |
reg_wdata\[14\] | |
reg_wdata\[13\] | |
reg_wdata\[12\] | |
reg_wdata\[11\] | |
reg_wdata\[10\] | |
reg_wdata\[9\] | |
reg_wdata\[8\] | |
reg_wdata\[7\] | |
reg_wdata\[6\] | |
reg_wdata\[5\] | |
reg_wdata\[4\] | |
reg_wdata\[3\] | |
reg_wdata\[2\] | |
reg_wdata\[1\] | |
reg_wdata\[0\] | |
reg_rdata\[31\] | |
reg_rdata\[30\] | |
reg_rdata\[29\] | |
reg_rdata\[28\] | |
reg_rdata\[27\] | |
reg_rdata\[26\] | |
reg_rdata\[25\] | |
reg_rdata\[24\] | |
reg_rdata\[23\] | |
reg_rdata\[22\] | |
reg_rdata\[21\] | |
reg_rdata\[20\] | |
reg_rdata\[19\] | |
reg_rdata\[18\] | |
reg_rdata\[17\] | |
reg_rdata\[16\] | |
reg_rdata\[15\] | |
reg_rdata\[14\] | |
reg_rdata\[13\] | |
reg_rdata\[12\] | |
reg_rdata\[11\] | |
reg_rdata\[10\] | |
reg_rdata\[9\] | |
reg_rdata\[8\] | |
reg_rdata\[7\] | |
reg_rdata\[6\] | |
reg_rdata\[5\] | |
reg_rdata\[4\] | |
reg_rdata\[3\] | |
reg_rdata\[2\] | |
reg_rdata\[1\] | |
reg_rdata\[0\] | |
reg_ack | |
irq_lines\[15\] 200 0 2 | |
irq_lines\[14\] | |
irq_lines\[13\] | |
irq_lines\[12\] | |
irq_lines\[11\] | |
irq_lines\[10\] | |
irq_lines\[9\] | |
irq_lines\[8\] | |
irq_lines\[7\] | |
irq_lines\[6\] | |
irq_lines\[5\] | |
irq_lines\[4\] | |
irq_lines\[3\] | |
irq_lines\[2\] | |
irq_lines\[1\] | |
irq_lines\[0\] | |
soft_irq | |
fuse_mhartid\[31\] | |
fuse_mhartid\[30\] | |
fuse_mhartid\[29\] | |
fuse_mhartid\[28\] | |
fuse_mhartid\[27\] | |
fuse_mhartid\[26\] | |
fuse_mhartid\[25\] | |
fuse_mhartid\[24\] | |
fuse_mhartid\[23\] | |
fuse_mhartid\[22\] | |
fuse_mhartid\[21\] | |
fuse_mhartid\[20\] | |
fuse_mhartid\[19\] | |
fuse_mhartid\[18\] | |
fuse_mhartid\[17\] | |
fuse_mhartid\[16\] | |
fuse_mhartid\[15\] | |
fuse_mhartid\[14\] | |
fuse_mhartid\[13\] | |
fuse_mhartid\[12\] | |
fuse_mhartid\[11\] | |
fuse_mhartid\[10\] | |
fuse_mhartid\[9\] | |
fuse_mhartid\[8\] | |
fuse_mhartid\[7\] | |
fuse_mhartid\[6\] | |
fuse_mhartid\[5\] | |
fuse_mhartid\[4\] | |
fuse_mhartid\[3\] | |
fuse_mhartid\[2\] | |
fuse_mhartid\[1\] | |
fuse_mhartid\[0\] | |