icache and dcache integration
diff --git a/.gitmodules b/.gitmodules index df69a25..9f8c7a0 100644 --- a/.gitmodules +++ b/.gitmodules
@@ -4,6 +4,6 @@ [submodule "verilog/rtl/qspim"] path = verilog/rtl/qspim url = https://github.com/dineshannayya/qspim.git -[submodule "verilog/rtl/yifive/ycr1c"] +[submodule "verilog/rtl/yifive/ycr1c1"] path = verilog/rtl/yifive/ycr1c url = https://github.com/dineshannayya/ycr1c.git
diff --git a/Makefile b/Makefile index ba40f56..f215afc 100644 --- a/Makefile +++ b/Makefile
@@ -25,11 +25,11 @@ ifeq ($(CARAVEL_LITE),1) CARAVEL_NAME := caravel-lite CARAVEL_REPO := https://github.com/efabless/caravel-lite - CARAVEL_BRANCH := main + CARAVEL_TAG := 'mpw-5a' else CARAVEL_NAME := caravel CARAVEL_REPO := https://github.com/efabless/caravel - CARAVEL_BRANCH := master + CARAVEL_TAG := 'mpw-5a' endif # Install caravel as submodule, (1): submodule, (0): clone @@ -96,8 +96,7 @@ $(MAKE) simlink else @echo "Installing $(CARAVEL_NAME).." - @git clone $(CARAVEL_REPO) $(CARAVEL_ROOT) - @cd $(CARAVEL_ROOT); git checkout $(CARAVEL_BRANCH) + @git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT) endif # Create symbolic links to caravel's main files @@ -116,30 +115,12 @@ # Update Caravel .PHONY: update_caravel update_caravel: check-caravel -ifeq ($(SUBMODULE),1) - @git submodule update --init --recursive - cd $(CARAVEL_ROOT) && \ - git checkout $(CARAVEL_BRANCH) && \ - git pull -else - cd $(CARAVEL_ROOT)/ && \ - git checkout $(CARAVEL_BRANCH) && \ - git pull -endif + cd $(CARAVEL_ROOT)/ && git checkout $(CARAVEL_TAG) && git pull # Uninstall Caravel .PHONY: uninstall uninstall: -ifeq ($(SUBMODULE),1) - git config -f .gitmodules --remove-section "submodule.$(CARAVEL_NAME)" - git add .gitmodules - git submodule deinit -f $(CARAVEL_ROOT) - git rm --cached $(CARAVEL_ROOT) - rm -rf .git/modules/$(CARAVEL_NAME) rm -rf $(CARAVEL_ROOT) -else - rm -rf $(CARAVEL_ROOT) -endif # Install Openlane .PHONY: openlane @@ -150,20 +131,15 @@ # Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>" .PHONY: precheck precheck: - @git clone https://github.com/efabless/mpw_precheck.git --depth=1 $(PRECHECK_ROOT) + @git clone --depth=1 --branch mpw-5 https://github.com/efabless/mpw_precheck.git $(PRECHECK_ROOT) @docker pull efabless/mpw_precheck:latest .PHONY: run-precheck run-precheck: check-precheck check-pdk check-caravel $(eval INPUT_DIRECTORY := $(shell pwd)) cd $(PRECHECK_ROOT) && \ - docker run -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \ - -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --pdk_root $(PDK_ROOT) --input_directory $(INPUT_DIRECTORY) --caravel_root $(CARAVEL_ROOT)" - -# Install PDK using OL's Docker Image -.PHONY: pdk-nonnative -pdk-nonnative: skywater-pdk skywater-library skywater-timing open_pdks - docker run --rm -v $(PDK_ROOT):$(PDK_ROOT) -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) -e CARAVEL_ROOT=$(CARAVEL_ROOT) -e PDK_ROOT=$(PDK_ROOT) -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/openlane:current sh -c "cd $(CARAVEL_ROOT); make build-pdk; make gen-sources" + docker run -e INPUT_DIRECTORY=$(INPUT_DIRECTORY) -e PDK_ROOT=$(PDK_ROOT) -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) -v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) -v $(PDK_ROOT):$(PDK_ROOT) \ + -u $(shell id -u $(USER)):$(shell id -g $(USER)) efabless/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --pdk_root $(PDK_ROOT) --input_directory $(INPUT_DIRECTORY)" # Clean .PHONY: clean
diff --git a/openlane/qspim/config.tcl b/openlane/qspim/config.tcl index d8f77f5..dd9596a 100755 --- a/openlane/qspim/config.tcl +++ b/openlane/qspim/config.tcl
@@ -71,7 +71,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 400 550" +set ::env(DIE_AREA) "0 0 450 550" set ::env(PL_TIME_DRIVEN) 1 set ::env(PL_TARGET_DENSITY) "0.42"
diff --git a/openlane/qspim/pin_order.cfg b/openlane/qspim/pin_order.cfg index 233a7ce..a0c3c37 100644 --- a/openlane/qspim/pin_order.cfg +++ b/openlane/qspim/pin_order.cfg
@@ -107,6 +107,17 @@ wbd_sel_i\[2\] wbd_sel_i\[1\] wbd_sel_i\[0\] +wbd_bl_i\[9\] +wbd_bl_i\[8\] +wbd_bl_i\[7\] +wbd_bl_i\[6\] +wbd_bl_i\[5\] +wbd_bl_i\[4\] +wbd_bl_i\[3\] +wbd_bl_i\[2\] +wbd_bl_i\[1\] +wbd_bl_i\[0\] +wbd_bry_i wbd_dat_i\[31\] wbd_dat_i\[30\] wbd_dat_i\[29\] @@ -172,4 +183,5 @@ wbd_dat_o\[1\] wbd_dat_o\[0\] wbd_ack_o +wbd_lack_o wbd_err_o
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 0f5a1c8..ae4bbce 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -16,12 +16,17 @@ # Base Configurations. Don't Touch # section begin +set ::env(PDK) "sky130A" +set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" + # YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/fixed_wrapper_cfgs.tcl + # YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/default_wrapper_cfgs.tcl + set script_dir [file dirname [file normalize [info script]]] set proj_dir [file dirname [file normalize [info script]]] @@ -53,7 +58,7 @@ set ::env(FP_SIZING) "absolute" set ::env(MACRO_PLACEMENT_CFG) $proj_dir/macro.cfg -set ::env(PDN_CFG) $proj_dir/pdn.tcl +#set ::env(PDN_CFG) $proj_dir/pdn.tcl set ::env(SDC_FILE) "$proj_dir/base.sdc" set ::env(BASE_SDC_FILE) "$proj_dir/base.sdc" @@ -65,7 +70,7 @@ $proj_dir/../../verilog/gl/qspim.v \ $proj_dir/../../verilog/gl/wb_interconnect.v \ $proj_dir/../../verilog/gl/pinmux.v \ - $proj_dir/../../verilog/gl/mbist.v \ + $proj_dir/../../verilog/gl/mbist_wrapper.v \ $proj_dir/../../verilog/gl/uart_i2cm_usb_spi.v \ $proj_dir/../../verilog/gl/wb_host.v \ $proj_dir/../../verilog/gl/yifive.v \ @@ -78,7 +83,7 @@ $lef_root/wb_interconnect.lef \ $lef_root/uart_i2cm_usb_spi.lef \ $lef_root/wb_host.lef \ - $lef_root/mbist.lef \ + $lef_root/mbist_wrapper.lef \ $lef_root/yifive.lef \ $lef_root/sky130_sram_2kbyte_1rw1r_32x512_8.lef \ " @@ -89,14 +94,14 @@ $gds_root/wb_interconnect.gds \ $gds_root/uart_i2cm_usb_spi.gds \ $gds_root/wb_host.gds \ - $gds_root/mbist.gds \ + $gds_root/mbist_wrapper.gds \ $gds_root/yifive.gds \ $gds_root/sky130_sram_2kbyte_1rw1r_32x512_8.gds \ " set ::env(SYNTH_DEFINES) [list SYNTHESIS ] -set ::env(VERILOG_INCLUDE_DIRS) [glob $proj_dir/../../verilog/rtl/yifive/ycr1/src/includes ] +set ::env(VERILOG_INCLUDE_DIRS) [glob $proj_dir/../../verilog/rtl/yifive/ycr1c/src/includes ] set ::env(GLB_RT_MAXLAYER) 5 @@ -114,25 +119,34 @@ set ::env(VDD_PIN) "vccd1 vccd2 vdda1 vdda2" set ::env(GND_PIN) "vssd1 vssd2 vssa1 vssa2" -set ::env(GLB_RT_OBS) " li1 150 1300 833.1 1716.54,\ - met1 150 1300 833.1 1716.54,\ - met3 150 1300 833.1 1716.54,\ - li1 950 1300 1633.1 1716.54,\ - met1 950 1300 1633.1 1716.54,\ - met2 950 1300 1633.1 1716.54,\ - met3 950 1300 1633.1 1716.54,\ - li1 150 1900 833.1 2316.54,\ - met1 150 1900 833.1 2316.54,\ - met3 150 1900 833.1 2316.54,\ - li1 950 1900 1633.1 2316.54,\ - met1 950 1900 1633.1 2316.54,\ - met3 950 1900 1633.1 2316.54,\ - li1 150 2900 833.1 3316.54,\ - met1 150 2900 833.1 3316.54,\ - met3 150 2900 833.1 3316.54,\ - li1 950 2900 1633.1 3316.54,\ - met1 950 2900 1633.1 3316.54,\ - met3 950 2900 1633.1 3316.54,\ +set ::env(GLB_RT_OBS) " li1 150 2100 833.1 2516.54,\ + met1 150 2100 833.1 2516.54,\ + met2 150 2100 833.1 2516.54,\ + met3 150 2100 833.1 2516.54,\ + li1 950 2100 1633.1 2516.54,\ + met1 950 2100 1633.1 2516.54,\ + met2 950 2100 1633.1 2516.54,\ + met3 950 2100 1633.1 2516.54,\ + li1 150 3000 833.1 3416.54,\ + met1 150 3000 833.1 3416.54,\ + met2 150 3000 833.1 3416.54,\ + met3 150 3000 833.1 3416.54,\ + li1 950 3000 1633.1 3416.54,\ + met1 950 3000 1633.1 3416.54,\ + met2 950 3000 1633.1 3416.54,\ + met3 950 3000 1633.1 3416.54,\ + li1 150 1400 833.1 1816.54,\ + met1 150 1400 833.1 1816.54,\ + met2 150 1400 833.1 1816.54,\ + met3 150 1400 833.1 1816.54,\ + li1 150 800 833.1 1216.54,\ + met1 150 800 833.1 1216.54,\ + met2 150 800 833.1 1216.54,\ + met3 150 800 833.1 1216.54,\ + li1 150 200 833.1 616.54,\ + met1 150 200 833.1 616.54,\ + met2 150 200 833.1 616.54,\ + met3 150 200 833.1 616.54,\ met5 0 0 2920 3520" set ::env(FP_PDN_MACRO_HOOKS) "\ @@ -141,7 +155,8 @@ u_qspi_master vccd1 vssd1 \ u_riscv_top vccd1 vssd1 \ u_tsram0_2kb vccd1 vssd1 \ - u_tsram1_2kb vccd1 vssd1 \ + u_icache_2kb vccd1 vssd1 \ + u_dcache_2kb vccd1 vssd1 \ u_mbist vccd1 vssd1 \ u_sram0_2kb vccd1 vssd1 \ u_sram1_2kb vccd1 vssd1 \ @@ -177,7 +192,7 @@ set ::env(FP_PDN_HPITCH) "90" -set ::env(FP_PDN_VPITCH) "180" +set ::env(FP_PDN_VPITCH) "100" set ::env(FP_PDN_HSPACING) "6"
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl index 4483faf..fde4083 100644 --- a/openlane/user_project_wrapper/interactive.tcl +++ b/openlane/user_project_wrapper/interactive.tcl
@@ -20,9 +20,6 @@ proc run_placement_step {args} { - # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def] - # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0] - # set_def $pdndef if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } { set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF) } else { @@ -33,7 +30,6 @@ } proc run_cts_step {args} { - # set_def $::env(opendp_result_file_tag).def if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } { set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF) } else { @@ -45,9 +41,6 @@ } proc run_routing_step {args} { - # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def] - # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0] - # set_def $resizerdef if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } { set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF) } else { @@ -57,7 +50,6 @@ } proc run_diode_insertion_2_5_step {args} { - # set_def $::env(tritonRoute_result_file_tag).def if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } { set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) } else { @@ -70,22 +62,7 @@ } -proc run_power_pins_insertion_step {args} { - # set_def $::env(tritonRoute_result_file_tag).def - if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } { - set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF) - } - if { $::env(LVS_INSERT_POWER_PINS) } { - write_powered_verilog - set_netlist $::env(lvs_result_file_tag).powered.v - } - -} - proc run_lvs_step {{ lvs_enabled 1 }} { - # set_def $::env(tritonRoute_result_file_tag).def if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } { set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF) } else { @@ -121,189 +98,6 @@ } } -proc gen_pdn {args} { - puts_info "Generating PDN..." - TIMER::timer_start - - set ::env(SAVE_DEF) [index_file $::env(pdn_tmp_file_tag).def] - set ::env(PGA_RPT_FILE) [index_file $::env(pdn_report_file_tag).pga.rpt] - - try_catch $::env(OPENROAD_BIN) -exit $::env(SCRIPTS_DIR)/openroad/pdn.tcl \ - |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(pdn_log_file_tag).log 0] - - - TIMER::timer_stop - exec echo "[TIMER::get_runtime]" >> [index_file $::env(pdn_log_file_tag)_runtime.txt 0] - - quit_on_unconnected_pdn_nodes - - set_def $::env(SAVE_DEF) -} - -proc run_power_grid_generation {args} { - if { [info exists ::env(VDD_NETS)] || [info exists ::env(GND_NETS)] } { - # they both must exist and be equal in length - # current assumption: they cannot have a common ground - if { ! [info exists ::env(VDD_NETS)] || ! [info exists ::env(GND_NETS)] } { - puts_err "VDD_NETS and GND_NETS must *both* either be defined or undefined" - return -code error - } - # standard cell power and ground nets are assumed to be the first net - set ::env(VDD_PIN) [lindex $::env(VDD_NETS) 0] - set ::env(GND_PIN) [lindex $::env(GND_NETS) 0] - } elseif { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } { - set ::env(VDD_NETS) [list] - set ::env(GND_NETS) [list] - # get the pins that are in $yosys_tmp_file_tag.pg_define.v - # that are not in $yosys_result_file_tag.v - # - set full_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_tmp_file_tag).pg_define.v] - puts_info $full_pins - - set non_pg_pins {*}[extract_pins_from_yosys_netlist $::env(yosys_result_file_tag).v] - puts_info $non_pg_pins - - # assumes the pins are ordered correctly (e.g., vdd1, vss1, vcc1, vss1, ...) - foreach {vdd gnd} $full_pins { - if { $vdd ne "" && $vdd ni $non_pg_pins } { - lappend ::env(VDD_NETS) $vdd - } - if { $gnd ne "" && $gnd ni $non_pg_pins } { - lappend ::env(GND_NETS) $gnd - } - } - } else { - set ::env(VDD_NETS) $::env(VDD_PIN) - set ::env(GND_NETS) $::env(GND_PIN) - } - - puts_info "Power planning the following nets" - puts_info "Power: $::env(VDD_NETS)" - puts_info "Ground: $::env(GND_NETS)" - - if { [llength $::env(VDD_NETS)] != [llength $::env(GND_NETS)] } { - puts_err "VDD_NETS and GND_NETS must be of equal lengths" - return -code error - } - - # internal macros power connections - if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} { - set macro_hooks [dict create] - set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","] - foreach pdn_hook $pdn_hooks { - set instance_name [lindex $pdn_hook 0] - set power_net [lindex $pdn_hook 1] - set ground_net [lindex $pdn_hook 2] - dict append macro_hooks $instance_name [subst {$power_net $ground_net}] - set power_net_indx [lsearch $::env(VDD_NETS) $power_net] - set ground_net_indx [lsearch $::env(GND_NETS) $ground_net] - - # make sure that the specified power domains exist. - if { $power_net_indx == -1 || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } { - puts_err "Can't find $power_net and $ground_net domain. \ - Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)." - } - } - - } - - # generate multiple power grids per pair of (VDD,GND) - # offseted by WIDTH + SPACING - foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) { - set ::env(VDD_NET) $vdd - set ::env(GND_NET) $gnd - puts_info "Connecting Power: $vdd & gnd to All internal macros." - - # internal macros power connections - set ::env(FP_PDN_MACROS) "" - if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 } { - # if macros connections to power are explicitly set - # default behavoir macro pins will be connected to the first power domain - if { [info exists ::env(FP_PDN_MACRO_HOOKS)] } { - set ::env(FP_PDN_ENABLE_MACROS_GRID) 0 - foreach {instance_name hooks} $macro_hooks { - set power [lindex $hooks 0] - set ground [lindex $hooks 1] - if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } { - set ::env(FP_PDN_ENABLE_MACROS_GRID) 1 - puts_info "Connecting $instance_name to $power and $ground nets." - lappend ::env(FP_PDN_MACROS) $instance_name - } - } - } - } else { - puts_warn "All internal macros will not be connected to power $vdd & $gnd." - } - - gen_pdn - - set ::env(FP_PDN_ENABLE_RAILS) 0 - set ::env(FP_PDN_ENABLE_MACROS_GRID) 0 - - # allow failure until open_pdks is up to date... - catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]} - catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]} - - catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \ - [expr $::env(FP_PDN_CORE_RING_VOFFSET)\ - +2*($::env(FP_PDN_CORE_RING_VWIDTH)\ - +max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]} - catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\ - +2*($::env(FP_PDN_CORE_RING_HWIDTH)+\ - max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]} - - puts "FP_PDN_VOFFSET: $::env(FP_PDN_VOFFSET)" - puts "FP_PDN_HOFFSET: $::env(FP_PDN_VOFFSET)" - puts "FP_PDN_CORE_RING_VOFFSET: $::env(FP_PDN_CORE_RING_VOFFSET)" - puts "FP_PDN_CORE_RING_HOFFSET: $::env(FP_PDN_CORE_RING_HOFFSET)" - } - set ::env(FP_PDN_ENABLE_RAILS) 1 -} - - -proc run_floorplan {args} { - puts_info "Running Floorplanning..." - # |----------------------------------------------------| - # |---------------- 2. FLOORPLAN ------------------| - # |----------------------------------------------------| - # - # intial fp - init_floorplan - - - # place io - if { [info exists ::env(FP_PIN_ORDER_CFG)] } { - place_io_ol - } else { - if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } { - place_io - global_placement_or - place_contextualized_io \ - -lef $::env(FP_CONTEXT_LEF) \ - -def $::env(FP_CONTEXT_DEF) - } else { - place_io - } - } - - apply_def_template - - if { [info exist ::env(EXTRA_LEFS)] } { - if { [info exist ::env(MACRO_PLACEMENT_CFG)] } { - file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(TMP_DIR)/macro_placement.cfg - manual_macro_placement f - } else { - global_placement_or - basic_macro_placement - } - } - - # tapcell - tap_decap_or - scrot_klayout -layout $::env(CURRENT_DEF) - # power grid generation - run_power_grid_generation -} proc run_flow {args} { @@ -331,7 +125,6 @@ "cts" {run_cts_step ""} \ "routing" {run_routing_step ""}\ "diode_insertion" {run_diode_insertion_2_5_step ""} \ - "power_pins_insertion" {run_power_pins_insertion_step ""} \ "gds_magic" {run_magic ""} \ "gds_drc_klayout" {run_klayout ""} \ "gds_xor_klayout" {run_klayout_gds_xor ""} \
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index 535ebc1..d45af45 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,14 +1,18 @@ -u_qspi_master 2200 600 N -u_uart_i2c_usb_spi 2200 1300 N -u_pinmux 2200 2200 N -u_riscv_top 150 600 N -u_tsram0_2kb 150 1300 N -u_tsram1_2kb 950 1300 N +u_qspi_master 2250 700 N +u_uart_i2c_usb_spi 2250 1400 N +u_pinmux 2250 2300 N +u_sram2_2kb 150 3000 N +u_sram3_2kb 950 3000 N -u_mbist 150 2500 N -u_sram0_2kb 150 1900 N -u_sram1_2kb 950 1900 FS -u_sram2_2kb 150 2900 N -u_sram3_2kb 950 2900 N -u_intercon 1850 600 N -u_wb_host 1450 250 N +u_mbist 150 2650 N +u_sram0_2kb 150 2100 N +u_sram1_2kb 950 2100 N + +u_riscv_top 950 450 N +u_dcache_2kb 150 1400 N +u_icache_2kb 150 800 N +u_tsram0_2kb 150 200 N + + +u_intercon 1850 700 N +u_wb_host 1450 075 N
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index 7861baf..eec3264 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -42,12 +42,12 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ - $script_dir/../../verilog/rtl/lib/wb_stagging.sv \ + $script_dir/../../verilog/rtl/lib/sync_wbb.sv \ + $script_dir/../../verilog/rtl/lib/sync_fifo2.sv \ $script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \ $script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv \ " -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/syntacore/scr1/src/includes $script_dir/../../verilog/rtl/sdram_ctrl/src/defs ] set ::env(SYNTH_DEFINES) [list SYNTHESIS ] set ::env(SYNTH_PARAMS) "CH_CLK_WD 8,\ @@ -70,7 +70,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 160 2200" +set ::env(DIE_AREA) "0 0 200 2300" # If you're going to use multiple power domains, then keep this disabled. @@ -80,24 +80,40 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(FP_CORE_UTIL) "50" -set ::env(PL_TARGET_DENSITY) "0.50" +set ::env(PL_TARGET_DENSITY) "0.30" # helps in anteena fix set ::env(USE_ARC_ANTENNA_CHECK) "0" -set ::env(FP_IO_VEXTEND) 4 -set ::env(FP_IO_HEXTEND) 4 -set ::env(FP_PDN_VPITCH) 100 -set ::env(FP_PDN_HPITCH) 100 -set ::env(FP_PDN_VWIDTH) 5 -set ::env(FP_PDN_HWIDTH) 5 - -set ::env(GLB_RT_MAXLAYER) 5 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 4 +## CTS +set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_16" +set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) 50 +set ::env(CTS_SINK_CLUSTERING_SIZE) 20 + +## Placement +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1 +set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1 + +set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 2 +set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2 + +## Routing +set ::env(GLB_RT_ADJUSTMENT) 0 +set ::env(GLB_RT_L2_ADJUSTMENT) 0.21 +set ::env(GLB_RT_L3_ADJUSTMENT) 0.21 +set ::env(GLB_RT_L4_ADJUSTMENT) 0.1 +set ::env(GLB_RT_L5_ADJUSTMENT) 0.1 +set ::env(GLB_RT_L6_ADJUSTMENT) 0.1 +set ::env(GLB_RT_ALLOW_CONGESTION) 0 +set ::env(GLB_RT_OVERFLOW_ITERS) 200 + +set ::env(GLB_RT_MINLAYER) 2 +set ::env(GLB_RT_MAXLAYER) 6 + set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" set ::env(QUIT_ON_MAGIC_DRC) "1" @@ -105,10 +121,10 @@ set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" -set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "1" +set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) "0" set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) "1" -set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "1000" -set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "1.5" +set ::env(PL_RESIZER_MAX_WIRE_LENGTH) "2000" +set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "2.0" set ::env(PL_RESIZER_MAX_CAP_MARGIN) "5" ## FANOUT Reduced to take care of long routes
diff --git a/openlane/wb_interconnect/pin_order.cfg b/openlane/wb_interconnect/pin_order.cfg index 295c0ef..9f2007f 100644 --- a/openlane/wb_interconnect/pin_order.cfg +++ b/openlane/wb_interconnect/pin_order.cfg
@@ -4,6 +4,10 @@ #S rst_n 000 0 2 +dcache_remap\[3\] +dcache_remap\[2\] +dcache_remap\[1\] +dcache_remap\[0\] boot_remap\[3\] boot_remap\[2\] boot_remap\[1\] @@ -164,13 +168,14 @@ m0_wbd_dat_o\[1\] m0_wbd_dat_o\[0\] m0_wbd_ack_o +m0_wbd_lack_o m0_wbd_err_o m0_wbd_cyc_i #W -ch_data_out\[84\] 0000 0 2 +ch_data_out\[84\] 0250 0 2 ch_data_out\[83\] ch_data_out\[82\] ch_data_out\[81\] @@ -227,7 +232,7 @@ ch_clk_out\[0\] -m1_wbd_stb_i 0200 0 2 +m1_wbd_stb_i 0450 0 2 m1_wbd_we_i m1_wbd_adr_i\[31\] m1_wbd_adr_i\[30\] @@ -330,10 +335,11 @@ m1_wbd_dat_o\[1\] m1_wbd_dat_o\[0\] m1_wbd_ack_o +m1_wbd_lack_o m1_wbd_err_o m1_wbd_cyc_i -m2_wbd_stb_i 0350 0 2 +m2_wbd_stb_i 0650 0 2 m2_wbd_we_i m2_wbd_adr_i\[31\] m2_wbd_adr_i\[30\] @@ -371,6 +377,17 @@ m2_wbd_sel_i\[2\] m2_wbd_sel_i\[1\] m2_wbd_sel_i\[0\] +m2_wbd_bl_i\[9\] +m2_wbd_bl_i\[8\] +m2_wbd_bl_i\[7\] +m2_wbd_bl_i\[6\] +m2_wbd_bl_i\[5\] +m2_wbd_bl_i\[4\] +m2_wbd_bl_i\[3\] +m2_wbd_bl_i\[2\] +m2_wbd_bl_i\[1\] +m2_wbd_bl_i\[0\] +m2_wbd_bry_i m2_wbd_dat_i\[31\] m2_wbd_dat_i\[30\] m2_wbd_dat_i\[29\] @@ -436,17 +453,103 @@ m2_wbd_dat_o\[1\] m2_wbd_dat_o\[0\] m2_wbd_ack_o +m2_wbd_lack_o m2_wbd_err_o m2_wbd_cyc_i +m3_wbd_stb_i 0850 0 2 +m3_wbd_we_i +m3_wbd_adr_i\[31\] +m3_wbd_adr_i\[30\] +m3_wbd_adr_i\[29\] +m3_wbd_adr_i\[28\] +m3_wbd_adr_i\[27\] +m3_wbd_adr_i\[26\] +m3_wbd_adr_i\[25\] +m3_wbd_adr_i\[24\] +m3_wbd_adr_i\[23\] +m3_wbd_adr_i\[22\] +m3_wbd_adr_i\[21\] +m3_wbd_adr_i\[20\] +m3_wbd_adr_i\[19\] +m3_wbd_adr_i\[18\] +m3_wbd_adr_i\[17\] +m3_wbd_adr_i\[16\] +m3_wbd_adr_i\[15\] +m3_wbd_adr_i\[14\] +m3_wbd_adr_i\[13\] +m3_wbd_adr_i\[12\] +m3_wbd_adr_i\[11\] +m3_wbd_adr_i\[10\] +m3_wbd_adr_i\[9\] +m3_wbd_adr_i\[8\] +m3_wbd_adr_i\[7\] +m3_wbd_adr_i\[6\] +m3_wbd_adr_i\[5\] +m3_wbd_adr_i\[4\] +m3_wbd_adr_i\[3\] +m3_wbd_adr_i\[2\] +m3_wbd_adr_i\[1\] +m3_wbd_adr_i\[0\] +m3_wbd_sel_i\[3\] +m3_wbd_sel_i\[2\] +m3_wbd_sel_i\[1\] +m3_wbd_sel_i\[0\] +m3_wbd_bl_i\[9\] +m3_wbd_bl_i\[8\] +m3_wbd_bl_i\[7\] +m3_wbd_bl_i\[6\] +m3_wbd_bl_i\[5\] +m3_wbd_bl_i\[4\] +m3_wbd_bl_i\[3\] +m3_wbd_bl_i\[2\] +m3_wbd_bl_i\[1\] +m3_wbd_bl_i\[0\] +m3_wbd_bry_i +m3_wbd_dat_o\[31\] +m3_wbd_dat_o\[30\] +m3_wbd_dat_o\[29\] +m3_wbd_dat_o\[28\] +m3_wbd_dat_o\[27\] +m3_wbd_dat_o\[26\] +m3_wbd_dat_o\[25\] +m3_wbd_dat_o\[24\] +m3_wbd_dat_o\[23\] +m3_wbd_dat_o\[22\] +m3_wbd_dat_o\[21\] +m3_wbd_dat_o\[20\] +m3_wbd_dat_o\[19\] +m3_wbd_dat_o\[18\] +m3_wbd_dat_o\[17\] +m3_wbd_dat_o\[16\] +m3_wbd_dat_o\[15\] +m3_wbd_dat_o\[14\] +m3_wbd_dat_o\[13\] +m3_wbd_dat_o\[12\] +m3_wbd_dat_o\[11\] +m3_wbd_dat_o\[10\] +m3_wbd_dat_o\[9\] +m3_wbd_dat_o\[8\] +m3_wbd_dat_o\[7\] +m3_wbd_dat_o\[6\] +m3_wbd_dat_o\[5\] +m3_wbd_dat_o\[4\] +m3_wbd_dat_o\[3\] +m3_wbd_dat_o\[2\] +m3_wbd_dat_o\[1\] +m3_wbd_dat_o\[0\] +m3_wbd_ack_o +m3_wbd_lack_o +m3_wbd_err_o +m3_wbd_cyc_i -ch_data_out\[23\] 1900 0 2 +ch_data_out\[23\] 1950 0 2 ch_data_out\[22\] ch_data_out\[21\] ch_data_out\[20\] ch_clk_out\[4\] -s3_wbd_cyc_o 1925 0 2 +s3_wbd_cyc_o 1975 0 2 s3_wbd_stb_o s3_wbd_we_o s3_wbd_adr_o\[12\] @@ -498,6 +601,17 @@ s3_wbd_sel_o\[2\] s3_wbd_sel_o\[1\] s3_wbd_sel_o\[0\] +s3_wbd_bl_o\[9\] +s3_wbd_bl_o\[8\] +s3_wbd_bl_o\[7\] +s3_wbd_bl_o\[6\] +s3_wbd_bl_o\[5\] +s3_wbd_bl_o\[4\] +s3_wbd_bl_o\[3\] +s3_wbd_bl_o\[2\] +s3_wbd_bl_o\[1\] +s3_wbd_bl_o\[0\] +s3_wbd_bry_o s3_wbd_dat_i\[31\] s3_wbd_dat_i\[30\] s3_wbd_dat_i\[29\] @@ -531,8 +645,9 @@ s3_wbd_dat_i\[1\] s3_wbd_dat_i\[0\] s3_wbd_ack_i +s3_wbd_lack_i -ch_data_in\[115\] 2050 0 2 +ch_data_in\[115\] 2110 0 2 ch_data_in\[114\] ch_data_in\[113\] ch_data_in\[112\] @@ -566,7 +681,7 @@ -ch_clk_out\[5\] 2150 0 2 +ch_clk_out\[5\] 2200 0 2 ch_clk_out\[6\] ch_clk_out\[7\] ch_data_out\[24\] @@ -631,6 +746,17 @@ s0_wbd_sel_o\[2\] s0_wbd_sel_o\[1\] s0_wbd_sel_o\[0\] +s0_wbd_bl_o\[9\] +s0_wbd_bl_o\[8\] +s0_wbd_bl_o\[7\] +s0_wbd_bl_o\[6\] +s0_wbd_bl_o\[5\] +s0_wbd_bl_o\[4\] +s0_wbd_bl_o\[3\] +s0_wbd_bl_o\[2\] +s0_wbd_bl_o\[1\] +s0_wbd_bl_o\[0\] +s0_wbd_bry_o s0_wbd_dat_o\[31\] s0_wbd_dat_o\[30\] s0_wbd_dat_o\[29\] @@ -696,6 +822,7 @@ s0_wbd_dat_i\[1\] s0_wbd_dat_i\[0\] s0_wbd_ack_i +s0_wbd_lack_i s0_wbd_cyc_o
diff --git a/openlane/yifive/config.tcl b/openlane/yifive/config.tcl index ea4e6c9..219ef26 100755 --- a/openlane/yifive/config.tcl +++ b/openlane/yifive/config.tcl
@@ -41,39 +41,51 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_top.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_core_top.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_dm.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_tapc_synchronizer.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_clk_ctrl.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_scu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_tapc.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_tapc_shift_reg.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/ycr1_dmi.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/primitives/ycr1_reset_cells.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_ifu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_idu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_exu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_mprf.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_csr.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_ialu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_mul.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_div.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_lsu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_hdu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_pipe_tdu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/core/pipeline/ycr1_ipic.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_dmem_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_imem_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_tcm.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_timer.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_top_wb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_dmem_wb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_imem_wb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1/src/top/ycr1_intf.sv \ - $script_dir/../../verilog/rtl/lib/async_fifo.sv " + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_top.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_core_top.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_dm.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_tapc_synchronizer.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_clk_ctrl.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_scu.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_tapc.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_tapc_shift_reg.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_dmi.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr1_reset_cells.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_ifu.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_idu.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_exu.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_mprf.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_csr.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_ialu.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_mul.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_div.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_lsu.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_hdu.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_tdu.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_ipic.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_dmem_router.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_imem_router.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_icache_router.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_dcache_router.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_tcm.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_timer.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_top_wb.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_dmem_wb.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_imem_wb.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_intf.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_top.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_top.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr1_async_wbb.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr1_arb.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/sync_fifo.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/async_fifo.sv \ + $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ctech_cells.sv \ + " -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr1/src/includes ] +set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ] set ::env(SYNTH_READ_BLACKBOX_LIB) 1 set ::env(SYNTH_DEFINES) [list SYNTHESIS ] @@ -94,7 +106,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) [list 0.0 0.0 1520.0 520.0] +set ::env(DIE_AREA) [list 0.0 0.0 750.0 1450.0] # If you're going to use multiple power domains, then keep this disabled. @@ -104,7 +116,8 @@ set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.32" +set ::env(PL_TARGET_DENSITY) "0.40" +set ::env(FP_CORE_UTIL) "50" # helps in anteena fix set ::env(USE_ARC_ANTENNA_CHECK) "0" @@ -117,7 +130,7 @@ set ::env(FP_PDN_VWIDTH) 3 set ::env(FP_PDN_HWIDTH) 3 -set ::env(GLB_RT_MAXLAYER) 5 +set ::env(GLB_RT_MAXLAYER) 6 set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/yifive/pin_order.cfg b/openlane/yifive/pin_order.cfg index d9738fe..e168c5f 100644 --- a/openlane/yifive/pin_order.cfg +++ b/openlane/yifive/pin_order.cfg
@@ -4,7 +4,7 @@ #E -soft_irq 0000 0 2 +soft_irq 0500 0 2 irq_lines\[15\] irq_lines\[14\] irq_lines\[13\] @@ -63,219 +63,583 @@ wb_clk -wbd_imem_stb_o 0200 0 -wbd_imem_we_o -wbd_imem_adr_o\[31\] -wbd_imem_adr_o\[30\] -wbd_imem_adr_o\[29\] -wbd_imem_adr_o\[28\] -wbd_imem_adr_o\[27\] -wbd_imem_adr_o\[26\] -wbd_imem_adr_o\[25\] -wbd_imem_adr_o\[24\] -wbd_imem_adr_o\[23\] -wbd_imem_adr_o\[22\] -wbd_imem_adr_o\[21\] -wbd_imem_adr_o\[20\] -wbd_imem_adr_o\[19\] -wbd_imem_adr_o\[18\] -wbd_imem_adr_o\[17\] -wbd_imem_adr_o\[16\] -wbd_imem_adr_o\[15\] -wbd_imem_adr_o\[14\] -wbd_imem_adr_o\[13\] -wbd_imem_adr_o\[12\] -wbd_imem_adr_o\[11\] -wbd_imem_adr_o\[10\] -wbd_imem_adr_o\[9\] -wbd_imem_adr_o\[8\] -wbd_imem_adr_o\[7\] -wbd_imem_adr_o\[6\] -wbd_imem_adr_o\[5\] -wbd_imem_adr_o\[4\] -wbd_imem_adr_o\[3\] -wbd_imem_adr_o\[2\] -wbd_imem_adr_o\[1\] -wbd_imem_adr_o\[0\] -wbd_imem_sel_o\[3\] -wbd_imem_sel_o\[2\] -wbd_imem_sel_o\[1\] -wbd_imem_sel_o\[0\] -wbd_imem_dat_o\[31\] -wbd_imem_dat_o\[30\] -wbd_imem_dat_o\[29\] -wbd_imem_dat_o\[28\] -wbd_imem_dat_o\[27\] -wbd_imem_dat_o\[26\] -wbd_imem_dat_o\[25\] -wbd_imem_dat_o\[24\] -wbd_imem_dat_o\[23\] -wbd_imem_dat_o\[22\] -wbd_imem_dat_o\[21\] -wbd_imem_dat_o\[20\] -wbd_imem_dat_o\[19\] -wbd_imem_dat_o\[18\] -wbd_imem_dat_o\[17\] -wbd_imem_dat_o\[16\] -wbd_imem_dat_o\[15\] -wbd_imem_dat_o\[14\] -wbd_imem_dat_o\[13\] -wbd_imem_dat_o\[12\] -wbd_imem_dat_o\[11\] -wbd_imem_dat_o\[10\] -wbd_imem_dat_o\[9\] -wbd_imem_dat_o\[8\] -wbd_imem_dat_o\[7\] -wbd_imem_dat_o\[6\] -wbd_imem_dat_o\[5\] -wbd_imem_dat_o\[4\] -wbd_imem_dat_o\[3\] -wbd_imem_dat_o\[2\] -wbd_imem_dat_o\[1\] -wbd_imem_dat_o\[0\] -wbd_imem_dat_i\[31\] -wbd_imem_dat_i\[30\] -wbd_imem_dat_i\[29\] -wbd_imem_dat_i\[28\] -wbd_imem_dat_i\[27\] -wbd_imem_dat_i\[26\] -wbd_imem_dat_i\[25\] -wbd_imem_dat_i\[24\] -wbd_imem_dat_i\[23\] -wbd_imem_dat_i\[22\] -wbd_imem_dat_i\[21\] -wbd_imem_dat_i\[20\] -wbd_imem_dat_i\[19\] -wbd_imem_dat_i\[18\] -wbd_imem_dat_i\[17\] -wbd_imem_dat_i\[16\] -wbd_imem_dat_i\[15\] -wbd_imem_dat_i\[14\] -wbd_imem_dat_i\[13\] -wbd_imem_dat_i\[12\] -wbd_imem_dat_i\[11\] -wbd_imem_dat_i\[10\] -wbd_imem_dat_i\[9\] -wbd_imem_dat_i\[8\] -wbd_imem_dat_i\[7\] -wbd_imem_dat_i\[6\] -wbd_imem_dat_i\[5\] -wbd_imem_dat_i\[4\] -wbd_imem_dat_i\[3\] -wbd_imem_dat_i\[2\] -wbd_imem_dat_i\[1\] -wbd_imem_dat_i\[0\] -wbd_imem_ack_i -wbd_imem_err_i +wbd_dmem_stb_o 0700 0 +wbd_dmem_we_o +wbd_dmem_adr_o\[31\] +wbd_dmem_adr_o\[30\] +wbd_dmem_adr_o\[29\] +wbd_dmem_adr_o\[28\] +wbd_dmem_adr_o\[27\] +wbd_dmem_adr_o\[26\] +wbd_dmem_adr_o\[25\] +wbd_dmem_adr_o\[24\] +wbd_dmem_adr_o\[23\] +wbd_dmem_adr_o\[22\] +wbd_dmem_adr_o\[21\] +wbd_dmem_adr_o\[20\] +wbd_dmem_adr_o\[19\] +wbd_dmem_adr_o\[18\] +wbd_dmem_adr_o\[17\] +wbd_dmem_adr_o\[16\] +wbd_dmem_adr_o\[15\] +wbd_dmem_adr_o\[14\] +wbd_dmem_adr_o\[13\] +wbd_dmem_adr_o\[12\] +wbd_dmem_adr_o\[11\] +wbd_dmem_adr_o\[10\] +wbd_dmem_adr_o\[9\] +wbd_dmem_adr_o\[8\] +wbd_dmem_adr_o\[7\] +wbd_dmem_adr_o\[6\] +wbd_dmem_adr_o\[5\] +wbd_dmem_adr_o\[4\] +wbd_dmem_adr_o\[3\] +wbd_dmem_adr_o\[2\] +wbd_dmem_adr_o\[1\] +wbd_dmem_adr_o\[0\] +wbd_dmem_sel_o\[3\] +wbd_dmem_sel_o\[2\] +wbd_dmem_sel_o\[1\] +wbd_dmem_sel_o\[0\] +wbd_dmem_dat_o\[31\] +wbd_dmem_dat_o\[30\] +wbd_dmem_dat_o\[29\] +wbd_dmem_dat_o\[28\] +wbd_dmem_dat_o\[27\] +wbd_dmem_dat_o\[26\] +wbd_dmem_dat_o\[25\] +wbd_dmem_dat_o\[24\] +wbd_dmem_dat_o\[23\] +wbd_dmem_dat_o\[22\] +wbd_dmem_dat_o\[21\] +wbd_dmem_dat_o\[20\] +wbd_dmem_dat_o\[19\] +wbd_dmem_dat_o\[18\] +wbd_dmem_dat_o\[17\] +wbd_dmem_dat_o\[16\] +wbd_dmem_dat_o\[15\] +wbd_dmem_dat_o\[14\] +wbd_dmem_dat_o\[13\] +wbd_dmem_dat_o\[12\] +wbd_dmem_dat_o\[11\] +wbd_dmem_dat_o\[10\] +wbd_dmem_dat_o\[9\] +wbd_dmem_dat_o\[8\] +wbd_dmem_dat_o\[7\] +wbd_dmem_dat_o\[6\] +wbd_dmem_dat_o\[5\] +wbd_dmem_dat_o\[4\] +wbd_dmem_dat_o\[3\] +wbd_dmem_dat_o\[2\] +wbd_dmem_dat_o\[1\] +wbd_dmem_dat_o\[0\] +wbd_dmem_dat_i\[31\] +wbd_dmem_dat_i\[30\] +wbd_dmem_dat_i\[29\] +wbd_dmem_dat_i\[28\] +wbd_dmem_dat_i\[27\] +wbd_dmem_dat_i\[26\] +wbd_dmem_dat_i\[25\] +wbd_dmem_dat_i\[24\] +wbd_dmem_dat_i\[23\] +wbd_dmem_dat_i\[22\] +wbd_dmem_dat_i\[21\] +wbd_dmem_dat_i\[20\] +wbd_dmem_dat_i\[19\] +wbd_dmem_dat_i\[18\] +wbd_dmem_dat_i\[17\] +wbd_dmem_dat_i\[16\] +wbd_dmem_dat_i\[15\] +wbd_dmem_dat_i\[14\] +wbd_dmem_dat_i\[13\] +wbd_dmem_dat_i\[12\] +wbd_dmem_dat_i\[11\] +wbd_dmem_dat_i\[10\] +wbd_dmem_dat_i\[9\] +wbd_dmem_dat_i\[8\] +wbd_dmem_dat_i\[7\] +wbd_dmem_dat_i\[6\] +wbd_dmem_dat_i\[5\] +wbd_dmem_dat_i\[4\] +wbd_dmem_dat_i\[3\] +wbd_dmem_dat_i\[2\] +wbd_dmem_dat_i\[1\] +wbd_dmem_dat_i\[0\] +wbd_dmem_ack_i +wbd_dmem_err_i -wbd_dmem_stb_o 0350 0 2 -wbd_dmem_we_o -wbd_dmem_adr_o\[31\] -wbd_dmem_adr_o\[30\] -wbd_dmem_adr_o\[29\] -wbd_dmem_adr_o\[28\] -wbd_dmem_adr_o\[27\] -wbd_dmem_adr_o\[26\] -wbd_dmem_adr_o\[25\] -wbd_dmem_adr_o\[24\] -wbd_dmem_adr_o\[23\] -wbd_dmem_adr_o\[22\] -wbd_dmem_adr_o\[21\] -wbd_dmem_adr_o\[20\] -wbd_dmem_adr_o\[19\] -wbd_dmem_adr_o\[18\] -wbd_dmem_adr_o\[17\] -wbd_dmem_adr_o\[16\] -wbd_dmem_adr_o\[15\] -wbd_dmem_adr_o\[14\] -wbd_dmem_adr_o\[13\] -wbd_dmem_adr_o\[12\] -wbd_dmem_adr_o\[11\] -wbd_dmem_adr_o\[10\] -wbd_dmem_adr_o\[9\] -wbd_dmem_adr_o\[8\] -wbd_dmem_adr_o\[7\] -wbd_dmem_adr_o\[6\] -wbd_dmem_adr_o\[5\] -wbd_dmem_adr_o\[4\] -wbd_dmem_adr_o\[3\] -wbd_dmem_adr_o\[2\] -wbd_dmem_adr_o\[1\] -wbd_dmem_adr_o\[0\] -wbd_dmem_sel_o\[3\] -wbd_dmem_sel_o\[2\] -wbd_dmem_sel_o\[1\] -wbd_dmem_sel_o\[0\] -wbd_dmem_dat_o\[31\] -wbd_dmem_dat_o\[30\] -wbd_dmem_dat_o\[29\] -wbd_dmem_dat_o\[28\] -wbd_dmem_dat_o\[27\] -wbd_dmem_dat_o\[26\] -wbd_dmem_dat_o\[25\] -wbd_dmem_dat_o\[24\] -wbd_dmem_dat_o\[23\] -wbd_dmem_dat_o\[22\] -wbd_dmem_dat_o\[21\] -wbd_dmem_dat_o\[20\] -wbd_dmem_dat_o\[19\] -wbd_dmem_dat_o\[18\] -wbd_dmem_dat_o\[17\] -wbd_dmem_dat_o\[16\] -wbd_dmem_dat_o\[15\] -wbd_dmem_dat_o\[14\] -wbd_dmem_dat_o\[13\] -wbd_dmem_dat_o\[12\] -wbd_dmem_dat_o\[11\] -wbd_dmem_dat_o\[10\] -wbd_dmem_dat_o\[9\] -wbd_dmem_dat_o\[8\] -wbd_dmem_dat_o\[7\] -wbd_dmem_dat_o\[6\] -wbd_dmem_dat_o\[5\] -wbd_dmem_dat_o\[4\] -wbd_dmem_dat_o\[3\] -wbd_dmem_dat_o\[2\] -wbd_dmem_dat_o\[1\] -wbd_dmem_dat_o\[0\] -wbd_dmem_dat_i\[31\] -wbd_dmem_dat_i\[30\] -wbd_dmem_dat_i\[29\] -wbd_dmem_dat_i\[28\] -wbd_dmem_dat_i\[27\] -wbd_dmem_dat_i\[26\] -wbd_dmem_dat_i\[25\] -wbd_dmem_dat_i\[24\] -wbd_dmem_dat_i\[23\] -wbd_dmem_dat_i\[22\] -wbd_dmem_dat_i\[21\] -wbd_dmem_dat_i\[20\] -wbd_dmem_dat_i\[19\] -wbd_dmem_dat_i\[18\] -wbd_dmem_dat_i\[17\] -wbd_dmem_dat_i\[16\] -wbd_dmem_dat_i\[15\] -wbd_dmem_dat_i\[14\] -wbd_dmem_dat_i\[13\] -wbd_dmem_dat_i\[12\] -wbd_dmem_dat_i\[11\] -wbd_dmem_dat_i\[10\] -wbd_dmem_dat_i\[9\] -wbd_dmem_dat_i\[8\] -wbd_dmem_dat_i\[7\] -wbd_dmem_dat_i\[6\] -wbd_dmem_dat_i\[5\] -wbd_dmem_dat_i\[4\] -wbd_dmem_dat_i\[3\] -wbd_dmem_dat_i\[2\] -wbd_dmem_dat_i\[1\] -wbd_dmem_dat_i\[0\] -wbd_dmem_ack_i -wbd_dmem_err_i +wb_dcache_stb_o 0900 0 2 +wb_dcache_we_o +wb_dcache_adr_o\[31\] +wb_dcache_adr_o\[30\] +wb_dcache_adr_o\[29\] +wb_dcache_adr_o\[28\] +wb_dcache_adr_o\[27\] +wb_dcache_adr_o\[26\] +wb_dcache_adr_o\[25\] +wb_dcache_adr_o\[24\] +wb_dcache_adr_o\[23\] +wb_dcache_adr_o\[22\] +wb_dcache_adr_o\[21\] +wb_dcache_adr_o\[20\] +wb_dcache_adr_o\[19\] +wb_dcache_adr_o\[18\] +wb_dcache_adr_o\[17\] +wb_dcache_adr_o\[16\] +wb_dcache_adr_o\[15\] +wb_dcache_adr_o\[14\] +wb_dcache_adr_o\[13\] +wb_dcache_adr_o\[12\] +wb_dcache_adr_o\[11\] +wb_dcache_adr_o\[10\] +wb_dcache_adr_o\[9\] +wb_dcache_adr_o\[8\] +wb_dcache_adr_o\[7\] +wb_dcache_adr_o\[6\] +wb_dcache_adr_o\[5\] +wb_dcache_adr_o\[4\] +wb_dcache_adr_o\[3\] +wb_dcache_adr_o\[2\] +wb_dcache_adr_o\[1\] +wb_dcache_adr_o\[0\] +wb_dcache_sel_o\[3\] +wb_dcache_sel_o\[2\] +wb_dcache_sel_o\[1\] +wb_dcache_sel_o\[0\] +wb_dcache_bl_o\[9\] +wb_dcache_bl_o\[8\] +wb_dcache_bl_o\[7\] +wb_dcache_bl_o\[6\] +wb_dcache_bl_o\[5\] +wb_dcache_bl_o\[4\] +wb_dcache_bl_o\[3\] +wb_dcache_bl_o\[2\] +wb_dcache_bl_o\[1\] +wb_dcache_bl_o\[0\] +wb_dcache_bry_o +wb_dcache_dat_o\[31\] +wb_dcache_dat_o\[30\] +wb_dcache_dat_o\[29\] +wb_dcache_dat_o\[28\] +wb_dcache_dat_o\[27\] +wb_dcache_dat_o\[26\] +wb_dcache_dat_o\[25\] +wb_dcache_dat_o\[24\] +wb_dcache_dat_o\[23\] +wb_dcache_dat_o\[22\] +wb_dcache_dat_o\[21\] +wb_dcache_dat_o\[20\] +wb_dcache_dat_o\[19\] +wb_dcache_dat_o\[18\] +wb_dcache_dat_o\[17\] +wb_dcache_dat_o\[16\] +wb_dcache_dat_o\[15\] +wb_dcache_dat_o\[14\] +wb_dcache_dat_o\[13\] +wb_dcache_dat_o\[12\] +wb_dcache_dat_o\[11\] +wb_dcache_dat_o\[10\] +wb_dcache_dat_o\[9\] +wb_dcache_dat_o\[8\] +wb_dcache_dat_o\[7\] +wb_dcache_dat_o\[6\] +wb_dcache_dat_o\[5\] +wb_dcache_dat_o\[4\] +wb_dcache_dat_o\[3\] +wb_dcache_dat_o\[2\] +wb_dcache_dat_o\[1\] +wb_dcache_dat_o\[0\] +wb_dcache_dat_i\[31\] +wb_dcache_dat_i\[30\] +wb_dcache_dat_i\[29\] +wb_dcache_dat_i\[28\] +wb_dcache_dat_i\[27\] +wb_dcache_dat_i\[26\] +wb_dcache_dat_i\[25\] +wb_dcache_dat_i\[24\] +wb_dcache_dat_i\[23\] +wb_dcache_dat_i\[22\] +wb_dcache_dat_i\[21\] +wb_dcache_dat_i\[20\] +wb_dcache_dat_i\[19\] +wb_dcache_dat_i\[18\] +wb_dcache_dat_i\[17\] +wb_dcache_dat_i\[16\] +wb_dcache_dat_i\[15\] +wb_dcache_dat_i\[14\] +wb_dcache_dat_i\[13\] +wb_dcache_dat_i\[12\] +wb_dcache_dat_i\[11\] +wb_dcache_dat_i\[10\] +wb_dcache_dat_i\[9\] +wb_dcache_dat_i\[8\] +wb_dcache_dat_i\[7\] +wb_dcache_dat_i\[6\] +wb_dcache_dat_i\[5\] +wb_dcache_dat_i\[4\] +wb_dcache_dat_i\[3\] +wb_dcache_dat_i\[2\] +wb_dcache_dat_i\[1\] +wb_dcache_dat_i\[0\] +wb_dcache_ack_i +wb_dcache_lack_i +wb_dcache_err_i + +wb_icache_stb_o 1100 0 2 +wb_icache_we_o +wb_icache_adr_o\[31\] +wb_icache_adr_o\[30\] +wb_icache_adr_o\[29\] +wb_icache_adr_o\[28\] +wb_icache_adr_o\[27\] +wb_icache_adr_o\[26\] +wb_icache_adr_o\[25\] +wb_icache_adr_o\[24\] +wb_icache_adr_o\[23\] +wb_icache_adr_o\[22\] +wb_icache_adr_o\[21\] +wb_icache_adr_o\[20\] +wb_icache_adr_o\[19\] +wb_icache_adr_o\[18\] +wb_icache_adr_o\[17\] +wb_icache_adr_o\[16\] +wb_icache_adr_o\[15\] +wb_icache_adr_o\[14\] +wb_icache_adr_o\[13\] +wb_icache_adr_o\[12\] +wb_icache_adr_o\[11\] +wb_icache_adr_o\[10\] +wb_icache_adr_o\[9\] +wb_icache_adr_o\[8\] +wb_icache_adr_o\[7\] +wb_icache_adr_o\[6\] +wb_icache_adr_o\[5\] +wb_icache_adr_o\[4\] +wb_icache_adr_o\[3\] +wb_icache_adr_o\[2\] +wb_icache_adr_o\[1\] +wb_icache_adr_o\[0\] +wb_icache_sel_o\[3\] +wb_icache_sel_o\[2\] +wb_icache_sel_o\[1\] +wb_icache_sel_o\[0\] +wb_icache_bl_o\[9\] +wb_icache_bl_o\[8\] +wb_icache_bl_o\[7\] +wb_icache_bl_o\[6\] +wb_icache_bl_o\[5\] +wb_icache_bl_o\[4\] +wb_icache_bl_o\[3\] +wb_icache_bl_o\[2\] +wb_icache_bl_o\[1\] +wb_icache_bl_o\[0\] +wb_icache_bry_o +wb_icache_dat_i\[31\] +wb_icache_dat_i\[30\] +wb_icache_dat_i\[29\] +wb_icache_dat_i\[28\] +wb_icache_dat_i\[27\] +wb_icache_dat_i\[26\] +wb_icache_dat_i\[25\] +wb_icache_dat_i\[24\] +wb_icache_dat_i\[23\] +wb_icache_dat_i\[22\] +wb_icache_dat_i\[21\] +wb_icache_dat_i\[20\] +wb_icache_dat_i\[19\] +wb_icache_dat_i\[18\] +wb_icache_dat_i\[17\] +wb_icache_dat_i\[16\] +wb_icache_dat_i\[15\] +wb_icache_dat_i\[14\] +wb_icache_dat_i\[13\] +wb_icache_dat_i\[12\] +wb_icache_dat_i\[11\] +wb_icache_dat_i\[10\] +wb_icache_dat_i\[9\] +wb_icache_dat_i\[8\] +wb_icache_dat_i\[7\] +wb_icache_dat_i\[6\] +wb_icache_dat_i\[5\] +wb_icache_dat_i\[4\] +wb_icache_dat_i\[3\] +wb_icache_dat_i\[2\] +wb_icache_dat_i\[1\] +wb_icache_dat_i\[0\] +wb_icache_ack_i +wb_icache_lack_i +wb_icache_err_i + +#W +sram0_clk1 0000 0 2 +sram0_csb1 +sram0_addr1\[8\] +sram0_addr1\[7\] +sram0_addr1\[6\] +sram0_addr1\[5\] +sram0_addr1\[4\] +sram0_addr1\[3\] +sram0_addr1\[2\] +sram0_addr1\[1\] +sram0_addr1\[0\] + +sram0_dout1\[0\] 0200 0 2 +sram0_dout1\[1\] +sram0_dout1\[2\] +sram0_dout1\[3\] +sram0_dout1\[4\] +sram0_dout1\[5\] +sram0_dout1\[6\] +sram0_dout1\[7\] +sram0_dout1\[8\] +sram0_dout1\[9\] +sram0_dout1\[10\] +sram0_dout1\[11\] +sram0_dout1\[12\] +sram0_dout1\[13\] +sram0_dout1\[14\] +sram0_dout1\[15\] +sram0_dout1\[16\] +sram0_dout1\[17\] +sram0_dout1\[18\] +sram0_dout1\[19\] +sram0_dout1\[20\] +sram0_dout1\[21\] +sram0_dout1\[22\] +sram0_dout1\[23\] +sram0_dout1\[24\] +sram0_dout1\[25\] +sram0_dout1\[26\] +sram0_dout1\[27\] +sram0_dout1\[28\] +sram0_dout1\[29\] +sram0_dout1\[30\] +sram0_dout1\[31\] + +icache_mem_clk0 300 0 2 +icache_mem_csb0 +icache_mem_web0 +icache_mem_addr0\[0\] +icache_mem_addr0\[1\] +icache_mem_addr0\[2\] +icache_mem_addr0\[3\] +icache_mem_addr0\[4\] +icache_mem_addr0\[5\] +icache_mem_addr0\[6\] +icache_mem_addr0\[7\] +icache_mem_addr0\[8\] +icache_mem_wmask0\[0\] +icache_mem_wmask0\[1\] +icache_mem_wmask0\[2\] +icache_mem_wmask0\[3\] +icache_mem_din0\[0\] +icache_mem_din0\[1\] +icache_mem_din0\[2\] +icache_mem_din0\[3\] +icache_mem_din0\[4\] +icache_mem_din0\[5\] +icache_mem_din0\[6\] +icache_mem_din0\[7\] +icache_mem_din0\[8\] +icache_mem_din0\[9\] +icache_mem_din0\[10\] +icache_mem_din0\[11\] +icache_mem_din0\[12\] +icache_mem_din0\[13\] +icache_mem_din0\[14\] +icache_mem_din0\[15\] +icache_mem_din0\[16\] +icache_mem_din0\[17\] +icache_mem_din0\[18\] +icache_mem_din0\[19\] +icache_mem_din0\[20\] +icache_mem_din0\[21\] +icache_mem_din0\[22\] +icache_mem_din0\[23\] +icache_mem_din0\[24\] +icache_mem_din0\[25\] +icache_mem_din0\[26\] +icache_mem_din0\[27\] +icache_mem_din0\[28\] +icache_mem_din0\[29\] +icache_mem_din0\[30\] +icache_mem_din0\[31\] + +icache_mem_clk1 0400 0 2 +icache_mem_csb1 +icache_mem_addr1\[8\] +icache_mem_addr1\[7\] +icache_mem_addr1\[6\] +icache_mem_addr1\[5\] +icache_mem_addr1\[4\] +icache_mem_addr1\[3\] +icache_mem_addr1\[2\] +icache_mem_addr1\[1\] +icache_mem_addr1\[0\] + +icache_mem_dout1\[0\] 0450 0 2 +icache_mem_dout1\[1\] +icache_mem_dout1\[2\] +icache_mem_dout1\[3\] +icache_mem_dout1\[4\] +icache_mem_dout1\[5\] +icache_mem_dout1\[6\] +icache_mem_dout1\[7\] +icache_mem_dout1\[8\] +icache_mem_dout1\[9\] +icache_mem_dout1\[10\] +icache_mem_dout1\[11\] +icache_mem_dout1\[12\] +icache_mem_dout1\[13\] +icache_mem_dout1\[14\] +icache_mem_dout1\[15\] +icache_mem_dout1\[16\] +icache_mem_dout1\[17\] +icache_mem_dout1\[18\] +icache_mem_dout1\[19\] +icache_mem_dout1\[20\] +icache_mem_dout1\[21\] +icache_mem_dout1\[22\] +icache_mem_dout1\[23\] +icache_mem_dout1\[24\] +icache_mem_dout1\[25\] +icache_mem_dout1\[26\] +icache_mem_dout1\[27\] +icache_mem_dout1\[28\] +icache_mem_dout1\[29\] +icache_mem_dout1\[30\] +icache_mem_dout1\[31\] + +dcache_mem_clk0 850 0 2 +dcache_mem_csb0 +dcache_mem_web0 +dcache_mem_addr0\[0\] +dcache_mem_addr0\[1\] +dcache_mem_addr0\[2\] +dcache_mem_addr0\[3\] +dcache_mem_addr0\[4\] +dcache_mem_addr0\[5\] +dcache_mem_addr0\[6\] +dcache_mem_addr0\[7\] +dcache_mem_addr0\[8\] +dcache_mem_wmask0\[0\] +dcache_mem_wmask0\[1\] +dcache_mem_wmask0\[2\] +dcache_mem_wmask0\[3\] +dcache_mem_din0\[0\] +dcache_mem_din0\[1\] +dcache_mem_din0\[2\] +dcache_mem_din0\[3\] +dcache_mem_din0\[4\] +dcache_mem_din0\[5\] +dcache_mem_din0\[6\] +dcache_mem_din0\[7\] +dcache_mem_din0\[8\] +dcache_mem_din0\[9\] +dcache_mem_din0\[10\] +dcache_mem_din0\[11\] +dcache_mem_din0\[12\] +dcache_mem_din0\[13\] +dcache_mem_din0\[14\] +dcache_mem_din0\[15\] +dcache_mem_din0\[16\] +dcache_mem_din0\[17\] +dcache_mem_din0\[18\] +dcache_mem_din0\[19\] +dcache_mem_din0\[20\] +dcache_mem_din0\[21\] +dcache_mem_din0\[22\] +dcache_mem_din0\[23\] +dcache_mem_din0\[24\] +dcache_mem_din0\[25\] +dcache_mem_din0\[26\] +dcache_mem_din0\[27\] +dcache_mem_din0\[28\] +dcache_mem_din0\[29\] +dcache_mem_din0\[30\] +dcache_mem_din0\[31\] -#N -sram0_clk0 250 0 2 +dcache_mem_dout0\[0\] 950 0 2 +dcache_mem_dout0\[1\] +dcache_mem_dout0\[2\] +dcache_mem_dout0\[3\] +dcache_mem_dout0\[4\] +dcache_mem_dout0\[5\] +dcache_mem_dout0\[6\] +dcache_mem_dout0\[7\] +dcache_mem_dout0\[8\] +dcache_mem_dout0\[9\] +dcache_mem_dout0\[10\] +dcache_mem_dout0\[11\] +dcache_mem_dout0\[12\] +dcache_mem_dout0\[13\] +dcache_mem_dout0\[14\] +dcache_mem_dout0\[15\] +dcache_mem_dout0\[16\] +dcache_mem_dout0\[17\] +dcache_mem_dout0\[18\] +dcache_mem_dout0\[19\] +dcache_mem_dout0\[20\] +dcache_mem_dout0\[21\] +dcache_mem_dout0\[22\] +dcache_mem_dout0\[23\] +dcache_mem_dout0\[24\] +dcache_mem_dout0\[25\] +dcache_mem_dout0\[26\] +dcache_mem_dout0\[27\] +dcache_mem_dout0\[28\] +dcache_mem_dout0\[29\] +dcache_mem_dout0\[30\] +dcache_mem_dout0\[31\] + +dcache_mem_clk1 1000 0 2 +dcache_mem_csb1 +dcache_mem_addr1\[8\] +dcache_mem_addr1\[7\] +dcache_mem_addr1\[6\] +dcache_mem_addr1\[5\] +dcache_mem_addr1\[4\] +dcache_mem_addr1\[3\] +dcache_mem_addr1\[2\] +dcache_mem_addr1\[1\] +dcache_mem_addr1\[0\] + +dcache_mem_dout1\[0\] 1050 0 2 +dcache_mem_dout1\[1\] +dcache_mem_dout1\[2\] +dcache_mem_dout1\[3\] +dcache_mem_dout1\[4\] +dcache_mem_dout1\[5\] +dcache_mem_dout1\[6\] +dcache_mem_dout1\[7\] +dcache_mem_dout1\[8\] +dcache_mem_dout1\[9\] +dcache_mem_dout1\[10\] +dcache_mem_dout1\[11\] +dcache_mem_dout1\[12\] +dcache_mem_dout1\[13\] +dcache_mem_dout1\[14\] +dcache_mem_dout1\[15\] +dcache_mem_dout1\[16\] +dcache_mem_dout1\[17\] +dcache_mem_dout1\[18\] +dcache_mem_dout1\[19\] +dcache_mem_dout1\[20\] +dcache_mem_dout1\[21\] +dcache_mem_dout1\[22\] +dcache_mem_dout1\[23\] +dcache_mem_dout1\[24\] +dcache_mem_dout1\[25\] +dcache_mem_dout1\[26\] +dcache_mem_dout1\[27\] +dcache_mem_dout1\[28\] +dcache_mem_dout1\[29\] +dcache_mem_dout1\[30\] +dcache_mem_dout1\[31\] + +#S +sram0_clk0 0 0 2 sram0_csb0 sram0_web0 sram0_addr0\[0\] @@ -325,7 +689,7 @@ sram0_din0\[31\] -sram0_dout0\[0\] 0350 0 2 +sram0_dout0\[0\] 0100 0 2 sram0_dout0\[1\] sram0_dout0\[2\] sram0_dout0\[3\] @@ -358,184 +722,7 @@ sram0_dout0\[30\] sram0_dout0\[31\] - -sram0_clk1 0450 0 2 -sram0_csb1 -sram0_addr1\[8\] -sram0_addr1\[7\] -sram0_addr1\[6\] -sram0_addr1\[5\] -sram0_addr1\[4\] -sram0_addr1\[3\] -sram0_addr1\[2\] -sram0_addr1\[1\] -sram0_addr1\[0\] - -sram0_dout1\[0\] 0550 0 2 -sram0_dout1\[1\] -sram0_dout1\[2\] -sram0_dout1\[3\] -sram0_dout1\[4\] -sram0_dout1\[5\] -sram0_dout1\[6\] -sram0_dout1\[7\] -sram0_dout1\[8\] -sram0_dout1\[9\] -sram0_dout1\[10\] -sram0_dout1\[11\] -sram0_dout1\[12\] -sram0_dout1\[13\] -sram0_dout1\[14\] -sram0_dout1\[15\] -sram0_dout1\[16\] -sram0_dout1\[17\] -sram0_dout1\[18\] -sram0_dout1\[19\] -sram0_dout1\[20\] -sram0_dout1\[21\] -sram0_dout1\[22\] -sram0_dout1\[23\] -sram0_dout1\[24\] -sram0_dout1\[25\] -sram0_dout1\[26\] -sram0_dout1\[27\] -sram0_dout1\[28\] -sram0_dout1\[29\] -sram0_dout1\[30\] -sram0_dout1\[31\] - - -sram1_clk0 1000 0 2 -sram1_csb0 -sram1_web0 -sram1_addr0\[0\] -sram1_addr0\[1\] -sram1_addr0\[2\] -sram1_addr0\[3\] -sram1_addr0\[4\] -sram1_addr0\[5\] -sram1_addr0\[6\] -sram1_addr0\[7\] -sram1_addr0\[8\] -sram1_wmask0\[0\] -sram1_wmask0\[1\] -sram1_wmask0\[2\] -sram1_wmask0\[3\] -sram1_din0\[0\] -sram1_din0\[1\] -sram1_din0\[2\] -sram1_din0\[3\] -sram1_din0\[4\] -sram1_din0\[5\] -sram1_din0\[6\] -sram1_din0\[7\] -sram1_din0\[8\] -sram1_din0\[9\] -sram1_din0\[10\] -sram1_din0\[11\] -sram1_din0\[12\] -sram1_din0\[13\] -sram1_din0\[14\] -sram1_din0\[15\] -sram1_din0\[16\] -sram1_din0\[17\] -sram1_din0\[18\] -sram1_din0\[19\] -sram1_din0\[20\] -sram1_din0\[21\] -sram1_din0\[22\] -sram1_din0\[23\] -sram1_din0\[24\] -sram1_din0\[25\] -sram1_din0\[26\] -sram1_din0\[27\] -sram1_din0\[28\] -sram1_din0\[29\] -sram1_din0\[30\] -sram1_din0\[31\] - - -sram1_dout0\[0\] 1100 0 2 -sram1_dout0\[1\] -sram1_dout0\[2\] -sram1_dout0\[3\] -sram1_dout0\[4\] -sram1_dout0\[5\] -sram1_dout0\[6\] -sram1_dout0\[7\] -sram1_dout0\[8\] -sram1_dout0\[9\] -sram1_dout0\[10\] -sram1_dout0\[11\] -sram1_dout0\[12\] -sram1_dout0\[13\] -sram1_dout0\[14\] -sram1_dout0\[15\] -sram1_dout0\[16\] -sram1_dout0\[17\] -sram1_dout0\[18\] -sram1_dout0\[19\] -sram1_dout0\[20\] -sram1_dout0\[21\] -sram1_dout0\[22\] -sram1_dout0\[23\] -sram1_dout0\[24\] -sram1_dout0\[25\] -sram1_dout0\[26\] -sram1_dout0\[27\] -sram1_dout0\[28\] -sram1_dout0\[29\] -sram1_dout0\[30\] -sram1_dout0\[31\] - - -sram1_clk1 1200 0 2 -sram1_csb1 -sram1_addr1\[8\] -sram1_addr1\[7\] -sram1_addr1\[6\] -sram1_addr1\[5\] -sram1_addr1\[4\] -sram1_addr1\[3\] -sram1_addr1\[2\] -sram1_addr1\[1\] -sram1_addr1\[0\] - -sram1_dout1\[0\] 1300 0 2 -sram1_dout1\[1\] -sram1_dout1\[2\] -sram1_dout1\[3\] -sram1_dout1\[4\] -sram1_dout1\[5\] -sram1_dout1\[6\] -sram1_dout1\[7\] -sram1_dout1\[8\] -sram1_dout1\[9\] -sram1_dout1\[10\] -sram1_dout1\[11\] -sram1_dout1\[12\] -sram1_dout1\[13\] -sram1_dout1\[14\] -sram1_dout1\[15\] -sram1_dout1\[16\] -sram1_dout1\[17\] -sram1_dout1\[18\] -sram1_dout1\[19\] -sram1_dout1\[20\] -sram1_dout1\[21\] -sram1_dout1\[22\] -sram1_dout1\[23\] -sram1_dout1\[24\] -sram1_dout1\[25\] -sram1_dout1\[26\] -sram1_dout1\[27\] -sram1_dout1\[28\] -sram1_dout1\[29\] -sram1_dout1\[30\] -sram1_dout1\[31\] - -#S -riscv_debug\[0\] 1000 0 2 +riscv_debug\[0\] 300 0 2 riscv_debug\[1\] riscv_debug\[2\] riscv_debug\[3\] @@ -601,7 +788,7 @@ riscv_debug\[63\] -wb_rst_n 1450 0 2 +wb_rst_n 500 0 2 pwrup_rst_n rst_n core_clk
diff --git a/signoff/mbist_wrapper/OPENLANE_VERSION b/signoff/mbist_wrapper/OPENLANE_VERSION new file mode 100644 index 0000000..80c7664 --- /dev/null +++ b/signoff/mbist_wrapper/OPENLANE_VERSION
@@ -0,0 +1 @@ +openlane N/A
diff --git a/signoff/mbist_wrapper/PDK_SOURCES b/signoff/mbist_wrapper/PDK_SOURCES new file mode 100644 index 0000000..ca3684a --- /dev/null +++ b/signoff/mbist_wrapper/PDK_SOURCES
@@ -0,0 +1,6 @@ +-ne openlane +8d686c081c2c9aefa16dbbd8ccf5bc8f4dcabc4b +-ne skywater-pdk +c094b6e83a4f9298e47f696ec5a7fd53535ec5eb +-ne open_pdks +14db32aa8ba330e88632ff3ad2ff52f4f4dae1ad
diff --git a/signoff/mbist_wrapper/final_summary_report.csv b/signoff/mbist_wrapper/final_summary_report.csv new file mode 100644 index 0000000..dde27c1 --- /dev/null +++ b/signoff/mbist_wrapper/final_summary_report.csv
@@ -0,0 +1,2 @@ +,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY +0,/project/openlane/mbist_wrapper,mbist_wrapper,mbist_wrapper,flow_completed,0h4m34s,-1,14342.857142857143,0.315,7171.428571428572,9.9,644.01,2259,0,0,0,0,0,0,-1,2,0,0,-1,167687,24265,-0.67,-5.59,-1,-1.19,-1,-0.67,-2630.72,-1,-1.19,-1,126574452.0,3.03,19.02,3.65,4.89,0.0,-1,1595,5654,730,4741,0,0,0,1483,0,0,0,0,0,0,0,4,737,586,15,138,4082,0,4220,90.9090909090909,11,10,AREA 0,4,50,1,140,140,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/pinmux/final_summary_report.csv b/signoff/pinmux/final_summary_report.csv index ed3dcac..a88c45c 100644 --- a/signoff/pinmux/final_summary_report.csv +++ b/signoff/pinmux/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h14m33s,-1,46109.09090909091,0.2475,23054.545454545456,27.06,725.12,5706,0,0,0,0,0,0,-1,1,0,-1,-1,429328,61246,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,317766216.0,6.39,43.04,33.51,11.97,0.39,-1,3574,8561,543,5529,0,0,0,4202,0,0,0,0,0,0,0,4,1343,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/pinmux,pinmux,pinmux,flow_completed,0h24m9s,-1,46109.09090909091,0.2475,23054.545454545456,27.06,722.6,5706,0,0,0,0,0,0,-1,1,0,-1,-1,429797,61501,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,317748797.0,6.41,43.62,33.59,11.07,0.27,-1,3574,8561,543,5529,0,0,0,4202,0,0,0,0,0,0,0,4,1343,1339,16,314,3259,0,3573,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.3,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/qspim/final_summary_report.csv b/signoff/qspim/final_summary_report.csv index 48489c6..e17c115 100644 --- a/signoff/qspim/final_summary_report.csv +++ b/signoff/qspim/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h12m38s,-1,69827.27272727272,0.22,34913.63636363636,40.98,754.58,7681,0,0,0,0,0,0,-1,1,0,-1,-1,362731,71425,0.0,-4.04,-1,0.0,-1,0.0,-2134.37,-1,0.0,-1,233420632.0,13.69,38.63,39.31,3.37,1.13,-1,6480,9736,734,3989,0,0,0,7426,0,0,0,0,0,0,0,4,1895,2312,21,388,2940,0,3328,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.42,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/qspim,qspim_top,qspim,flow_completed,0h20m0s,-1,65850.50505050505,0.2475,32925.25252525252,37.63,745.37,8149,0,0,0,0,0,0,-1,1,0,-1,-1,373982,74376,0.0,-4.44,-1,0.0,-1,0.0,-2107.85,-1,0.0,-1,236380045.0,0.0,37.41,33.44,4.51,0.78,-1,7004,10337,741,4073,0,0,0,7930,0,0,0,0,0,0,0,4,1937,2441,22,388,3234,0,3622,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.42,0.0,sky130_fd_sc_hd,4,4
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index 221a94b..a82158b 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h40m57s,-1,2.529576587795766,10.2784,1.264788293897883,-1,530.45,13,0,0,0,0,0,0,-1,0,0,-1,-1,1176117,8176,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,40144.36,3.16,3.65,0.41,0.63,-1,272,2536,272,2536,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,180,90,0.55,0.0,sky130_fd_sc_hd,4,0 +0,/project/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow_completed,0h49m1s,-1,2.724159402241594,10.2784,1.362079701120797,-1,538.05,14,0,0,0,0,0,0,-1,0,0,-1,-1,1480871,10235,0.0,-1,-1,0.0,-1,0.0,-1,-1,0.0,-1,-1,64380.84,4.37,5.34,0.99,0.77,-1,313,2874,313,2874,0,0,0,14,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,90.9090909090909,11,10,AREA 0,5,50,1,100,90,0.55,0.0,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_interconnect/final_summary_report.csv b/signoff/wb_interconnect/final_summary_report.csv index de2a952..af52d28 100644 --- a/signoff/wb_interconnect/final_summary_report.csv +++ b/signoff/wb_interconnect/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h8m25s,-1,10670.454545454546,0.35200000000000004,5335.227272727273,4.18,656.2,1878,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,595153,26667,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,524917517.0,43.3,14.09,52.85,1.35,22.33,-1,948,3082,178,2312,0,0,0,1249,0,0,0,0,0,0,0,4,439,494,10,1600,4411,0,6011,90.9090909090909,11,10,AREA 0,2,50,1,100,100,0.5,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/wb_interconnect,wb_interconnect,wb_interconnect,flow_completed,0h17m1s,-1,19817.391304347824,0.46,9908.695652173912,9.26,733.2,4558,0,-1,-1,-1,-1,0,0,1,0,-1,-1,845641,51327,-1.0,-9.35,-1,-0.57,-1,-120.98,-2527.7,-1,-31.1,-1,738740222.0,0.0,15.77,51.42,2.18,44.71,0.0,1769,5285,252,3767,0,0,0,2675,0,0,0,0,0,0,0,4,1191,1078,18,1674,5873,0,7547,90.9090909090909,11,10,AREA 0,2,50,1,153.6,153.18,0.3,0,sky130_fd_sc_hd,4,4
diff --git a/signoff/yifive/final_summary_report.csv b/signoff/yifive/final_summary_report.csv index bc3a2be..25aa043 100644 --- a/signoff/yifive/final_summary_report.csv +++ b/signoff/yifive/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,0h38m35s,-1,53646.25506072874,0.7904,26823.12753036437,30.96,1188.15,21201,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,1626736,237479,-1.77,-17.38,-1,0.0,-1,-2145.74,-21120.0,-1,0.0,-1,1293377672.0,0.0,62.57,24.05,22.6,0.0,-1,18589,30059,1068,12431,0,0,0,21971,0,0,0,0,0,0,0,4,5240,5924,49,366,10822,0,11188,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.32,0.0,sky130_fd_sc_hd,4,4 +0,/project/openlane/yifive,ycr1_top_wb,yifive,flow_completed,1h36m1s,-1,58992.183908045976,1.0875,29496.091954022988,33.75,1525.48,32077,0,-1,-1,-1,-1,0,-1,1,0,-1,-1,2442216,371640,-27.11,-54.85,-1,-9.94,-1,-72257.27,-140592.75,-1,-4304.53,-1,1669037052.0,11.0,44.4,52.11,9.29,10.28,-1,26877,46216,1728,20697,0,0,0,32103,0,0,0,0,0,0,0,4,7879,8416,55,1050,15019,0,16069,90.9090909090909,11,10,AREA 0,4,50,1,100,100,0.4,0.0,sky130_fd_sc_hd,4,4
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v index fbad972..faa6d8c 100644 --- a/verilog/dv/user_basic/user_basic_tb.v +++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -242,8 +242,8 @@ wb_user_core_write('h3080_0000,'h1); wb_user_core_read_check(32'h30020058,read_data,32'h8273_8343); - wb_user_core_read_check(32'h3002005C,read_data,32'h1501_2022); - wb_user_core_read_check(32'h30020060,read_data,32'h0003_1000); + wb_user_core_read_check(32'h3002005C,read_data,32'h0202_2022); + wb_user_core_read_check(32'h30020060,read_data,32'h0003_2000); end
diff --git a/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv b/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv index c838f52..77e50d4 100644 --- a/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv +++ b/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv
@@ -90,7 +90,6 @@ // WB I/F input wire wb_clk_i, // System clock input wire wb_clk2_i, // System clock2 is no cts - input wire wb_cyc_i, // strobe/request input wire wb_stb_i, // strobe/request input wire [(BIST_NO_SRAM+1)/2-1:0] wb_cs_i, input wire [BIST_ADDR_WD-1:0] wb_adr_i, // address @@ -102,9 +101,40 @@ output wire [BIST_DATA_WD-1:0] wb_dat_o, // data input output wire wb_ack_o, // acknowlegement output wire wb_lack_o, // acknowlegement - output wire wb_err_o // error + output wire wb_err_o, // error + // towards memory + // PORT-A + output wire [BIST_NO_SRAM-1:0] mem_clk_a, + output wire [BIST_ADDR_WD-1:0] mem_addr_a0, + output wire [BIST_ADDR_WD-1:0] mem_addr_a1, + output wire [BIST_ADDR_WD-1:0] mem_addr_a2, + output wire [BIST_ADDR_WD-1:0] mem_addr_a3, + output wire [BIST_NO_SRAM-1:0] mem_cen_a, + output wire [BIST_NO_SRAM-1:0] mem_web_a, + output wire [BIST_DATA_WD/8-1:0] mem_mask_a0, + output wire [BIST_DATA_WD/8-1:0] mem_mask_a1, + output wire [BIST_DATA_WD/8-1:0] mem_mask_a2, + output wire [BIST_DATA_WD/8-1:0] mem_mask_a3, + output wire [BIST_DATA_WD-1:0] mem_din_a0, + output wire [BIST_DATA_WD-1:0] mem_din_a1, + output wire [BIST_DATA_WD-1:0] mem_din_a2, + output wire [BIST_DATA_WD-1:0] mem_din_a3, + + input wire [BIST_DATA_WD-1:0] mem_dout_a0, + input wire [BIST_DATA_WD-1:0] mem_dout_a1, + input wire [BIST_DATA_WD-1:0] mem_dout_a2, + input wire [BIST_DATA_WD-1:0] mem_dout_a3, + + + // PORT-B + output wire [BIST_NO_SRAM-1:0] mem_clk_b, + output wire [BIST_NO_SRAM-1:0] mem_cen_b, + output wire [BIST_ADDR_WD-1:0] mem_addr_b0, + output wire [BIST_ADDR_WD-1:0] mem_addr_b1, + output wire [BIST_ADDR_WD-1:0] mem_addr_b2, + output wire [BIST_ADDR_WD-1:0] mem_addr_b3 @@ -113,44 +143,6 @@ parameter NO_SRAM_WD = (BIST_NO_SRAM+1)/2; parameter BIST1_ADDR_WD = 11; // 512x32 SRAM -// FUNCTIONAL PORT -// towards memory MBIST1 -// PORT-A -wire [BIST_NO_SRAM-1:0] mem_clk_a; -wire [BIST1_ADDR_WD-1:2] mem0_addr_a; -wire [BIST1_ADDR_WD-1:2] mem1_addr_a; -wire [BIST1_ADDR_WD-1:2] mem2_addr_a; -wire [BIST1_ADDR_WD-1:2] mem3_addr_a; -wire [BIST_NO_SRAM-1:0] mem_cen_a; -wire [BIST_NO_SRAM-1:0] mem_web_a; -wire [BIST_DATA_WD/8-1:0] mem0_mask_a; -wire [BIST_DATA_WD/8-1:0] mem1_mask_a; -wire [BIST_DATA_WD/8-1:0] mem2_mask_a; -wire [BIST_DATA_WD/8-1:0] mem3_mask_a; -wire [BIST_DATA_WD-1:0] mem0_din_a; -wire [BIST_DATA_WD-1:0] mem1_din_a; -wire [BIST_DATA_WD-1:0] mem2_din_a; -wire [BIST_DATA_WD-1:0] mem3_din_a; -wire [BIST_DATA_WD-1:0] mem0_dout_a; -wire [BIST_DATA_WD-1:0] mem1_dout_a; -wire [BIST_DATA_WD-1:0] mem2_dout_a; -wire [BIST_DATA_WD-1:0] mem3_dout_a; - -// PORT-B -wire [BIST_NO_SRAM-1:0] mem_clk_b; -wire [BIST_NO_SRAM-1:0] mem_cen_b; -wire [BIST1_ADDR_WD-1:2] mem0_addr_b; -wire [BIST1_ADDR_WD-1:2] mem1_addr_b; -wire [BIST1_ADDR_WD-1:2] mem2_addr_b; -wire [BIST1_ADDR_WD-1:2] mem3_addr_b; - -logic mem_req; -logic [(BIST_NO_SRAM+1)/2-1:0] mem_cs; -logic [BIST_ADDR_WD-1:0] mem_addr; -logic [31:0] mem_wdata; -logic mem_we; -logic [3:0] mem_wmask; -logic [31:0] mem_rdata; mbist_wb #( .BIST_NO_SRAM (4 ), @@ -280,7 +272,7 @@ ); - +/** sky130_sram_2kbyte_1rw1r_32x512_8 u_sram0_2kb( `ifdef USE_POWER_PINS .vccd1 (vccd1),// User area 1 1.8V supply @@ -362,5 +354,8 @@ .dout1 () ); + +***/ + endmodule
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v index efe14c3..3e91285 100644 --- a/verilog/rtl/user_project_wrapper.v +++ b/verilog/rtl/user_project_wrapper.v
@@ -31,7 +31,8 @@ //// 4. UART //// //// 5, USB 1.1 //// //// 6. SPI Master (Single) //// -//// 7. SRAM 2KB //// +//// 7. TCM SRAM 2KB //// +//// 8. 2KB icache and 2KB dcache //// //// 8. 6 Channel ADC //// //// 9. Pinmux with GPIO and 6 PWM //// //// //// @@ -232,384 +233,412 @@ // Local Parameter Declaration // -------------------------------------------------- -parameter BIST_NO_SRAM= 4; // NO of MBIST MEMORY -parameter SDR_DW = 8; // SDR Data Width -parameter SDR_BW = 1; // SDR Byte Width -parameter WB_WIDTH = 32; // WB ADDRESS/DARA WIDTH +parameter BIST_NO_SRAM = 4; // NO of MBIST MEMORY +parameter SDR_DW = 8; // SDR Data Width +parameter SDR_BW = 1; // SDR Byte Width +parameter WB_WIDTH = 32; // WB ADDRESS/DARA WIDTH parameter BIST1_ADDR_WD = 11; // 512x32 SRAM -parameter BIST_DATA_WD = 32; +parameter BIST_DATA_WD = 32; //--------------------------------------------------------------------- // Wishbone Risc V Dcache Memory Interface //--------------------------------------------------------------------- -wire wbd_riscv_dcache_stb_i; // strobe/request -wire [WB_WIDTH-1:0] wbd_riscv_dcache_adr_i; // address -wire wbd_riscv_dcache_we_i; // write -wire [WB_WIDTH-1:0] wbd_riscv_dcache_dat_i; // data output -wire [3:0] wbd_riscv_dcache_sel_i; // byte enable -wire [9:0] wbd_riscv_dcache_bl_i; // burst length -wire wbd_riscv_dcache_bry_i; // burst ready -wire [WB_WIDTH-1:0] wbd_riscv_dcache_dat_o; // data input -wire wbd_riscv_dcache_ack_o; // acknowlegement -wire wbd_riscv_dcache_lack_o;// last burst acknowlegement -wire wbd_riscv_dcache_err_o; // error +wire wbd_riscv_dcache_stb_i ; // strobe/request +wire [WB_WIDTH-1:0] wbd_riscv_dcache_adr_i ; // address +wire wbd_riscv_dcache_we_i ; // write +wire [WB_WIDTH-1:0] wbd_riscv_dcache_dat_i ; // data output +wire [3:0] wbd_riscv_dcache_sel_i ; // byte enable +wire [9:0] wbd_riscv_dcache_bl_i ; // burst length +wire wbd_riscv_dcache_bry_i ; // burst ready +wire [WB_WIDTH-1:0] wbd_riscv_dcache_dat_o ; // data input +wire wbd_riscv_dcache_ack_o ; // acknowlegement +wire wbd_riscv_dcache_lack_o ; // last burst acknowlegement +wire wbd_riscv_dcache_err_o ; // error +// CACHE SRAM Memory I/F +wire dcache_mem_clk0 ; // CLK +wire dcache_mem_csb0 ; // CS# +wire dcache_mem_web0 ; // WE# +wire [8:0] dcache_mem_addr0 ; // Address +wire [3:0] dcache_mem_wmask0 ; // WMASK# +wire [31:0] dcache_mem_din0 ; // Write Data +wire [31:0] dcache_mem_dout0 ; // Read Data + +// SRAM-0 PORT-1, IMEM I/F +wire dcache_mem_clk1 ; // CLK +wire dcache_mem_csb1 ; // CS# +wire [8:0] dcache_mem_addr1 ; // Address +wire [31:0] dcache_mem_dout1 ; // Read Data //--------------------------------------------------------------------- // Wishbone Risc V Icache Memory Interface //--------------------------------------------------------------------- -wire wbd_riscv_icache_stb_i; // strobe/request -wire [WB_WIDTH-1:0] wbd_riscv_icache_adr_i; // address -wire wbd_riscv_icache_we_i; // write -wire [WB_WIDTH-1:0] wbd_riscv_icache_dat_i; // data output -wire [3:0] wbd_riscv_icache_sel_i; // byte enable -wire [9:0] wbd_riscv_icache_bl_i; // burst length -wire wbd_riscv_icache_bry_i; // burst ready -wire [WB_WIDTH-1:0] wbd_riscv_icache_dat_o; // data input -wire wbd_riscv_icache_ack_o; // acknowlegement -wire wbd_riscv_icache_lack_o;// last burst acknowlegement -wire wbd_riscv_icache_err_o; // error +wire wbd_riscv_icache_stb_i ; // strobe/request +wire [WB_WIDTH-1:0] wbd_riscv_icache_adr_i ; // address +wire wbd_riscv_icache_we_i ; // write +wire [3:0] wbd_riscv_icache_sel_i ; // byte enable +wire [9:0] wbd_riscv_icache_bl_i ; // burst length +wire wbd_riscv_icache_bry_i ; // burst ready +wire [WB_WIDTH-1:0] wbd_riscv_icache_dat_o ; // data input +wire wbd_riscv_icache_ack_o ; // acknowlegement +wire wbd_riscv_icache_lack_o ; // last burst acknowlegement +wire wbd_riscv_icache_err_o ; // error + +// CACHE SRAM Memory I/F +wire icache_mem_clk0 ; // CLK +wire icache_mem_csb0 ; // CS# +wire icache_mem_web0 ; // WE# +wire [8:0] icache_mem_addr0 ; // Address +wire [3:0] icache_mem_wmask0 ; // WMASK# +wire [31:0] icache_mem_din0 ; // Write Data +// wire [31:0] icache_mem_dout0 ; // Read Data + +// SRAM-0 PORT-1, IMEM I/F +wire icache_mem_clk1 ; // CLK +wire icache_mem_csb1 ; // CS# +wire [8:0] icache_mem_addr1 ; // Address +wire [31:0] icache_mem_dout1 ; // Read Data //--------------------------------------------------------------------- // RISC V Wishbone Data Memory Interface //--------------------------------------------------------------------- -wire wbd_riscv_dmem_stb_i; // strobe/request -wire [WB_WIDTH-1:0] wbd_riscv_dmem_adr_i; // address -wire wbd_riscv_dmem_we_i; // write -wire [WB_WIDTH-1:0] wbd_riscv_dmem_dat_i; // data output -wire [3:0] wbd_riscv_dmem_sel_i; // byte enable -wire [WB_WIDTH-1:0] wbd_riscv_dmem_dat_o; // data input -wire wbd_riscv_dmem_ack_o; // acknowlegement -wire wbd_riscv_dmem_err_o; // error +wire wbd_riscv_dmem_stb_i ; // strobe/request +wire [WB_WIDTH-1:0] wbd_riscv_dmem_adr_i ; // address +wire wbd_riscv_dmem_we_i ; // write +wire [WB_WIDTH-1:0] wbd_riscv_dmem_dat_i ; // data output +wire [3:0] wbd_riscv_dmem_sel_i ; // byte enable +wire [WB_WIDTH-1:0] wbd_riscv_dmem_dat_o ; // data input +wire wbd_riscv_dmem_ack_o ; // acknowlegement +wire wbd_riscv_dmem_err_o ; // error //--------------------------------------------------------------------- // WB HOST Interface //--------------------------------------------------------------------- -wire wbd_int_cyc_i; // strobe/request -wire wbd_int_stb_i; // strobe/request -wire [WB_WIDTH-1:0] wbd_int_adr_i; // address -wire wbd_int_we_i; // write -wire [WB_WIDTH-1:0] wbd_int_dat_i; // data output -wire [3:0] wbd_int_sel_i; // byte enable -wire [WB_WIDTH-1:0] wbd_int_dat_o; // data input -wire wbd_int_ack_o; // acknowlegement -wire wbd_int_err_o; // error +wire wbd_int_cyc_i ; // strobe/request +wire wbd_int_stb_i ; // strobe/request +wire [WB_WIDTH-1:0] wbd_int_adr_i ; // address +wire wbd_int_we_i ; // write +wire [WB_WIDTH-1:0] wbd_int_dat_i ; // data output +wire [3:0] wbd_int_sel_i ; // byte enable +wire [WB_WIDTH-1:0] wbd_int_dat_o ; // data input +wire wbd_int_ack_o ; // acknowlegement +wire wbd_int_err_o ; // error //--------------------------------------------------------------------- // SPI Master Wishbone Interface //--------------------------------------------------------------------- -wire wbd_spim_stb_o; // strobe/request -wire [WB_WIDTH-1:0] wbd_spim_adr_o; // address -wire wbd_spim_we_o; // write -wire [WB_WIDTH-1:0] wbd_spim_dat_o; // data output -wire [3:0] wbd_spim_sel_o; // byte enable -wire [9:0] wbd_spim_bl_o; // Burst count -wire wbd_spim_bry_o; // Busrt Ready -wire wbd_spim_cyc_o ; -wire [WB_WIDTH-1:0] wbd_spim_dat_i; // data input -wire wbd_spim_ack_i; // acknowlegement -wire wbd_spim_lack_i;// Last acknowlegement -wire wbd_spim_err_i; // error +wire wbd_spim_stb_o ; // strobe/request +wire [WB_WIDTH-1:0] wbd_spim_adr_o ; // address +wire wbd_spim_we_o ; // write +wire [WB_WIDTH-1:0] wbd_spim_dat_o ; // data output +wire [3:0] wbd_spim_sel_o ; // byte enable +wire [9:0] wbd_spim_bl_o ; // Burst count +wire wbd_spim_bry_o ; // Busrt Ready +wire wbd_spim_cyc_o ; +wire [WB_WIDTH-1:0] wbd_spim_dat_i ; // data input +wire wbd_spim_ack_i ; // acknowlegement +wire wbd_spim_lack_i ; // Last acknowlegement +wire wbd_spim_err_i ; // error //--------------------------------------------------------------------- // SPI Master Wishbone Interface //--------------------------------------------------------------------- -wire wbd_adc_stb_o ; -wire [7:0] wbd_adc_adr_o ; -wire wbd_adc_we_o ; // 1 - Write, 0 - Read -wire [WB_WIDTH-1:0] wbd_adc_dat_o ; -wire [WB_WIDTH/8-1:0] wbd_adc_sel_o ; // Byte enable -wire wbd_adc_cyc_o ; -wire [2:0] wbd_adc_cti_o ; -wire [WB_WIDTH-1:0] wbd_adc_dat_i ; -wire wbd_adc_ack_i ; +wire wbd_adc_stb_o ; +wire [7:0] wbd_adc_adr_o ; +wire wbd_adc_we_o ; // 1 - Write, 0 - Read +wire [WB_WIDTH-1:0] wbd_adc_dat_o ; +wire [WB_WIDTH/8-1:0] wbd_adc_sel_o ; // Byte enable +wire wbd_adc_cyc_o ; +wire [2:0] wbd_adc_cti_o ; +wire [WB_WIDTH-1:0] wbd_adc_dat_i ; +wire wbd_adc_ack_i ; //--------------------------------------------------------------------- // Global Register Wishbone Interface //--------------------------------------------------------------------- -wire wbd_glbl_stb_o; // strobe/request -wire [7:0] wbd_glbl_adr_o; // address -wire wbd_glbl_we_o; // write -wire [WB_WIDTH-1:0] wbd_glbl_dat_o; // data output -wire [3:0] wbd_glbl_sel_o; // byte enable -wire wbd_glbl_cyc_o ; -wire [WB_WIDTH-1:0] wbd_glbl_dat_i; // data input -wire wbd_glbl_ack_i; // acknowlegement -wire wbd_glbl_err_i; // error +wire wbd_glbl_stb_o ; // strobe/request +wire [7:0] wbd_glbl_adr_o ; // address +wire wbd_glbl_we_o ; // write +wire [WB_WIDTH-1:0] wbd_glbl_dat_o ; // data output +wire [3:0] wbd_glbl_sel_o ; // byte enable +wire wbd_glbl_cyc_o ; +wire [WB_WIDTH-1:0] wbd_glbl_dat_i ; // data input +wire wbd_glbl_ack_i ; // acknowlegement +wire wbd_glbl_err_i ; // error //--------------------------------------------------------------------- // Global Register Wishbone Interface //--------------------------------------------------------------------- -wire wbd_uart_stb_o; // strobe/request -wire [7:0] wbd_uart_adr_o; // address -wire wbd_uart_we_o; // write -wire [31:0] wbd_uart_dat_o; // data output -wire [3:0] wbd_uart_sel_o; // byte enable -wire wbd_uart_cyc_o ; -wire [31:0] wbd_uart_dat_i; // data input -wire wbd_uart_ack_i; // acknowlegement -wire wbd_uart_err_i; // error +wire wbd_uart_stb_o ; // strobe/request +wire [7:0] wbd_uart_adr_o ; // address +wire wbd_uart_we_o ; // write +wire [31:0] wbd_uart_dat_o ; // data output +wire [3:0] wbd_uart_sel_o ; // byte enable +wire wbd_uart_cyc_o ; +wire [31:0] wbd_uart_dat_i ; // data input +wire wbd_uart_ack_i ; // acknowlegement +wire wbd_uart_err_i ; // error //--------------------------------------------------------------------- // MBIST1 //--------------------------------------------------------------------- -wire wbd_mbist_stb_o; // strobe/request -wire [12:0] wbd_mbist_adr_o; // address -wire wbd_mbist_we_o; // write -wire [WB_WIDTH-1:0] wbd_mbist_dat_o; // data output -wire [3:0] wbd_mbist_sel_o; // byte enable -wire [9:0] wbd_mbist_bl_o; // byte enable -wire wbd_mbist_bry_o; // byte enable -wire wbd_mbist_cyc_o ; -wire [WB_WIDTH-1:0] wbd_mbist_dat_i; // data input -wire wbd_mbist_ack_i; // acknowlegement -wire wbd_mbist_lack_i; // acknowlegement -wire wbd_mbist_err_i; // error +wire wbd_mbist_stb_o ; // strobe/request +wire [12:0] wbd_mbist_adr_o ; // address +wire wbd_mbist_we_o ; // write +wire [WB_WIDTH-1:0] wbd_mbist_dat_o ; // data output +wire [3:0] wbd_mbist_sel_o ; // byte enable +wire [9:0] wbd_mbist_bl_o ; // byte enable +wire wbd_mbist_bry_o ; // byte enable +wire wbd_mbist_cyc_o ; +wire [WB_WIDTH-1:0] wbd_mbist_dat_i ; // data input +wire wbd_mbist_ack_i ; // acknowlegement +wire wbd_mbist_lack_i ; // acknowlegement +wire wbd_mbist_err_i ; // error //---------------------------------------------------- // CPU Configuration //---------------------------------------------------- -wire cpu_rst_n ; -wire qspim_rst_n ; -wire sspim_rst_n ; -wire uart_rst_n ;// uart reset -wire i2c_rst_n ;// i2c reset -wire usb_rst_n ;// i2c reset -wire [3:0] boot_remap ;// Boot Remap -wire [3:0] dcache_remap ;// Remap the dcache address -wire cpu_clk ; -wire rtc_clk ; -wire usb_clk ; -wire wbd_clk_int ; +wire cpu_rst_n ; +wire qspim_rst_n ; +wire sspim_rst_n ; +wire uart_rst_n ; // uart reset +wire i2c_rst_n ; // i2c reset +wire usb_rst_n ; // i2c reset +wire [3:0] boot_remap ; // Boot Remap +wire [3:0] dcache_remap ; // Remap the dcache address +wire cpu_clk ; +wire rtc_clk ; +wire usb_clk ; +wire wbd_clk_int ; -wire wbd_clk_pinmux ; -//wire wbd_clk_int1 ; -//wire wbd_clk_int2 ; -wire wbd_int_rst_n ; -//wire wbd_int1_rst_n ; -//wire wbd_int2_rst_n ; +wire wbd_clk_pinmux ; +//wire wbd_clk_int1 ; +//wire wbd_clk_int2 ; +wire wbd_int_rst_n ; +//wire wbd_int1_rst_n ; +//wire wbd_int2_rst_n ; -wire [31:0] fuse_mhartid ; -wire [15:0] irq_lines ; -wire soft_irq ; +wire [31:0] fuse_mhartid ; +wire [15:0] irq_lines ; +wire soft_irq ; -wire [7:0] cfg_glb_ctrl ; -wire [31:0] cfg_clk_ctrl1 ; -wire [31:0] cfg_clk_ctrl2 ; -wire [3:0] cfg_cska_wi ; // clock skew adjust for wishbone interconnect -wire [3:0] cfg_cska_wh ; // clock skew adjust for web host +wire [7:0] cfg_glb_ctrl ; +wire [31:0] cfg_clk_ctrl1 ; +wire [31:0] cfg_clk_ctrl2 ; +wire [3:0] cfg_cska_wi ; // clock skew adjust for wishbone interconnect +wire [3:0] cfg_cska_wh ; // clock skew adjust for web host -wire [3:0] cfg_cska_riscv; // clock skew adjust for riscv -wire [3:0] cfg_cska_uart ; // clock skew adjust for uart -wire [3:0] cfg_cska_qspi ; // clock skew adjust for spi -wire [3:0] cfg_cska_pinmux; // clock skew adjust for pinmux -wire [3:0] cfg_cska_qspi_co ; // clock skew adjust for global reg -wire [3:0] cfg_cska_mbist1; -wire [3:0] cfg_cska_mbist2; -wire [3:0] cfg_cska_mbist3; -wire [3:0] cfg_cska_mbist4; +wire [3:0] cfg_cska_riscv ; // clock skew adjust for riscv +wire [3:0] cfg_cska_uart ; // clock skew adjust for uart +wire [3:0] cfg_cska_qspi ; // clock skew adjust for spi +wire [3:0] cfg_cska_pinmux ; // clock skew adjust for pinmux +wire [3:0] cfg_cska_qspi_co ; // clock skew adjust for global reg +wire [3:0] cfg_cska_mbist1 ; +wire [3:0] cfg_cska_mbist2 ; +wire [3:0] cfg_cska_mbist3 ; +wire [3:0] cfg_cska_mbist4 ; // Bus Repeater Signals output from Wishbone Interface -wire [3:0] cfg_cska_riscv_rp ; // clock skew adjust for riscv -wire [3:0] cfg_cska_uart_rp ; // clock skew adjust for uart -wire [3:0] cfg_cska_qspi_rp ; // clock skew adjust for spi -wire [3:0] cfg_cska_pinmux_rp ; // clock skew adjust for pinmux -wire [3:0] cfg_cska_qspi_co_rp; // clock skew adjust for global reg -wire [3:0] cfg_cska_mbist1_rp ; -wire [3:0] cfg_cska_mbist2_rp ; -wire [3:0] cfg_cska_mbist3_rp ; -wire [3:0] cfg_cska_mbist4_rp ; +wire [3:0] cfg_cska_riscv_rp ; // clock skew adjust for riscv +wire [3:0] cfg_cska_uart_rp ; // clock skew adjust for uart +wire [3:0] cfg_cska_qspi_rp ; // clock skew adjust for spi +wire [3:0] cfg_cska_pinmux_rp ; // clock skew adjust for pinmux +wire [3:0] cfg_cska_qspi_co_rp ; // clock skew adjust for global reg +wire [3:0] cfg_cska_mbist1_rp ; +wire [3:0] cfg_cska_mbist2_rp ; +wire [3:0] cfg_cska_mbist3_rp ; +wire [3:0] cfg_cska_mbist4_rp ; -wire [31:0] fuse_mhartid_rp ; // Repeater -wire [15:0] irq_lines_rp ; // Repeater -wire soft_irq_rp ; // Repeater +wire [31:0] fuse_mhartid_rp ; // Repeater +wire [15:0] irq_lines_rp ; // Repeater +wire soft_irq_rp ; // Repeater -wire wbd_clk_risc_rp ; -wire wbd_clk_qspi_rp ; -wire wbd_clk_uart_rp ; -wire wbd_clk_pinmux_rp ; -wire wbd_clk_mbist1_rp ; -wire wbd_clk_mbist2_rp ; -wire wbd_clk_mbist3_rp ; -wire wbd_clk_mbist4_rp ; +wire wbd_clk_risc_rp ; +wire wbd_clk_qspi_rp ; +wire wbd_clk_uart_rp ; +wire wbd_clk_pinmux_rp ; +wire wbd_clk_mbist1_rp ; +wire wbd_clk_mbist2_rp ; +wire wbd_clk_mbist3_rp ; +wire wbd_clk_mbist4_rp ; // Progammable Clock Skew inserted signals -wire wbd_clk_wi_skew ; // clock for wishbone interconnect with clock skew -wire wbd_clk_riscv_skew ; // clock for riscv with clock skew -wire wbd_clk_uart_skew ; // clock for uart with clock skew -wire wbd_clk_spi_skew ; // clock for spi with clock skew -wire wbd_clk_glbl_skew ; // clock for global reg with clock skew -wire wbd_clk_wh_skew ; // clock for global reg -wire wbd_clk_mbist_skew; // clock for global reg -wire wbd_clk_mbist2_skew; // clock for global reg -wire wbd_clk_mbist3_skew; // clock for global reg -wire wbd_clk_mbist4_skew; // clock for global reg +wire wbd_clk_wi_skew ; // clock for wishbone interconnect with clock skew +wire wbd_clk_riscv_skew ; // clock for riscv with clock skew +wire wbd_clk_uart_skew ; // clock for uart with clock skew +wire wbd_clk_spi_skew ; // clock for spi with clock skew +wire wbd_clk_glbl_skew ; // clock for global reg with clock skew +wire wbd_clk_wh_skew ; // clock for global reg +wire wbd_clk_mbist_skew ; // clock for global reg +wire wbd_clk_mbist2_skew ; // clock for global reg +wire wbd_clk_mbist3_skew ; // clock for global reg +wire wbd_clk_mbist4_skew ; // clock for global reg -wire [31:0] spi_debug ; -wire [31:0] pinmux_debug ; -wire [63:0] riscv_debug ; +wire [31:0] spi_debug ; +wire [31:0] pinmux_debug ; +wire [63:0] riscv_debug ; // SFLASH I/F -wire sflash_sck ; -wire sflash_ss ; -wire [3:0] sflash_oen ; -wire [3:0] sflash_do ; -wire [3:0] sflash_di ; +wire sflash_sck ; +wire sflash_ss ; +wire [3:0] sflash_oen ; +wire [3:0] sflash_do ; +wire [3:0] sflash_di ; // SSRAM I/F -//wire ssram_sck ; -//wire ssram_ss ; -//wire ssram_oen ; -//wire [3:0] ssram_do ; -//wire [3:0] ssram_di ; +//wire ssram_sck ; +//wire ssram_ss ; +//wire ssram_oen ; +//wire [3:0] ssram_do ; +//wire [3:0] ssram_di ; // USB I/F -wire usb_dp_o ; -wire usb_dn_o ; -wire usb_oen ; -wire usb_dp_i ; -wire usb_dn_i ; +wire usb_dp_o ; +wire usb_dn_o ; +wire usb_oen ; +wire usb_dp_i ; +wire usb_dn_i ; // UART I/F -wire uart_txd ; -wire uart_rxd ; +wire uart_txd ; +wire uart_rxd ; // I2CM I/F -wire i2cm_clk_o ; -wire i2cm_clk_i ; -wire i2cm_clk_oen ; -wire i2cm_data_oen ; -wire i2cm_data_o ; -wire i2cm_data_i ; +wire i2cm_clk_o ; +wire i2cm_clk_i ; +wire i2cm_clk_oen ; +wire i2cm_data_oen ; +wire i2cm_data_o ; +wire i2cm_data_i ; // SPI MASTER -wire spim_sck ; -wire spim_ss ; -wire spim_miso ; -wire spim_mosi ; +wire spim_sck ; +wire spim_ss ; +wire spim_miso ; +wire spim_mosi ; -wire [7:0] sar2dac ; -wire analog_dac_out ; -wire pulse1m_mclk ; -wire h_reset_n ; +wire [7:0] sar2dac ; +wire analog_dac_out ; +wire pulse1m_mclk ; +wire h_reset_n ; `ifndef SCR1_TCM_MEM // SRAM-0 PORT-0 - DMEM I/F -wire sram0_clk0 ; // CLK -wire sram0_csb0 ; // CS# -wire sram0_web0 ; // WE# -wire [8:0] sram0_addr0 ; // Address -wire [3:0] sram0_wmask0 ; // WMASK# -wire [31:0] sram0_din0 ; // Write Data -wire [31:0] sram0_dout0 ; // Read Data +wire sram0_clk0 ; // CLK +wire sram0_csb0 ; // CS# +wire sram0_web0 ; // WE# +wire [8:0] sram0_addr0 ; // Address +wire [3:0] sram0_wmask0 ; // WMASK# +wire [31:0] sram0_din0 ; // Write Data +wire [31:0] sram0_dout0 ; // Read Data // SRAM-0 PORT-1, IMEM I/F -wire sram0_clk1 ; // CLK -wire sram0_csb1 ; // CS# -wire [8:0] sram0_addr1 ; // Address -wire [31:0] sram0_dout1 ; // Read Data +wire sram0_clk1 ; // CLK +wire sram0_csb1 ; // CS# +wire [8:0] sram0_addr1 ; // Address +wire [31:0] sram0_dout1 ; // Read Data // SRAM-1 PORT-0 - DMEM I/F -wire sram1_clk0 ; // CLK -wire sram1_csb0 ; // CS# -wire sram1_web0 ; // WE# -wire [8:0] sram1_addr0 ; // Address -wire [3:0] sram1_wmask0 ; // WMASK# -wire [31:0] sram1_din0 ; // Write Data -wire [31:0] sram1_dout0 ; // Read Data +wire sram1_clk0 ; // CLK +wire sram1_csb0 ; // CS# +wire sram1_web0 ; // WE# +wire [8:0] sram1_addr0 ; // Address +wire [3:0] sram1_wmask0 ; // WMASK# +wire [31:0] sram1_din0 ; // Write Data +wire [31:0] sram1_dout0 ; // Read Data // SRAM-1 PORT-1, IMEM I/F -wire sram1_clk1 ; // CLK -wire sram1_csb1 ; // CS# -wire [8:0] sram1_addr1 ; // Address -wire [31:0] sram1_dout1 ; // Read Data +wire sram1_clk1 ; // CLK +wire sram1_csb1 ; // CS# +wire [8:0] sram1_addr1 ; // Address +wire [31:0] sram1_dout1 ; // Read Data `endif // SPIM I/F -wire sspim_sck ; // clock out -wire sspim_so ; // serial data out -wire sspim_si ; // serial data in -wire sspim_ssn ; // cs_n +wire sspim_sck ; // clock out +wire sspim_so ; // serial data out +wire sspim_si ; // serial data in +wire sspim_ssn ; // cs_n -wire usb_intr_o ; -wire i2cm_intr_o ; +wire usb_intr_o ; +wire i2cm_intr_o ; //---------------------------------------------------------------- // UART Master I/F // ------------------------------------------------------------- -wire uartm_rxd ; -wire uartm_txd ; +wire uartm_rxd ; +wire uartm_txd ; //---------------------------------------------------------- // BIST I/F // --------------------------------------------------------- -wire bist_en ; -wire bist_run ; -wire bist_load ; +wire bist_en ; +wire bist_run ; +wire bist_load ; -wire bist_sdi ; -wire bist_shift ; -wire bist_sdo ; +wire bist_sdi ; +wire bist_shift ; +wire bist_sdo ; -wire bist_done ; -wire [3:0] bist_error ; -wire [3:0] bist_correct ; -wire [3:0] bist_error_cnt0 ; -wire [3:0] bist_error_cnt1 ; -wire [3:0] bist_error_cnt2 ; -wire [3:0] bist_error_cnt3 ; +wire bist_done ; +wire [3:0] bist_error ; +wire [3:0] bist_correct ; +wire [3:0] bist_error_cnt0 ; +wire [3:0] bist_error_cnt1 ; +wire [3:0] bist_error_cnt2 ; +wire [3:0] bist_error_cnt3 ; // With Repeater Buffer -wire bist_en_rp ; -wire bist_run_rp ; -wire bist_load_rp ; +wire bist_en_rp ; +wire bist_run_rp ; +wire bist_load_rp ; -wire bist_sdi_rp ; -wire bist_shift_rp ; -wire bist_sdo_rp ; +wire bist_sdi_rp ; +wire bist_shift_rp ; +wire bist_sdo_rp ; -wire bist_done_rp ; -wire [3:0] bist_error_rp ; -wire [3:0] bist_correct_rp ; -wire [3:0] bist_error_cnt0_rp ; -wire [3:0] bist_error_cnt1_rp ; -wire [3:0] bist_error_cnt2_rp ; -wire [3:0] bist_error_cnt3_rp ; +wire bist_done_rp ; +wire [3:0] bist_error_rp ; +wire [3:0] bist_correct_rp ; +wire [3:0] bist_error_cnt0_rp ; +wire [3:0] bist_error_cnt1_rp ; +wire [3:0] bist_error_cnt2_rp ; +wire [3:0] bist_error_cnt3_rp ; // towards memory MBIST1 // PORT-A -//wire [BIST_NO_SRAM-1:0] mem_clk_a; -//wire [BIST1_ADDR_WD-1:2] mem0_addr_a; -//wire [BIST1_ADDR_WD-1:2] mem1_addr_a; -//wire [BIST1_ADDR_WD-1:2] mem2_addr_a; -//wire [BIST1_ADDR_WD-1:2] mem3_addr_a; -//wire [BIST_NO_SRAM-1:0] mem_cen_a; -//wire [BIST_NO_SRAM-1:0] mem_web_a; -//wire [BIST_DATA_WD/8-1:0] mem0_mask_a; -//wire [BIST_DATA_WD/8-1:0] mem1_mask_a; -//wire [BIST_DATA_WD/8-1:0] mem2_mask_a; -//wire [BIST_DATA_WD/8-1:0] mem3_mask_a; -//wire [BIST_DATA_WD-1:0] mem0_din_a; -//wire [BIST_DATA_WD-1:0] mem1_din_a; -//wire [BIST_DATA_WD-1:0] mem2_din_a; -//wire [BIST_DATA_WD-1:0] mem3_din_a; -//wire [BIST_DATA_WD-1:0] mem0_dout_a; -//wire [BIST_DATA_WD-1:0] mem1_dout_a; -//wire [BIST_DATA_WD-1:0] mem2_dout_a; -//wire [BIST_DATA_WD-1:0] mem3_dout_a; +wire [BIST_NO_SRAM-1:0] mem_clk_a ; +wire [BIST1_ADDR_WD-1:2] mem0_addr_a ; +wire [BIST1_ADDR_WD-1:2] mem1_addr_a ; +wire [BIST1_ADDR_WD-1:2] mem2_addr_a ; +wire [BIST1_ADDR_WD-1:2] mem3_addr_a ; +wire [BIST_NO_SRAM-1:0] mem_cen_a ; +wire [BIST_NO_SRAM-1:0] mem_web_a ; +wire [BIST_DATA_WD/8-1:0] mem0_mask_a ; +wire [BIST_DATA_WD/8-1:0] mem1_mask_a ; +wire [BIST_DATA_WD/8-1:0] mem2_mask_a ; +wire [BIST_DATA_WD/8-1:0] mem3_mask_a ; +wire [BIST_DATA_WD-1:0] mem0_din_a ; +wire [BIST_DATA_WD-1:0] mem1_din_a ; +wire [BIST_DATA_WD-1:0] mem2_din_a ; +wire [BIST_DATA_WD-1:0] mem3_din_a ; +wire [BIST_DATA_WD-1:0] mem0_dout_a ; +wire [BIST_DATA_WD-1:0] mem1_dout_a ; +wire [BIST_DATA_WD-1:0] mem2_dout_a ; +wire [BIST_DATA_WD-1:0] mem3_dout_a ; // PORT-B -//wire [BIST_NO_SRAM-1:0] mem_clk_b; -//wire [BIST_NO_SRAM-1:0] mem_cen_b; -//wire [BIST1_ADDR_WD-1:2] mem0_addr_b; -//wire [BIST1_ADDR_WD-1:2] mem1_addr_b; -//wire [BIST1_ADDR_WD-1:2] mem2_addr_b; -//wire [BIST1_ADDR_WD-1:2] mem3_addr_b; +wire [BIST_NO_SRAM-1:0] mem_clk_b ; +wire [BIST_NO_SRAM-1:0] mem_cen_b ; +wire [BIST1_ADDR_WD-1:2] mem0_addr_b ; +wire [BIST1_ADDR_WD-1:2] mem1_addr_b ; +wire [BIST1_ADDR_WD-1:2] mem2_addr_b ; +wire [BIST1_ADDR_WD-1:2] mem3_addr_b ; -wire [3:0] spi_csn; +wire [3:0] spi_csn ; ///////////////////////////////////////////////////////// // Clock Skew Ctrl @@ -641,63 +670,63 @@ wb_host u_wb_host( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .user_clock1 (wb_clk_i ), - .user_clock2 (user_clock2 ), + .user_clock1 (wb_clk_i ), + .user_clock2 (user_clock2 ), - .cpu_clk (cpu_clk ), - .rtc_clk (rtc_clk ), - .usb_clk (usb_clk ), + .cpu_clk (cpu_clk ), + .rtc_clk (rtc_clk ), + .usb_clk (usb_clk ), - .wbd_int_rst_n (wbd_int_rst_n ), - .cpu_rst_n (cpu_rst_n ), - .qspim_rst_n (qspim_rst_n ), - .sspim_rst_n (sspim_rst_n ), // spi reset - .uart_rst_n (uart_rst_n ), // uart reset - .i2cm_rst_n (i2c_rst_n ), // i2c reset - .usb_rst_n (usb_rst_n ), // usb reset - .bist_rst_n (bist_rst_n ), // BIST Reset + .wbd_int_rst_n (wbd_int_rst_n ), + .cpu_rst_n (cpu_rst_n ), + .qspim_rst_n (qspim_rst_n ), + .sspim_rst_n (sspim_rst_n ), // spi reset + .uart_rst_n (uart_rst_n ), // uart reset + .i2cm_rst_n (i2c_rst_n ), // i2c reset + .usb_rst_n (usb_rst_n ), // usb reset + .bist_rst_n (bist_rst_n ), // BIST Reset // Master Port - .wbm_rst_i (wb_rst_i ), - .wbm_clk_i (wb_clk_i ), - .wbm_cyc_i (wbs_cyc_i ), - .wbm_stb_i (wbs_stb_i ), - .wbm_adr_i (wbs_adr_i ), - .wbm_we_i (wbs_we_i ), - .wbm_dat_i (wbs_dat_i ), - .wbm_sel_i (wbs_sel_i ), - .wbm_dat_o (wbs_dat_o ), - .wbm_ack_o (wbs_ack_o ), - .wbm_err_o ( ), + .wbm_rst_i (wb_rst_i ), + .wbm_clk_i (wb_clk_i ), + .wbm_cyc_i (wbs_cyc_i ), + .wbm_stb_i (wbs_stb_i ), + .wbm_adr_i (wbs_adr_i ), + .wbm_we_i (wbs_we_i ), + .wbm_dat_i (wbs_dat_i ), + .wbm_sel_i (wbs_sel_i ), + .wbm_dat_o (wbs_dat_o ), + .wbm_ack_o (wbs_ack_o ), + .wbm_err_o ( ), // Clock Skeq Adjust - .wbd_clk_int (wbd_clk_int ), - .wbd_clk_wh (wbd_clk_wh ), - .cfg_cska_wh (cfg_cska_wh ), + .wbd_clk_int (wbd_clk_int ), + .wbd_clk_wh (wbd_clk_wh ), + .cfg_cska_wh (cfg_cska_wh ), // Slave Port - .wbs_clk_out (wbd_clk_int ), - .wbs_clk_i (wbd_clk_wh ), - .wbs_cyc_o (wbd_int_cyc_i ), - .wbs_stb_o (wbd_int_stb_i ), - .wbs_adr_o (wbd_int_adr_i ), - .wbs_we_o (wbd_int_we_i ), - .wbs_dat_o (wbd_int_dat_i ), - .wbs_sel_o (wbd_int_sel_i ), - .wbs_dat_i (wbd_int_dat_o ), - .wbs_ack_i (wbd_int_ack_o ), - .wbs_err_i (wbd_int_err_o ), + .wbs_clk_out (wbd_clk_int ), + .wbs_clk_i (wbd_clk_wh ), + .wbs_cyc_o (wbd_int_cyc_i ), + .wbs_stb_o (wbd_int_stb_i ), + .wbs_adr_o (wbd_int_adr_i ), + .wbs_we_o (wbd_int_we_i ), + .wbs_dat_o (wbd_int_dat_i ), + .wbs_sel_o (wbd_int_sel_i ), + .wbs_dat_i (wbd_int_dat_o ), + .wbs_ack_i (wbd_int_ack_o ), + .wbs_err_i (wbd_int_err_o ), - .cfg_clk_ctrl1 (cfg_clk_ctrl1 ), - .cfg_clk_ctrl2 (cfg_clk_ctrl2 ), + .cfg_clk_ctrl1 (cfg_clk_ctrl1 ), + .cfg_clk_ctrl2 (cfg_clk_ctrl2 ), - .la_data_in (la_data_in[17:0] ), + .la_data_in (la_data_in[17:0] ), - .uartm_rxd (uartm_rxd ), - .uartm_txd (uartm_txd ) + .uartm_rxd (uartm_rxd ), + .uartm_txd (uartm_txd ) ); @@ -710,198 +739,267 @@ //------------------------------------------------------------------------------ ycr1_top_wb u_riscv_top ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .wbd_clk_int (wbd_clk_risc_rp ), - .cfg_cska_riscv (cfg_cska_riscv_rp ), - .wbd_clk_riscv (wbd_clk_riscv_skew ), + .wbd_clk_int (wbd_clk_risc_rp ), + .cfg_cska_riscv (cfg_cska_riscv_rp ), + .wbd_clk_riscv (wbd_clk_riscv_skew ), // Reset - .pwrup_rst_n (wbd_int_rst_n ), - .rst_n (wbd_int_rst_n ), - .cpu_rst_n (cpu_rst_n ), - .riscv_debug (riscv_debug ), + .pwrup_rst_n (wbd_int_rst_n ), + .rst_n (wbd_int_rst_n ), + .cpu_rst_n (cpu_rst_n ), + .riscv_debug (riscv_debug ), // Clock - .core_clk (cpu_clk ), - .rtc_clk (rtc_clk ), + .core_clk (cpu_clk ), + .rtc_clk (rtc_clk ), // Fuses - .fuse_mhartid (fuse_mhartid_rp ), + .fuse_mhartid (fuse_mhartid_rp ), // IRQ - .irq_lines (irq_lines_rp ), - .soft_irq (soft_irq_rp ), // TODO - Interrupts + .irq_lines (irq_lines_rp ), + .soft_irq (soft_irq_rp ), // TODO - Interrupts // DFT - // .test_mode (1'b0 ), // Moved inside IP - // .test_rst_n (1'b1 ), // Moved inside IP + // .test_mode (1'b0 ), // Moved inside IP + // .test_rst_n (1'b1 ), // Moved inside IP `ifndef SCR1_TCM_MEM // SRAM-0 PORT-0 - .sram0_clk0 (sram0_clk0 ), - .sram0_csb0 (sram0_csb0 ), - .sram0_web0 (sram0_web0 ), - .sram0_addr0 (sram0_addr0 ), - .sram0_wmask0 (sram0_wmask0 ), - .sram0_din0 (sram0_din0 ), - .sram0_dout0 (sram0_dout0 ), + .sram0_clk0 (sram0_clk0 ), + .sram0_csb0 (sram0_csb0 ), + .sram0_web0 (sram0_web0 ), + .sram0_addr0 (sram0_addr0 ), + .sram0_wmask0 (sram0_wmask0 ), + .sram0_din0 (sram0_din0 ), + .sram0_dout0 (sram0_dout0 ), // SRAM-0 PORT-0 - .sram0_clk1 (sram0_clk1 ), - .sram0_csb1 (sram0_csb1 ), - .sram0_addr1 (sram0_addr1 ), - .sram0_dout1 (sram0_dout1 ), + .sram0_clk1 (sram0_clk1 ), + .sram0_csb1 (sram0_csb1 ), + .sram0_addr1 (sram0_addr1 ), + .sram0_dout1 (sram0_dout1 ), // // SRAM-1 PORT-0 - // .sram1_clk0 (sram1_clk0 ), - // .sram1_csb0 (sram1_csb0 ), - // .sram1_web0 (sram1_web0 ), - // .sram1_addr0 (sram1_addr0 ), - // .sram1_wmask0 (sram1_wmask0 ), - // .sram1_din0 (sram1_din0 ), - // .sram1_dout0 (sram1_dout0 ), + // .sram1_clk0 (sram1_clk0 ), + // .sram1_csb0 (sram1_csb0 ), + // .sram1_web0 (sram1_web0 ), + // .sram1_addr0 (sram1_addr0 ), + // .sram1_wmask0 (sram1_wmask0 ), + // .sram1_din0 (sram1_din0 ), + // .sram1_dout0 (sram1_dout0 ), // // // SRAM PORT-0 - // .sram1_clk1 (sram1_clk1 ), - // .sram1_csb1 (sram1_csb1 ), - // .sram1_addr1 (sram1_addr1 ), - // .sram1_dout1 (sram1_dout1 ), + // .sram1_clk1 (sram1_clk1 ), + // .sram1_csb1 (sram1_csb1 ), + // .sram1_addr1 (sram1_addr1 ), + // .sram1_dout1 (sram1_dout1 ), `endif - .wb_rst_n (wbd_int_rst_n ), - .wb_clk (wbd_clk_riscv_skew ), + .wb_rst_n (wbd_int_rst_n ), + .wb_clk (wbd_clk_riscv_skew ), // Instruction cache memory interface - .wb_icache_stb_o (wbd_riscv_icache_stb_i ), - .wb_icache_adr_o (wbd_riscv_icache_adr_i ), - .wb_icache_we_o (wbd_riscv_icache_we_i ), - .wb_icache_dat_o (wbd_riscv_icache_dat_i ), - .wb_icache_sel_o (wbd_riscv_icache_sel_i ), - .wb_icache_bl_o (wbd_riscv_icache_bl_i ), - .wb_icache_bry_o (wbd_riscv_icache_bry_i ), - .wb_icache_dat_i (wbd_riscv_icache_dat_o ), - .wb_icache_ack_i (wbd_riscv_icache_ack_o ), - .wb_icache_lack_i (wbd_riscv_icache_lack_o ), - .wb_icache_err_i (wbd_riscv_icache_err_o ), + .wb_icache_stb_o (wbd_riscv_icache_stb_i ), + .wb_icache_adr_o (wbd_riscv_icache_adr_i ), + .wb_icache_we_o (wbd_riscv_icache_we_i ), + .wb_icache_sel_o (wbd_riscv_icache_sel_i ), + .wb_icache_bl_o (wbd_riscv_icache_bl_i ), + .wb_icache_bry_o (wbd_riscv_icache_bry_i ), + .wb_icache_dat_i (wbd_riscv_icache_dat_o ), + .wb_icache_ack_i (wbd_riscv_icache_ack_o ), + .wb_icache_lack_i (wbd_riscv_icache_lack_o ), + .wb_icache_err_i (wbd_riscv_icache_err_o ), + + .icache_mem_clk0 (icache_mem_clk0 ), // CLK + .icache_mem_csb0 (icache_mem_csb0 ), // CS# + .icache_mem_web0 (icache_mem_web0 ), // WE# + .icache_mem_addr0 (icache_mem_addr0 ), // Address + .icache_mem_wmask0 (icache_mem_wmask0 ), // WMASK# + .icache_mem_din0 (icache_mem_din0 ), // Write Data +// .icache_mem_dout0 (icache_mem_dout0 ), // Read Data + + + .icache_mem_clk1 (icache_mem_clk1 ), // CLK + .icache_mem_csb1 (icache_mem_csb1 ), // CS# + .icache_mem_addr1 (icache_mem_addr1 ), // Address + .icache_mem_dout1 (icache_mem_dout1 ), // Read Data // Data cache memory interface - .wb_dcache_stb_o (wbd_riscv_dcache_stb_i ), - .wb_dcache_adr_o (wbd_riscv_dcache_adr_i ), - .wb_dcache_we_o (wbd_riscv_dcache_we_i ), - .wb_dcache_dat_o (wbd_riscv_dcache_dat_i ), - .wb_dcache_sel_o (wbd_riscv_dcache_sel_i ), - .wb_dcache_bl_o (wbd_riscv_dcache_bl_i ), - .wb_dcache_bry_o (wbd_riscv_dcache_bry_i ), - .wb_dcache_dat_i (wbd_riscv_dcache_dat_o ), - .wb_dcache_ack_i (wbd_riscv_dcache_ack_o ), - .wb_dcache_lack_i (wbd_riscv_dcache_lack_o ), - .wb_dcache_err_i (wbd_riscv_dcache_err_o ), + .wb_dcache_stb_o (wbd_riscv_dcache_stb_i ), + .wb_dcache_adr_o (wbd_riscv_dcache_adr_i ), + .wb_dcache_we_o (wbd_riscv_dcache_we_i ), + .wb_dcache_dat_o (wbd_riscv_dcache_dat_i ), + .wb_dcache_sel_o (wbd_riscv_dcache_sel_i ), + .wb_dcache_bl_o (wbd_riscv_dcache_bl_i ), + .wb_dcache_bry_o (wbd_riscv_dcache_bry_i ), + .wb_dcache_dat_i (wbd_riscv_dcache_dat_o ), + .wb_dcache_ack_i (wbd_riscv_dcache_ack_o ), + .wb_dcache_lack_i (wbd_riscv_dcache_lack_o ), + .wb_dcache_err_i (wbd_riscv_dcache_err_o ), + + .dcache_mem_clk0 (dcache_mem_clk0 ), // CLK + .dcache_mem_csb0 (dcache_mem_csb0 ), // CS# + .dcache_mem_web0 (dcache_mem_web0 ), // WE# + .dcache_mem_addr0 (dcache_mem_addr0 ), // Address + .dcache_mem_wmask0 (dcache_mem_wmask0 ), // WMASK# + .dcache_mem_din0 (dcache_mem_din0 ), // Write Data + .dcache_mem_dout0 (dcache_mem_dout0 ), // Read Data + + + .dcache_mem_clk1 (dcache_mem_clk1 ), // CLK + .dcache_mem_csb1 (dcache_mem_csb1 ), // CS# + .dcache_mem_addr1 (dcache_mem_addr1 ), // Address + .dcache_mem_dout1 (dcache_mem_dout1 ), // Read Data + // Data memory interface - .wbd_dmem_stb_o (wbd_riscv_dmem_stb_i ), - .wbd_dmem_adr_o (wbd_riscv_dmem_adr_i ), - .wbd_dmem_we_o (wbd_riscv_dmem_we_i ), - .wbd_dmem_dat_o (wbd_riscv_dmem_dat_i ), - .wbd_dmem_sel_o (wbd_riscv_dmem_sel_i ), - .wbd_dmem_dat_i (wbd_riscv_dmem_dat_o ), - .wbd_dmem_ack_i (wbd_riscv_dmem_ack_o ), - .wbd_dmem_err_i (wbd_riscv_dmem_err_o ) + .wbd_dmem_stb_o (wbd_riscv_dmem_stb_i ), + .wbd_dmem_adr_o (wbd_riscv_dmem_adr_i ), + .wbd_dmem_we_o (wbd_riscv_dmem_we_i ), + .wbd_dmem_dat_o (wbd_riscv_dmem_dat_i ), + .wbd_dmem_sel_o (wbd_riscv_dmem_sel_i ), + .wbd_dmem_dat_i (wbd_riscv_dmem_dat_o ), + .wbd_dmem_ack_i (wbd_riscv_dmem_ack_o ), + .wbd_dmem_err_i (wbd_riscv_dmem_err_o ) ); `ifndef SCR1_TCM_MEM sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram0_2kb( `ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground + .vccd1 (vccd1 ),// area 1 1.8V supply + .vssd1 (vssd1 ),// area 1 digital ground `endif // Port 0: RW - .clk0 (sram0_clk0), - .csb0 (sram0_csb0), - .web0 (sram0_web0), - .wmask0 (sram0_wmask0), - .addr0 (sram0_addr0), - .din0 (sram0_din0), - .dout0 (sram0_dout0), + .clk0 (sram0_clk0 ), + .csb0 (sram0_csb0 ), + .web0 (sram0_web0 ), + .wmask0 (sram0_wmask0 ), + .addr0 (sram0_addr0 ), + .din0 (sram0_din0 ), + .dout0 (sram0_dout0 ), // Port 1: R - .clk1 (sram0_clk1), - .csb1 (sram0_csb1), - .addr1 (sram0_addr1), - .dout1 (sram0_dout1) + .clk1 (sram0_clk1 ), + .csb1 (sram0_csb1 ), + .addr1 (sram0_addr1 ), + .dout1 (sram0_dout1 ) ); /*** sky130_sram_2kbyte_1rw1r_32x512_8 u_tsram1_2kb( `ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif // Port 0: RW - .clk0 (sram1_clk0), - .csb0 (sram1_csb0), - .web0 (sram1_web0), - .wmask0 (sram1_wmask0), - .addr0 (sram1_addr0), - .din0 (sram1_din0), - .dout0 (sram1_dout0), + .clk0 (sram1_clk0 ), + .csb0 (sram1_csb0 ), + .web0 (sram1_web0 ), + .wmask0 (sram1_wmask0 ), + .addr0 (sram1_addr0 ), + .din0 (sram1_din0 ), + .dout0 (sram1_dout0 ), // Port 1: R - .clk1 (sram1_clk1), - .csb1 (sram1_csb1), - .addr1 (sram1_addr1), - .dout1 (sram1_dout1) + .clk1 (sram1_clk1 ), + .csb1 (sram1_csb1 ), + .addr1 (sram1_addr1 ), + .dout1 (sram1_dout1 ) ); ***/ `endif +sky130_sram_2kbyte_1rw1r_32x512_8 u_icache_2kb( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground +`endif +// Port 0: RW + .clk0 (icache_mem_clk0 ), + .csb0 (icache_mem_csb0 ), + .web0 (icache_mem_web0 ), + .wmask0 (icache_mem_wmask0 ), + .addr0 (icache_mem_addr0 ), + .din0 (icache_mem_din0 ), + .dout0 ( ), +// Port 1: R + .clk1 (icache_mem_clk1 ), + .csb1 (icache_mem_csb1 ), + .addr1 (icache_mem_addr1 ), + .dout1 (icache_mem_dout1 ) + ); + +sky130_sram_2kbyte_1rw1r_32x512_8 u_dcache_2kb( +`ifdef USE_POWER_PINS + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground +`endif +// Port 0: RW + .clk0 (dcache_mem_clk0 ), + .csb0 (dcache_mem_csb0 ), + .web0 (dcache_mem_web0 ), + .wmask0 (dcache_mem_wmask0 ), + .addr0 (dcache_mem_addr0 ), + .din0 (dcache_mem_din0 ), + .dout0 (dcache_mem_dout0 ), +// Port 1: R + .clk1 (dcache_mem_clk1 ), + .csb1 (dcache_mem_csb1 ), + .addr1 (dcache_mem_addr1 ), + .dout1 (dcache_mem_dout1 ) + ); + + /********************************************************* * SPI Master -* This is an implementation of an SPI master that is controlled via an AXI bus. +* This is implementation of an SPI master that is controlled via an AXI bus . * It has FIFOs for transmitting and receiving data. * It supports both the normal SPI mode and QPI mode with 4 data lines. * *******************************************************/ qspim_top -#( +# ( `ifndef SYNTHESIS - .WB_WIDTH (WB_WIDTH) + .WB_WIDTH (WB_WIDTH ) `endif ) u_qspi_master ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .mclk (wbd_clk_spi ), - .rst_n (qspim_rst_n ), + .mclk (wbd_clk_spi ), + .rst_n (qspim_rst_n ), // Clock Skew Adjust - .cfg_cska_sp_co (cfg_cska_qspi_co_rp ), - .cfg_cska_spi (cfg_cska_qspi_rp ), - .wbd_clk_int (wbd_clk_qspi_rp ), - .wbd_clk_spi (wbd_clk_spi ), + .cfg_cska_sp_co (cfg_cska_qspi_co_rp ), + .cfg_cska_spi (cfg_cska_qspi_rp ), + .wbd_clk_int (wbd_clk_qspi_rp ), + .wbd_clk_spi (wbd_clk_spi ), - .wbd_stb_i (wbd_spim_stb_o ), - .wbd_adr_i (wbd_spim_adr_o ), - .wbd_we_i (wbd_spim_we_o ), - .wbd_dat_i (wbd_spim_dat_o ), - .wbd_sel_i (wbd_spim_sel_o ), - .wbd_bl_i (wbd_spim_bl_o ), - .wbd_bry_i (wbd_spim_bry_o ), - .wbd_dat_o (wbd_spim_dat_i ), - .wbd_ack_o (wbd_spim_ack_i ), - .wbd_lack_o (wbd_spim_lack_i ), - .wbd_err_o (wbd_spim_err_i ), + .wbd_stb_i (wbd_spim_stb_o ), + .wbd_adr_i (wbd_spim_adr_o ), + .wbd_we_i (wbd_spim_we_o ), + .wbd_dat_i (wbd_spim_dat_o ), + .wbd_sel_i (wbd_spim_sel_o ), + .wbd_bl_i (wbd_spim_bl_o ), + .wbd_bry_i (wbd_spim_bry_o ), + .wbd_dat_o (wbd_spim_dat_i ), + .wbd_ack_o (wbd_spim_ack_i ), + .wbd_lack_o (wbd_spim_lack_i ), + .wbd_err_o (wbd_spim_err_i ), - .spi_debug (spi_debug ), + .spi_debug (spi_debug ), // Pad Interface - .spi_sdi (sflash_di ), - .spi_clk (sflash_sck ), - .spi_csn (spi_csn ), - .spi_sdo (sflash_do ), - .spi_oen (sflash_oen ) + .spi_sdi (sflash_di ), + .spi_clk (sflash_sck ), + .spi_csn (spi_csn ), + .spi_sdo (sflash_do ), + .spi_oen (sflash_oen ) ); @@ -909,15 +1007,15 @@ wb_interconnect #( `ifndef SYNTHESIS - .CH_CLK_WD(8), - .CH_DATA_WD(116) + .CH_CLK_WD (8 ), + .CH_DATA_WD (116 ) `endif ) u_intercon ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif - .ch_clk_in ({ + .ch_clk_in ({ wbd_clk_int, wbd_clk_int, wbd_clk_int, @@ -925,8 +1023,8 @@ wbd_clk_int, wbd_clk_int, wbd_clk_int, - wbd_clk_int}), - .ch_clk_out ({ + wbd_clk_int} ), + .ch_clk_out ({ wbd_clk_mbist4_rp, wbd_clk_mbist3_rp, wbd_clk_mbist2_rp, @@ -934,8 +1032,8 @@ wbd_clk_pinmux_rp, wbd_clk_uart_rp, wbd_clk_qspi_rp, - wbd_clk_risc_rp}), - .ch_data_in ({ + wbd_clk_risc_rp} ), + .ch_data_in ({ bist_error_cnt3[3:0], bist_correct[3], bist_error[3], @@ -974,7 +1072,7 @@ cfg_cska_qspi[3:0], cfg_cska_riscv[3:0] } ), - .ch_data_out ({ + .ch_data_out ({ bist_error_cnt3_rp[3:0], bist_correct_rp[3], bist_error_rp[3], @@ -1013,115 +1111,114 @@ cfg_cska_riscv_rp[3:0] }), // Clock Skew adjust - .wbd_clk_int (wbd_clk_int ), - .cfg_cska_wi (cfg_cska_wi ), - .wbd_clk_wi (wbd_clk_wi_skew ), + .wbd_clk_int (wbd_clk_int ), + .cfg_cska_wi (cfg_cska_wi ), + .wbd_clk_wi (wbd_clk_wi_skew ), - .clk_i (wbd_clk_wi_skew ), - .rst_n (wbd_int_rst_n ), - .dcache_remap (dcache_remap ), - .boot_remap (boot_remap ), + .clk_i (wbd_clk_wi_skew ), + .rst_n (wbd_int_rst_n ), + .dcache_remap (dcache_remap ), + .boot_remap (boot_remap ), // Master 0 Interface - .m0_wbd_dat_i (wbd_int_dat_i ), - .m0_wbd_adr_i (wbd_int_adr_i ), - .m0_wbd_sel_i (wbd_int_sel_i ), - .m0_wbd_we_i (wbd_int_we_i ), - .m0_wbd_cyc_i (wbd_int_cyc_i ), - .m0_wbd_stb_i (wbd_int_stb_i ), - .m0_wbd_dat_o (wbd_int_dat_o ), - .m0_wbd_ack_o (wbd_int_ack_o ), - .m0_wbd_err_o (wbd_int_err_o ), + .m0_wbd_dat_i (wbd_int_dat_i ), + .m0_wbd_adr_i (wbd_int_adr_i ), + .m0_wbd_sel_i (wbd_int_sel_i ), + .m0_wbd_we_i (wbd_int_we_i ), + .m0_wbd_cyc_i (wbd_int_cyc_i ), + .m0_wbd_stb_i (wbd_int_stb_i ), + .m0_wbd_dat_o (wbd_int_dat_o ), + .m0_wbd_ack_o (wbd_int_ack_o ), + .m0_wbd_err_o (wbd_int_err_o ), // Master 1 Interface - .m1_wbd_dat_i (wbd_riscv_dmem_dat_i ), - .m1_wbd_adr_i (wbd_riscv_dmem_adr_i ), - .m1_wbd_sel_i (wbd_riscv_dmem_sel_i ), - .m1_wbd_we_i (wbd_riscv_dmem_we_i ), - .m1_wbd_cyc_i (wbd_riscv_dmem_stb_i ), - .m1_wbd_stb_i (wbd_riscv_dmem_stb_i ), - .m1_wbd_dat_o (wbd_riscv_dmem_dat_o ), - .m1_wbd_ack_o (wbd_riscv_dmem_ack_o ), - .m1_wbd_err_o (wbd_riscv_dmem_err_o ), + .m1_wbd_dat_i (wbd_riscv_dmem_dat_i ), + .m1_wbd_adr_i (wbd_riscv_dmem_adr_i ), + .m1_wbd_sel_i (wbd_riscv_dmem_sel_i ), + .m1_wbd_we_i (wbd_riscv_dmem_we_i ), + .m1_wbd_cyc_i (wbd_riscv_dmem_stb_i ), + .m1_wbd_stb_i (wbd_riscv_dmem_stb_i ), + .m1_wbd_dat_o (wbd_riscv_dmem_dat_o ), + .m1_wbd_ack_o (wbd_riscv_dmem_ack_o ), + .m1_wbd_err_o (wbd_riscv_dmem_err_o ), // Master 2 Interface - .m2_wbd_dat_i (wbd_riscv_dcache_dat_i ), - .m2_wbd_adr_i (wbd_riscv_dcache_adr_i ), - .m2_wbd_sel_i (wbd_riscv_dcache_sel_i ), - .m2_wbd_bl_i (wbd_riscv_dcache_bl_i ), - .m2_wbd_bry_i (wbd_riscv_dcache_bry_i ), - .m2_wbd_we_i (wbd_riscv_dcache_we_i ), - .m2_wbd_cyc_i (wbd_riscv_dcache_stb_i ), - .m2_wbd_stb_i (wbd_riscv_dcache_stb_i ), - .m2_wbd_dat_o (wbd_riscv_dcache_dat_o ), - .m2_wbd_ack_o (wbd_riscv_dcache_ack_o ), - .m2_wbd_lack_o (wbd_riscv_dcache_lack_o ), - .m2_wbd_err_o (wbd_riscv_dcache_err_o ), + .m2_wbd_dat_i (wbd_riscv_dcache_dat_i ), + .m2_wbd_adr_i (wbd_riscv_dcache_adr_i ), + .m2_wbd_sel_i (wbd_riscv_dcache_sel_i ), + .m2_wbd_bl_i (wbd_riscv_dcache_bl_i ), + .m2_wbd_bry_i (wbd_riscv_dcache_bry_i ), + .m2_wbd_we_i (wbd_riscv_dcache_we_i ), + .m2_wbd_cyc_i (wbd_riscv_dcache_stb_i ), + .m2_wbd_stb_i (wbd_riscv_dcache_stb_i ), + .m2_wbd_dat_o (wbd_riscv_dcache_dat_o ), + .m2_wbd_ack_o (wbd_riscv_dcache_ack_o ), + .m2_wbd_lack_o (wbd_riscv_dcache_lack_o ), + .m2_wbd_err_o (wbd_riscv_dcache_err_o ), // Master 3 Interface - .m3_wbd_dat_i (wbd_riscv_icache_dat_i ), - .m3_wbd_adr_i (wbd_riscv_icache_adr_i ), - .m3_wbd_sel_i (wbd_riscv_icache_sel_i ), - .m3_wbd_bl_i (wbd_riscv_icache_bl_i ), - .m3_wbd_bry_i (wbd_riscv_icache_bry_i ), - .m3_wbd_we_i (wbd_riscv_icache_we_i ), - .m3_wbd_cyc_i (wbd_riscv_icache_stb_i ), - .m3_wbd_stb_i (wbd_riscv_icache_stb_i ), - .m3_wbd_dat_o (wbd_riscv_icache_dat_o ), - .m3_wbd_ack_o (wbd_riscv_icache_ack_o ), - .m3_wbd_lack_o (wbd_riscv_icache_lack_o ), - .m3_wbd_err_o (wbd_riscv_icache_err_o ), + .m3_wbd_adr_i (wbd_riscv_icache_adr_i ), + .m3_wbd_sel_i (wbd_riscv_icache_sel_i ), + .m3_wbd_bl_i (wbd_riscv_icache_bl_i ), + .m3_wbd_bry_i (wbd_riscv_icache_bry_i ), + .m3_wbd_we_i (wbd_riscv_icache_we_i ), + .m3_wbd_cyc_i (wbd_riscv_icache_stb_i ), + .m3_wbd_stb_i (wbd_riscv_icache_stb_i ), + .m3_wbd_dat_o (wbd_riscv_icache_dat_o ), + .m3_wbd_ack_o (wbd_riscv_icache_ack_o ), + .m3_wbd_lack_o (wbd_riscv_icache_lack_o ), + .m3_wbd_err_o (wbd_riscv_icache_err_o ), // Slave 0 Interface // .s0_wbd_err_i (1'b0 ), - Moved inside IP - .s0_wbd_dat_i (wbd_spim_dat_i ), - .s0_wbd_ack_i (wbd_spim_ack_i ), - .s0_wbd_lack_i (wbd_spim_lack_i ), - .s0_wbd_dat_o (wbd_spim_dat_o ), - .s0_wbd_adr_o (wbd_spim_adr_o ), - .s0_wbd_bry_o (wbd_spim_bry_o ), - .s0_wbd_bl_o (wbd_spim_bl_o ), - .s0_wbd_sel_o (wbd_spim_sel_o ), - .s0_wbd_we_o (wbd_spim_we_o ), - .s0_wbd_cyc_o (wbd_spim_cyc_o ), - .s0_wbd_stb_o (wbd_spim_stb_o ), + .s0_wbd_dat_i (wbd_spim_dat_i ), + .s0_wbd_ack_i (wbd_spim_ack_i ), + .s0_wbd_lack_i (wbd_spim_lack_i ), + .s0_wbd_dat_o (wbd_spim_dat_o ), + .s0_wbd_adr_o (wbd_spim_adr_o ), + .s0_wbd_bry_o (wbd_spim_bry_o ), + .s0_wbd_bl_o (wbd_spim_bl_o ), + .s0_wbd_sel_o (wbd_spim_sel_o ), + .s0_wbd_we_o (wbd_spim_we_o ), + .s0_wbd_cyc_o (wbd_spim_cyc_o ), + .s0_wbd_stb_o (wbd_spim_stb_o ), // Slave 1 Interface // .s1_wbd_err_i (1'b0 ), - Moved inside IP - .s1_wbd_dat_i (wbd_uart_dat_i ), - .s1_wbd_ack_i (wbd_uart_ack_i ), - .s1_wbd_dat_o (wbd_uart_dat_o ), - .s1_wbd_adr_o (wbd_uart_adr_o ), - .s1_wbd_sel_o (wbd_uart_sel_o ), - .s1_wbd_we_o (wbd_uart_we_o ), - .s1_wbd_cyc_o (wbd_uart_cyc_o ), - .s1_wbd_stb_o (wbd_uart_stb_o ), + .s1_wbd_dat_i (wbd_uart_dat_i ), + .s1_wbd_ack_i (wbd_uart_ack_i ), + .s1_wbd_dat_o (wbd_uart_dat_o ), + .s1_wbd_adr_o (wbd_uart_adr_o ), + .s1_wbd_sel_o (wbd_uart_sel_o ), + .s1_wbd_we_o (wbd_uart_we_o ), + .s1_wbd_cyc_o (wbd_uart_cyc_o ), + .s1_wbd_stb_o (wbd_uart_stb_o ), // Slave 2 Interface // .s2_wbd_err_i (1'b0 ), - Moved inside IP - .s2_wbd_dat_i (wbd_glbl_dat_i ), - .s2_wbd_ack_i (wbd_glbl_ack_i ), - .s2_wbd_dat_o (wbd_glbl_dat_o ), - .s2_wbd_adr_o (wbd_glbl_adr_o ), - .s2_wbd_sel_o (wbd_glbl_sel_o ), - .s2_wbd_we_o (wbd_glbl_we_o ), - .s2_wbd_cyc_o (wbd_glbl_cyc_o ), - .s2_wbd_stb_o (wbd_glbl_stb_o ), + .s2_wbd_dat_i (wbd_glbl_dat_i ), + .s2_wbd_ack_i (wbd_glbl_ack_i ), + .s2_wbd_dat_o (wbd_glbl_dat_o ), + .s2_wbd_adr_o (wbd_glbl_adr_o ), + .s2_wbd_sel_o (wbd_glbl_sel_o ), + .s2_wbd_we_o (wbd_glbl_we_o ), + .s2_wbd_cyc_o (wbd_glbl_cyc_o ), + .s2_wbd_stb_o (wbd_glbl_stb_o ), // Slave 3 Interface // .s3_wbd_err_i (1'b0 ), - Moved inside IP - .s3_wbd_dat_i (wbd_mbist_dat_i ), - .s3_wbd_ack_i (wbd_mbist_ack_i ), - .s3_wbd_lack_i (wbd_mbist_lack_i ), - .s3_wbd_dat_o (wbd_mbist_dat_o ), - .s3_wbd_adr_o (wbd_mbist_adr_o ), - .s3_wbd_sel_o (wbd_mbist_sel_o ), - .s3_wbd_bry_o (wbd_mbist_bry_o ), - .s3_wbd_bl_o (wbd_mbist_bl_o ), - .s3_wbd_we_o (wbd_mbist_we_o ), - .s3_wbd_cyc_o (wbd_mbist_cyc_o ), - .s3_wbd_stb_o (wbd_mbist_stb_o ) + .s3_wbd_dat_i (wbd_mbist_dat_i ), + .s3_wbd_ack_i (wbd_mbist_ack_i ), + .s3_wbd_lack_i (wbd_mbist_lack_i ), + .s3_wbd_dat_o (wbd_mbist_dat_o ), + .s3_wbd_adr_o (wbd_mbist_adr_o ), + .s3_wbd_sel_o (wbd_mbist_sel_o ), + .s3_wbd_bry_o (wbd_mbist_bry_o ), + .s3_wbd_bl_o (wbd_mbist_bl_o ), + .s3_wbd_we_o (wbd_mbist_we_o ), + .s3_wbd_cyc_o (wbd_mbist_cyc_o ), + .s3_wbd_stb_o (wbd_mbist_stb_o ) ); @@ -1303,165 +1400,162 @@ u_mbist ( `ifdef USE_POWER_PINS - .vccd1 (vccd1 ),// User area 1 1.8V supply - .vssd1 (vssd1 ),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif // Clock Skew adjust - .wbd_clk_int (wbd_clk_mbist1_rp ), - .cfg_cska_mbist (cfg_cska_mbist1_rp ), - .wbd_clk_mbist (wbd_clk_mbist_skew ), + .wbd_clk_int (wbd_clk_mbist1_rp ), + .cfg_cska_mbist (cfg_cska_mbist1_rp ), + .wbd_clk_mbist (wbd_clk_mbist_skew ), // WB I/F - .wb_clk2_i (wbd_clk_mbist_skew ), - .wb_clk_i (wbd_clk_mbist_skew ), - .wb_cyc_i (wbd_mbist_cyc_o), - .wb_stb_i (wbd_mbist_stb_o), - .wb_cs_i (wbd_mbist_adr_o[12:11]), - .wb_adr_i (wbd_mbist_adr_o[BIST1_ADDR_WD-1:2]), - .wb_we_i (wbd_mbist_we_o ), - .wb_dat_i (wbd_mbist_dat_o), - .wb_sel_i (wbd_mbist_sel_o), - .wb_bl_i (wbd_mbist_bl_o), - .wb_bry_i (wbd_mbist_bry_o), - .wb_dat_o (wbd_mbist_dat_i), - .wb_ack_o (wbd_mbist_ack_i), - .wb_lack_o (wbd_mbist_lack_i), - .wb_err_o ( ), + .wb_clk2_i (wbd_clk_mbist_skew ), + .wb_clk_i (wbd_clk_mbist_skew ), + .wb_stb_i (wbd_mbist_stb_o), + .wb_cs_i (wbd_mbist_adr_o[12:11]), + .wb_adr_i (wbd_mbist_adr_o[BIST1_ADDR_WD-1:2]), + .wb_we_i (wbd_mbist_we_o ), + .wb_dat_i (wbd_mbist_dat_o), + .wb_sel_i (wbd_mbist_sel_o), + .wb_bl_i (wbd_mbist_bl_o), + .wb_bry_i (wbd_mbist_bry_o), + .wb_dat_o (wbd_mbist_dat_i), + .wb_ack_o (wbd_mbist_ack_i), + .wb_lack_o (wbd_mbist_lack_i), + .wb_err_o ( ), - .rst_n (bist_rst_n ), + .rst_n (bist_rst_n ), - .bist_en (bist_en_rp ), - .bist_run (bist_run_rp ), - .bist_shift (bist_shift_rp ), - .bist_load (bist_load_rp ), - .bist_sdi (bist_sdi_rp ), + .bist_en (bist_en_rp ), + .bist_run (bist_run_rp ), + .bist_shift (bist_shift_rp ), + .bist_load (bist_load_rp ), + .bist_sdi (bist_sdi_rp ), - .bist_error_cnt3 (bist_error_cnt3 ), - .bist_error_cnt2 (bist_error_cnt2 ), - .bist_error_cnt1 (bist_error_cnt1 ), - .bist_error_cnt0 (bist_error_cnt0 ), - .bist_correct (bist_correct ), - .bist_error (bist_error ), - .bist_done (bist_done ), - .bist_sdo (bist_sdo ) + .bist_error_cnt3 (bist_error_cnt3 ), + .bist_error_cnt2 (bist_error_cnt2 ), + .bist_error_cnt1 (bist_error_cnt1 ), + .bist_error_cnt0 (bist_error_cnt0 ), + .bist_correct (bist_correct ), + .bist_error (bist_error ), + .bist_done (bist_done ), + .bist_sdo (bist_sdo ), - // // towards memory - // // PORT-A - // .mem_clk_a (mem_clk_a ), - // .mem_addr_a0 (mem0_addr_a ), - // .mem_addr_a1 (mem1_addr_a ), - // .mem_addr_a2 (mem2_addr_a ), - // .mem_addr_a3 (mem3_addr_a ), - // .mem_cen_a (mem_cen_a ), - // .mem_web_a (mem_web_a ), - // .mem_mask_a0 (mem0_mask_a ), - // .mem_mask_a1 (mem1_mask_a ), - // .mem_mask_a2 (mem2_mask_a ), - // .mem_mask_a3 (mem3_mask_a ), - // .mem_din_a0 (mem0_din_a ), - // .mem_din_a1 (mem1_din_a ), - // .mem_din_a2 (mem2_din_a ), - // .mem_din_a3 (mem3_din_a ), - // .mem_dout_a0 (mem0_dout_a ), - // .mem_dout_a1 (mem1_dout_a ), - // .mem_dout_a2 (mem2_dout_a ), - // .mem_dout_a3 (mem3_dout_a ), - // // PORT-B - // .mem_clk_b (mem_clk_b ), - // .mem_cen_b (mem_cen_b ), - // .mem_addr_b0 (mem0_addr_b ), - // .mem_addr_b1 (mem1_addr_b ), - // .mem_addr_b2 (mem2_addr_b ), - // .mem_addr_b3 (mem3_addr_b ) + // towards memory + // PORT-A + .mem_clk_a (mem_clk_a ), + .mem_addr_a0 (mem0_addr_a ), + .mem_addr_a1 (mem1_addr_a ), + .mem_addr_a2 (mem2_addr_a ), + .mem_addr_a3 (mem3_addr_a ), + .mem_cen_a (mem_cen_a ), + .mem_web_a (mem_web_a ), + .mem_mask_a0 (mem0_mask_a ), + .mem_mask_a1 (mem1_mask_a ), + .mem_mask_a2 (mem2_mask_a ), + .mem_mask_a3 (mem3_mask_a ), + .mem_din_a0 (mem0_din_a ), + .mem_din_a1 (mem1_din_a ), + .mem_din_a2 (mem2_din_a ), + .mem_din_a3 (mem3_din_a ), + .mem_dout_a0 (mem0_dout_a ), + .mem_dout_a1 (mem1_dout_a ), + .mem_dout_a2 (mem2_dout_a ), + .mem_dout_a3 (mem3_dout_a ), + // PORT-B + .mem_clk_b (mem_clk_b ), + .mem_cen_b (mem_cen_b ), + .mem_addr_b0 (mem0_addr_b ), + .mem_addr_b1 (mem1_addr_b ), + .mem_addr_b2 (mem2_addr_b ), + .mem_addr_b3 (mem3_addr_b ) ); -/*** sky130_sram_2kbyte_1rw1r_32x512_8 u_sram0_2kb( `ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif // Port 0: RW - .clk0 (mem_clk_a[0]), - .csb0 (mem_cen_a[0]), - .web0 (mem_web_a[0]), - .wmask0 (mem0_mask_a), - .addr0 (mem0_addr_a), - .din0 (mem0_din_a), - .dout0 (mem0_dout_a), + .clk0 (mem_clk_a[0] ), + .csb0 (mem_cen_a[0] ), + .web0 (mem_web_a[0] ), + .wmask0 (mem0_mask_a ), + .addr0 (mem0_addr_a ), + .din0 (mem0_din_a ), + .dout0 (mem0_dout_a ), // Port 1: R - .clk1 (mem_clk_b[0]), - .csb1 (mem_cen_b[0]), - .addr1 (mem0_addr_b), - .dout1 () + .clk1 (mem_clk_b[0] ), + .csb1 (mem_cen_b[0] ), + .addr1 (mem0_addr_b ), + .dout1 ( ) ); sky130_sram_2kbyte_1rw1r_32x512_8 u_sram1_2kb( `ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif // Port 0: RW - .clk0 (mem_clk_a[1]), - .csb0 (mem_cen_a[1]), - .web0 (mem_web_a[1]), - .wmask0 (mem1_mask_a), - .addr0 (mem1_addr_a), - .din0 (mem1_din_a), - .dout0 (mem1_dout_a), + .clk0 (mem_clk_a[1] ), + .csb0 (mem_cen_a[1] ), + .web0 (mem_web_a[1] ), + .wmask0 (mem1_mask_a ), + .addr0 (mem1_addr_a ), + .din0 (mem1_din_a ), + .dout0 (mem1_dout_a ), // Port 1: R - .clk1 (mem_clk_b[1]), - .csb1 (mem_cen_b[1]), - .addr1 (mem1_addr_b), - .dout1 () + .clk1 (mem_clk_b[1] ), + .csb1 (mem_cen_b[1] ), + .addr1 (mem1_addr_b ), + .dout1 ( ) ); sky130_sram_2kbyte_1rw1r_32x512_8 u_sram2_2kb( `ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif // Port 0: RW - .clk0 (mem_clk_a[2]), - .csb0 (mem_cen_a[2]), - .web0 (mem_web_a[2]), - .wmask0 (mem2_mask_a), - .addr0 (mem2_addr_a), - .din0 (mem2_din_a), - .dout0 (mem2_dout_a), + .clk0 (mem_clk_a[2] ), + .csb0 (mem_cen_a[2] ), + .web0 (mem_web_a[2] ), + .wmask0 (mem2_mask_a ), + .addr0 (mem2_addr_a ), + .din0 (mem2_din_a ), + .dout0 (mem2_dout_a ), // Port 1: R - .clk1 (mem_clk_b[2]), - .csb1 (mem_cen_b[2]), - .addr1 (mem2_addr_b), - .dout1 () + .clk1 (mem_clk_b[2] ), + .csb1 (mem_cen_b[2] ), + .addr1 (mem2_addr_b ), + .dout1 ( ) ); sky130_sram_2kbyte_1rw1r_32x512_8 u_sram3_2kb( `ifdef USE_POWER_PINS - .vccd1 (vccd1),// User area 1 1.8V supply - .vssd1 (vssd1),// User area 1 digital ground + .vccd1 (vccd1 ),// User area 1 1.8V supply + .vssd1 (vssd1 ),// User area 1 digital ground `endif // Port 0: RW - .clk0 (mem_clk_a[3]), - .csb0 (mem_cen_a[3]), - .web0 (mem_web_a[3]), - .wmask0 (mem3_mask_a), - .addr0 (mem3_addr_a), - .din0 (mem3_din_a), - .dout0 (mem3_dout_a), + .clk0 (mem_clk_a[3] ), + .csb0 (mem_cen_a[3] ), + .web0 (mem_web_a[3] ), + .wmask0 (mem3_mask_a ), + .addr0 (mem3_addr_a ), + .din0 (mem3_din_a ), + .dout0 (mem3_dout_a ), // Port 1: R - .clk1 (mem_clk_b[3]), - .csb1 (mem_cen_b[3]), - .addr1 (mem3_addr_b), - .dout1 () + .clk1 (mem_clk_b[3] ), + .csb1 (mem_cen_b[3] ), + .addr1 (mem3_addr_b ), + .dout1 ( ) ); -**/ /*** sar_adc u_adc (
diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index 1f83bc6..ef22d72 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -169,7 +169,6 @@ output logic m2_wbd_err_o, // Master 3 Interface - input logic [31:0] m3_wbd_dat_i, input logic [31:0] m3_wbd_adr_i, input logic [3:0] m3_wbd_sel_i, input logic [9:0] m3_wbd_bl_i, @@ -428,7 +427,7 @@ assign m2_wb_wr.wbd_stb = m2_wbd_stb_i; assign m2_wb_wr.wbd_tid = m2_wbd_tid_i; -assign m3_wb_wr.wbd_dat = m3_wbd_dat_i; +assign m3_wb_wr.wbd_dat = 'h0; assign m3_wb_wr.wbd_adr = {m3_wbd_adr_i[31:2],2'b00}; assign m3_wb_wr.wbd_sel = m3_wbd_sel_i; assign m3_wb_wr.wbd_bl = m3_wbd_bl_i;
diff --git a/verilog/rtl/yifive/ycr1c b/verilog/rtl/yifive/ycr1c index 8b57442..08852b6 160000 --- a/verilog/rtl/yifive/ycr1c +++ b/verilog/rtl/yifive/ycr1c
@@ -1 +1 @@ -Subproject commit 8b5744202fecf8a87d84da5dc7583a84aeef4fc1 +Subproject commit 08852b63dac383caf5161340680e28ce834065a4