re-hardening with mpw-7 tool set and sky130b pdk
diff --git a/gds/pinmux.gds.gz b/gds/pinmux.gds.gz index 2124fbf..0bbec7c 100644 --- a/gds/pinmux.gds.gz +++ b/gds/pinmux.gds.gz Binary files differ
diff --git a/gds/qspim_top.gds.gz b/gds/qspim_top.gds.gz index c200079..61c0b87 100644 --- a/gds/qspim_top.gds.gz +++ b/gds/qspim_top.gds.gz Binary files differ
diff --git a/gds/uart_i2c_usb_spi_top.gds.gz b/gds/uart_i2c_usb_spi_top.gds.gz index 7916f13..1c0bce6 100644 --- a/gds/uart_i2c_usb_spi_top.gds.gz +++ b/gds/uart_i2c_usb_spi_top.gds.gz Binary files differ
diff --git a/gds/user_project_wrapper.gds.gz b/gds/user_project_wrapper.gds.gz index 97b442b..f9429d9 100644 --- a/gds/user_project_wrapper.gds.gz +++ b/gds/user_project_wrapper.gds.gz Binary files differ
diff --git a/gds/wb_host.gds.gz b/gds/wb_host.gds.gz index 29b4c27..92a9c94 100644 --- a/gds/wb_host.gds.gz +++ b/gds/wb_host.gds.gz Binary files differ
diff --git a/gds/wb_interconnect.gds.gz b/gds/wb_interconnect.gds.gz index 7ebc79b..23ce9c8 100644 --- a/gds/wb_interconnect.gds.gz +++ b/gds/wb_interconnect.gds.gz Binary files differ
diff --git a/gds/ycr4_iconnect.gds.gz b/gds/ycr4_iconnect.gds.gz index d303f3b..efeb1cf 100644 --- a/gds/ycr4_iconnect.gds.gz +++ b/gds/ycr4_iconnect.gds.gz Binary files differ
diff --git a/gds/ycr_core_top.gds.gz b/gds/ycr_core_top.gds.gz index 2cbe5a3..58b6620 100644 --- a/gds/ycr_core_top.gds.gz +++ b/gds/ycr_core_top.gds.gz Binary files differ
diff --git a/gds/ycr_intf.gds.gz b/gds/ycr_intf.gds.gz index bd4c353..dd5941c 100644 --- a/gds/ycr_intf.gds.gz +++ b/gds/ycr_intf.gds.gz Binary files differ
diff --git a/lef/pinmux.lef.gz b/lef/pinmux.lef.gz index b2366fa..4bebdbf 100644 --- a/lef/pinmux.lef.gz +++ b/lef/pinmux.lef.gz Binary files differ
diff --git a/lef/qspim_top.lef.gz b/lef/qspim_top.lef.gz index 7ef573b..dc9cfc3 100644 --- a/lef/qspim_top.lef.gz +++ b/lef/qspim_top.lef.gz Binary files differ
diff --git a/lef/uart_i2c_usb_spi_top.lef.gz b/lef/uart_i2c_usb_spi_top.lef.gz index 19397fd..b65b27a 100644 --- a/lef/uart_i2c_usb_spi_top.lef.gz +++ b/lef/uart_i2c_usb_spi_top.lef.gz Binary files differ
diff --git a/lef/user_project_wrapper.lef.gz b/lef/user_project_wrapper.lef.gz index 7e5aa17..ada9c2e 100644 --- a/lef/user_project_wrapper.lef.gz +++ b/lef/user_project_wrapper.lef.gz Binary files differ
diff --git a/lef/wb_host.lef.gz b/lef/wb_host.lef.gz index ab38f73..71ef2ad 100644 --- a/lef/wb_host.lef.gz +++ b/lef/wb_host.lef.gz Binary files differ
diff --git a/lef/wb_interconnect.lef.gz b/lef/wb_interconnect.lef.gz index 60b69e7..ed2ebf8 100644 --- a/lef/wb_interconnect.lef.gz +++ b/lef/wb_interconnect.lef.gz Binary files differ
diff --git a/lef/ycr4_iconnect.lef.gz b/lef/ycr4_iconnect.lef.gz index ae91045..cbd1815 100644 --- a/lef/ycr4_iconnect.lef.gz +++ b/lef/ycr4_iconnect.lef.gz Binary files differ
diff --git a/lef/ycr_core_top.lef.gz b/lef/ycr_core_top.lef.gz index 0fa5f32..cb63167 100644 --- a/lef/ycr_core_top.lef.gz +++ b/lef/ycr_core_top.lef.gz Binary files differ
diff --git a/lef/ycr_intf.lef.gz b/lef/ycr_intf.lef.gz index b4064c5..fa324d9 100644 --- a/lef/ycr_intf.lef.gz +++ b/lef/ycr_intf.lef.gz Binary files differ
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl index 26ce028..c27d14e 100755 --- a/openlane/pinmux/config.tcl +++ b/openlane/pinmux/config.tcl
@@ -41,24 +41,24 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ - $script_dir/../../verilog/rtl/pinmux/src/pinmux.sv \ - $script_dir/../../verilog/rtl/pinmux/src/pinmux_reg.sv \ - $script_dir/../../verilog/rtl/pinmux/src/gpio_intr.sv \ - $script_dir/../../verilog/rtl/pinmux/src/pwm.sv \ - $script_dir/../../verilog/rtl/pinmux/src/timer.sv \ - $script_dir/../../verilog/rtl/lib/pulse_gen_type1.sv \ - $script_dir/../../verilog/rtl/lib/pulse_gen_type2.sv \ - $script_dir/../../verilog/rtl/lib/registers.v \ - $script_dir/../../verilog/rtl/lib/ctech_cells.sv \ - $script_dir/../../verilog/rtl/lib/reset_sync.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pinmux_reg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/gpio_intr.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/pwm.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/pinmux/src/timer.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type1.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/pulse_gen_type2.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \ " set ::env(SYNTH_DEFINES) [list SYNTHESIS ] set ::env(SYNTH_READ_BLACKBOX_LIB) 1 -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" +set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc +set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc set ::env(LEC_ENABLE) 0 @@ -102,7 +102,7 @@ #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/qspim_top/base.sdc b/openlane/qspim_top/base.sdc index 327d1f4..c0e8993 100644 --- a/openlane/qspim_top/base.sdc +++ b/openlane/qspim_top/base.sdc
@@ -24,7 +24,7 @@ set_propagated_clock [get_clocks {spiclk}] set_clock_transition 0.1500 [all_clocks] -set_clock_uncertainty -setup 0.2500 [all_clocks] +set_clock_uncertainty -setup 0.5000 [all_clocks] set_clock_uncertainty -hold 0.2500 [all_clocks] set ::env(SYNTH_TIMING_DERATE) 0.05
diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl index 187e486..0ce98bf 100755 --- a/openlane/qspim_top/config.tcl +++ b/openlane/qspim_top/config.tcl
@@ -41,23 +41,23 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/lib/clk_skew_adjust.gv \ - $script_dir/../../verilog/rtl/lib/reset_sync.sv \ - $script_dir/../../verilog/rtl/qspim/src/qspim_top.sv \ - $script_dir/../../verilog/rtl/qspim/src/qspim_if.sv \ - $script_dir/../../verilog/rtl/qspim/src/qspim_regs.sv \ - $script_dir/../../verilog/rtl/qspim/src/qspim_fifo.sv \ - $script_dir/../../verilog/rtl/qspim/src/qspim_clkgen.sv \ - $script_dir/../../verilog/rtl/qspim/src/qspim_ctrl.sv \ - $script_dir/../../verilog/rtl/qspim/src/qspim_rx.sv \ - $script_dir/../../verilog/rtl/qspim/src/qspim_tx.sv \ - $script_dir/../../verilog/rtl/lib/ctech_cells.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_if.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_regs.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_fifo.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_clkgen.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_ctrl.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_rx.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/qspim/src/qspim_tx.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \ " set ::env(SYNTH_DEFINES) [list SYNTHESIS ] set ::env(SYNTH_READ_BLACKBOX_LIB) 1 -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" +set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc +set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc set ::env(LEC_ENABLE) 0 @@ -95,7 +95,7 @@ #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/uart_i2cm_usb_spi_top/base.sdc b/openlane/uart_i2cm_usb_spi_top/base.sdc index 4a33fc5..623b2ef 100644 --- a/openlane/uart_i2cm_usb_spi_top/base.sdc +++ b/openlane/uart_i2cm_usb_spi_top/base.sdc
@@ -12,7 +12,7 @@ create_clock -name usb_clk -period 100.0000 [get_ports {usb_clk}] set_clock_transition 0.1500 [all_clocks] -set_clock_uncertainty -setup 0.2500 [all_clocks] +set_clock_uncertainty -setup 0.5000 [all_clocks] set_clock_uncertainty -hold 0.2500 [all_clocks] @@ -44,7 +44,7 @@ set_input_delay -min 1.5000 -clock [get_clocks {app_clk}] -add_delay [get_ports {usb_rstn}] -set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_addr[*]}] +set_input_delay -max 5.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_addr[*]}] set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_be[*]}] set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_cs}] set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_wdata[*]}]
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl index 802f0cf..586d0e1 100644 --- a/openlane/uart_i2cm_usb_spi_top/config.tcl +++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -41,44 +41,44 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ - $script_dir/../../verilog/rtl/uart/src/uart_core.sv \ - $script_dir/../../verilog/rtl/uart/src/uart_cfg.sv \ - $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \ - $script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \ - $script_dir/../../verilog/rtl/lib/async_wb.sv \ - $script_dir/../../verilog/rtl/lib/async_fifo.sv \ - $script_dir/../../verilog/rtl/lib/async_fifo_th.sv \ - $script_dir/../../verilog/rtl/lib/reset_sync.sv \ - $script_dir/../../verilog/rtl/lib/double_sync_low.v \ - $script_dir/../../verilog/rtl/lib/clk_ctl.v \ - $script_dir/../../verilog/rtl/lib/registers.v \ - $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v \ - $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v \ - $script_dir/../../verilog/rtl/i2cm/src/core/i2cm_top.v \ - $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_core.sv \ - $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc16.sv \ - $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_crc5.sv \ - $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_fifo.sv \ - $script_dir/../../verilog/rtl/usb1_host/src/core/usbh_sie.sv \ - $script_dir/../../verilog/rtl/usb1_host/src/phy/usb_fs_phy.v \ - $script_dir/../../verilog/rtl/usb1_host/src/phy/usb_transceiver.v\ - $script_dir/../../verilog/rtl/usb1_host/src/top/usb1_host.sv \ - $script_dir/../../verilog/rtl/sspim/src/sspim_top.sv \ - $script_dir/../../verilog/rtl/sspim/src/sspim_ctl.sv \ - $script_dir/../../verilog/rtl/sspim/src/sspim_if.sv \ - $script_dir/../../verilog/rtl/sspim/src/sspim_cfg.sv \ - $script_dir/../../verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv\ - $script_dir/../../verilog/rtl/lib/ctech_cells.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_core.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_cfg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_rxfsm.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_txfsm.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_wb.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_fifo.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_fifo_th.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/double_sync_low.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_ctl.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/i2cm/src/core/i2cm_top.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_core.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_crc16.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_crc5.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_fifo.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/core/usbh_sie.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/phy/usb_fs_phy.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/phy/usb_transceiver.v\ + $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/top/usb1_host.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_ctl.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_if.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/sspim/src/sspim_cfg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv\ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \ " set ::env(SYNTH_NO_FLAT) {1} set ::env(SYNTH_READ_BLACKBOX_LIB) 1 -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/i2cm/src/includes $script_dir/../../verilog/rtl/usb1_host/src/includes ] +set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/i2cm/src/includes $::env(DESIGN_DIR)/../../verilog/rtl/usb1_host/src/includes ] set ::env(SYNTH_DEFINES) [list SYNTHESIS ] -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" +set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc +set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc set ::env(LEC_ENABLE) 0 @@ -91,7 +91,7 @@ set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) "absolute" -set ::env(DIE_AREA) [list 0.0 0.0 510.0 725.0] +set ::env(DIE_AREA) [list 0.0 0.0 520.0 725.0] @@ -117,13 +117,14 @@ #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 4 set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1} set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1} -set ::env(GLB_RT_ADJUSTMENT) {0.25} +#set ::env(GLB_RT_ADJUSTMENT) {0.25} +set ::env(GLB_RT_LAYER_ADJUSTMENTS) {0.25,0,0,0,0,0} set ::env(CELL_PAD) {2} set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl index 4598f8a..cd0740e 100644 --- a/openlane/user_project_wrapper/config.tcl +++ b/openlane/user_project_wrapper/config.tcl
@@ -31,9 +31,9 @@ set proj_dir [file dirname [file normalize [info script]]] set ::env(DESIGN_NAME) user_project_wrapper -set verilog_root $proj_dir/../../verilog/ -set lef_root $proj_dir/../../lef/ -set gds_root $proj_dir/../../gds/ +set verilog_root $::env(DESIGN_DIR)/../../verilog/ +set lef_root $::env(DESIGN_DIR)/../../lef/ +set gds_root $::env(DESIGN_DIR)/../../gds/ #section end # User Configurations @@ -44,8 +44,8 @@ ## Source Verilog Files set ::env(VERILOG_FILES) "\ - $proj_dir/../../verilog/rtl//yifive/ycr4c/src/top/ycr4_top_wb.sv \ - $proj_dir/../../verilog/rtl/user_project_wrapper.v" + $::env(DESIGN_DIR)/../../verilog/rtl//yifive/ycr4c/src/top/ycr4_top_wb.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/user_project_wrapper.v" ## Clock configurations @@ -57,27 +57,27 @@ ## Internal Macros ### Macro Placement set ::env(FP_SIZING) "absolute" -set ::env(MACRO_PLACEMENT_CFG) $proj_dir/macro.cfg +set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg set ::env(PDN_CFG) $proj_dir/pdn_cfg.tcl -set ::env(SDC_FILE) "$proj_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$proj_dir/base.sdc" +set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc +set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc set ::env(SYNTH_READ_BLACKBOX_LIB) 1 ### Black-box verilog and views set ::env(VERILOG_FILES_BLACKBOX) "\ - $proj_dir/../../verilog/gl/qspim_top.v \ - $proj_dir/../../verilog/gl/wb_interconnect.v \ - $proj_dir/../../verilog/gl/pinmux.v \ - $proj_dir/../../verilog/gl/uart_i2c_usb_spi_top.v \ - $proj_dir/../../verilog/gl/wb_host.v \ - $proj_dir/../../verilog/gl/ycr_intf.v \ - $proj_dir/../../verilog/gl/ycr_core_top.v \ - $proj_dir/../../verilog/gl/ycr4_iconnect.v \ - $proj_dir/../../verilog/gl/digital_pll.v \ - $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \ + $::env(DESIGN_DIR)/../../verilog/gl/qspim_top.v \ + $::env(DESIGN_DIR)/../../verilog/gl/wb_interconnect.v \ + $::env(DESIGN_DIR)/../../verilog/gl/pinmux.v \ + $::env(DESIGN_DIR)/../../verilog/gl/uart_i2c_usb_spi_top.v \ + $::env(DESIGN_DIR)/../../verilog/gl/wb_host.v \ + $::env(DESIGN_DIR)/../../verilog/gl/ycr_intf.v \ + $::env(DESIGN_DIR)/../../verilog/gl/ycr_core_top.v \ + $::env(DESIGN_DIR)/../../verilog/gl/ycr4_iconnect.v \ + $::env(DESIGN_DIR)/../../verilog/gl/digital_pll.v \ + $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \ " set ::env(EXTRA_LEFS) "\ @@ -108,7 +108,7 @@ set ::env(SYNTH_DEFINES) [list SYNTHESIS ] -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr4c/src/includes ] +set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/includes ] #set ::env(GLB_RT_MAXLAYER) 6 set ::env(RT_MAX_LAYER) {met5} @@ -131,17 +131,15 @@ li1 150 130 833.1 546.54,\ met1 150 130 833.1 546.54,\ met2 150 130 833.1 546.54,\ - met3 150 130 833.1 546.54,\ - + met3 150 130 833.1 546.54,\ li1 950 130 1633.1 546.54,\ met1 950 130 1633.1 546.54,\ met2 950 130 1633.1 546.54,\ - met3 950 130 1633.1 546.54,\ - - li1 150 750 833.1 1166.54,\ - met1 150 750 833.1 1166.54,\ - met2 150 750 833.1 1166.54,\ - met3 150 750 833.1 1166.54,\ + met3 950 130 1633.1 546.54,\ + li1 150 750 833.1 1166.54,\ + met1 150 750 833.1 1166.54,\ + met2 150 750 833.1 1166.54,\ + met3 150 750 833.1 1166.54,\ met5 0 0 2920 3520" set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0" @@ -166,6 +164,7 @@ # The following is because there are no std cells in the example wrapper project. +set ::env(CELL_PAD) "4" set ::env(SYNTH_TOP_LEVEL) 0 set ::env(PL_RANDOM_GLB_PLACEMENT) 1 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg index 5b5ee9b..67d04cb 100644 --- a/openlane/user_project_wrapper/macro.cfg +++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,6 +1,6 @@ u_qspi_master 2250 650 N u_uart_i2c_usb_spi 2250 1350 N -u_pinmux 2250 2200 N +u_pinmux 2250 2150 N u_riscv_top.i_core_top_0 75 1400 N u_riscv_top.i_core_top_1 1200 1400 FN
diff --git a/openlane/user_project_wrapper/mpw5/config.tcl b/openlane/user_project_wrapper/mpw5/config.tcl new file mode 100644 index 0000000..e2b18aa --- /dev/null +++ b/openlane/user_project_wrapper/mpw5/config.tcl
@@ -0,0 +1,200 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +# Base Configurations. Don't Touch +# section begin + +set ::env(PDK) "sky130A" +set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" + +# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS +source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl + + +# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL +source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl + + +set script_dir [file dirname [file normalize [info script]]] +set proj_dir [file dirname [file normalize [info script]]] + +set ::env(DESIGN_NAME) user_project_wrapper +set verilog_root $proj_dir/../../verilog/ +set lef_root $proj_dir/../../lef/ +set gds_root $proj_dir/../../gds/ +#section end + +# User Configurations +# +set ::env(DESIGN_IS_CORE) 1 +set ::env(FP_PDN_CORE_RING) 1 + + +## Source Verilog Files +set ::env(VERILOG_FILES) "\ + $proj_dir/../../verilog/rtl//yifive/ycr4c/src/top/ycr4_top_wb.sv \ + $proj_dir/../../verilog/rtl/user_project_wrapper.v" + + +## Clock configurations +set ::env(CLOCK_PORT) "user_clock2 wb_clk_i" +#set ::env(CLOCK_NET) "mprj.clk" + +set ::env(CLOCK_PERIOD) "10" + +## Internal Macros +### Macro Placement +set ::env(FP_SIZING) "absolute" +set ::env(MACRO_PLACEMENT_CFG) $proj_dir/macro.cfg + +set ::env(PDN_CFG) $proj_dir/pdn_cfg.tcl + +set ::env(SDC_FILE) "$proj_dir/base.sdc" +set ::env(BASE_SDC_FILE) "$proj_dir/base.sdc" + +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 + +### Black-box verilog and views +set ::env(VERILOG_FILES_BLACKBOX) "\ + $proj_dir/../../verilog/gl/qspim_top.v \ + $proj_dir/../../verilog/gl/wb_interconnect.v \ + $proj_dir/../../verilog/gl/pinmux.v \ + $proj_dir/../../verilog/gl/uart_i2c_usb_spi_top.v \ + $proj_dir/../../verilog/gl/wb_host.v \ + $proj_dir/../../verilog/gl/ycr_intf.v \ + $proj_dir/../../verilog/gl/ycr_core_top.v \ + $proj_dir/../../verilog/gl/ycr4_iconnect.v \ + $proj_dir/../../verilog/gl/digital_pll.v \ + $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \ + " + +set ::env(EXTRA_LEFS) "\ + $lef_root/qspim_top.lef \ + $lef_root/pinmux.lef \ + $lef_root/wb_interconnect.lef \ + $lef_root/uart_i2c_usb_spi_top.lef \ + $lef_root/wb_host.lef \ + $lef_root/ycr_intf.lef \ + $lef_root/ycr_core_top.lef \ + $lef_root/ycr4_iconnect.lef \ + $lef_root/digital_pll.lef \ + $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \ + " + +set ::env(EXTRA_GDS_FILES) "\ + $gds_root/qspim_top.gds \ + $gds_root/pinmux.gds \ + $gds_root/wb_interconnect.gds \ + $gds_root/uart_i2c_usb_spi_top.gds \ + $gds_root/wb_host.gds \ + $gds_root/ycr_intf.gds \ + $gds_root/ycr_core_top.gds \ + $gds_root/ycr4_iconnect.gds \ + $gds_root/digital_pll.gds \ + $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \ + " + +set ::env(SYNTH_DEFINES) [list SYNTHESIS ] + +set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr4c/src/includes ] + +#set ::env(GLB_RT_MAXLAYER) 6 +set ::env(RT_MAX_LAYER) {met5} + +set ::env(FP_PDN_CHECK_NODES) 0 + + +## Internal Macros +### Macro PDN Connections +set ::env(FP_PDN_ENABLE_MACROS_GRID) "1" +set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1" + +set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2} +set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2} +# +set ::env(VDD_PIN) {vccd1} +set ::env(GND_PIN) {vssd1} + +set ::env(GLB_RT_OBS) " \ + li1 150 130 833.1 546.54,\ + met1 150 130 833.1 546.54,\ + met2 150 130 833.1 546.54,\ + met3 150 130 833.1 546.54,\ + li1 950 130 1633.1 546.54,\ + met1 950 130 1633.1 546.54,\ + met2 950 130 1633.1 546.54,\ + met3 950 130 1633.1 546.54,\ + li1 150 750 833.1 1166.54,\ + met1 150 750 833.1 1166.54,\ + met2 150 750 833.1 1166.54,\ + met3 150 750 833.1 1166.54,\ + met1 2250 2150 2800 2600,\ + met2 2250 2150 2800 2600,\ + met3 2250 2150 2800 2600,\ + met1 950 650 1760 1290,\ + met2 950 650 1760 1290,\ + met3 950 650 1760 1290,\ + + met5 0 0 2920 3520" + +set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0" + +#set ::env(FP_PDN_MACRO_HOOKS) " \ +# u_intercon vccd1 vssd1,\ +# u_pinmux vccd1 vssd1,\ +# u_qspi_master vccd1 vssd1,\ +# u_riscv_top vccd1 vssd1,\ +# u_tsram0_2kb vccd1 vssd1,\ +# u_icache_2kb vccd1 vssd1,\ +# u_dcache_2kb vccd1 vssd1,\ +# u_sram0_2kb vccd1 vssd1,\ +# u_sram1_2kb vccd1 vssd1,\ +# u_sram2_2kb vccd1 vssd1,\ +# u_sram3_2kb vccd1 vssd1,\ +# u_uart_i2c_usb_spi vccd1 vssd1,\ +# u_wb_host vccd1 vssd1,\ +# u_riscv_top.i_core_top_0 vccd1 vssd1, \ +# u_riscv_top.u_intf vccd1 vssd1 \ +# " + + +# The following is because there are no std cells in the example wrapper project. +set ::env(SYNTH_TOP_LEVEL) 0 +set ::env(PL_RANDOM_GLB_PLACEMENT) 1 +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0 +set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0 +set ::env(FP_PDN_ENABLE_RAILS) 0 +set ::env(DIODE_INSERTION_STRATEGY) 0 +set ::env(FILL_INSERTION) 0 +set ::env(TAP_DECAP_INSERTION) 0 +set ::env(CLOCK_TREE_SYNTH) 0 +set ::env(QUIT_ON_LVS_ERROR) "1" +set ::env(QUIT_ON_MAGIC_DRC) "0" +set ::env(QUIT_ON_NEGATIVE_WNS) "0" +set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" +set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" +set ::env(FP_PDN_IRDROP) "0" +set ::env(FP_PDN_HORIZONTAL_HALO) "10" +set ::env(FP_PDN_VERTICAL_HALO) "10" +set ::env(FP_PDN_VOFFSET) "5" +set ::env(FP_PDN_VPITCH) "80" +set ::env(FP_PDN_VSPACING) "15.5" +set ::env(FP_PDN_VWIDTH) "3.1" +set ::env(FP_PDN_HOFFSET) "10" +set ::env(FP_PDN_HPITCH) "90" +set ::env(FP_PDN_HSPACING) "10" +set ::env(FP_PDN_HWIDTH) "3.1"
diff --git a/openlane/user_project_wrapper/mpw5/interactive.tcl b/openlane/user_project_wrapper/mpw5/interactive.tcl new file mode 100644 index 0000000..ccfa729 --- /dev/null +++ b/openlane/user_project_wrapper/mpw5/interactive.tcl
@@ -0,0 +1,371 @@ +#!/usr/bin/tclsh +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# Copyright 2020 Efabless Corporation +# Copyright 2020 Sylvain Munaut +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 +package require openlane; +proc run_placement_step {args} { + if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } { + set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF) + } + run_placement +} +proc run_cts_step {args} { + if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } { + set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF) + } + run_cts + run_resizer_timing +} +proc run_routing_step {args} { + if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } { + set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF) + } + run_routing +} +proc run_diode_insertion_2_5_step {args} { + if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } { + set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF) + } + if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } { + run_antenna_check + heal_antenna_violators; # modifies the routed DEF + } +} +proc run_lvs_step {{ lvs_enabled 1 }} { + if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } { + set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF) + } + if { $lvs_enabled } { + run_magic_spice_export + run_lvs; # requires run_magic_spice_export + } +} +proc run_drc_step {{ drc_enabled 1 }} { + if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } { + set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF) + } + if { $drc_enabled } { + run_magic_drc + run_klayout_drc + } +} +proc run_antenna_check_step {{ antenna_check_enabled 1 }} { + if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } { + set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF) + } + if { $antenna_check_enabled } { + run_antenna_check + } +} +proc run_eco_step {args} { + if { $::env(ECO_ENABLE) == 1 } { + run_eco + } +} +proc save_final_views {args} { + set options { + {-save_path optional} + } + set flags {} + parse_key_args "save_final_views" args arg_values $options flags_map $flags + set arg_list [list] + # If they don't exist, save_views will simply not copy them + lappend arg_list -lef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef + lappend arg_list -gds_path $::env(finishing_results)/$::env(DESIGN_NAME).gds + lappend arg_list -mag_path $::env(finishing_results)/$::env(DESIGN_NAME).mag + lappend arg_list -maglef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef.mag + lappend arg_list -spice_path $::env(finishing_results)/$::env(DESIGN_NAME).spice + + # Guaranteed to have default values + lappend arg_list -def_path $::env(CURRENT_DEF) + lappend arg_list -verilog_path $::env(CURRENT_NETLIST) + # Not guaranteed to have default values + if { [info exists ::env(SPEF_TYPICAL)] } { + lappend arg_list -spef_path $::env(SPEF_TYPICAL) + } + if { [info exists ::env(CURRENT_SDF)] } { + lappend arg_list -sdf_path $::env(CURRENT_SDF) + } + if { [info exists ::env(CURRENT_SDC)] } { + lappend arg_list -sdc_path $::env(CURRENT_SDC) + } + # Add the path if it exists... + if { [info exists arg_values(-save_path) ] } { + lappend arg_list -save_path $arg_values(-save_path) + } + # Aaand fire! + save_views {*}$arg_list +} +proc run_post_run_hooks {} { + if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} { + puts_info "Running post run hook" + set result [exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py] + puts_info "$result" + } else { + puts_info "hooks/post_run.py not found, skipping" + } +} +proc gen_pdn {args} { + puts_info "Generating PDN..." + TIMER::timer_start + + set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles).def] + set ::env(PGA_RPT_FILE) [index_file $::env(floorplan_tmpfiles).pga.rpt] + run_openroad_script $::env(SCRIPTS_DIR)/openroad/pdn.tcl \ + |& -indexed_log [index_file $::env(floorplan_logs)/pdn.log] + TIMER::timer_stop + exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "pdn generation - openroad" + quit_on_unconnected_pdn_nodes + set_def $::env(SAVE_DEF) +} +proc run_power_grid_generation {args} { + if {[info exists ::env(FP_PDN_POWER_STRAPS)]} { + set power_domains [split $::env(FP_PDN_POWER_STRAPS) ","] + } + # internal macros power connections + if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} { + set macro_hooks [dict create] + set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","] + foreach pdn_hook $pdn_hooks { + set instance_name [lindex $pdn_hook 0] + set power_net [lindex $pdn_hook 1] + set ground_net [lindex $pdn_hook 2] + dict append macro_hooks $instance_name [subst {$power_net $ground_net}] + } + + set power_net_indx [lsearch $::env(VDD_NETS) $power_net] + set ground_net_indx [lsearch $::env(GND_NETS) $ground_net] + # make sure that the specified power domains exist. + if { $power_net_indx == -1 || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } { + puts_err "Can't find $power_net and $ground_net domain. \ + Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)." + } + } + + # generate multiple power grids per pair of (VDD,GND) + # offseted by WIDTH + SPACING + foreach domain $power_domains { + set ::env(VDD_NET) [lindex $domain 0] + set ::env(GND_NET) [lindex $domain 1] + set ::env(_WITH_STRAPS) [lindex $domain 2] + puts_info "Connecting Power: $::env(VDD_NET) & $::env(GND_NET) to All internal macros." + # internal macros power connections + set ::env(FP_PDN_MACROS) "" + if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 } { + # if macros connections to power are explicitly set + # default behavoir macro pins will be connected to the first power domain + if { [info exists ::env(FP_PDN_MACRO_HOOKS)] } { + set ::env(FP_PDN_ENABLE_MACROS_GRID) 0 + foreach {instance_name hooks} $macro_hooks { + set power [lindex $hooks 0] + set ground [lindex $hooks 1] + if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } { + set ::env(FP_PDN_ENABLE_MACROS_GRID) 1 + set ::env(FP_PDN_IRDROP) "0" + puts_info "Connecting $instance_name to $power and $ground nets." + lappend ::env(FP_PDN_MACROS) $instance_name + } + } + } + } else { + puts_warn "All internal macros will not be connected to power $::env(VDD_NET) & $::env(GND_NET)." + } + + gen_pdn + set ::env(FP_PDN_ENABLE_RAILS) 0 + set ::env(FP_PDN_ENABLE_MACROS_GRID) 0 + set ::env(FP_PDN_IRDROP) "0" + # allow failure until open_pdks is up to date... + catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]} + catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]} + catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \ + [expr $::env(FP_PDN_CORE_RING_VOFFSET)\ + +2*($::env(FP_PDN_CORE_RING_VWIDTH)\ + +max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]} + catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\ + +2*($::env(FP_PDN_CORE_RING_HWIDTH)+\ + max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]} + puts "FP_PDN_VOFFSET: $::env(FP_PDN_VOFFSET)" + puts "FP_PDN_HOFFSET: $::env(FP_PDN_HOFFSET)" + puts "FP_PDN_CORE_RING_VOFFSET: $::env(FP_PDN_CORE_RING_VOFFSET)" + puts "FP_PDN_CORE_RING_HOFFSET: $::env(FP_PDN_CORE_RING_HOFFSET)" + } + set ::env(FP_PDN_ENABLE_RAILS) 1 +} +proc run_floorplan {args} { + puts_info "Running Floorplanning..." + # |----------------------------------------------------| + # |---------------- 2. FLOORPLAN ------------------| + # |----------------------------------------------------| + # + # intial fp + init_floorplan + # check for deprecated io variables + if { [info exists ::env(FP_IO_HMETAL)]} { + set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]] + puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future." + puts_warn "We recommend you update your configuration as follows:" + puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}" + } + if { [info exists ::env(FP_IO_VMETAL)]} { + set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]] + puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future." + puts_warn "We recommend you update your configuration as follows:" + puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}" + } + # place io + if { [info exists ::env(FP_PIN_ORDER_CFG)] } { + place_io_ol + } else { + if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } { + place_io + global_placement_or + place_contextualized_io \ + -lef $::env(FP_CONTEXT_LEF) \ + -def $::env(FP_CONTEXT_DEF) + } else { + place_io + } + } + apply_def_template + if { [info exist ::env(EXTRA_LEFS)] } { + if { [info exist ::env(MACRO_PLACEMENT_CFG)] } { + file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg + manual_macro_placement f + } else { + global_placement_or + basic_macro_placement + } + } + tap_decap_or + scrot_klayout -layout $::env(CURRENT_DEF) $::env(floorplan_logs)/screenshot.log + run_power_grid_generation +} +proc run_flow {args} { + set options { + {-design required} + {-from optional} + {-to optional} + {-save_path optional} + {-override_env optional} + } + set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck } + parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume + prep {*}$args + # signal trap SIGINT save_state; + if { [info exists arg_values(-override_env)] } { + set env_overrides [split $arg_values(-override_env) ','] + foreach override $env_overrides { + set kva [split $override '='] + set key [lindex $kva 0] + set value [lindex $kva 1] + set ::env(${key}) $value + } + } + set LVS_ENABLED 1 + set DRC_ENABLED 0 + set ANTENNACHECK_ENABLED 1 + set steps [dict create \ + "synthesis" {run_synthesis "" } \ + "floorplan" {run_floorplan ""} \ + "placement" {run_placement_step ""} \ + "cts" {run_cts_step ""} \ + "routing" {run_routing_step ""}\ + "eco" {run_eco_step ""} \ + "diode_insertion" {run_diode_insertion_2_5_step ""} \ + "gds_magic" {run_magic ""} \ + "gds_drc_klayout" {run_klayout ""} \ + "gds_xor_klayout" {run_klayout_gds_xor ""} \ + "lvs" "run_lvs_step $LVS_ENABLED" \ + "drc" "run_drc_step $DRC_ENABLED" \ + "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \ + "cvc" {run_lef_cvc} + ] + set_if_unset arg_values(-to) "cvc"; + if { [info exists ::env(CURRENT_STEP) ] } { + puts "\[INFO\]:Picking up where last execution left off" + puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)] + } else { + set ::env(CURRENT_STEP) "synthesis"; + } + set_if_unset arg_values(-from) $::env(CURRENT_STEP); + set exe 0; + dict for {step_name step_exe} $steps { + if { [ string equal $arg_values(-from) $step_name ] } { + set exe 1; + } + if { $exe } { + # For when it fails + set ::env(CURRENT_STEP) $step_name + [lindex $step_exe 0] [lindex $step_exe 1] ; + } + if { [ string equal $arg_values(-to) $step_name ] } { + set exe 0: + break; + } + } + # for when it resumes + set steps_as_list [dict keys $steps] + set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1] + set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx] + # Saves to <RUN_DIR>/results/final + if { $::env(SAVE_FINAL_VIEWS) == "1" } { + save_final_views + } + # Saves to design directory or custom + if { [info exists flags_map(-save) ] } { + if { ! [info exists arg_values(-save_path)] } { + set arg_values(-save_path) $::env(DESIGN_DIR) + } + save_final_views\ + -save_path $arg_values(-save_path)\ + -tag $::env(RUN_TAG) + } + calc_total_runtime + save_state + generate_final_summary_report + + check_timing_violations + + if { [info exists arg_values(-save_path)]\ + && $arg_values(-save_path) != "" } { + set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]" + } else { + set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final + } + + if {[info exists flags_map(-run_hooks)]} { + run_post_run_hooks + } + + puts_success "Flow complete." + show_warnings "Note that the following warnings have been generated:" +} +run_flow {*}$argv
diff --git a/openlane/user_project_wrapper/mpw5/pdn_cfg.tcl b/openlane/user_project_wrapper/mpw5/pdn_cfg.tcl new file mode 100644 index 0000000..552a90e --- /dev/null +++ b/openlane/user_project_wrapper/mpw5/pdn_cfg.tcl
@@ -0,0 +1,82 @@ +# Power nets +if { ! [info exists ::env(VDD_NET)] } { + set ::env(VDD_NET) $::env(VDD_PIN) +} +if { ! [info exists ::env(GND_NET)] } { + set ::env(GND_NET) $::env(GND_PIN) +} +set ::power_nets $::env(VDD_NET) +set ::ground_nets $::env(GND_NET) +if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } { + if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } { + foreach power_pin $::env(STD_CELL_POWER_PINS) { + add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern $power_pin -power + } + foreach ground_pin $::env(STD_CELL_GROUND_PINS) { + add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern $ground_pin -ground + } + } +} +set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) +# Assesses whether the deisgn is the core of the chip or not based on the +# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section +if { $::env(DESIGN_IS_CORE) == 1 } { + # Used if the design is the core of the chip + define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] + if { $::env(_WITH_STRAPS) } { + add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER + add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_UPPER_LAYER) -width $::env(FP_PDN_HWIDTH) -pitch $::env(FP_PDN_HPITCH) -offset $::env(FP_PDN_HOFFSET) -starts_with POWER + } + add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] +} else { + # Used if the design is a macro in the core + define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins $::env(FP_PDN_LOWER_LAYER) + add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER +} +# Adds the standard cell rails if enabled. +if { $::env(FP_PDN_ENABLE_RAILS) == 1 } { + add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_RAILS_LAYER) -width $::env(FP_PDN_RAIL_WIDTH) -followpins -starts_with POWER + add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}] +} +# Adds the core ring if enabled. +if { $::env(FP_PDN_CORE_RING) == 1 } { + add_pdn_ring -grid stdcell_grid -layer [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] \ + -widths [subst {$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)}] \ + -spacings [subst {$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)}] \ + -core_offset [subst {$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)}] +} +# A general macro that follows the premise of the set heirarchy. You may want to modify this or add other macro configs +# The macro power pin names are assumed to match the VDD and GND net names +# TODO: parameterize the power pin names +set macro { + orient {R0 R180 MX MY R90 R270 MXR90 MYR90} + power_pins $::env(VDD_NET) + ground_pins $::env(GND_NET) + blockages $::env(MACRO_BLOCKAGES_LAYER) + straps { + } + connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}} +} +if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1} { + if { [llength $::env(FP_PDN_MACROS)] > 0 } { + # generate automatically per instance: + foreach macro_instance $::env(FP_PDN_MACROS) { + set macro_instance_grid [subst $macro] + dict append $macro_instance_grid instance $macro_instance + set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)] + pdngen::specify_grid macro [subst $macro_instance_grid] + } + } else { + set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)] + pdngen::specify_grid macro [subst $macro] + } + # CAN NOT ENABLE THE TCL COMMAND BECAUSE THERE IS NO ARGUMENT FOR SPECIFYING THE POWER AND GROUND PIN NAMES ON THE MACRO + # define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -pin_direction vertical -halo [subst {$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)}] + # add_pdn_connect -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] +} else { + define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -halo [subst {$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)}] +} +# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area +set ::rails_start_with "POWER" ; +# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area +set ::stripes_start_with "POWER" ;
diff --git a/openlane/user_project_wrapper/mpw6/config.tcl b/openlane/user_project_wrapper/mpw6/config.tcl new file mode 100644 index 0000000..ec81ead --- /dev/null +++ b/openlane/user_project_wrapper/mpw6/config.tcl
@@ -0,0 +1,217 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +# Base Configurations. Don't Touch +# section begin + +set ::env(PDK) "sky130A" +set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" + +# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS +source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl + + +# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL +source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl + + +set script_dir [file dirname [file normalize [info script]]] +set proj_dir [file dirname [file normalize [info script]]] + +set ::env(DESIGN_NAME) user_project_wrapper +set verilog_root $proj_dir/../../verilog/ +set lef_root $proj_dir/../../lef/ +set gds_root $proj_dir/../../gds/ +#section end + +# User Configurations +# +set ::env(DESIGN_IS_CORE) 1 +set ::env(FP_PDN_CORE_RING) 1 + + +## Source Verilog Files +set ::env(VERILOG_FILES) "\ + $proj_dir/../../verilog/rtl//yifive/ycr4c/src/top/ycr4_top_wb.sv \ + $proj_dir/../../verilog/rtl/user_project_wrapper.v" + + +## Clock configurations +set ::env(CLOCK_PORT) "user_clock2 wb_clk_i" +#set ::env(CLOCK_NET) "mprj.clk" + +set ::env(CLOCK_PERIOD) "10" + +## Internal Macros +### Macro Placement +set ::env(FP_SIZING) "absolute" +set ::env(MACRO_PLACEMENT_CFG) $proj_dir/macro.cfg + +set ::env(PDN_CFG) $proj_dir/pdn_cfg.tcl + +set ::env(SDC_FILE) "$proj_dir/base.sdc" +set ::env(BASE_SDC_FILE) "$proj_dir/base.sdc" + +set ::env(SYNTH_READ_BLACKBOX_LIB) 1 + +### Black-box verilog and views +set ::env(VERILOG_FILES_BLACKBOX) "\ + $proj_dir/../../verilog/gl/qspim_top.v \ + $proj_dir/../../verilog/gl/wb_interconnect.v \ + $proj_dir/../../verilog/gl/pinmux.v \ + $proj_dir/../../verilog/gl/uart_i2c_usb_spi_top.v \ + $proj_dir/../../verilog/gl/wb_host.v \ + $proj_dir/../../verilog/gl/ycr_intf.v \ + $proj_dir/../../verilog/gl/ycr_core_top.v \ + $proj_dir/../../verilog/gl/ycr4_iconnect.v \ + $proj_dir/../../verilog/gl/digital_pll.v \ + $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v \ + " + +set ::env(EXTRA_LEFS) "\ + $lef_root/qspim_top.lef \ + $lef_root/pinmux.lef \ + $lef_root/wb_interconnect.lef \ + $lef_root/uart_i2c_usb_spi_top.lef \ + $lef_root/wb_host.lef \ + $lef_root/ycr_intf.lef \ + $lef_root/ycr_core_top.lef \ + $lef_root/ycr4_iconnect.lef \ + $lef_root/digital_pll.lef \ + $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef \ + " + +set ::env(EXTRA_GDS_FILES) "\ + $gds_root/qspim_top.gds \ + $gds_root/pinmux.gds \ + $gds_root/wb_interconnect.gds \ + $gds_root/uart_i2c_usb_spi_top.gds \ + $gds_root/wb_host.gds \ + $gds_root/ycr_intf.gds \ + $gds_root/ycr_core_top.gds \ + $gds_root/ycr4_iconnect.gds \ + $gds_root/digital_pll.gds \ + $::env(PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds \ + " + +set ::env(SYNTH_DEFINES) [list SYNTHESIS ] + +set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr4c/src/includes ] + +#set ::env(GLB_RT_MAXLAYER) 6 +set ::env(RT_MAX_LAYER) {met5} + +set ::env(FP_PDN_CHECK_NODES) 0 + + +## Internal Macros +### Macro PDN Connections +set ::env(FP_PDN_ENABLE_MACROS_GRID) "1" +set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1" + +set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2} +set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2} +# +set ::env(VDD_PIN) {vccd1} +set ::env(GND_PIN) {vssd1} + +set ::env(GLB_RT_OBS) " \ + li1 150 130 833.1 546.54,\ + met1 150 130 833.1 546.54,\ + met2 150 130 833.1 546.54,\ + met3 150 130 833.1 546.54,\ + + li1 950 130 1633.1 546.54,\ + met1 950 130 1633.1 546.54,\ + met2 950 130 1633.1 546.54,\ + met3 950 130 1633.1 546.54,\ + + li1 150 750 833.1 1166.54,\ + met1 150 750 833.1 1166.54,\ + met2 150 750 833.1 1166.54,\ + met3 150 750 833.1 1166.54,\ + met5 0 0 2920 3520" + +set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0" + +set ::env(FP_PDN_MACRO_HOOKS) " \ + u_intercon vccd1 vssd1,\ + u_pinmux vccd1 vssd1,\ + u_qspi_master vccd1 vssd1,\ + u_riscv_top vccd1 vssd1,\ + u_tsram0_2kb vccd1 vssd1,\ + u_icache_2kb vccd1 vssd1,\ + u_dcache_2kb vccd1 vssd1,\ + u_sram0_2kb vccd1 vssd1,\ + u_sram1_2kb vccd1 vssd1,\ + u_sram2_2kb vccd1 vssd1,\ + u_sram3_2kb vccd1 vssd1,\ + u_uart_i2c_usb_spi vccd1 vssd1,\ + u_wb_host vccd1 vssd1,\ + u_riscv_top.i_core_top_0 vccd1 vssd1, \ + u_riscv_top.i_core_top_1 vccd1 vssd1, \ + u_riscv_top.u_intf vccd1 vssd1 \ + " + + +# The following is because there are no std cells in the example wrapper project. +set ::env(SYNTH_TOP_LEVEL) 0 +set ::env(PL_RANDOM_GLB_PLACEMENT) 1 + +set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0 +set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0 +set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0 + +set ::env(FP_PDN_ENABLE_RAILS) 0 + +set ::env(DIODE_INSERTION_STRATEGY) 0 +set ::env(FILL_INSERTION) 0 +set ::env(TAP_DECAP_INSERTION) 0 +set ::env(CLOCK_TREE_SYNTH) 0 + +set ::env(QUIT_ON_LVS_ERROR) "1" +set ::env(QUIT_ON_MAGIC_DRC) "0" +set ::env(QUIT_ON_NEGATIVE_WNS) "0" +set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" +set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" + +set ::env(FP_PDN_IRDROP) "0" +set ::env(FP_PDN_HORIZONTAL_HALO) "10" +set ::env(FP_PDN_VERTICAL_HALO) "10" + +# + +set ::env(FP_PDN_CORE_RING_HOFFSET) {12.45} +set ::env(FP_PDN_CORE_RING_HSPACING) {1.7} +set ::env(FP_PDN_CORE_RING_HWIDTH) {3.1} + +set ::env(FP_PDN_CORE_RING_VOFFSET) {12.45} +set ::env(FP_PDN_CORE_RING_VSPACING) {1.7} +set ::env(FP_PDN_CORE_RING_VWIDTH) {3.1} + + +set ::env(FP_PDN_VOFFSET) "5" +set ::env(FP_PDN_VPITCH) "80" +set ::env(FP_PDN_VSPACING) "15.5" +set ::env(FP_PDN_VWIDTH) "3.1" + +set ::env(FP_PDN_HOFFSET) "10" +set ::env(FP_PDN_HPITCH) "90" +set ::env(FP_PDN_HSPACING) "10" +set ::env(FP_PDN_HWIDTH) "3.1" + + +
diff --git a/openlane/user_project_wrapper/mpw6/interactive.tcl b/openlane/user_project_wrapper/mpw6/interactive.tcl new file mode 100644 index 0000000..07190b7 --- /dev/null +++ b/openlane/user_project_wrapper/mpw6/interactive.tcl
@@ -0,0 +1,456 @@ +#!/usr/bin/tclsh +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# Copyright 2020 Efabless Corporation +# Copyright 2020 Sylvain Munaut +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +package require openlane; + +proc run_placement_step {args} { + if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } { + set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF) + } + + run_placement +} + +proc run_cts_step {args} { + if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } { + set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF) + } + + run_cts + run_resizer_timing +} + +proc run_routing_step {args} { + if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } { + set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF) + } + run_routing +} + +proc run_parasitics_sta_step {args} { + if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } { + set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF) + } + + if { $::env(RUN_SPEF_EXTRACTION) } { + run_parasitics_sta + } +} + +proc run_diode_insertion_2_5_step {args} { + if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } { + set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF) + } + if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } { + run_antenna_check + heal_antenna_violators; # modifies the routed DEF + } + +} + +proc run_lvs_step {{ lvs_enabled 1 }} { + if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } { + set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF) + } + + if { $lvs_enabled && $::env(RUN_LVS) } { + run_magic_spice_export; + run_lvs; # requires run_magic_spice_export + } + +} + +proc run_drc_step {{ drc_enabled 1 }} { + if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } { + set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF) + } + if { $drc_enabled } { + if { $::env(RUN_MAGIC_DRC) } { + run_magic_drc + } + if {$::env(RUN_KLAYOUT_DRC)} { + run_klayout_drc + } + } +} + +proc run_antenna_check_step {{ antenna_check_enabled 1 }} { + if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } { + set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF) + } else { + set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF) + } + if { $antenna_check_enabled } { + run_antenna_check + } +} + +proc run_eco_step {args} { + if { $::env(ECO_ENABLE) == 1 } { + run_eco_flow + } +} + +proc run_magic_step {args} { + if {$::env(RUN_MAGIC)} { + run_magic + } +} + +proc run_klayout_step {args} { + if {$::env(RUN_KLAYOUT)} { + run_klayout + } + if {$::env(RUN_KLAYOUT_XOR)} { + run_klayout_gds_xor + } +} + +proc save_final_views {args} { + set options { + {-save_path optional} + } + set flags {} + parse_key_args "save_final_views" args arg_values $options flags_map $flags + + set arg_list [list] + + # If they don't exist, save_views will simply not copy them + lappend arg_list -lef_path $::env(signoff_results)/$::env(DESIGN_NAME).lef + lappend arg_list -gds_path $::env(signoff_results)/$::env(DESIGN_NAME).gds + lappend arg_list -mag_path $::env(signoff_results)/$::env(DESIGN_NAME).mag + lappend arg_list -maglef_path $::env(signoff_results)/$::env(DESIGN_NAME).lef.mag + lappend arg_list -spice_path $::env(signoff_results)/$::env(DESIGN_NAME).spice + + # Guaranteed to have default values + lappend arg_list -def_path $::env(CURRENT_DEF) + lappend arg_list -verilog_path $::env(CURRENT_NETLIST) + + # Not guaranteed to have default values + if { [info exists ::env(CURRENT_SPEF)] } { + lappend arg_list -spef_path $::env(CURRENT_SPEF) + } + if { [info exists ::env(CURRENT_SDF)] } { + lappend arg_list -sdf_path $::env(CURRENT_SDF) + } + if { [info exists ::env(CURRENT_SDC)] } { + lappend arg_list -sdc_path $::env(CURRENT_SDC) + } + + # Add the path if it exists... + if { [info exists arg_values(-save_path) ] } { + lappend arg_list -save_path $arg_values(-save_path) + } + + # Aaand fire! + save_views {*}$arg_list + +} + +proc run_post_run_hooks {} { + if { [file exists $::env(DESIGN_DIR)/hooks/post_run.py]} { + puts_info "Running post run hook" + set result [exec $::env(OPENROAD_BIN) -python $::env(DESIGN_DIR)/hooks/post_run.py] + puts_info "$result" + } else { + puts_info "hooks/post_run.py not found, skipping" + } +} + +proc gen_pdn {args} { + increment_index + TIMER::timer_start + puts_info "Generating PDN..." + + set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles)/pdn.def] + set ::env(PGA_RPT_FILE) [index_file $::env(floorplan_tmpfiles)/pdn.pga.rpt] + + run_openroad_script $::env(SCRIPTS_DIR)/openroad/pdn.tcl \ + |& -indexed_log [index_file $::env(floorplan_logs)/pdn.log] + + + TIMER::timer_stop + exec echo "[TIMER::get_runtime]" | python3 $::env(SCRIPTS_DIR)/write_runtime.py "pdn generation - openroad" + + quit_on_unconnected_pdn_nodes + + set_def $::env(SAVE_DEF) +} + +proc run_power_grid_generation {args} { + if { [info exists ::env(VDD_NETS)] || [info exists ::env(GND_NETS)] } { + # they both must exist and be equal in length + # current assumption: they cannot have a common ground + if { ! [info exists ::env(VDD_NETS)] || ! [info exists ::env(GND_NETS)] } { + puts_err "VDD_NETS and GND_NETS must *both* either be defined or undefined" + return -code error + } + # standard cell power and ground nets are assumed to be the first net + set ::env(VDD_PIN) [lindex $::env(VDD_NETS) 0] + set ::env(GND_PIN) [lindex $::env(GND_NETS) 0] + } elseif { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } { + set ::env(VDD_NETS) [list] + set ::env(GND_NETS) [list] + # get the pins that are in $synthesis_tmpfiles.pg_define.v + # that are not in $synthesis_results.v + # + set full_pins {*}[extract_pins_from_yosys_netlist $::env(synthesis_tmpfiles)/pg_define.v] + puts_info $full_pins + + set non_pg_pins {*}[extract_pins_from_yosys_netlist $::env(synthesis_results)/$::env(DESIGN_NAME).v] + puts_info $non_pg_pins + + # assumes the pins are ordered correctly (e.g., vdd1, vss1, vcc1, vss1, ...) + foreach {vdd gnd} $full_pins { + if { $vdd ne "" && $vdd ni $non_pg_pins } { + lappend ::env(VDD_NETS) $vdd + } + if { $gnd ne "" && $gnd ni $non_pg_pins } { + lappend ::env(GND_NETS) $gnd + } + } + } else { + set ::env(VDD_NETS) $::env(VDD_PIN) + set ::env(GND_NETS) $::env(GND_PIN) + } + + puts_info "Power planning with power {$::env(VDD_NETS)} and ground {$::env(GND_NETS)}..." + + if { [llength $::env(VDD_NETS)] != [llength $::env(GND_NETS)] } { + puts_err "VDD_NETS and GND_NETS must be of equal lengths" + return -code error + } + + # check internal macros' power connection definitions + if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} { + set macro_hooks [dict create] + set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","] + foreach pdn_hook $pdn_hooks { + set instance_name [lindex $pdn_hook 0] + set power_net [lindex $pdn_hook 1] + set ground_net [lindex $pdn_hook 2] + dict append macro_hooks $instance_name [subst {$power_net $ground_net}] + } + + set power_net_indx [lsearch $::env(VDD_NETS) $power_net] + set ground_net_indx [lsearch $::env(GND_NETS) $ground_net] + + # make sure that the specified power domains exist. + if { $power_net_indx == -1 || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } { + puts_err "Can't find $power_net and $ground_net domain. \ + Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)." + } + } + + gen_pdn +} + +proc run_floorplan {args} { + puts_info "Running Floorplanning..." + # |----------------------------------------------------| + # |---------------- 2. FLOORPLAN ------------------| + # |----------------------------------------------------| + # + # intial fp + init_floorplan + + # check for deprecated io variables + if { [info exists ::env(FP_IO_HMETAL)]} { + set ::env(FP_IO_HLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_HMETAL) - 1}]] + puts_warn "You're using FP_IO_HMETAL in your configuration, which is a deprecated variable that will be removed in the future." + puts_warn "We recommend you update your configuration as follows:" + puts_warn "\tset ::env(FP_IO_HLAYER) {$::env(FP_IO_HLAYER)}" + } + + if { [info exists ::env(FP_IO_VMETAL)]} { + set ::env(FP_IO_VLAYER) [lindex $::env(TECH_METAL_LAYERS) [expr {$::env(FP_IO_VMETAL) - 1}]] + puts_warn "You're using FP_IO_VMETAL in your configuration, which is a deprecated variable that will be removed in the future." + puts_warn "We recommend you update your configuration as follows:" + puts_warn "\tset ::env(FP_IO_VLAYER) {$::env(FP_IO_VLAYER)}" + } + + + # place io + if { [info exists ::env(FP_PIN_ORDER_CFG)] } { + place_io_ol + } else { + if { [info exists ::env(FP_CONTEXT_DEF)] && [info exists ::env(FP_CONTEXT_LEF)] } { + place_io + global_placement_or + place_contextualized_io \ + -lef $::env(FP_CONTEXT_LEF) \ + -def $::env(FP_CONTEXT_DEF) + } else { + place_io + } + } + + apply_def_template + + if { [info exist ::env(EXTRA_LEFS)] } { + if { [info exist ::env(MACRO_PLACEMENT_CFG)] } { + file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg + manual_macro_placement f + } else { + global_placement_or + basic_macro_placement + } + } + + tap_decap_or + + scrot_klayout -layout $::env(CURRENT_DEF) $::env(floorplan_logs)/screenshot.log + + run_power_grid_generation +} + + +proc run_flow {args} { + set options { + {-design required} + {-from optional} + {-to optional} + {-save_path optional} + {-override_env optional} + } + set flags {-save -run_hooks -no_lvs -no_drc -no_antennacheck } + parse_key_args "run_non_interactive_mode" args arg_values $options flags_map $flags -no_consume + prep {*}$args + # signal trap SIGINT save_state; + + if { [info exists flags_map(-gui)] } { + or_gui + return + } + if { [info exists arg_values(-override_env)] } { + set env_overrides [split $arg_values(-override_env) ','] + foreach override $env_overrides { + set kva [split $override '='] + set key [lindex $kva 0] + set value [lindex $kva 1] + set ::env(${key}) $value + } + } + + set LVS_ENABLED 1 + set DRC_ENABLED 0 + set ANTENNACHECK_ENABLED 1 + + set steps [dict create \ + "synthesis" "run_synthesis" \ + "floorplan" "run_floorplan" \ + "placement" "run_placement_step" \ + "cts" "run_cts_step" \ + "routing" "run_routing_step" \ + "parasitics_sta" "run_parasitics_sta_step" \ + "eco" "run_eco_step" \ + "diode_insertion" "run_diode_insertion_2_5_step" \ + "gds_magic" "run_magic_step" \ + "gds_klayout" "run_klayout_step" \ + "lvs" "run_lvs_step $LVS_ENABLED " \ + "drc" "run_drc_step $DRC_ENABLED " \ + "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \ + "cvc" "run_lef_cvc" + ] + + set_if_unset arg_values(-to) "cvc"; + + if { [info exists ::env(CURRENT_STEP) ] } { + puts "\[INFO\]:Picking up where last execution left off" + puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)] + } else { + set ::env(CURRENT_STEP) "synthesis"; + } + + set_if_unset arg_values(-from) $::env(CURRENT_STEP); + set exe 0; + dict for {step_name step_exe} $steps { + if { [ string equal $arg_values(-from) $step_name ] } { + set exe 1; + } + + if { $exe } { + # For when it fails + set ::env(CURRENT_STEP) $step_name + [lindex $step_exe 0] [lindex $step_exe 1] ; + } + + if { [ string equal $arg_values(-to) $step_name ] } { + set exe 0: + break; + } + + } + + # for when it resumes + set steps_as_list [dict keys $steps] + set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1] + set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx] + + # Saves to <RUN_DIR>/results/final + if { $::env(SAVE_FINAL_VIEWS) == "1" } { + save_final_views + } + + # Saves to design directory or custom + if { [info exists flags_map(-save) ] } { + if { ! [info exists arg_values(-save_path)] } { + set arg_values(-save_path) $::env(DESIGN_DIR) + } + save_final_views\ + -save_path $arg_values(-save_path)\ + -tag $::env(RUN_TAG) + } + calc_total_runtime + save_state + generate_final_summary_report + + check_timing_violations + + if { [info exists arg_values(-save_path)]\ + && $arg_values(-save_path) != "" } { + set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]" + } else { + set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final + } + + if {[info exists flags_map(-run_hooks)]} { + run_post_run_hooks + } + + puts_success "Flow complete." + + show_warnings "Note that the following warnings have been generated:" + +} + +run_flow {*}$argv
diff --git a/openlane/user_project_wrapper/mpw6/pdn_cfg.tcl b/openlane/user_project_wrapper/mpw6/pdn_cfg.tcl new file mode 100644 index 0000000..1bd5f1e --- /dev/null +++ b/openlane/user_project_wrapper/mpw6/pdn_cfg.tcl
@@ -0,0 +1,165 @@ +# Power nets + +if { ! [info exists ::env(VDD_NET)] } { + set ::env(VDD_NET) $::env(VDD_PIN) +} + +if { ! [info exists ::env(GND_NET)] } { + set ::env(GND_NET) $::env(GND_PIN) +} + +if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } { + if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } { + foreach power_pin $::env(STD_CELL_POWER_PINS) { + add_global_connection \ + -net $::env(VDD_NET) \ + -inst_pattern .* \ + -pin_pattern $power_pin \ + -power + } + foreach ground_pin $::env(STD_CELL_GROUND_PINS) { + add_global_connection \ + -net $::env(GND_NET) \ + -inst_pattern .* \ + -pin_pattern $ground_pin \ + -ground + } + } +} + +if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 && + [info exists ::env(FP_PDN_MACRO_HOOKS)]} { + set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","] + foreach pdn_hook $pdn_hooks { + set instance_name [lindex $pdn_hook 0] + set power_net [lindex $pdn_hook 1] + set ground_net [lindex $pdn_hook 2] + # This assumes the power pin and the power net have the same name. + # The macro hooks only give an instance name and not power pin names. + + add_global_connection \ + -net $power_net \ + -inst_pattern $instance_name \ + -pin_pattern $power_net \ + -power + + add_global_connection \ + -net $ground_net \ + -inst_pattern $instance_name \ + -pin_pattern $ground_net \ + -ground + } +} + +set secondary [] + +foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) { + if { $vdd != $::env(VDD_NET)} { + lappend secondary $vdd + + set db_net [[ord::get_db_block] findNet $vdd] + if {$db_net == "NULL"} { + set net [odb::dbNet_create [ord::get_db_block] $vdd] + $net setSpecial + $net setSigType "POWER" + } + } + + if { $gnd != $::env(GND_NET)} { + lappend secondary $gnd + + set db_net [[ord::get_db_block] findNet $gnd] + if {$db_net == "NULL"} { + set net [odb::dbNet_create [ord::get_db_block] $gnd] + $net setSpecial + $net setSigType "GROUND" + } + } +} + +set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \ + -secondary_power $secondary + +# Assesses whether the design is the core of the chip or not based on the +# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section +if { $::env(DESIGN_IS_CORE) == 1 } { + # Used if the design is the core of the chip + define_pdn_grid \ + -name stdcell_grid \ + -starts_with POWER \ + -voltage_domain CORE \ + -pins "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)" + + add_pdn_stripe \ + -grid stdcell_grid \ + -layer $::env(FP_PDN_LOWER_LAYER) \ + -width $::env(FP_PDN_VWIDTH) \ + -pitch $::env(FP_PDN_VPITCH) \ + -offset $::env(FP_PDN_VOFFSET) \ + -nets "$::env(VDD_NET) $::env(GND_NET)" \ + -starts_with POWER -extend_to_core_ring + + add_pdn_stripe \ + -grid stdcell_grid \ + -layer $::env(FP_PDN_UPPER_LAYER) \ + -width $::env(FP_PDN_HWIDTH) \ + -pitch $::env(FP_PDN_HPITCH) \ + -offset $::env(FP_PDN_HOFFSET) \ + -nets "$::env(VDD_NET) $::env(GND_NET)" \ + -starts_with POWER -extend_to_core_ring + + add_pdn_connect \ + -grid stdcell_grid \ + -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)" +} else { + # Used if the design is a macro in the core + define_pdn_grid \ + -name stdcell_grid \ + -starts_with POWER \ + -voltage_domain CORE \ + -pins $::env(FP_PDN_LOWER_LAYER) + + add_pdn_stripe \ + -grid stdcell_grid \ + -layer $::env(FP_PDN_LOWER_LAYER) \ + -width $::env(FP_PDN_VWIDTH) \ + -pitch $::env(FP_PDN_VPITCH) \ + -offset $::env(FP_PDN_VOFFSET) \ + -starts_with POWER +} + +# Adds the standard cell rails if enabled. +if { $::env(FP_PDN_ENABLE_RAILS) == 1 } { + add_pdn_stripe \ + -grid stdcell_grid \ + -layer $::env(FP_PDN_RAILS_LAYER) \ + -width $::env(FP_PDN_RAIL_WIDTH) \ + -followpins \ + -starts_with POWER + + add_pdn_connect \ + -grid stdcell_grid \ + -layers "$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)" +} + + +# Adds the core ring if enabled. +if { $::env(FP_PDN_CORE_RING) == 1 } { + add_pdn_ring \ + -grid stdcell_grid \ + -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)" \ + -widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \ + -spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \ + -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)" +} + +define_pdn_grid \ + -macro \ + -default \ + -name macro \ + -starts_with POWER \ + -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)" + +add_pdn_connect \ + -grid macro \ + -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl index 4b29f05..527f4cc 100755 --- a/openlane/wb_host/config.tcl +++ b/openlane/wb_host/config.tcl
@@ -40,31 +40,31 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ - $script_dir/../../verilog/rtl/wb_host/src/wb_host.sv \ - $script_dir/../../verilog/rtl/lib/async_fifo.sv \ - $script_dir/../../verilog/rtl/lib/async_wb.sv \ - $script_dir/../../verilog/rtl/lib/clk_ctl.v \ - $script_dir/../../verilog/rtl/lib/ctech_cells.sv \ - $script_dir/../../verilog/rtl/lib/registers.v \ - $script_dir/../../verilog/rtl/lib/reset_sync.sv \ - $script_dir/../../verilog/rtl/lib/async_reg_bus.sv \ - $script_dir/../../verilog/rtl/uart/src/uart_txfsm.sv \ - $script_dir/../../verilog/rtl/uart/src/uart_rxfsm.sv \ - $script_dir/../../verilog/rtl/lib/double_sync_low.v \ - $script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \ - $script_dir/../../verilog/rtl/uart2wb/src/uart2wb.sv \ - $script_dir/../../verilog/rtl/uart2wb/src/uart2_core.sv \ - $script_dir/../../verilog/rtl/uart2wb/src/uart_msg_handler.v \ - $script_dir/../../verilog/rtl/sspis/src/sspis_top.sv \ - $script_dir/../../verilog/rtl/sspis/src/sspis_if.sv \ - $script_dir/../../verilog/rtl/sspis/src/spi2wb.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/wb_host/src/wb_host.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_fifo.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_wb.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/clk_ctl.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/ctech_cells.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/registers.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/reset_sync.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/async_reg_bus.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_txfsm.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/uart/src/uart_rxfsm.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/double_sync_low.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart2wb.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart2_core.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/uart2wb/src/uart_msg_handler.v \ + $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/sspis_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/sspis_if.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/sspis/src/spi2wb.sv \ " set ::env(SYNTH_READ_BLACKBOX_LIB) 1 set ::env(SYNTH_DEFINES) [list SYNTHESIS ] -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" +set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc +set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc set ::env(LEC_ENABLE) 0 @@ -102,7 +102,7 @@ #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/wb_interconnect/base.sdc b/openlane/wb_interconnect/base.sdc index d815c04..d4e6271 100644 --- a/openlane/wb_interconnect/base.sdc +++ b/openlane/wb_interconnect/base.sdc
@@ -9,7 +9,7 @@ create_clock -name clk_i -period 10.0000 [get_ports {clk_i}] set_clock_transition 0.1500 [all_clocks] -set_clock_uncertainty -setup 0.2500 [all_clocks] +set_clock_uncertainty -setup 0.5000 [all_clocks] set_clock_uncertainty -hold 0.2500 [all_clocks] #Clock Skew adjustment
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl index 55b38f4..c58574a 100755 --- a/openlane/wb_interconnect/config.tcl +++ b/openlane/wb_interconnect/config.tcl
@@ -40,23 +40,23 @@ # Local sources + no2usb sources set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ - $script_dir/../../verilog/rtl/lib/sync_wbb.sv \ - $script_dir/../../verilog/rtl/lib/sync_fifo2.sv \ - $script_dir/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \ - $script_dir/../../verilog/rtl/wb_interconnect/src/wb_slave_port.sv \ - $script_dir/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_wbb.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/lib/sync_fifo2.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_arb.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_slave_port.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/src/wb_interconnect.sv \ " set ::env(SYNTH_DEFINES) [list SYNTHESIS ] -set ::env(SYNTH_PARAMS) "CH_CLK_WD 4,\ - CH_DATA_WD 37 \ +set ::env(SYNTH_PARAMETERS) "CH_CLK_WD=4\ + CH_DATA_WD=37 \ " set ::env(SYNTH_READ_BLACKBOX_LIB) 1 -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" +set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc +set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc set ::env(LEC_ENABLE) 0 @@ -88,7 +88,7 @@ set ::env(USE_ARC_ANTENNA_CHECK) "0" -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 4 ## CTS @@ -104,14 +104,17 @@ set ::env(PL_RESIZER_MAX_CAP_MARGIN) 2 ## Routing -set ::env(GLB_RT_ADJUSTMENT) 0 -set ::env(GLB_RT_L2_ADJUSTMENT) 0.21 -set ::env(GLB_RT_L3_ADJUSTMENT) 0.21 -set ::env(GLB_RT_L4_ADJUSTMENT) 0.1 -set ::env(GLB_RT_L5_ADJUSTMENT) 0.1 -set ::env(GLB_RT_L6_ADJUSTMENT) 0.1 -set ::env(GLB_RT_ALLOW_CONGESTION) 0 -set ::env(GLB_RT_OVERFLOW_ITERS) 200 +set ::env(GRT_ADJUSTMENT) 0.1 +set ::env(DPL_CELL_PADDING) 1 + +#set ::env(GLB_RT_ADJUSTMENT) 0 +#set ::env(GLB_RT_L2_ADJUSTMENT) 0.21 +#set ::env(GLB_RT_L3_ADJUSTMENT) 0.21 +#set ::env(GLB_RT_L4_ADJUSTMENT) 0.1 +#set ::env(GLB_RT_L5_ADJUSTMENT) 0.1 +#set ::env(GLB_RT_L6_ADJUSTMENT) 0.1 +#set ::env(GLB_RT_ALLOW_CONGESTION) 0 +#set ::env(GLB_RT_OVERFLOW_ITERS) 200 #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4}
diff --git a/openlane/ycr4_iconnect/config.tcl b/openlane/ycr4_iconnect/config.tcl index a4afaf5..6d9057d 100644 --- a/openlane/ycr4_iconnect/config.tcl +++ b/openlane/ycr4_iconnect/config.tcl
@@ -34,40 +34,38 @@ set ::env(LEC_ENABLE) 0 set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_iconnect.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_cross_bar.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_dmem_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_sram_mux.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_tcm.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_timer.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_req_retiming.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/ycr_arb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/ctech_cells.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/sync_fifo2.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/primitives/ycr_reset_cells.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_iconnect.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_cross_bar.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr4_router.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr_dmem_router.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr_sram_mux.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr_tcm.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr_timer.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr_req_retiming.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/ycr_arb.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/ctech_cells.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/sync_fifo2.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/primitives/ycr_reset_cells.sv \ " -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr4c/src/includes ] +set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/includes ] set ::env(SYNTH_READ_BLACKBOX_LIB) 1 set ::env(SYNTH_DEFINES) [list SYNTHESIS ] -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" +set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc +set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc set ::env(LEC_ENABLE) 0 ## Floorplan -set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg +set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute set ::env(DIE_AREA) "0 0 390 1900" -#set ::env(PDN_CFG) $script_dir/pdn_cfg.tcl -#set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg set ::env(PL_TARGET_DENSITY) 0.20 set ::env(CELL_PAD) "2" -set ::env(GLB_RT_ADJUSTMENT) {0.2} +#set ::env(GLB_RT_ADJUSTMENT) {0.2} #set ::env(PL_ROUTABILITY_DRIVEN) "1" set ::env(PL_TIME_DRIVEN) "1" @@ -97,7 +95,7 @@ #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20 +#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20 set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl index 6be1e18..31262eb 100644 --- a/openlane/ycr_core_top/config.tcl +++ b/openlane/ycr_core_top/config.tcl
@@ -33,38 +33,38 @@ set ::env(LEC_ENABLE) 0 set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_top.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/ycr_core_top.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/ycr_dm.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/ycr_tapc_synchronizer.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/ycr_clk_ctrl.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/ycr_scu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/ycr_tapc.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/ycr_tapc_shift_reg.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/ycr_dmi.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/primitives/ycr_reset_cells.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_ifu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_idu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_exu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_mprf.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_csr.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_ialu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_mul.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_div.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_lsu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_hdu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_tdu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_ipic.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_req_retiming.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/sync_fifo2.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/ycr_core_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/ycr_dm.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/ycr_tapc_synchronizer.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/ycr_clk_ctrl.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/ycr_scu.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/ycr_tapc.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/ycr_tapc_shift_reg.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/ycr_dmi.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/primitives/ycr_reset_cells.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_ifu.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_idu.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_exu.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_mprf.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_csr.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_ialu.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_mul.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_div.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_lsu.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_hdu.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_tdu.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_ipic.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr_req_retiming.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/sync_fifo2.sv \ " -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr4c/src/includes ] +set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/includes ] set ::env(SYNTH_READ_BLACKBOX_LIB) 1 set ::env(SYNTH_DEFINES) [list SYNTHESIS ] -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" +set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc +set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc set ::env(LEC_ENABLE) 0 @@ -72,17 +72,16 @@ set ::env(GND_PIN) [list {vssd1}] ## Floorplan -set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg +set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute set ::env(DIE_AREA) "0 0 540 950 " -set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg set ::env(PL_TARGET_DENSITY) 0.43 set ::env(CELL_PAD) "4" #set ::env(GLB_RT_MAXLAYER) 5 set ::env(RT_MAX_LAYER) {met4} -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/openlane/ycr_core_top/macro_placement.cfg b/openlane/ycr_core_top/macro_placement.cfg index 8ec6301..e69de29 100644 --- a/openlane/ycr_core_top/macro_placement.cfg +++ b/openlane/ycr_core_top/macro_placement.cfg
@@ -1,2 +0,0 @@ -u_icache.u_cmem_2kb 285.000 291.000 FS -u_dcache.u_cmem_2kb 1185.000 291.000 N
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl index 92f8034..814e2b0 100644 --- a/openlane/ycr_intf/config.tcl +++ b/openlane/ycr_intf/config.tcl
@@ -34,27 +34,27 @@ set ::env(LEC_ENABLE) 0 set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/clk_skew_adjust.gv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/ctech_cells.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/cache/src/core/dcache_top.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/cache/src/core/dcache_tag_fifo.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/cache/src/core/icache_tag_fifo.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/cache/src/core/icache_top.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/cache/src/core/icache_app_fsm.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/ycr_async_wbb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_dmem_wb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_intf.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_sram_mux.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/async_fifo.sv \ - $script_dir/../../verilog/rtl/yifive/ycr4c/src/core/primitives/ycr_reset_cells.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/clk_skew_adjust.gv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/ctech_cells.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/cache/src/core/dcache_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/cache/src/core/dcache_tag_fifo.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/cache/src/core/icache_tag_fifo.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/cache/src/core/icache_top.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/cache/src/core/icache_app_fsm.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/ycr_async_wbb.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr_dmem_wb.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr_intf.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/top/ycr_sram_mux.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/lib/async_fifo.sv \ + $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/core/primitives/ycr_reset_cells.sv \ " -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr4c/src/includes ] +set ::env(VERILOG_INCLUDE_DIRS) [glob $::env(DESIGN_DIR)/../../verilog/rtl/yifive/ycr4c/src/includes ] set ::env(SYNTH_READ_BLACKBOX_LIB) 1 set ::env(SYNTH_DEFINES) [list SYNTHESIS ] -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" +set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc +set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc set ::env(LEC_ENABLE) 0 @@ -62,12 +62,11 @@ set ::env(GND_PIN) [list {vssd1}] ## Floorplan -set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg +set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg set ::env(FP_SIZING) absolute set ::env(DIE_AREA) "0 0 810 640 " set ::env(CELL_PAD) "6" -set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg set ::env(PL_TARGET_DENSITY) 0.37 set ::env(FP_IO_VEXTEND) {6} @@ -75,7 +74,7 @@ set ::env(RT_MAX_LAYER) {met4} #set ::env(GLB_RT_MAXLAYER) "5" -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 +#set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/signoff/pinmux/OPENLANE_VERSION b/signoff/pinmux/OPENLANE_VERSION index 078e9d2..ee22c3e 100644 --- a/signoff/pinmux/OPENLANE_VERSION +++ b/signoff/pinmux/OPENLANE_VERSION
@@ -1 +1 @@ -openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2 +openlane 4476a58407d670d251aa0be6a55e5391bb181c4e
diff --git a/signoff/pinmux/PDK_SOURCES b/signoff/pinmux/PDK_SOURCES index b08beb4..e8e14ea 100644 --- a/signoff/pinmux/PDK_SOURCES +++ b/signoff/pinmux/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6 +open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION index 078e9d2..ee22c3e 100644 --- a/signoff/qspim_top/OPENLANE_VERSION +++ b/signoff/qspim_top/OPENLANE_VERSION
@@ -1 +1 @@ -openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2 +openlane 4476a58407d670d251aa0be6a55e5391bb181c4e
diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES index b08beb4..e8e14ea 100644 --- a/signoff/qspim_top/PDK_SOURCES +++ b/signoff/qspim_top/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6 +open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION index 078e9d2..ee22c3e 100644 --- a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION +++ b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
@@ -1 +1 @@ -openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2 +openlane 4476a58407d670d251aa0be6a55e5391bb181c4e
diff --git a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES index b08beb4..e8e14ea 100644 --- a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES +++ b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6 +open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv index b81db37..4a2c698 100644 --- a/signoff/user_project_wrapper/final_summary_report.csv +++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@ ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY -0,/home/dinesha/workarea/opencore/git/riscduino_qcore/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h5m19s0ms,0h4m16s0ms,-2.0,-1,-1,-1,602.16,15,0,0,0,0,0,0,-1,0,0,-1,-1,1545431,14283,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.52,9.31,1.62,2.13,0.0,413,4334,413,4334,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0 +0,/home/dinesha/workarea/opencore/git/riscduino_qcore/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h5m41s0ms,0h4m15s0ms,-2.0,-1,-1,-1,601.77,15,0,0,0,0,0,0,-1,0,0,-1,-1,1536771,14397,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,7.49,9.18,1.73,2.26,0.0,413,4334,413,4334,0,0,0,15,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION index 078e9d2..ee22c3e 100644 --- a/signoff/wb_host/OPENLANE_VERSION +++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@ -openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2 +openlane 4476a58407d670d251aa0be6a55e5391bb181c4e
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES index b08beb4..e8e14ea 100644 --- a/signoff/wb_host/PDK_SOURCES +++ b/signoff/wb_host/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6 +open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION index 078e9d2..ee22c3e 100644 --- a/signoff/wb_interconnect/OPENLANE_VERSION +++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@ -openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2 +openlane 4476a58407d670d251aa0be6a55e5391bb181c4e
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES index b08beb4..e8e14ea 100644 --- a/signoff/wb_interconnect/PDK_SOURCES +++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6 +open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/ycr4_iconnect/OPENLANE_VERSION b/signoff/ycr4_iconnect/OPENLANE_VERSION index 078e9d2..ee22c3e 100644 --- a/signoff/ycr4_iconnect/OPENLANE_VERSION +++ b/signoff/ycr4_iconnect/OPENLANE_VERSION
@@ -1 +1 @@ -openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2 +openlane 4476a58407d670d251aa0be6a55e5391bb181c4e
diff --git a/signoff/ycr4_iconnect/PDK_SOURCES b/signoff/ycr4_iconnect/PDK_SOURCES index b08beb4..e8e14ea 100644 --- a/signoff/ycr4_iconnect/PDK_SOURCES +++ b/signoff/ycr4_iconnect/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6 +open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION index 078e9d2..ee22c3e 100644 --- a/signoff/ycr_core_top/OPENLANE_VERSION +++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -1 +1 @@ -openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2 +openlane 4476a58407d670d251aa0be6a55e5391bb181c4e
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES index b08beb4..e8e14ea 100644 --- a/signoff/ycr_core_top/PDK_SOURCES +++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6 +open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION index 078e9d2..ee22c3e 100644 --- a/signoff/ycr_intf/OPENLANE_VERSION +++ b/signoff/ycr_intf/OPENLANE_VERSION
@@ -1 +1 @@ -openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2 +openlane 4476a58407d670d251aa0be6a55e5391bb181c4e
diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES index b08beb4..e8e14ea 100644 --- a/signoff/ycr_intf/PDK_SOURCES +++ b/signoff/ycr_intf/PDK_SOURCES
@@ -1 +1 @@ -open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6 +open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
diff --git a/spef/pinmux.spef.gz b/spef/pinmux.spef.gz index 1c2aa4d..9bee627 100644 --- a/spef/pinmux.spef.gz +++ b/spef/pinmux.spef.gz Binary files differ
diff --git a/spef/qspim_top.spef.gz b/spef/qspim_top.spef.gz index 7521bfb..ab0453c 100644 --- a/spef/qspim_top.spef.gz +++ b/spef/qspim_top.spef.gz Binary files differ
diff --git a/spef/uart_i2c_usb_spi_top.spef.gz b/spef/uart_i2c_usb_spi_top.spef.gz index 9473011..ef60432 100644 --- a/spef/uart_i2c_usb_spi_top.spef.gz +++ b/spef/uart_i2c_usb_spi_top.spef.gz Binary files differ
diff --git a/spef/user_project_wrapper.spef.gz b/spef/user_project_wrapper.spef.gz index 0498c37..ff5af62 100644 --- a/spef/user_project_wrapper.spef.gz +++ b/spef/user_project_wrapper.spef.gz Binary files differ
diff --git a/spef/wb_host.spef.gz b/spef/wb_host.spef.gz index 90c66ef..611eb0f 100644 --- a/spef/wb_host.spef.gz +++ b/spef/wb_host.spef.gz Binary files differ
diff --git a/spef/wb_interconnect.spef.gz b/spef/wb_interconnect.spef.gz index 0cc6e30..d56ea35 100644 --- a/spef/wb_interconnect.spef.gz +++ b/spef/wb_interconnect.spef.gz Binary files differ
diff --git a/spef/ycr4_iconnect.spef.gz b/spef/ycr4_iconnect.spef.gz index 1c0666a..897750d 100644 --- a/spef/ycr4_iconnect.spef.gz +++ b/spef/ycr4_iconnect.spef.gz Binary files differ
diff --git a/spef/ycr_core_top.spef.gz b/spef/ycr_core_top.spef.gz index 77e77d9..0f468a4 100644 --- a/spef/ycr_core_top.spef.gz +++ b/spef/ycr_core_top.spef.gz Binary files differ
diff --git a/spef/ycr_intf.spef.gz b/spef/ycr_intf.spef.gz index cdb6524..b1ef309 100644 --- a/spef/ycr_intf.spef.gz +++ b/spef/ycr_intf.spef.gz Binary files differ
diff --git a/spi/lvs/pinmux.spice.gz b/spi/lvs/pinmux.spice.gz index a19f3e2..b51151c 100644 --- a/spi/lvs/pinmux.spice.gz +++ b/spi/lvs/pinmux.spice.gz Binary files differ
diff --git a/spi/lvs/qspim_top.spice.gz b/spi/lvs/qspim_top.spice.gz index fc02ddc..444ea2e 100644 --- a/spi/lvs/qspim_top.spice.gz +++ b/spi/lvs/qspim_top.spice.gz Binary files differ
diff --git a/spi/lvs/uart_i2c_usb_spi_top.spice.gz b/spi/lvs/uart_i2c_usb_spi_top.spice.gz index bddd43b..1689564 100644 --- a/spi/lvs/uart_i2c_usb_spi_top.spice.gz +++ b/spi/lvs/uart_i2c_usb_spi_top.spice.gz Binary files differ
diff --git a/spi/lvs/user_project_wrapper.spice.gz b/spi/lvs/user_project_wrapper.spice.gz index e137eb4..3d1cec9 100644 --- a/spi/lvs/user_project_wrapper.spice.gz +++ b/spi/lvs/user_project_wrapper.spice.gz Binary files differ
diff --git a/spi/lvs/wb_host.spice.gz b/spi/lvs/wb_host.spice.gz index ef2b145..6adab57 100644 --- a/spi/lvs/wb_host.spice.gz +++ b/spi/lvs/wb_host.spice.gz Binary files differ
diff --git a/spi/lvs/wb_interconnect.spice.gz b/spi/lvs/wb_interconnect.spice.gz index 4ec89d1..b352f49 100644 --- a/spi/lvs/wb_interconnect.spice.gz +++ b/spi/lvs/wb_interconnect.spice.gz Binary files differ
diff --git a/spi/lvs/ycr4_iconnect.spice.gz b/spi/lvs/ycr4_iconnect.spice.gz index a99415f..ccba229 100644 --- a/spi/lvs/ycr4_iconnect.spice.gz +++ b/spi/lvs/ycr4_iconnect.spice.gz Binary files differ
diff --git a/spi/lvs/ycr_core_top.spice.gz b/spi/lvs/ycr_core_top.spice.gz index 13e4b14..869ee3f 100644 --- a/spi/lvs/ycr_core_top.spice.gz +++ b/spi/lvs/ycr_core_top.spice.gz Binary files differ
diff --git a/spi/lvs/ycr_intf.spice.gz b/spi/lvs/ycr_intf.spice.gz index 7dce46a..97eb4ac 100644 --- a/spi/lvs/ycr_intf.spice.gz +++ b/spi/lvs/ycr_intf.spice.gz Binary files differ
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl index e80b873..ca5f009 100644 --- a/sta/scripts/caravel_timing.tcl +++ b/sta/scripts/caravel_timing.tcl
@@ -1,26 +1,26 @@ set ::env(USER_ROOT) ".." - set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-6/caravel" - set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw6" + set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-7/caravel" + set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw7/sky130B" - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib - read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib + read_liberty $::env(CARAVEL_PDK_ROOT)/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core.v read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/DFFRAM.v read_verilog $::env(CARAVEL_ROOT)/mgmt_core_wrapper/verilog/gl/mgmt_core_wrapper.v
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc index 02e4326..049e647 100644 --- a/sta/sdc/caravel.sdc +++ b/sta/sdc/caravel.sdc
@@ -36,10 +36,10 @@ ## Case analysis -set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}] +set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[0]}] set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[1]}] -set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}] -set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}] +set_case_analysis 1 [get_pins {mprj/u_intercon/cfg_cska_wi[2]}] +set_case_analysis 0 [get_pins {mprj/u_intercon/cfg_cska_wi[3]}] set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[0]}] set_case_analysis 0 [get_pins {mprj/u_pinmux/cfg_cska_pinmux[1]}] @@ -51,15 +51,15 @@ set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[2]}] set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_sp_co[3]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] -set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] +set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[0]}] +set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[1]}] set_case_analysis 0 [get_pins {mprj/u_qspi_master/cfg_cska_spi[2]}] set_case_analysis 1 [get_pins {mprj/u_qspi_master/cfg_cska_spi[3]}] -set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[0]}] set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[1]}] -set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[2]}] -set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[3]}] +set_case_analysis 1 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[2]}] +set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_cska_riscv[3]}] set_case_analysis 1 [get_pins {mprj/u_wb_host/cfg_cska_wh[0]}] set_case_analysis 0 [get_pins {mprj/u_wb_host/cfg_cska_wh[1]}]
diff --git a/verilog/dv/bfm/bfm_spim.v b/verilog/dv/bfm/bfm_spim.v new file mode 100644 index 0000000..f04f8b9 --- /dev/null +++ b/verilog/dv/bfm/bfm_spim.v
@@ -0,0 +1,260 @@ + + +// SPI Master BFM +// Command-1 : 0x10, +// SI : <CMD[7:0]> <ADDR[31:0]><Dummy[7:0]> +// SO : ------------------------------------<RDATA[31:0]> +// Command-2 : 0x2F , +// SI : <CMD[7:0]> <ADDR[31:0]><WDATA[31:0]><Dummy[7:0]> +// SO : --------------------------------------------- + +`timescale 1 ns / 1 ps +`define TB_SPI_CLK_PW 100 + +module bfm_spim ( + + // SPI + spi_clk, + spi_sel_n, + spi_din, + spi_dout + + ); + +output spi_clk; +output spi_sel_n; +output spi_din; +input spi_dout; + +reg spi_clk; +reg spi_sel_n; +reg spi_din; +reg error_ind; + +event error_detected; +integer err_cnt; + + +initial begin + +spi_clk = 0; +spi_sel_n = 1; +spi_din = 0; +error_ind = 0; +err_cnt = 0; + +end + +task init; +begin + spi_clk=1; + spi_sel_n=1; + spi_din=1; +end +endtask + + +always @error_detected begin + error_ind = 1; + err_cnt = err_cnt + 1; +end + + + +task set_spi_sel_n; +begin + #10; + spi_sel_n=0; + #100; +end +endtask + +task reset_spi_sel_n; +begin + #10; + spi_sel_n=1; + #100; +end +endtask + + + + +//----------------------------- +// Reg Write 32 Bit +//----------------------------- + +task reg_wr_dword; +input [31:0] addr; +input [31:0] dword; +reg [31:0] addr; +reg [31:0] dword; +begin + + set_spi_sel_n; + send_cmd(8'h2F); + send_dword(addr); + send_dword(dword); + send_byte(8'h0); // Dummy byte + + $display("STATUS: At time %t: SPI WRITE : ADDR = %h DATA = %h ", $time, addr, dword); + + reset_spi_sel_n; + +end +endtask + +//----------------------------- +// Reg Read 32 Bit +//----------------------------- +task reg_rd_dword; +input [31:0] addr; +output [31:0] dword; +reg [31:0] addr; +reg [31:0] dword; +integer i; +begin + + set_spi_sel_n; + send_cmd(8'h10); + send_dword(addr); + send_byte(8'h0); // Dummy byte + receive_dword(dword); + + $display("STATUS: At time %t: SPI READ :addr = %h data = %h ", $time, addr, dword); + + reset_spi_sel_n; +end +endtask + +//----------------------------- +// Reg Read 32 Bit compare +//----------------------------- +task reg_rd_dword_cmp; +input [31:0] addr; +input [31:0] exp_dword; +reg [31:0] addr; +reg [31:0] dword; +integer i; +begin + + set_spi_sel_n; + send_cmd(8'h10); + send_dword(addr); + send_byte(8'h0); // Dummy byte + receive_dword(dword); + + if (exp_dword !== dword) + begin + $display("ERROR: At time %t: SPI READ FAILED ADDR: %x EXP = %x RXD : %x ",$time,addr,exp_dword,dword); + -> error_detected; + end else begin + $display("STATUS: At time %t: SPI READ ADDR: %x RXD : %x ",$time,addr,dword); + + end + + reset_spi_sel_n; +end +endtask + + +//----------------------------- +// Command Byte +//----------------------------- +task send_cmd; +input [7:0] data; +begin +begin + send_byte(data[7:0]); +end + +end +endtask +// Write 4 Byte +task send_dword; +input dword; +reg [31:0] dword; +begin + send_word(dword[31:16]); + send_word(dword[15:0]); +end +endtask + +// Write 2 Byte +task send_word; +input word; +reg [15:0] word; +begin + send_byte(word[15:8]); + send_byte(word[7:0]); +end +endtask // spi_send_word + + + +// Write 1 Byte +task send_byte; +input data; +reg [7:0] data; +integer i; +begin + + for (i=7; i>=0; i=i-1) + begin + spi_clk=0; + spi_din = data[i]; + #`TB_SPI_CLK_PW; + spi_clk=1; + // if (i != 0) + #`TB_SPI_CLK_PW; + end + +end +endtask +//---------------------------- +// READ TASK +//---------------------------- + +// READ 4 BYTE +task receive_dword; +output dword; +reg [31:0] dword; +begin + receive_word(dword[31:16]); + receive_word(dword[15:0]); +end +endtask + +// READ 2 BYTE +task receive_word; +output word; +reg [15:0] word; +begin + receive_byte(word[15:8]); + receive_byte(word[7:0]); +end +endtask + + + +// READ 1 BYTE +task receive_byte; +output data; +reg [7:0] data; +integer i; +begin + for (i=7; i>=0; i=i-1) + begin + spi_clk=0; + #`TB_SPI_CLK_PW; + spi_clk=1; + data[i] = spi_dout; +// if (i !=0) + #`TB_SPI_CLK_PW; + end + +end +endtask + +endmodule +
diff --git a/verilog/dv/user_spi_isp/Makefile b/verilog/dv/user_spi_isp/Makefile new file mode 100644 index 0000000..f655404 --- /dev/null +++ b/verilog/dv/user_spi_isp/Makefile
@@ -0,0 +1,88 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + +# ---- Include Partitioned Makefiles ---- + +CONFIG = caravel_user_project + +####################################################################### +## Caravel Verilog for Integration Tests +####################################################################### + +DESIGNS?=../../.. + +export USER_PROJECT_VERILOG ?= $(DESIGNS)/verilog +## YIFIVE FIRMWARE +YIFIVE_FIRMWARE_PATH = $(USER_PROJECT_VERILOG)/dv/firmware +GCC_PREFIX?=riscv32-unknown-elf + + +## Simulation mode: RTL/GL +SIM?=RTL +DUMP?=OFF + +### To Enable IVERILOG FST DUMP +export IVERILOG_DUMPER = fst + + +.SUFFIXES: + +PATTERN = user_spi_isp + +all: ${PATTERN:=.vcd} + + +vvp: ${PATTERN:=.vvp} + +%.vvp: %_tb.v +ifeq ($(SIM),RTL) + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DSIM -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.lib \ + $< -o $@ + endif +else + ifeq ($(DUMP),OFF) + iverilog -g2012 -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + else + iverilog -g2012 -DWFDUMP -DFUNCTIONAL -DUSE_POWER_PINS -DGL -I $(PDK_PATH) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) \ + -f$(USER_PROJECT_VERILOG)/includes/includes.gl.lib \ + $< -o $@ + endif +endif + +%.vcd: %.vvp + vvp $< + + + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log *.dump + +.PHONY: clean all
diff --git a/verilog/dv/user_spi_isp/run_iverilog b/verilog/dv/user_spi_isp/run_iverilog new file mode 100755 index 0000000..e461fd1 --- /dev/null +++ b/verilog/dv/user_spi_isp/run_iverilog
@@ -0,0 +1,42 @@ +# ////////////////////////////////////////////////////////////////////////////// +# // SPDX-FileCopyrightText: 2021, Dinesh Annayya +# // +# // Licensed under the Apache License, Version 2.0 (the "License"); +# // you may not use this file except in compliance with the License. +# // You may obtain a copy of the License at +# // +# // http://www.apache.org/licenses/LICENSE-2.0 +# // +# // Unless required by applicable law or agreed to in writing, software +# // distributed under the License is distributed on an "AS IS" BASIS, +# // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# // See the License for the specific language governing permissions and +# // limitations under the License. +# // SPDX-License-Identifier: Apache-2.0 +# // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> +# // ////////////////////////////////////////////////////////////////////////// +riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common user_uart.c -o user_uart.o + +riscv64-unknown-elf-gcc -O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las -D__RVC_EXT -static -std=gnu99 -fno-common -fno-builtin-printf -DTCM=1 -Wa,-march=rv32imc -march=rv32imc -mabi=ilp32 -DFLAGS_STR=\""-O2 -funroll-loops -fpeel-loops -fgcse-sm -fgcse-las "\" -D__ASSEMBLY__=1 -c -I./ -I../../rtl/syntacore/scr1/sim/tests/common/ ../../rtl/syntacore/scr1/sim/tests/common/crt_tcm.S -o crt_tcm.o + +riscv64-unknown-elf-gcc -o user_uart.elf -T ../../rtl/syntacore/scr1/sim/tests/common/link_tcm.ld user_uart.o crt_tcm.o -nostartfiles -nostdlib -lc -lgcc -march=rv32imc -mabi=ilp32 + +riscv64-unknown-elf-objcopy -O verilog user_uart.elf user_uart.hex + +riscv64-unknown-elf-objdump -D user_uart.elf > user_uart.dump + +rm crt_tcm.o user_uart.o + +#iverilog with waveform dump +iverilog -g2005-sv -DWFDUMP -DFUNCTIONAL -DSIM -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../ -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I ../../../verilog/rtl/i2cm/src/includes -I ../../../verilog/rtl/usb1_host/src/includes -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp + + +#iverilog -g2005-sv -I $PDK_PATH -DFUNCTIONAL -DSIM -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/rtl -I ../../../verilog -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp + +# GLS +#iverilog -g2005-sv -D GL -D FUNCTIONAL -I $PDK_PATH -I ../../../caravel/verilog/rtl -I ../ -I ../../../verilog/gl -I ../../../verilog -I /home/dinesha/workarea/pdk/sky130A -I ../../../verilog/rtl/syntacore/scr1/src/includes -I ../../../verilog/rtl/sdram_ctrl/src/defs -I $CARAVEL_ROOT/verilog/dv/caravel -I ../model -I ../agents user_uart_tb.v -o user_uart_tb.vvp +# + +vvp user_uart_tb.vvp | tee test.log + +\rm -rf user_uart_tb.vvp
diff --git a/verilog/dv/user_spi_isp/user_spi_isp_tb.v b/verilog/dv/user_spi_isp/user_spi_isp_tb.v new file mode 100644 index 0000000..a0e0fb5 --- /dev/null +++ b/verilog/dv/user_spi_isp/user_spi_isp_tb.v
@@ -0,0 +1,254 @@ +//////////////////////////////////////////////////////////////////////////// +// SPDX-FileCopyrightText: 2021 , Dinesh Annayya +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> +////////////////////////////////////////////////////////////////////// +//// //// +//// Standalone User validation Test bench //// +//// //// +//// This file is part of the Riscduino cores project //// +//// https://github.com/dineshannayya/riscduino.git //// +//// //// +//// Description //// +//// This is a standalone test bench to validate the //// +//// Digital core using spi isp i/f. //// +//// //// +//// To Do: //// +//// nothing //// +//// //// +//// Author(s): //// +//// - Dinesh Annayya, dinesha@opencores.org //// +//// //// +//// Revision : //// +//// 0.1 - 20th Feb 2022, Dinesh A //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +`default_nettype wire + +`timescale 1 ns / 1 ps + +`include "sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v" +`include "bfm_spim.v" + +module user_spi_isp_tb; + +reg clock ; +reg wb_rst_i ; +reg power1, power2; +reg power3, power4; + +reg wbd_ext_cyc_i; // strobe/request +reg wbd_ext_stb_i; // strobe/request +reg [31:0] wbd_ext_adr_i; // address +reg wbd_ext_we_i; // write +reg [31:0] wbd_ext_dat_i; // data output +reg [3:0] wbd_ext_sel_i; // byte enable + +wire [31:0] wbd_ext_dat_o; // data input +wire wbd_ext_ack_o; // acknowlegement +wire wbd_ext_err_o; // error + +// User I/O +wire [37:0] io_oeb ; +wire [37:0] io_out ; +wire [37:0] io_in ; + +wire [37:0] mprj_io ; +wire [7:0] mprj_io_0 ; +reg test_fail ; +reg [31:0] read_data ; + +reg [127:0] la_data_in; +reg flag; + +// SCLK +wire sclk; +wire ssn; +wire sdi; +wire sdo; +wire sd_oen; + +integer i,j; + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #12.5 clock <= (clock === 1'b0); + + initial begin + clock = 0; + la_data_in = 1; + end + + `ifdef WFDUMP + initial begin + $dumpfile("simx.vcd"); + $dumpvars(0, user_spi_isp_tb); + end + `endif + + initial begin + clock = 0; + wbd_ext_cyc_i ='h0; // strobe/request + wbd_ext_stb_i ='h0; // strobe/request + wbd_ext_adr_i ='h0; // address + wbd_ext_we_i ='h0; // write + wbd_ext_dat_i ='h0; // data output + wbd_ext_sel_i ='h0; // byte enable + end +initial +begin + wb_rst_i <= 1'b1; + + #100; + wb_rst_i <= 1'b0; // Release reset + + $display("Monitor: Standalone User SPI ISP Test Started"); + + + // Remove Wb Reset + u_spim.reg_wr_dword(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1); + + repeat (2) @(posedge clock); + #1; + + $display("Monitor: Writing expected value"); + + test_fail = 0; + u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344); + u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455); + u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566); + u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677); + u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788); + u_spim.reg_wr_dword(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899); + + u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,32'h11223344); + u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,32'h22334455); + u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,32'h33445566); + u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_4,32'h44556677); + u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_5,32'h55667788); + u_spim.reg_rd_dword_cmp(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_6,32'h66778899); + + + + $display("###################################################"); + if(u_spim.err_cnt == 0) begin + `ifdef GL + $display("Monitor: Standalone User SPI ISP (GL) Passed"); + `else + $display("Monitor: Standalone User SPI ISP (RTL) Passed"); + `endif + end else begin + `ifdef GL + $display("Monitor: Standalone User SPI ISP (GL) Failed"); + `else + $display("Monitor: Standalone User SPI ISP (RTL) Failed"); + `endif + end + $display("###################################################"); + #100 + $finish; +end + + +wire USER_VDD1V8 = 1'b1; +wire VSS = 1'b0; + + +user_project_wrapper u_top( +`ifdef USE_POWER_PINS + .vccd1(USER_VDD1V8), // User area 1 1.8V supply + .vssd1(VSS), // User area 1 digital ground +`endif + .wb_clk_i (clock), // System clock + .user_clock2 (1'b1), // Real-time clock + .wb_rst_i (wb_rst_i), // Regular Reset signal + + .wbs_cyc_i (wbd_ext_cyc_i), // strobe/request + .wbs_stb_i (wbd_ext_stb_i), // strobe/request + .wbs_adr_i (wbd_ext_adr_i), // address + .wbs_we_i (wbd_ext_we_i), // write + .wbs_dat_i (wbd_ext_dat_i), // data output + .wbs_sel_i (wbd_ext_sel_i), // byte enable + + .wbs_dat_o (wbd_ext_dat_o), // data input + .wbs_ack_o (wbd_ext_ack_o), // acknowlegement + + + // Logic Analyzer Signals + .la_data_in (la_data_in) , + .la_data_out (), + .la_oenb ('0), + + + // IOs + .io_in (io_in) , + .io_out (io_out) , + .io_oeb (io_oeb) , + + .user_irq () + +); + +`ifndef GL // Drive Power for Hold Fix Buf + // All standard cell need power hook-up for functionality work + initial begin + end +`endif + +assign io_in[0] = 1'b0; +assign io_in[16] = sclk; +assign io_in[15] = sdi; +assign sdo = io_out[14]; + +bfm_spim u_spim ( + // SPI + .spi_clk (sclk ), + .spi_sel_n (ssn ), + .spi_din (sdi ), + .spi_dout (sdo ) + + ); + + +endmodule +`default_nettype wire
diff --git a/verilog/gl/pinmux.v.gz b/verilog/gl/pinmux.v.gz index cc59e29..6aa0e96 100644 --- a/verilog/gl/pinmux.v.gz +++ b/verilog/gl/pinmux.v.gz Binary files differ
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diff --git a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv index 9fb6344..d50ba34 100644 --- a/verilog/rtl/wb_interconnect/src/wb_interconnect.sv +++ b/verilog/rtl/wb_interconnect/src/wb_interconnect.sv
@@ -300,8 +300,8 @@ // 0x1001_0040 to 0x1001_007F - I2C // 0x1001_0080 to 0x1001_00BF - USB // 0x1001_00C0 to 0x1001_00FF - SSPIM -// 0x1002_0000 to 0x1002_00FF - PINMUX // 0x1001_0100 to 0x1001_013F - UART1 +// 0x1002_0000 to 0x1002_00FF - PINMUX // 0x3080_0000 to 0x3080_00FF - WB HOST (This decoding happens at wb_host block) // --------------------------------------------------------------------------- //