openlane/qspim_top/pin_order.cfg

#BUS_SORT
#MANUAL_PLACE

#E
spi_debug\[0\]        0000 0  2
spi_debug\[1\]        
spi_debug\[2\]        
spi_debug\[3\]        
spi_debug\[4\]        
spi_debug\[5\]        
spi_debug\[6\]        
spi_debug\[7\]        
spi_debug\[8\]        
spi_debug\[9\]        
spi_debug\[10\]        
spi_debug\[11\]        
spi_debug\[12\]        
spi_debug\[13\]        
spi_debug\[14\]        
spi_debug\[15\]        
spi_debug\[16\]        
spi_debug\[17\]        
spi_debug\[18\]        
spi_debug\[19\]        
spi_debug\[20\]        
spi_debug\[21\]        
spi_debug\[22\]        
spi_debug\[23\]        
spi_debug\[24\]        
spi_debug\[25\]        
spi_debug\[26\]        
spi_debug\[27\]        
spi_debug\[28\]        
spi_debug\[29\]        
spi_debug\[30\]        
spi_debug\[31\]        

spi_sdi\[3\]             0200 0 2
spi_sdi\[2\]        
spi_sdi\[1\]        
spi_sdi\[0\]        
spi_sdo\[3\]        
spi_sdo\[2\]        
spi_sdo\[1\]        
spi_sdo\[0\]  
spi_clk 
spi_csn\[3\]
spi_csn\[2\]
spi_csn\[1\]
spi_csn\[0\]
spi_oen\[3\]     
spi_oen\[2\]     
spi_oen\[1\]     
spi_oen\[0\]     


#W
cfg_cska_sp_co\[3\]   0000 0 2
cfg_cska_sp_co\[2\]
cfg_cska_sp_co\[1\]
cfg_cska_sp_co\[0\]
cfg_cska_spi\[3\]
cfg_cska_spi\[2\]
cfg_cska_spi\[1\]
cfg_cska_spi\[0\]
wbd_clk_int
wbd_clk_spi
mclk                   

wbd_stb_i              0100 0 2
wbd_we_i               
wbd_adr_i\[31\]        
wbd_adr_i\[30\]        
wbd_adr_i\[29\]        
wbd_adr_i\[28\]        
wbd_adr_i\[27\]        
wbd_adr_i\[26\]        
wbd_adr_i\[25\]        
wbd_adr_i\[24\]        
wbd_adr_i\[23\]      
wbd_adr_i\[22\]      
wbd_adr_i\[21\]      
wbd_adr_i\[20\]      
wbd_adr_i\[19\]      
wbd_adr_i\[18\]      
wbd_adr_i\[17\]      
wbd_adr_i\[16\]      
wbd_adr_i\[15\]      
wbd_adr_i\[14\]      
wbd_adr_i\[13\]      
wbd_adr_i\[12\]      
wbd_adr_i\[11\]      
wbd_adr_i\[10\]      
wbd_adr_i\[9\]       
wbd_adr_i\[8\]       
wbd_adr_i\[7\]       
wbd_adr_i\[6\]       
wbd_adr_i\[5\]       
wbd_adr_i\[4\]       
wbd_adr_i\[3\]       
wbd_adr_i\[2\]       
wbd_adr_i\[1\]       
wbd_adr_i\[0\]       
wbd_sel_i\[3\]       
wbd_sel_i\[2\]       
wbd_sel_i\[1\]       
wbd_sel_i\[0\]       
wbd_bl_i\[9\]       
wbd_bl_i\[8\]       
wbd_bl_i\[7\]       
wbd_bl_i\[6\]       
wbd_bl_i\[5\]       
wbd_bl_i\[4\]       
wbd_bl_i\[3\]       
wbd_bl_i\[2\]       
wbd_bl_i\[1\]       
wbd_bl_i\[0\]       
wbd_bry_i
wbd_dat_i\[31\]      
wbd_dat_i\[30\]      
wbd_dat_i\[29\]      
wbd_dat_i\[28\]      
wbd_dat_i\[27\]      
wbd_dat_i\[26\]      
wbd_dat_i\[25\]      
wbd_dat_i\[24\]      
wbd_dat_i\[23\]      
wbd_dat_i\[22\]      
wbd_dat_i\[21\]      
wbd_dat_i\[20\]      
wbd_dat_i\[19\]      
wbd_dat_i\[18\]      
wbd_dat_i\[17\]      
wbd_dat_i\[16\]      
wbd_dat_i\[15\]      
wbd_dat_i\[14\]      
wbd_dat_i\[13\]      
wbd_dat_i\[12\]      
wbd_dat_i\[11\]      
wbd_dat_i\[10\]      
wbd_dat_i\[9\]       
wbd_dat_i\[8\]       
wbd_dat_i\[7\]       
wbd_dat_i\[6\]       
wbd_dat_i\[5\]       
wbd_dat_i\[4\]       
wbd_dat_i\[3\]       
wbd_dat_i\[2\]       
wbd_dat_i\[1\]       
wbd_dat_i\[0\]       
wbd_dat_o\[31\]      
wbd_dat_o\[30\]      
wbd_dat_o\[29\]      
wbd_dat_o\[28\]      
wbd_dat_o\[27\]      
wbd_dat_o\[26\]      
wbd_dat_o\[25\]      
wbd_dat_o\[24\]      
wbd_dat_o\[23\]      
wbd_dat_o\[22\]      
wbd_dat_o\[21\]      
wbd_dat_o\[20\]      
wbd_dat_o\[19\]      
wbd_dat_o\[18\]      
wbd_dat_o\[17\]      
wbd_dat_o\[16\]      
wbd_dat_o\[15\]      
wbd_dat_o\[14\]      
wbd_dat_o\[13\]      
wbd_dat_o\[12\]      
wbd_dat_o\[11\]      
wbd_dat_o\[10\]      
wbd_dat_o\[9\]      
wbd_dat_o\[8\]      
wbd_dat_o\[7\]      
wbd_dat_o\[6\]      
wbd_dat_o\[5\]      
wbd_dat_o\[4\]      
wbd_dat_o\[3\]      
wbd_dat_o\[2\]      
wbd_dat_o\[1\]      
wbd_dat_o\[0\]      
wbd_ack_o           
wbd_lack_o           
wbd_err_o           


#S
rst_n                  
cfg_init_bypass
strap_sram
strap_pre_sram
strap_flash\[1\]
strap_flash\[0\]