sync with mpw6 tools set and risc timing closure 100mhz
diff --git a/Makefile b/Makefile
index b89e69f..8769137 100644
--- a/Makefile
+++ b/Makefile
@@ -86,18 +86,16 @@
$(blocks): % :
export CARAVEL_ROOT=$(CARAVEL_ROOT) && cd openlane && $(MAKE) $*
-dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
-dv-targets-rtl=$(dv_patterns:%=verify-%-rtl)
-dv-targets-gl=$(dv_patterns:%=verify-%-gl)
-dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf)
+PATTERNS=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+DV_PATTERNS = $(foreach dv, $(PATTERNS), verify-$(dv))
TARGET_PATH=$(shell pwd)
verify_command="cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} DUMP=${DUMP} RISC_CORE=${RISC_CORE} && make"
-dv_base_dependencies= ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo
-docker_run_verify=\
+$(DV_PATTERNS): verify-% : ./verilog/dv/% check-coremark_repo check-riscv_comp_repo check-riscv_test_repo
docker run -v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
-e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+ -e PDK=${PDK} \
-e CARAVEL_ROOT=${CARAVEL_ROOT} \
-e TOOLS=/opt/riscv64i \
-e DESIGNS=$(TARGET_PATH) \
@@ -107,40 +105,13 @@
-u $$(id -u $$USER):$$(id -g $$USER) riscduino/dv_setup:latest \
sh -c $(verify_command)
-.PHONY: harden
-harden: $(blocks)
.PHONY: verify
-verify: $(dv-targets)
+verify:
+ cd ./verilog/dv/ && \
+ export SIM=${SIM} DUMP=${DUMP} && \
+ $(MAKE) -j$(THREADS)
-$(dv-targets-rtl): SIM=RTL
-$(dv-targets-rtl): verify-%-rtl: $(dv_base_dependencies)
- $(docker_run_verify)
-
-$(dv-targets-gl): SIM=GL
-$(dv-targets-gl): verify-%-gl: $(dv_base_dependencies)
- $(docker_run_verify)
-
-$(dv-targets-gl-sdf): SIM=GL_SDF
-$(dv-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies)
- $(docker_run_verify)
-
-clean-targets=$(blocks:%=clean-%)
-.PHONY: $(clean-targets)
-$(clean-targets): clean-% :
- rm -f ./verilog/gl/$*.v
- rm -f ./spef/$*.spef
- rm -f ./sdc/$*.sdc
- rm -f ./sdf/$*.sdf
- rm -f ./gds/$*.gds
- rm -f ./mag/$*.mag
- rm -f ./lef/$*.lef
- rm -f ./maglef/*.maglef
-
-make_what=setup $(blocks) $(dv-targets-rtl) $(dv-targets-gl) $(dv-targets-gl-sdf) $(clean-targets)
-.PHONY: what
-what:
- # $(make_what)
# Install Openlane
.PHONY: openlane
diff --git a/openlane/Makefile b/openlane/Makefile
index e2e91a5..aea51b8 100644
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -1,5 +1,4 @@
# SPDX-FileCopyrightText: 2020 Efabless Corporation
-#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
@@ -13,16 +12,16 @@
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
-
#SHELL = sh -xv
+
BLOCKS = $(shell find * -maxdepth 0 -type d)
CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
-OPENLANE_TAG = mpw5
-OPENLANE_IMAGE_NAME = riscduino/openlane:$(OPENLANE_TAG)
-OPENLANE_BASIC_COMMAND = "cd /project/openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
-OPENLANE_INTERACTIVE_COMMAND = "cd /project/openlane && flow.tcl -it -file ./$*/interactive.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_TAG ?= mpw6
+OPENLANE_IMAGE_NAME ?= riscduino/openlane:$(OPENLANE_TAG)
+OPENLANE_BASIC_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
+OPENLANE_INTERACTIVE_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite -it -file ./$*/interactive.tcl"
all: $(BLOCKS)
@@ -30,18 +29,45 @@
@echo "Missing $@. Please create a configuration for that design"
@exit 1
-$(BLOCKS) : % : ./%/config.tcl FORCE
+.PHONY: $(BLOCKS)
+$(BLOCKS) : % : ./%/config.tcl
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+ifeq ($(PDK_ROOT),)
+ @echo "Please export PDK_ROOT"
+ @exit 1
+endif
@echo "###############################################"
@sleep 1
@if [ -f ./$*/interactive.tcl ]; then\
- docker run -it \
- -v $(PWD)/..:/project \
+ docker run --rm -v $(OPENLANE_ROOT):/openlane \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -v $(PWD)/..:$(PWD)/.. \
+ -v $(MCW_ROOT):$(MCW_ROOT) \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -e MCW_ROOT=$(MCW_ROOT) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+ -e PDK=$(PDK) \
+ -e TEST_MISMATCHES=tools \
+ -e MISMATCHES_OK=1 \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
else\
- docker run -it \
- -v $(PWD)/..:/project \
+ docker run --rm -v $(OPENLANE_ROOT):/openlane \
+ -v $(PDK_ROOT):$(PDK_ROOT) \
+ -v $(PWD)/..:$(PWD)/.. \
+ -v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+ -v $(MCW_ROOT):$(MCW_ROOT) \
+ -e MCW_ROOT=$(MCW_ROOT) \
+ -e PDK=$(PDK) \
+ -e PDK_ROOT=$(PDK_ROOT) \
+ -e CARAVEL_ROOT=$(CARAVEL_ROOT) \
+ -e TEST_MISMATCHES=tools \
+ -e MISMATCHES_OK=1 \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
fi
@@ -50,6 +76,25 @@
cp $*/runs/$*/PDK_SOURCES ../signoff/$*/
cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/
+.PHONY: openlane
+openlane: check-openlane-env
+ if [ -d "$(OPENLANE_ROOT)" ]; then\
+ echo "Deleting exisiting $(OPENLANE_ROOT)" && \
+ rm -rf $(OPENLANE_ROOT) && sleep 2; \
+ fi
+ git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
+ cd $(OPENLANE_ROOT) && \
+ export OPENLANE_IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+ export IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
+ $(MAKE) pull-openlane
+
+.PHONY: check-openlane-env
+check-openlane-env:
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+
FORCE:
clean:
diff --git a/openlane/pinmux/config.tcl b/openlane/pinmux/config.tcl
index 68f6db6..7650732 100755
--- a/openlane/pinmux/config.tcl
+++ b/openlane/pinmux/config.tcl
@@ -97,7 +97,7 @@
set ::env(FP_PDN_VWIDTH) 5
set ::env(FP_PDN_HWIDTH) 5
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
diff --git a/openlane/qspim_top/config.tcl b/openlane/qspim_top/config.tcl
index e2a3b24..f17f63d 100755
--- a/openlane/qspim_top/config.tcl
+++ b/openlane/qspim_top/config.tcl
@@ -93,7 +93,7 @@
set ::env(FP_PDN_VWIDTH) 5
set ::env(FP_PDN_HWIDTH) 5
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/sar_adc/config.tcl b/openlane/sar_adc/config.tcl
index 7b6c845..e63b7fd 100644
--- a/openlane/sar_adc/config.tcl
+++ b/openlane/sar_adc/config.tcl
@@ -53,7 +53,8 @@
set ::env(CLOCK_TREE_SYNTH) 0
set ::env(PL_TARGET_DENSITY) "0.01"
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
set ::env(GLB_RT_ADJUSTMENT) 0.15
set ::env(FP_PDN_CHECK_NODES) 0
diff --git a/openlane/uart_i2cm_usb_spi_top/base.sdc b/openlane/uart_i2cm_usb_spi_top/base.sdc
index 735b5fb..69c2345 100644
--- a/openlane/uart_i2cm_usb_spi_top/base.sdc
+++ b/openlane/uart_i2cm_usb_spi_top/base.sdc
@@ -35,10 +35,13 @@
set_max_delay 5 -from wbd_clk_int -to wbd_clk_uart
+set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {i2c_rstn}]
+set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {uart_rstn}]
+set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {usb_rstn}]
-set_input_delay 3.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {i2c_rstn}]
-set_input_delay 3.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {uart_rstn}]
-set_input_delay 3.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {usb_rstn}]
+set_input_delay -min 1.5000 -clock [get_clocks {app_clk}] -add_delay [get_ports {i2c_rstn}]
+set_input_delay -min 1.5000 -clock [get_clocks {app_clk}] -add_delay [get_ports {uart_rstn}]
+set_input_delay -min 1.5000 -clock [get_clocks {app_clk}] -add_delay [get_ports {usb_rstn}]
set_input_delay -max 6.0000 -clock [get_clocks {app_clk}] -add_delay [get_ports {reg_addr[*]}]
diff --git a/openlane/uart_i2cm_usb_spi_top/config.tcl b/openlane/uart_i2cm_usb_spi_top/config.tcl
index 2627452..9b0cbc5 100644
--- a/openlane/uart_i2cm_usb_spi_top/config.tcl
+++ b/openlane/uart_i2cm_usb_spi_top/config.tcl
@@ -72,6 +72,7 @@
$script_dir/../../verilog/rtl/lib/ctech_cells.sv \
"
+set ::env(SYNTH_NO_FLAT) {1}
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/i2cm/src/includes $script_dir/../../verilog/rtl/usb1_host/src/includes ]
set ::env(SYNTH_DEFINES) [list SYNTHESIS ]
@@ -101,7 +102,7 @@
set ::env(PL_TIME_DRIVEN) 1
-set ::env(PL_TARGET_DENSITY) "0.45"
+set ::env(PL_TARGET_DENSITY) "0.46"
# helps in anteena fix
set ::env(USE_ARC_ANTENNA_CHECK) "0"
@@ -114,7 +115,7 @@
set ::env(FP_PDN_VWIDTH) 5
set ::env(FP_PDN_HWIDTH) 5
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 4
@@ -122,6 +123,9 @@
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {1}
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {1}
+set ::env(GLB_RT_ADJUSTMENT) {0.25}
+set ::env(CELL_PAD) {2}
+
set ::env(QUIT_ON_TIMING_VIOLATIONS) "0"
set ::env(QUIT_ON_MAGIC_DRC) "1"
set ::env(QUIT_ON_LVS_ERROR) "0"
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index a766a77..641005b 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -107,7 +107,7 @@
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr4c/src/includes ]
-set ::env(GLB_RT_MAXLAYER) 6
+#set ::env(GLB_RT_MAXLAYER) 6
set ::env(RT_MAX_LAYER) {met5}
set ::env(FP_PDN_CHECK_NODES) 0
@@ -118,11 +118,11 @@
set ::env(FP_PDN_ENABLE_MACROS_GRID) "1"
set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) "1"
-set ::env(VDD_NETS) "vccd1 vccd2 vdda1 vdda2"
-set ::env(GND_NETS) "vssd1 vssd2 vssa1 vssa2"
+set ::env(VDD_NETS) {vccd1 vccd2 vdda1 vdda2}
+set ::env(GND_NETS) {vssd1 vssd2 vssa1 vssa2}
#
-set ::env(VDD_PIN) "vccd1"
-set ::env(GND_PIN) "vssd1"
+set ::env(VDD_PIN) {vccd1}
+set ::env(GND_PIN) {vssd1}
set ::env(GLB_RT_OBS) " \
li1 150 130 833.1 546.54,\
@@ -143,20 +143,24 @@
set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"
-#set ::env(FP_PDN_MACRO_HOOKS) " \
-# u_intercon vccd1 vssd1 \
-# u_pinmux vccd1 vssd1 \
-# u_qspi_master vccd1 vssd1 \
-# u_riscv_top vccd1 vssd1 \
-# u_tsram0_2kb vccd1 vssd1 \
-# u_icache_2kb vccd1 vssd1 \
-# u_dcache_2kb vccd1 vssd1 \
-# u_sram0_2kb vccd1 vssd1 \
-# u_sram1_2kb vccd1 vssd1 \
-# u_sram2_2kb vccd1 vssd1 \
-# u_sram3_2kb vccd1 vssd1 \
-# u_uart_i2c_usb_spi vccd1 vssd1 \
-# u_wb_host vccd1 vssd1 "
+set ::env(FP_PDN_MACRO_HOOKS) " \
+ u_intercon vccd1 vssd1,\
+ u_pinmux vccd1 vssd1,\
+ u_qspi_master vccd1 vssd1,\
+ u_riscv_top vccd1 vssd1,\
+ u_tsram0_2kb vccd1 vssd1,\
+ u_icache_2kb vccd1 vssd1,\
+ u_dcache_2kb vccd1 vssd1,\
+ u_sram0_2kb vccd1 vssd1,\
+ u_sram1_2kb vccd1 vssd1,\
+ u_sram2_2kb vccd1 vssd1,\
+ u_sram3_2kb vccd1 vssd1,\
+ u_uart_i2c_usb_spi vccd1 vssd1,\
+ u_wb_host vccd1 vssd1,\
+ u_riscv_top.i_core_top_0 vccd1 vssd1, \
+ u_riscv_top.i_core_top_1 vccd1 vssd1, \
+ u_riscv_top.u_intf vccd1 vssd1 \
+ "
# The following is because there are no std cells in the example wrapper project.
@@ -185,6 +189,17 @@
set ::env(FP_PDN_HORIZONTAL_HALO) "10"
set ::env(FP_PDN_VERTICAL_HALO) "10"
+#
+
+set ::env(FP_PDN_CORE_RING_HOFFSET) {12.45}
+set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_HWIDTH) {3.1}
+
+set ::env(FP_PDN_CORE_RING_VOFFSET) {12.45}
+set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
+set ::env(FP_PDN_CORE_RING_VWIDTH) {3.1}
+
+
set ::env(FP_PDN_VOFFSET) "5"
set ::env(FP_PDN_VPITCH) "80"
set ::env(FP_PDN_VSPACING) "15.5"
diff --git a/openlane/user_project_wrapper/interactive.tcl b/openlane/user_project_wrapper/interactive.tcl
index 92de09f..07190b7 100644
--- a/openlane/user_project_wrapper/interactive.tcl
+++ b/openlane/user_project_wrapper/interactive.tcl
@@ -19,41 +19,53 @@
package require openlane;
proc run_placement_step {args} {
- if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
- set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
- }
+ if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } {
+ set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF)
+ }
- run_placement
+ run_placement
}
proc run_cts_step {args} {
- if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
- set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
- }
+ if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } {
+ set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF)
+ }
- run_cts
- run_resizer_timing
+ run_cts
+ run_resizer_timing
}
proc run_routing_step {args} {
- if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
- set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
- }
- run_routing
+ if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } {
+ set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF)
+ }
+ run_routing
+}
+
+proc run_parasitics_sta_step {args} {
+ if { ! [ info exists ::env(PARSITICS_CURRENT_DEF) ] } {
+ set ::env(PARSITICS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(PARSITICS_CURRENT_DEF)
+ }
+
+ if { $::env(RUN_SPEF_EXTRACTION) } {
+ run_parasitics_sta
+ }
}
proc run_diode_insertion_2_5_step {args} {
- if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
- set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
- }
+ if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } {
+ set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF)
+ }
if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
run_antenna_check
heal_antenna_violators; # modifies the routed DEF
@@ -62,36 +74,41 @@
}
proc run_lvs_step {{ lvs_enabled 1 }} {
- if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
- set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
- }
- if { $lvs_enabled } {
- run_magic_spice_export
+ if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } {
+ set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF)
+ }
+
+ if { $lvs_enabled && $::env(RUN_LVS) } {
+ run_magic_spice_export;
run_lvs; # requires run_magic_spice_export
}
}
proc run_drc_step {{ drc_enabled 1 }} {
- if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
- set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
- }
+ if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } {
+ set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF)
+ }
if { $drc_enabled } {
- run_magic_drc
- run_klayout_drc
+ if { $::env(RUN_MAGIC_DRC) } {
+ run_magic_drc
+ }
+ if {$::env(RUN_KLAYOUT_DRC)} {
+ run_klayout_drc
+ }
}
}
proc run_antenna_check_step {{ antenna_check_enabled 1 }} {
- if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
- set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
- } else {
- set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
- }
+ if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } {
+ set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF)
+ } else {
+ set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF)
+ }
if { $antenna_check_enabled } {
run_antenna_check
}
@@ -99,8 +116,23 @@
proc run_eco_step {args} {
if { $::env(ECO_ENABLE) == 1 } {
- run_eco
- }
+ run_eco_flow
+ }
+}
+
+proc run_magic_step {args} {
+ if {$::env(RUN_MAGIC)} {
+ run_magic
+ }
+}
+
+proc run_klayout_step {args} {
+ if {$::env(RUN_KLAYOUT)} {
+ run_klayout
+ }
+ if {$::env(RUN_KLAYOUT_XOR)} {
+ run_klayout_gds_xor
+ }
}
proc save_final_views {args} {
@@ -113,19 +145,19 @@
set arg_list [list]
# If they don't exist, save_views will simply not copy them
- lappend arg_list -lef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef
- lappend arg_list -gds_path $::env(finishing_results)/$::env(DESIGN_NAME).gds
- lappend arg_list -mag_path $::env(finishing_results)/$::env(DESIGN_NAME).mag
- lappend arg_list -maglef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef.mag
- lappend arg_list -spice_path $::env(finishing_results)/$::env(DESIGN_NAME).spice
-
+ lappend arg_list -lef_path $::env(signoff_results)/$::env(DESIGN_NAME).lef
+ lappend arg_list -gds_path $::env(signoff_results)/$::env(DESIGN_NAME).gds
+ lappend arg_list -mag_path $::env(signoff_results)/$::env(DESIGN_NAME).mag
+ lappend arg_list -maglef_path $::env(signoff_results)/$::env(DESIGN_NAME).lef.mag
+ lappend arg_list -spice_path $::env(signoff_results)/$::env(DESIGN_NAME).spice
+
# Guaranteed to have default values
lappend arg_list -def_path $::env(CURRENT_DEF)
lappend arg_list -verilog_path $::env(CURRENT_NETLIST)
# Not guaranteed to have default values
- if { [info exists ::env(SPEF_TYPICAL)] } {
- lappend arg_list -spef_path $::env(SPEF_TYPICAL)
+ if { [info exists ::env(CURRENT_SPEF)] } {
+ lappend arg_list -spef_path $::env(CURRENT_SPEF)
}
if { [info exists ::env(CURRENT_SDF)] } {
lappend arg_list -sdf_path $::env(CURRENT_SDF)
@@ -154,15 +186,13 @@
}
}
-
-
-
proc gen_pdn {args} {
- puts_info "Generating PDN..."
+ increment_index
TIMER::timer_start
-
- set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles).def]
- set ::env(PGA_RPT_FILE) [index_file $::env(floorplan_tmpfiles).pga.rpt]
+ puts_info "Generating PDN..."
+
+ set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles)/pdn.def]
+ set ::env(PGA_RPT_FILE) [index_file $::env(floorplan_tmpfiles)/pdn.pga.rpt]
run_openroad_script $::env(SCRIPTS_DIR)/openroad/pdn.tcl \
|& -indexed_log [index_file $::env(floorplan_logs)/pdn.log]
@@ -177,12 +207,50 @@
}
proc run_power_grid_generation {args} {
+ if { [info exists ::env(VDD_NETS)] || [info exists ::env(GND_NETS)] } {
+ # they both must exist and be equal in length
+ # current assumption: they cannot have a common ground
+ if { ! [info exists ::env(VDD_NETS)] || ! [info exists ::env(GND_NETS)] } {
+ puts_err "VDD_NETS and GND_NETS must *both* either be defined or undefined"
+ return -code error
+ }
+ # standard cell power and ground nets are assumed to be the first net
+ set ::env(VDD_PIN) [lindex $::env(VDD_NETS) 0]
+ set ::env(GND_PIN) [lindex $::env(GND_NETS) 0]
+ } elseif { [info exists ::env(SYNTH_USE_PG_PINS_DEFINES)] } {
+ set ::env(VDD_NETS) [list]
+ set ::env(GND_NETS) [list]
+ # get the pins that are in $synthesis_tmpfiles.pg_define.v
+ # that are not in $synthesis_results.v
+ #
+ set full_pins {*}[extract_pins_from_yosys_netlist $::env(synthesis_tmpfiles)/pg_define.v]
+ puts_info $full_pins
- if {[info exists ::env(FP_PDN_POWER_STRAPS)]} {
- set power_domains [split $::env(FP_PDN_POWER_STRAPS) ","]
+ set non_pg_pins {*}[extract_pins_from_yosys_netlist $::env(synthesis_results)/$::env(DESIGN_NAME).v]
+ puts_info $non_pg_pins
+
+ # assumes the pins are ordered correctly (e.g., vdd1, vss1, vcc1, vss1, ...)
+ foreach {vdd gnd} $full_pins {
+ if { $vdd ne "" && $vdd ni $non_pg_pins } {
+ lappend ::env(VDD_NETS) $vdd
+ }
+ if { $gnd ne "" && $gnd ni $non_pg_pins } {
+ lappend ::env(GND_NETS) $gnd
+ }
+ }
+ } else {
+ set ::env(VDD_NETS) $::env(VDD_PIN)
+ set ::env(GND_NETS) $::env(GND_PIN)
}
- # internal macros power connections
+ puts_info "Power planning with power {$::env(VDD_NETS)} and ground {$::env(GND_NETS)}..."
+
+ if { [llength $::env(VDD_NETS)] != [llength $::env(GND_NETS)] } {
+ puts_err "VDD_NETS and GND_NETS must be of equal lengths"
+ return -code error
+ }
+
+ # check internal macros' power connection definitions
if {[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
set macro_hooks [dict create]
set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
@@ -192,73 +260,19 @@
set ground_net [lindex $pdn_hook 2]
dict append macro_hooks $instance_name [subst {$power_net $ground_net}]
}
-
+
set power_net_indx [lsearch $::env(VDD_NETS) $power_net]
set ground_net_indx [lsearch $::env(GND_NETS) $ground_net]
# make sure that the specified power domains exist.
if { $power_net_indx == -1 || $ground_net_indx == -1 || $power_net_indx != $ground_net_indx } {
puts_err "Can't find $power_net and $ground_net domain. \
- Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)."
- }
- }
-
- # generate multiple power grids per pair of (VDD,GND)
- # offseted by WIDTH + SPACING
- foreach domain $power_domains {
- set ::env(VDD_NET) [lindex $domain 0]
- set ::env(GND_NET) [lindex $domain 1]
- set ::env(_WITH_STRAPS) [lindex $domain 2]
-
- puts_info "Connecting Power: $::env(VDD_NET) & $::env(GND_NET) to All internal macros."
- # internal macros power connections
- set ::env(FP_PDN_MACROS) ""
- if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 } {
- # if macros connections to power are explicitly set
- # default behavoir macro pins will be connected to the first power domain
- if { [info exists ::env(FP_PDN_MACRO_HOOKS)] } {
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
- foreach {instance_name hooks} $macro_hooks {
- set power [lindex $hooks 0]
- set ground [lindex $hooks 1]
- if { $power == $::env(VDD_NET) && $ground == $::env(GND_NET) } {
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 1
- set ::env(FP_PDN_IRDROP) "0"
- puts_info "Connecting $instance_name to $power and $ground nets."
- lappend ::env(FP_PDN_MACROS) $instance_name
- }
- }
- }
- } else {
- puts_warn "All internal macros will not be connected to power $::env(VDD_NET) & $::env(GND_NET)."
+ Make sure that both exist in $::env(VDD_NETS) and $::env(GND_NETS)."
}
-
- gen_pdn
-
- set ::env(FP_PDN_ENABLE_RAILS) 0
- set ::env(FP_PDN_ENABLE_MACROS_GRID) 0
- set ::env(FP_PDN_IRDROP) "0"
-
- # allow failure until open_pdks is up to date...
- catch {set ::env(FP_PDN_VOFFSET) [expr $::env(FP_PDN_VOFFSET)+$::env(FP_PDN_VWIDTH)+$::env(FP_PDN_VSPACING)]}
- catch {set ::env(FP_PDN_HOFFSET) [expr $::env(FP_PDN_HOFFSET)+$::env(FP_PDN_HWIDTH)+$::env(FP_PDN_HSPACING)]}
-
- catch {set ::env(FP_PDN_CORE_RING_VOFFSET) \
- [expr $::env(FP_PDN_CORE_RING_VOFFSET)\
- +2*($::env(FP_PDN_CORE_RING_VWIDTH)\
- +max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
- catch {set ::env(FP_PDN_CORE_RING_HOFFSET) [expr $::env(FP_PDN_CORE_RING_HOFFSET)\
- +2*($::env(FP_PDN_CORE_RING_HWIDTH)+\
- max($::env(FP_PDN_CORE_RING_VSPACING), $::env(FP_PDN_CORE_RING_HSPACING)))]}
- puts "FP_PDN_VOFFSET: $::env(FP_PDN_VOFFSET)"
- puts "FP_PDN_HOFFSET: $::env(FP_PDN_HOFFSET)"
- puts "FP_PDN_CORE_RING_VOFFSET: $::env(FP_PDN_CORE_RING_VOFFSET)"
- puts "FP_PDN_CORE_RING_HOFFSET: $::env(FP_PDN_CORE_RING_HOFFSET)"
-
}
- set ::env(FP_PDN_ENABLE_RAILS) 1
-}
+ gen_pdn
+}
proc run_floorplan {args} {
puts_info "Running Floorplanning..."
@@ -333,6 +347,10 @@
prep {*}$args
# signal trap SIGINT save_state;
+ if { [info exists flags_map(-gui)] } {
+ or_gui
+ return
+ }
if { [info exists arg_values(-override_env)] } {
set env_overrides [split $arg_values(-override_env) ',']
foreach override $env_overrides {
@@ -347,22 +365,22 @@
set DRC_ENABLED 0
set ANTENNACHECK_ENABLED 1
- set steps [dict create \
- "synthesis" {run_synthesis "" } \
- "floorplan" {run_floorplan ""} \
- "placement" {run_placement_step ""} \
- "cts" {run_cts_step ""} \
- "routing" {run_routing_step ""}\
- "eco" {run_eco_step ""} \
- "diode_insertion" {run_diode_insertion_2_5_step ""} \
- "gds_magic" {run_magic ""} \
- "gds_drc_klayout" {run_klayout ""} \
- "gds_xor_klayout" {run_klayout_gds_xor ""} \
- "lvs" "run_lvs_step $LVS_ENABLED" \
- "drc" "run_drc_step $DRC_ENABLED" \
- "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \
- "cvc" {run_lef_cvc}
- ]
+ set steps [dict create \
+ "synthesis" "run_synthesis" \
+ "floorplan" "run_floorplan" \
+ "placement" "run_placement_step" \
+ "cts" "run_cts_step" \
+ "routing" "run_routing_step" \
+ "parasitics_sta" "run_parasitics_sta_step" \
+ "eco" "run_eco_step" \
+ "diode_insertion" "run_diode_insertion_2_5_step" \
+ "gds_magic" "run_magic_step" \
+ "gds_klayout" "run_klayout_step" \
+ "lvs" "run_lvs_step $LVS_ENABLED " \
+ "drc" "run_drc_step $DRC_ENABLED " \
+ "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED " \
+ "cvc" "run_lef_cvc"
+ ]
set_if_unset arg_values(-to) "cvc";
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index cf294f1..602ee8d 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -2,9 +2,9 @@
u_uart_i2c_usb_spi 2250 1350 N
u_pinmux 2250 2150 N
-u_riscv_top.i_core_top_0 50 1400 N
+u_riscv_top.i_core_top_0 75 1400 N
u_riscv_top.i_core_top_1 1200 1400 FN
-u_riscv_top.i_core_top_2 50 2475 N
+u_riscv_top.i_core_top_2 75 2475 N
u_riscv_top.i_core_top_3 1200 2475 FN
u_riscv_top.u_connect 725 1400 N
u_riscv_top.u_intf 950 650 N
diff --git a/openlane/user_project_wrapper/pdn_cfg.tcl b/openlane/user_project_wrapper/pdn_cfg.tcl
index 7813f95..1bd5f1e 100644
--- a/openlane/user_project_wrapper/pdn_cfg.tcl
+++ b/openlane/user_project_wrapper/pdn_cfg.tcl
@@ -8,89 +8,158 @@
set ::env(GND_NET) $::env(GND_PIN)
}
-set ::power_nets $::env(VDD_NET)
-set ::ground_nets $::env(GND_NET)
-
if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
foreach power_pin $::env(STD_CELL_POWER_PINS) {
- add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern $power_pin -power
+ add_global_connection \
+ -net $::env(VDD_NET) \
+ -inst_pattern .* \
+ -pin_pattern $power_pin \
+ -power
}
foreach ground_pin $::env(STD_CELL_GROUND_PINS) {
- add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern $ground_pin -ground
+ add_global_connection \
+ -net $::env(GND_NET) \
+ -inst_pattern .* \
+ -pin_pattern $ground_pin \
+ -ground
}
}
}
-set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
+if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 &&
+ [info exists ::env(FP_PDN_MACRO_HOOKS)]} {
+ set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
+ foreach pdn_hook $pdn_hooks {
+ set instance_name [lindex $pdn_hook 0]
+ set power_net [lindex $pdn_hook 1]
+ set ground_net [lindex $pdn_hook 2]
+ # This assumes the power pin and the power net have the same name.
+ # The macro hooks only give an instance name and not power pin names.
-# Assesses whether the deisgn is the core of the chip or not based on the
+ add_global_connection \
+ -net $power_net \
+ -inst_pattern $instance_name \
+ -pin_pattern $power_net \
+ -power
+
+ add_global_connection \
+ -net $ground_net \
+ -inst_pattern $instance_name \
+ -pin_pattern $ground_net \
+ -ground
+ }
+}
+
+set secondary []
+
+foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
+ if { $vdd != $::env(VDD_NET)} {
+ lappend secondary $vdd
+
+ set db_net [[ord::get_db_block] findNet $vdd]
+ if {$db_net == "NULL"} {
+ set net [odb::dbNet_create [ord::get_db_block] $vdd]
+ $net setSpecial
+ $net setSigType "POWER"
+ }
+ }
+
+ if { $gnd != $::env(GND_NET)} {
+ lappend secondary $gnd
+
+ set db_net [[ord::get_db_block] findNet $gnd]
+ if {$db_net == "NULL"} {
+ set net [odb::dbNet_create [ord::get_db_block] $gnd]
+ $net setSpecial
+ $net setSigType "GROUND"
+ }
+ }
+}
+
+set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
+ -secondary_power $secondary
+
+# Assesses whether the design is the core of the chip or not based on the
# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
if { $::env(DESIGN_IS_CORE) == 1 } {
# Used if the design is the core of the chip
- define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
- if { $::env(_WITH_STRAPS) } {
- add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
- add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_UPPER_LAYER) -width $::env(FP_PDN_HWIDTH) -pitch $::env(FP_PDN_HPITCH) -offset $::env(FP_PDN_HOFFSET) -starts_with POWER
- }
- add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
+ define_pdn_grid \
+ -name stdcell_grid \
+ -starts_with POWER \
+ -voltage_domain CORE \
+ -pins "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_LOWER_LAYER) \
+ -width $::env(FP_PDN_VWIDTH) \
+ -pitch $::env(FP_PDN_VPITCH) \
+ -offset $::env(FP_PDN_VOFFSET) \
+ -nets "$::env(VDD_NET) $::env(GND_NET)" \
+ -starts_with POWER -extend_to_core_ring
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_UPPER_LAYER) \
+ -width $::env(FP_PDN_HWIDTH) \
+ -pitch $::env(FP_PDN_HPITCH) \
+ -offset $::env(FP_PDN_HOFFSET) \
+ -nets "$::env(VDD_NET) $::env(GND_NET)" \
+ -starts_with POWER -extend_to_core_ring
+
+ add_pdn_connect \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
} else {
# Used if the design is a macro in the core
- define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins $::env(FP_PDN_LOWER_LAYER)
- add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
+ define_pdn_grid \
+ -name stdcell_grid \
+ -starts_with POWER \
+ -voltage_domain CORE \
+ -pins $::env(FP_PDN_LOWER_LAYER)
+
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_LOWER_LAYER) \
+ -width $::env(FP_PDN_VWIDTH) \
+ -pitch $::env(FP_PDN_VPITCH) \
+ -offset $::env(FP_PDN_VOFFSET) \
+ -starts_with POWER
}
# Adds the standard cell rails if enabled.
if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
- add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_RAILS_LAYER) -width $::env(FP_PDN_RAIL_WIDTH) -followpins -starts_with POWER
- add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}]
+ add_pdn_stripe \
+ -grid stdcell_grid \
+ -layer $::env(FP_PDN_RAILS_LAYER) \
+ -width $::env(FP_PDN_RAIL_WIDTH) \
+ -followpins \
+ -starts_with POWER
+
+ add_pdn_connect \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)"
}
# Adds the core ring if enabled.
if { $::env(FP_PDN_CORE_RING) == 1 } {
- add_pdn_ring -grid stdcell_grid -layer [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] \
- -widths [subst {$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)}] \
- -spacings [subst {$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)}] \
- -core_offset [subst {$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)}]
+ add_pdn_ring \
+ -grid stdcell_grid \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)" \
+ -widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
+ -spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
+ -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
}
-# A general macro that follows the premise of the set heirarchy. You may want to modify this or add other macro configs
-# The macro power pin names are assumed to match the VDD and GND net names
-# TODO: parameterize the power pin names
-set macro {
- orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
- power_pins $::env(VDD_NET)
- ground_pins $::env(GND_NET)
- blockages $::env(MACRO_BLOCKAGES_LAYER)
- straps {
- }
- connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}}
-}
+define_pdn_grid \
+ -macro \
+ -default \
+ -name macro \
+ -starts_with POWER \
+ -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
-if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1} {
- if { [llength $::env(FP_PDN_MACROS)] > 0 } {
- # generate automatically per instance:
- foreach macro_instance $::env(FP_PDN_MACROS) {
- set macro_instance_grid [subst $macro]
- dict append $macro_instance_grid instance $macro_instance
- set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
- pdngen::specify_grid macro [subst $macro_instance_grid]
- }
- } else {
- set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
- pdngen::specify_grid macro [subst $macro]
- }
- # CAN NOT ENABLE THE TCL COMMAND BECAUSE THERE IS NO ARGUMENT FOR SPECIFYING THE POWER AND GROUND PIN NAMES ON THE MACRO
- # define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -pin_direction vertical -halo [subst {$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)}]
- # add_pdn_connect -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
-} else {
- define_pdn_grid -macro -orient {R0 R180 MX MY R90 R270 MXR90 MYR90} -grid_over_pg_pins -starts_with POWER -halo [subst {$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)}]
-}
-
-# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
-set ::rails_start_with "POWER" ;
-
-# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
-set ::stripes_start_with "POWER" ;
-
+add_pdn_connect \
+ -grid macro \
+ -layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
diff --git a/openlane/wb_host/config.tcl b/openlane/wb_host/config.tcl
index 1dabc40..4ebb2bb 100755
--- a/openlane/wb_host/config.tcl
+++ b/openlane/wb_host/config.tcl
@@ -97,7 +97,7 @@
set ::env(FP_PDN_VWIDTH) 5
set ::env(FP_PDN_HWIDTH) 5
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
diff --git a/openlane/wb_interconnect/config.tcl b/openlane/wb_interconnect/config.tcl
index 2b03cd9..33ac3c6 100755
--- a/openlane/wb_interconnect/config.tcl
+++ b/openlane/wb_interconnect/config.tcl
@@ -113,7 +113,7 @@
set ::env(GLB_RT_ALLOW_CONGESTION) 0
set ::env(GLB_RT_OVERFLOW_ITERS) 200
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
diff --git a/openlane/ycr4_iconnect/base.sdc b/openlane/ycr4_iconnect/base.sdc
index 38463e4..e30007e 100644
--- a/openlane/ycr4_iconnect/base.sdc
+++ b/openlane/ycr4_iconnect/base.sdc
@@ -1,7 +1,7 @@
###############################################################################
# Timing Constraints
###############################################################################
-create_clock -name core_clk -period 20.0000 [get_ports {core_clk}]
+create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
set_clock_transition 0.1500 [all_clocks]
set_clock_uncertainty -setup 0.2500 [all_clocks]
@@ -13,10 +13,10 @@
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
#CORE-0 IMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_bl[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_req}]
@@ -30,11 +30,11 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_imem_rdata[*]}]
#CORE-0 DMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_wdata[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_width[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_req}]
@@ -49,10 +49,10 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core0_dmem_rdata[*]}]
#CORE-1 IMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_bl[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_req}]
@@ -66,11 +66,11 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_imem_rdata[*]}]
#CORE-1 DMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_wdata[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_width[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_req}]
@@ -85,10 +85,10 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core1_dmem_rdata[*]}]
#CORE-2 IMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_bl[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_bl[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_req}]
@@ -102,11 +102,11 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_imem_rdata[*]}]
#CORE-2 DMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_wdata[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_wdata[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_width[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_req}]
@@ -121,10 +121,10 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2_dmem_rdata[*]}]
#CORE-3 IMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_bl[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_bl[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_req}]
@@ -138,11 +138,11 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_imem_rdata[*]}]
#CORE-3 DMEM Constraints
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_cmd}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_req}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_addr[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_wdata[*]}]
-set_input_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_wdata[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_width[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_cmd}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core3_dmem_req}]
diff --git a/openlane/ycr4_iconnect/config.tcl b/openlane/ycr4_iconnect/config.tcl
index 01b9806..bc48c32 100644
--- a/openlane/ycr4_iconnect/config.tcl
+++ b/openlane/ycr4_iconnect/config.tcl
@@ -41,7 +41,10 @@
$script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_sram_mux.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_tcm.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_timer.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_req_retiming.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/ycr_arb.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/ctech_cells.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/sync_fifo2.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/core/primitives/ycr_reset_cells.sv \
"
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr4c/src/includes ]
@@ -62,7 +65,9 @@
#set ::env(PDN_CFG) $script_dir/pdn_cfg.tcl
#set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
set ::env(PL_TARGET_DENSITY) 0.20
-set ::env(CELL_PAD) "14"
+set ::env(CELL_PAD) "2"
+
+set ::env(GLB_RT_ADJUSTMENT) {0.2}
#set ::env(PL_ROUTABILITY_DRIVEN) "1"
set ::env(PL_TIME_DRIVEN) "1"
@@ -83,7 +88,8 @@
#set ::env(FP_PDN_HWIDTH) "3.1"
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
+set ::env(RT_MAX_LAYER) {met4}
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 20
set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/openlane/ycr_core_top/base.sdc b/openlane/ycr_core_top/base.sdc
index f0ec289..0a05d50 100644
--- a/openlane/ycr_core_top/base.sdc
+++ b/openlane/ycr_core_top/base.sdc
@@ -1,7 +1,7 @@
###############################################################################
# Timing Constraints
###############################################################################
-create_clock -name core_clk -period 20.0000 [get_ports {clk}]
+create_clock -name core_clk -period 10.0000 [get_ports {clk}]
set_clock_transition 0.1500 [all_clocks]
set_clock_uncertainty -setup 0.2500 [all_clocks]
@@ -13,28 +13,30 @@
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
#IMEM Constraints
-set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
-set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
-set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
-set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
+set_output_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_cmd_o}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_req_o}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_addr_o[*]}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2imem_bl_o[*]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_req_ack_i}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_rdata_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {imem2core_resp_i[*]}]
#DMEM Constraints
-set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
-set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
-set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
-set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
-set_output_delay -max 12.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
+set_output_delay -max 2.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_addr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
+set_output_delay -max 8.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_cmd_o}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_req_o}]
@@ -42,11 +44,13 @@
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_wdata_o[*]}]
set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core2dmem_width_o[*]}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
-set_input_delay -max 4.5000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_resp_i[*]}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_req_ack_i}]
set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_rdata_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {dmem2core_resp_i[*]}]
###############################################################################
# Environment
diff --git a/openlane/ycr_core_top/config.tcl b/openlane/ycr_core_top/config.tcl
index c49c07b..3b8f8cd 100644
--- a/openlane/ycr_core_top/config.tcl
+++ b/openlane/ycr_core_top/config.tcl
@@ -55,6 +55,8 @@
$script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_hdu.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_tdu.sv \
$script_dir/../../verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_ipic.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr4c/src/top/ycr_req_retiming.sv \
+ $script_dir/../../verilog/rtl/yifive/ycr4c/src/lib/sync_fifo2.sv \
"
set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr4c/src/includes ]
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
@@ -72,13 +74,13 @@
## Floorplan
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 560 950 "
+set ::env(DIE_AREA) "0 0 540 950 "
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
-set ::env(PL_TARGET_DENSITY) 0.40
-set ::env(CELL_PAD) "4"
+set ::env(PL_TARGET_DENSITY) 0.43
+set ::env(CELL_PAD) "2"
-set ::env(GLB_RT_MAXLAYER) 5
+#set ::env(GLB_RT_MAXLAYER) 5
set ::env(RT_MAX_LAYER) {met4}
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 3
@@ -90,5 +92,5 @@
set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
#Need to cross-check why global timing opimization creating setup vio with hugh hold fix
-set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0"
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "1"
diff --git a/openlane/ycr_intf/base.sdc b/openlane/ycr_intf/base.sdc
index 00fe508..2774794 100644
--- a/openlane/ycr_intf/base.sdc
+++ b/openlane/ycr_intf/base.sdc
@@ -1,10 +1,15 @@
###############################################################################
# Timing Constraints
###############################################################################
-create_clock -name core_clk -period 20.0000 [get_ports {core_clk}]
+create_clock -name core_clk -period 10.0000 [get_ports {core_clk}]
create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}]
create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}]
+create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock0} [get_ports dcache_mem_clk0]
+create_generated_clock -name dcache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache mem clock1} [get_ports dcache_mem_clk1]
+create_generated_clock -name icache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache mem clock0} [get_ports icache_mem_clk0]
+create_generated_clock -name icache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache mem clock1} [get_ports icache_mem_clk1]
+
set_clock_transition 0.1500 [all_clocks]
set_clock_uncertainty -setup 0.2500 [all_clocks]
set_clock_uncertainty -hold 0.2500 [all_clocks]
@@ -15,10 +20,223 @@
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
set_clock_groups -name async_clock -asynchronous \
- -group [get_clocks {core_clk}]\
+ -group [get_clocks {core_clk dcache_mem_clk0 dcache_mem_clk1 icache_mem_clk0 icache_mem_clk1}]\
-group [get_clocks {rtc_clk}]\
-group [get_clocks {wb_clk}] -comment {Async Clock group}
+#Assumed config are static
+set_false_path -from [get_ports {cfg_dcache_force_flush}]
+set_false_path -from [get_ports {cfg_dcache_pfet_dis}]
+set_false_path -from [get_ports {cfg_icache_ntag_pfet_dis}]
+set_false_path -from [get_ports {cfg_icache_pfet_dis}]
+set_false_path -from [get_ports {cfg_cska_riscv[3]}]
+set_false_path -from [get_ports {cfg_cska_riscv[2]}]
+set_false_path -from [get_ports {cfg_cska_riscv[1]}]
+set_false_path -from [get_ports {cfg_cska_riscv[0]}]
+set_false_path -from [get_ports {cfg_sram_lphase[1]}]
+set_false_path -from [get_ports {cfg_sram_lphase[0]}]
+
+#All reset has reset synchronization logic inside block ??
+set_false_path -from [get_ports {cpu_intf_rst_n}]
+set_false_path -from [get_ports {pwrup_rst_n}]
+set_false_path -from [get_ports {wb_rst_n}]
+
+#CORE Instruction Memory Interface
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_resp[*]}]
+
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_bl[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_width[*]}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_bl[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_icache_width[*]}]
+
+#Wishbone ICACHE I/F
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_sel_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bl_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bry_o}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_sel_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bl_o[*]}]
+set_output_delay -max 2.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_bry_o}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_lack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_err_i}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_lack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_icache_err_i}]
+
+
+
+# CORE Data Memory Interface
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_resp[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_width[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_wdata[*]}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dcache_wdata[*]}]
+
+
+# Data memory interface from router to WB bridge
+
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_req_ack}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_rdata[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_resp[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_req_ack}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_rdata[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_resp[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_req}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_cmd}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_width[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_addr[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_wdata[*]}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_req}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_cmd}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_width[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_addr[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {core_clk}] -add_delay [get_ports {core_dmem_wdata[*]}]
+
+#WB Data Memory Interface
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}]
+set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_err_i}]
+
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}]
+set_input_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_err_i}]
+
+
+## ICACHE PORT-0 SRAM Memory I/F
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}]
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}]
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}]
+
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}]
+
+## ICACHE PORT-1 SRAM Memory I/F
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_csb1}]
+set_output_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_addr1[*]}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_csb1}]
+set_output_delay -max 3.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_addr1[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_dout1[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_dout1[*]}]
+
+
+# Wishbone DCACHE I/F
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_cyc_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_stb_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_adr_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_we_o}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bl_o[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bry_o}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_cyc_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_stb_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_adr_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_we_o}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_o[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bl_o[*]}]
+set_output_delay -max 5.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_bry_o}]
+
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}]
+set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_err_i}]
+
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_dat_i[*]}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_ack_i}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_lack_i}]
+set_output_delay -max 6.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_dcache_err_i}]
+
+## DCACHE PORT-0 SRAM I/F
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}]
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}]
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}]
+
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}]
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}]
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}]
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}]
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_dout0[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_dout0[*]}]
+
+
+## DCACHE PORT-1 SRAM I/F
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}]
+set_output_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}]
+
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}]
+set_output_delay -max 3.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}]
+
+set_input_delay -min 2.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_dout1[*]}]
+set_input_delay -max 6.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_dout1[*]}]
+
+
###############################################################################
# Environment
###############################################################################
diff --git a/openlane/ycr_intf/config.tcl b/openlane/ycr_intf/config.tcl
index 528078c..cc500ad 100644
--- a/openlane/ycr_intf/config.tcl
+++ b/openlane/ycr_intf/config.tcl
@@ -72,7 +72,7 @@
set ::env(RT_MAX_LAYER) {met4}
-set ::env(GLB_RT_MAXLAYER) "5"
+#set ::env(GLB_RT_MAXLAYER) "5"
set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10
set ::env(DIODE_INSERTION_STRATEGY) 3
diff --git a/signoff/pinmux/OPENLANE_VERSION b/signoff/pinmux/OPENLANE_VERSION
index 80c7664..078e9d2 100644
--- a/signoff/pinmux/OPENLANE_VERSION
+++ b/signoff/pinmux/OPENLANE_VERSION
@@ -1 +1 @@
-openlane N/A
+openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
diff --git a/signoff/pinmux/PDK_SOURCES b/signoff/pinmux/PDK_SOURCES
index 22e7dc1..b08beb4 100644
--- a/signoff/pinmux/PDK_SOURCES
+++ b/signoff/pinmux/PDK_SOURCES
@@ -1,3 +1 @@
-openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
-skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
+open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
diff --git a/signoff/qspim_top/OPENLANE_VERSION b/signoff/qspim_top/OPENLANE_VERSION
index 80c7664..078e9d2 100644
--- a/signoff/qspim_top/OPENLANE_VERSION
+++ b/signoff/qspim_top/OPENLANE_VERSION
@@ -1 +1 @@
-openlane N/A
+openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
diff --git a/signoff/qspim_top/PDK_SOURCES b/signoff/qspim_top/PDK_SOURCES
index 22e7dc1..b08beb4 100644
--- a/signoff/qspim_top/PDK_SOURCES
+++ b/signoff/qspim_top/PDK_SOURCES
@@ -1,3 +1 @@
-openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
-skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
+open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
diff --git a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
index 80c7664..078e9d2 100644
--- a/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
+++ b/signoff/uart_i2cm_usb_spi_top/OPENLANE_VERSION
@@ -1 +1 @@
-openlane N/A
+openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
diff --git a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
index 22e7dc1..b08beb4 100644
--- a/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
+++ b/signoff/uart_i2cm_usb_spi_top/PDK_SOURCES
@@ -1,3 +1 @@
-openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
-skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
+open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
diff --git a/signoff/user_project_wrapper/OPENLANE_VERSION b/signoff/user_project_wrapper/OPENLANE_VERSION
index 80c7664..078e9d2 100644
--- a/signoff/user_project_wrapper/OPENLANE_VERSION
+++ b/signoff/user_project_wrapper/OPENLANE_VERSION
@@ -1 +1 @@
-openlane N/A
+openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
diff --git a/signoff/user_project_wrapper/PDK_SOURCES b/signoff/user_project_wrapper/PDK_SOURCES
index 22e7dc1..b08beb4 100644
--- a/signoff/user_project_wrapper/PDK_SOURCES
+++ b/signoff/user_project_wrapper/PDK_SOURCES
@@ -1,3 +1 @@
-openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
-skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
+open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
diff --git a/signoff/wb_host/OPENLANE_VERSION b/signoff/wb_host/OPENLANE_VERSION
index 80c7664..078e9d2 100644
--- a/signoff/wb_host/OPENLANE_VERSION
+++ b/signoff/wb_host/OPENLANE_VERSION
@@ -1 +1 @@
-openlane N/A
+openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
diff --git a/signoff/wb_host/PDK_SOURCES b/signoff/wb_host/PDK_SOURCES
index 22e7dc1..b08beb4 100644
--- a/signoff/wb_host/PDK_SOURCES
+++ b/signoff/wb_host/PDK_SOURCES
@@ -1,3 +1 @@
-openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
-skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
+open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
diff --git a/signoff/wb_interconnect/OPENLANE_VERSION b/signoff/wb_interconnect/OPENLANE_VERSION
index 80c7664..078e9d2 100644
--- a/signoff/wb_interconnect/OPENLANE_VERSION
+++ b/signoff/wb_interconnect/OPENLANE_VERSION
@@ -1 +1 @@
-openlane N/A
+openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
diff --git a/signoff/wb_interconnect/PDK_SOURCES b/signoff/wb_interconnect/PDK_SOURCES
index 22e7dc1..b08beb4 100644
--- a/signoff/wb_interconnect/PDK_SOURCES
+++ b/signoff/wb_interconnect/PDK_SOURCES
@@ -1,3 +1 @@
-openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
-skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
+open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
diff --git a/signoff/ycr4_iconnect/OPENLANE_VERSION b/signoff/ycr4_iconnect/OPENLANE_VERSION
index 80c7664..078e9d2 100644
--- a/signoff/ycr4_iconnect/OPENLANE_VERSION
+++ b/signoff/ycr4_iconnect/OPENLANE_VERSION
@@ -1 +1 @@
-openlane N/A
+openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
diff --git a/signoff/ycr4_iconnect/PDK_SOURCES b/signoff/ycr4_iconnect/PDK_SOURCES
index 22e7dc1..b08beb4 100644
--- a/signoff/ycr4_iconnect/PDK_SOURCES
+++ b/signoff/ycr4_iconnect/PDK_SOURCES
@@ -1,3 +1 @@
-openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
-skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
+open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
diff --git a/signoff/ycr_core_top/OPENLANE_VERSION b/signoff/ycr_core_top/OPENLANE_VERSION
index 80c7664..078e9d2 100644
--- a/signoff/ycr_core_top/OPENLANE_VERSION
+++ b/signoff/ycr_core_top/OPENLANE_VERSION
@@ -1 +1 @@
-openlane N/A
+openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
diff --git a/signoff/ycr_core_top/PDK_SOURCES b/signoff/ycr_core_top/PDK_SOURCES
index 22e7dc1..b08beb4 100644
--- a/signoff/ycr_core_top/PDK_SOURCES
+++ b/signoff/ycr_core_top/PDK_SOURCES
@@ -1,3 +1 @@
-openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
-skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
+open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
diff --git a/signoff/ycr_intf/OPENLANE_VERSION b/signoff/ycr_intf/OPENLANE_VERSION
index 80c7664..078e9d2 100644
--- a/signoff/ycr_intf/OPENLANE_VERSION
+++ b/signoff/ycr_intf/OPENLANE_VERSION
@@ -1 +1 @@
-openlane N/A
+openlane 0dc6fb79c91082b94f8ded78d70f8bacbab96bf2
diff --git a/signoff/ycr_intf/PDK_SOURCES b/signoff/ycr_intf/PDK_SOURCES
index 22e7dc1..b08beb4 100644
--- a/signoff/ycr_intf/PDK_SOURCES
+++ b/signoff/ycr_intf/PDK_SOURCES
@@ -1,3 +1 @@
-openlane 70923d7fbd8998c8da87d905cf9e69bffc13709f
-skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
+open_pdks 41c0908b47130d5675ff8484255b43f66463a7d6
diff --git a/sta/scripts/caravel_timing.tcl b/sta/scripts/caravel_timing.tcl
index c2424ad..d1d8819 100644
--- a/sta/scripts/caravel_timing.tcl
+++ b/sta/scripts/caravel_timing.tcl
@@ -1,7 +1,7 @@
set ::env(USER_ROOT) ".."
- set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-5/caravel"
- set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw5"
+ set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-6/caravel"
+ set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw6"
read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
@@ -105,11 +105,8 @@
read_spef -path \gpio_control_in_2[7] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
read_spef -path \gpio_control_in_2[8] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
read_spef -path \gpio_control_in_2[9] $::env(CARAVEL_ROOT)/spef/gpio_control_block.spef
- read_spef -path gpio_defaults_block_0 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
- read_spef -path gpio_defaults_block_1 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_1803.spef
- read_spef -path gpio_defaults_block_2 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
- read_spef -path gpio_defaults_block_3 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
- read_spef -path gpio_defaults_block_4 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block_0403.spef
+ read_spef -path gpio_defaults_block_0[0] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_0[1] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_5 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_6 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_7 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
@@ -135,6 +132,9 @@
read_spef -path gpio_defaults_block_27 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_28 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_29 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_2[0] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_2[1] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
+ read_spef -path gpio_defaults_block_2[2] $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_30 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_31 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
read_spef -path gpio_defaults_block_32 $::env(CARAVEL_ROOT)/spef/gpio_defaults_block.spef
diff --git a/sta/sdc/caravel.sdc b/sta/sdc/caravel.sdc
index 494f7e6..c9efeb9 100644
--- a/sta/sdc/caravel.sdc
+++ b/sta/sdc/caravel.sdc
@@ -14,13 +14,13 @@
#create_clock [get_pins clocking/pll_clk90 ] -name "pll_clk90" -period 25
create_generated_clock -name wb_clk -add -source [get_ports {clock}] -master_clock [get_clocks clock] -divide_by 1 -comment {Wishbone User Clock} [get_pins mprj/wb_clk_i]
-create_clock -name wbs_clk_i -period 15.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}]
+create_clock -name wbs_clk_i -period 10.0000 [get_pins {mprj/u_wb_host/wbs_clk_out}]
create_clock -name cpu_ref_clk -period 10.0000 [get_pins {mprj/u_wb_host/u_cpu_ref_sel.u_mux/X}]
-create_clock -name cpu_clk -period 20.0000 [get_pins {mprj/u_wb_host/cpu_clk}]
+create_clock -name cpu_clk -period 10.0000 [get_pins {mprj/u_wb_host/cpu_clk}]
create_clock -name rtc_clk -period 50.0000 [get_pins {mprj/u_wb_host/rtc_clk}]
create_clock -name usb_clk -period 20.0000 [get_pins {mprj/u_wb_host/usb_clk}]
create_clock -name uarts0_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.u_mux/X}]
-create_clock -name uarts1_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart0_core.u_lineclk_buf.u_mux/X}]
+create_clock -name uarts1_clk -period 100.0000 [get_pins {mprj/u_uart_i2c_usb_spi/u_uart1_core.u_lineclk_buf.u_mux/X}]
create_clock -name uartm_clk -period 100.0000 [get_pins {mprj/u_wb_host/u_uart2wb.u_core.u_uart_clk.u_mux/X}]
@@ -62,6 +62,12 @@
set_case_analysis 0 [get_pins {mprj/u_uart_i2c_usb_spi/cfg_cska_uart[3]}]
+#Keept the SRAM clock driving edge at pos edge
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_intf/cfg_sram_lphase[1]}]
+
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[0]}]
+set_case_analysis 0 [get_pins {mprj/u_riscv_top.u_connect/cfg_sram_lphase[1]}]
#disable clock gating check at static clock select pins
set_false_path -through [get_pins mprj/u_wb_host/u_wbs_clk_sel.u_mux/S]
@@ -69,7 +75,7 @@
set_propagated_clock [all_clocks]
set_clock_groups -name async_clock -asynchronous \
- -group [get_clocks {clock wb_clk mem_clk0 mem_clk1 mem_clk2 mem_clk3}]\
+ -group [get_clocks {clock wb_clk }]\
-group [get_clocks {user_clk2}]\
-group [get_clocks {wbs_clk_i}]\
-group [get_clocks {cpu_clk}]\
diff --git a/verilog/dv/user_basic/user_basic_tb.v b/verilog/dv/user_basic/user_basic_tb.v
index fb09225..e3e17d9 100644
--- a/verilog/dv/user_basic/user_basic_tb.v
+++ b/verilog/dv/user_basic/user_basic_tb.v
@@ -240,8 +240,8 @@
wb_user_core_write(`ADDR_SPACE_WBHOST+`WBHOST_GLBL_CFG,'h1);
wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_1,read_data,32'h8273_8343);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h0604_2022);
- wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_2000);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_2,read_data,32'h2405_2022);
+ wb_user_core_read_check(`ADDR_SPACE_PINMUX+`PINMUX_SOFT_REG_3,read_data,32'h0004_3000);
end
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index 14c6038..bf8f349 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -98,6 +98,7 @@
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr4_top_wb.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_icache_router.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_dcache_router.sv
+-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/top/ycr_req_retiming.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/cache/src/core/icache_top.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/cache/src/core/icache_app_fsm.sv
-v $(USER_PROJECT_VERILOG)/rtl/yifive/ycr4c/src/cache/src/core/icache_tag_fifo.sv
diff --git a/verilog/rtl/lib/ctech_cells.sv b/verilog/rtl/lib/ctech_cells.sv
index c9528de..f28fced 100644
--- a/verilog/rtl/lib/ctech_cells.sv
+++ b/verilog/rtl/lib/ctech_cells.sv
@@ -1,9 +1,9 @@
-module ctech_mux2x1 (
- input logic A0,
- input logic A1,
+module ctech_mux2x1 #(parameter WB = 1) (
+ input logic [WB-1:0] A0,
+ input logic [WB-1:0] A1,
input logic S ,
- output logic X);
+ output logic [WB-1:0] X);
`ifndef SYNTHESIS
assign X = (S) ? A1 : A0;
@@ -13,11 +13,11 @@
endmodule
-module ctech_mux2x1_2 (
- input logic A0,
- input logic A1,
+module ctech_mux2x1_2 #(parameter WB = 1) (
+ input logic [WB-1:0] A0,
+ input logic [WB-1:0] A1,
input logic S ,
- output logic X);
+ output logic [WB-1:0] X);
`ifndef SYNTHESIS
assign X = (S) ? A1 : A0;
@@ -27,11 +27,11 @@
endmodule
-module ctech_mux2x1_4 (
- input logic A0,
- input logic A1,
+module ctech_mux2x1_4 #(parameter WB = 1) (
+ input logic [WB-1:0] A0,
+ input logic [WB-1:0] A1,
input logic S ,
- output logic X);
+ output logic [WB-1:0] X);
`ifndef SYNTHESIS
assign X = (S) ? A1 : A0;
diff --git a/verilog/rtl/pinmux/src/pinmux_reg.sv b/verilog/rtl/pinmux/src/pinmux_reg.sv
index 46642c7..4f21946 100644
--- a/verilog/rtl/pinmux/src/pinmux_reg.sv
+++ b/verilog/rtl/pinmux/src/pinmux_reg.sv
@@ -718,7 +718,7 @@
//-----------------------------------------
// Software Reg-2, Release date: <DAY><MONTH><YEAR>
// ----------------------------------------
-gen_32b_reg #(32'h0604_2022) u_reg_23 (
+gen_32b_reg #(32'h2405_2022) u_reg_23 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
@@ -731,9 +731,9 @@
);
//-----------------------------------------
-// Software Reg-3: Poject Revison 4.1 = 0004200
+// Software Reg-3: Poject Revison 4.3 = 0004300
// ----------------------------------------
-gen_32b_reg #(32'h0004_2000) u_reg_24 (
+gen_32b_reg #(32'h0004_3000) u_reg_24 (
//List of Inputs
.reset_n (h_reset_n ),
.clk (mclk ),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index d9366d0..93cab85 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -203,6 +203,9 @@
//// 4.2 April 6 2022, Dinesh A ////
//// 1. SSPI CS# increased from 1 to 4 ////
//// 2. uart port increase to two ////
+//// 4.3 May 24 2022, Dinesh A ////
+//// Re targetted the design to mpw-6 tools set and risc ////
+//// core logic are timing optimized to 100mhz ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
diff --git a/verilog/rtl/yifive/ycr4c b/verilog/rtl/yifive/ycr4c
index 53ae743..e153157 160000
--- a/verilog/rtl/yifive/ycr4c
+++ b/verilog/rtl/yifive/ycr4c
@@ -1 +1 @@
-Subproject commit 53ae7435180d758ffd1833f224fd4e1f7b4d65a8
+Subproject commit e153157fa5b26f62d23fe6cb3e7922b113efe5d4
