| /root/riscduino-qcore_q2_/Makefile |
| /root/riscduino-qcore_q2_/run_regress |
| /root/riscduino-qcore_q2_/gds/.magicrc |
| /root/riscduino-qcore_q2_/hacks/patch/pdngen.patch |
| /root/riscduino-qcore_q2_/hacks/patch/resizer.patch |
| /root/riscduino-qcore_q2_/hacks/src/OpenROAD/PdnGen.tcl |
| /root/riscduino-qcore_q2_/hacks/src/OpenROAD/Resizer.cc |
| /root/riscduino-qcore_q2_/hacks/src/OpenSTA/network/ConcreteNetwork.cc |
| /root/riscduino-qcore_q2_/hacks/src/OpenSTA/tcl/NetworkEdit.tcl |
| /root/riscduino-qcore_q2_/hacks/src/OpenSTA/tcl/Sta.tcl |
| /root/riscduino-qcore_q2_/hacks/src/openlane/io_place.py |
| /root/riscduino-qcore_q2_/hacks/src/openlane/synth.tcl |
| /root/riscduino-qcore_q2_/hacks/src/openlane/synth_top.tcl |
| /root/riscduino-qcore_q2_/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib |
| /root/riscduino-qcore_q2_/openlane/Makefile |
| /root/riscduino-qcore_q2_/openlane/Read.me |
| /root/riscduino-qcore_q2_/openlane/clk_skew_adjust/config.tcl |
| /root/riscduino-qcore_q2_/openlane/pinmux_top/base.sdc |
| /root/riscduino-qcore_q2_/openlane/pinmux_top/config.tcl |
| /root/riscduino-qcore_q2_/openlane/qspim_top/base.sdc |
| /root/riscduino-qcore_q2_/openlane/qspim_top/config.tcl |
| /root/riscduino-qcore_q2_/openlane/qspim_top/pdn.tcl |
| /root/riscduino-qcore_q2_/openlane/qspim_top/sta.tcl |
| /root/riscduino-qcore_q2_/openlane/sar_adc/config.tcl |
| /root/riscduino-qcore_q2_/openlane/sar_adc/interactive.tcl |
| /root/riscduino-qcore_q2_/openlane/sar_adc/pdn.tcl |
| /root/riscduino-qcore_q2_/openlane/uart_i2cm_usb_spi_top/base.sdc |
| /root/riscduino-qcore_q2_/openlane/uart_i2cm_usb_spi_top/config.tcl |
| /root/riscduino-qcore_q2_/openlane/uart_i2cm_usb_spi_top/pdn.tcl |
| /root/riscduino-qcore_q2_/openlane/uart_i2cm_usb_spi_top/sta.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/base.sdc |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/config.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/gen_pdn.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/interactive.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/mod.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/pdn_cfg.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/sta.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/mpw5/config.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/mpw5/interactive.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/mpw5/pdn_cfg.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/mpw6/config.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/mpw6/interactive.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/mpw6/pdn_cfg.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/mpw7/config.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/mpw7/interactive.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/mpw7/pdn.tcl |
| /root/riscduino-qcore_q2_/openlane/user_project_wrapper/mpw7/pdn_cfg.tcl |
| /root/riscduino-qcore_q2_/openlane/wb_host/base.sdc |
| /root/riscduino-qcore_q2_/openlane/wb_host/config.tcl |
| /root/riscduino-qcore_q2_/openlane/wb_interconnect/base.sdc |
| /root/riscduino-qcore_q2_/openlane/wb_interconnect/config.tcl |
| /root/riscduino-qcore_q2_/openlane/wb_interconnect/pdn.tcl |
| /root/riscduino-qcore_q2_/openlane/wb_interconnect/sta.tcl |
| /root/riscduino-qcore_q2_/openlane/ycr4_iconnect/base.sdc |
| /root/riscduino-qcore_q2_/openlane/ycr4_iconnect/config.tcl |
| /root/riscduino-qcore_q2_/openlane/ycr4_iconnect/drc_exclude.cells |
| /root/riscduino-qcore_q2_/openlane/ycr_core_top/base.sdc |
| /root/riscduino-qcore_q2_/openlane/ycr_core_top/config.tcl |
| /root/riscduino-qcore_q2_/openlane/ycr_intf/base.sdc |
| /root/riscduino-qcore_q2_/openlane/ycr_intf/config.tcl |
| /root/riscduino-qcore_q2_/spef/digital_pll.spef |
| /root/riscduino-qcore_q2_/spef/pinmux_top.spef |
| /root/riscduino-qcore_q2_/spef/qspim_top.spef |
| /root/riscduino-qcore_q2_/spef/uart_i2c_usb_spi_top.spef |
| /root/riscduino-qcore_q2_/spef/user_project_wrapper.spef |
| /root/riscduino-qcore_q2_/spef/wb_host.spef |
| /root/riscduino-qcore_q2_/spef/wb_interconnect.spef |
| /root/riscduino-qcore_q2_/spef/ycr4_iconnect.spef |
| /root/riscduino-qcore_q2_/spef/ycr_core_top.spef |
| /root/riscduino-qcore_q2_/spef/ycr_intf.spef |
| /root/riscduino-qcore_q2_/sta/Makefile |
| /root/riscduino-qcore_q2_/sta/base.sdc |
| /root/riscduino-qcore_q2_/sta/run_sta |
| /root/riscduino-qcore_q2_/sta/scripts/caravel_timing.tcl |
| /root/riscduino-qcore_q2_/sta/scripts/or_write_verilog.tcl |
| /root/riscduino-qcore_q2_/sta/scripts/riscdunio.tcl |
| /root/riscduino-qcore_q2_/sta/scripts/sta.tcl |
| /root/riscduino-qcore_q2_/sta/scripts/statistic.tcl |
| /root/riscduino-qcore_q2_/sta/scripts/ycr_core_timing.tcl |
| /root/riscduino-qcore_q2_/sta/sdc/caravel.sdc |
| /root/riscduino-qcore_q2_/sta/sdc/ycr_core_top.sdc |
| /root/riscduino-qcore_q2_/verilog/dv/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_arrays/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_arrays/arduino_arrays.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_arrays/arduino_arrays.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_arrays/arduino_arrays_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_ascii_table/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_ascii_table/arduino_ascii_table.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_ascii_table/arduino_ascii_table_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_character_analysis/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_character_analysis/arduino_character_analysis.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_character_analysis/arduino_character_analysis_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_digital_port_control/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_digital_port_control/arduino_digital_port_control.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_digital_port_control/arduino_digital_port_control_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_gpio_intr/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_gpio_intr/arduino_gpio_intr.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_gpio_intr/arduino_gpio_intr.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_gpio_intr/arduino_gpio_intr_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_hello_world/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_hello_world/arduino_hello_world.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_hello_world/arduino_hello_world.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_hello_world/arduino_hello_world_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_i2c_scaner/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_i2c_scaner/arduino_i2c_scaner_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_i2c_wr_rd/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_i2c_wr_rd/arduino_i2c_wr_rd_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_multi_serial/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_multi_serial/arduino_multi_serial.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_multi_serial/arduino_multi_serial_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_risc_boot/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_risc_boot/arduino_risc_boot.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_risc_boot/arduino_risc_boot_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_string/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_string/arduino_string.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_string/arduino_string.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_string/arduino_string_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_switchCase2/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_switchCase2/arduino_switchCase2.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_switchCase2/arduino_switchCase2_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_timer_intr/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_timer_intr/arduino_timer_intr.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_timer_intr/arduino_timer_intr_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_ws281x/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_ws281x/arduino_ws281x.ino |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_ws281x/arduino_ws281x.ino.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/arduino_ws281x/arduino_ws281x_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/agents/caravel_task.sv |
| /root/riscduino-qcore_q2_/verilog/dv/common/agents/test_control.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/agents/uart_agent.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/agents/uart_master_tasks.sv |
| /root/riscduino-qcore_q2_/verilog/dv/common/agents/usb_agents.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/agents/user_tasks.sv |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/bfm_ad5205.sv |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/bfm_spim.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/bfm_ws281x.sv |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb1d_defines.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usbd_files.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_core.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_crc16.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_crc5.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_fifo2.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_generic_dpram.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_generic_fifo.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_idma.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_pa.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_pd.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_pe.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_pl.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_rom1.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_sync_fifo.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/core/usb1d_utmi_if.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/phy/usb1d_phy.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/phy/usb1d_rx_phy.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/phy/usb1d_tx_phy.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/bfm/usb_device/top/usb1d_top.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/common.mk |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/common_bthread.c |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/common_bthread.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/common_misc.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/crt.S |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/crt_tcm.S |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/csr.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/ext_reg_map.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/int_reg_map.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/link.ld |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/link_tcm.ld |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/reloc.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/riscv_csr_encoding.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/riscv_macros.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/sc_print.c |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/sc_print.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/sc_test.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/firmware/ycr_specific.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/model/i2c_slave_model.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/model/is62wvs1288.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/model/s25fl256s.sv |
| /root/riscduino-qcore_q2_/verilog/dv/common/model/spiram.v |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/package_riscduino_index.json |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino-0.0.9.tar |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/CHANGELOG |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/installed.json |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Arduino.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/HardwareSerial.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Print.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Print.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Printable.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Stream.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/Stream.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/TIMERClass.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/TIMERClass.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/UARTClass.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/UARTClass.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WCharacter.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WInterrupts.c |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WInterrupts.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WMath.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WMath.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WString.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/WString.h |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/abi.cpp |
| /root/riscduino-qcore_q2_/verilog/dv/common/riscduino_board/custom_board/riscduino/cores/arduino/binary.h |
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| /root/riscduino-qcore_q2_/verilog/dv/riscv_regress/tests/riscv_isa/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/riscv_regress/tests/riscv_isa/riscv_test.h |
| /root/riscduino-qcore_q2_/verilog/dv/riscv_regress/tests/riscv_isa/rv32_tests.inc |
| /root/riscduino-qcore_q2_/verilog/dv/riscv_regress/tests/riscv_isa/test_macros.h |
| /root/riscduino-qcore_q2_/verilog/dv/uart_master/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/uart_master/run_verilog |
| /root/riscduino-qcore_q2_/verilog/dv/uart_master/uart_master.c |
| /root/riscduino-qcore_q2_/verilog/dv/uart_master/uart_master_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_aes/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_aes/aes.c |
| /root/riscduino-qcore_q2_/verilog/dv/user_aes/aes.h |
| /root/riscduino-qcore_q2_/verilog/dv/user_aes/user_aes.c |
| /root/riscduino-qcore_q2_/verilog/dv/user_aes/user_aes_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_basic/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_basic/user_basic_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_cache_bypass/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_cache_bypass/run_iverilog |
| /root/riscduino-qcore_q2_/verilog/dv/user_cache_bypass/user_cache_bypass.c |
| /root/riscduino-qcore_q2_/verilog/dv/user_cache_bypass/user_cache_bypass_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_gpio/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_gpio/user_gpio_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_i2cm/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_i2cm/run_iverilog |
| /root/riscduino-qcore_q2_/verilog/dv/user_i2cm/user_i2cm_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_i2cm/user_uart.c |
| /root/riscduino-qcore_q2_/verilog/dv/user_mcore_test1/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_mcore_test1/user_mcore_test1.c |
| /root/riscduino-qcore_q2_/verilog/dv/user_mcore_test1/user_mcore_test1_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_mcore_test2/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_mcore_test2/user_mcore_test2.c |
| /root/riscduino-qcore_q2_/verilog/dv/user_mcore_test2/user_mcore_test2_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_pwm/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_pwm/user_pwm_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_qspi/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_qspi/run_iverilog |
| /root/riscduino-qcore_q2_/verilog/dv/user_qspi/user_qspi_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_qspi/user_risc_boot.c |
| /root/riscduino-qcore_q2_/verilog/dv/user_risc_boot/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_risc_boot/run_iverilog |
| /root/riscduino-qcore_q2_/verilog/dv/user_risc_boot/user_risc_boot.c |
| /root/riscduino-qcore_q2_/verilog/dv/user_risc_boot/user_risc_boot_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_sema/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_sema/user_sema_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_spi_isp/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_spi_isp/run_iverilog |
| /root/riscduino-qcore_q2_/verilog/dv/user_spi_isp/user_spi_isp_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_sram_exec/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_sram_exec/user_sram_exec.c |
| /root/riscduino-qcore_q2_/verilog/dv/user_sram_exec/user_sram_exec_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_sspi/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_sspi/sspi_task.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_sspi/user_sspi_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_timer/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_timer/user_timer_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_uart/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_uart/run_iverilog |
| /root/riscduino-qcore_q2_/verilog/dv/user_uart/user_uart.c |
| /root/riscduino-qcore_q2_/verilog/dv/user_uart/user_uart_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_uart1/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_uart1/run_iverilog |
| /root/riscduino-qcore_q2_/verilog/dv/user_uart1/user_uart1.c |
| /root/riscduino-qcore_q2_/verilog/dv/user_uart1/user_uart1_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_uart_master/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_uart_master/run_iverilog |
| /root/riscduino-qcore_q2_/verilog/dv/user_uart_master/user_uart.c |
| /root/riscduino-qcore_q2_/verilog/dv/user_uart_master/user_uart_master_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_usb/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/user_usb/user_usb_tb.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_usb/tests/usb_test1.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_usb/tests/usb_test2.v |
| /root/riscduino-qcore_q2_/verilog/dv/user_usb/tests/usb_test3.v |
| /root/riscduino-qcore_q2_/verilog/dv/wb_port/Makefile |
| /root/riscduino-qcore_q2_/verilog/dv/wb_port/run_verilog |
| /root/riscduino-qcore_q2_/verilog/dv/wb_port/wb_port.c |
| /root/riscduino-qcore_q2_/verilog/dv/wb_port/wb_port_tb.v |
| /root/riscduino-qcore_q2_/verilog/includes/includes.gl.caravel_user_project |
| /root/riscduino-qcore_q2_/verilog/includes/includes.gl.lib |
| /root/riscduino-qcore_q2_/verilog/includes/includes.rtl.caravel_user_project |
| /root/riscduino-qcore_q2_/verilog/includes/includes.rtl.lib |
| /root/riscduino-qcore_q2_/verilog/rtl/uprj_netlists.v |
| /root/riscduino-qcore_q2_/verilog/rtl/user_defines.v |
| /root/riscduino-qcore_q2_/verilog/rtl/user_params.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/user_project_wrapper.v |
| /root/riscduino-qcore_q2_/verilog/rtl/user_reg_map.v |
| /root/riscduino-qcore_q2_/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv |
| /root/riscduino-qcore_q2_/verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.v |
| /root/riscduino-qcore_q2_/verilog/rtl/clk_skew_adjust/synth/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/clk_skew_adjust/synth/synth.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/digital_core/filelist_rtl.f |
| /root/riscduino-qcore_q2_/verilog/rtl/digital_core/run_modelsim |
| /root/riscduino-qcore_q2_/verilog/rtl/digital_core/src/digital_core.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/digital_core/src/glbl_cfg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/digital_pll/src/digital_pll.v |
| /root/riscduino-qcore_q2_/verilog/rtl/digital_pll/src/digital_pll_controller.v |
| /root/riscduino-qcore_q2_/verilog/rtl/digital_pll/src/ring_osc2x13.v |
| /root/riscduino-qcore_q2_/verilog/rtl/i2cm/src/core/i2cm_bit_ctrl.v |
| /root/riscduino-qcore_q2_/verilog/rtl/i2cm/src/core/i2cm_byte_ctrl.v |
| /root/riscduino-qcore_q2_/verilog/rtl/i2cm/src/core/i2cm_top.v |
| /root/riscduino-qcore_q2_/verilog/rtl/i2cm/src/includes/i2cm_defines.v |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/async_fifo.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/async_fifo_th.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/async_reg_bus.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/async_wb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/clk_buf.v |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/clk_ctl.v |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/clk_div8.v |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/clk_skew_adjust.gv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/ctech_cells.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/double_sync_high.v |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/double_sync_low.v |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/pulse_gen_type1.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/pulse_gen_type2.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/registers.v |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/reset_sync.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/ser_inf_32b.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/ser_shift.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/sync_fifo.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/sync_fifo2.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/sync_wbb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/wb_interface.v |
| /root/riscduino-qcore_q2_/verilog/rtl/lib/wb_stagging.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/run_iverilog |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/run_verilator |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/include/mbist_def.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/src/core/mbist_addr_gen.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/src/core/mbist_data_cmp.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/src/core/mbist_fsm.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/src/core/mbist_mux.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/src/core/mbist_op_sel.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/src/core/mbist_pat_sel.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/src/core/mbist_repair_addr.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/src/core/mbist_sti_sel.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/src/top/mbist_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/src/top/mbist_top1.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist/src/top/mbist_top2.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist_wrapper/src/mbist_wb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/mbist_wrapper/src/mbist_wrapper.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/glbl_reg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/glbl_rst_reg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/gpio_intr.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/gpio_reg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/gpio_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/pinmux.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/pinmux_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/pwm.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/pwm_reg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/pwm_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/semaphore_reg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/strap_ctrl.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/timer.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/timer_reg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/timer_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/ws281x_driver.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/ws281x_reg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/pinmux/src/ws281x_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/lib/clk_skew_adjust.gv |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/lib/ctech_cells.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/lib/reset_sync.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/model/cy15b104qs.v |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/model/s25fl256s.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/model/spiram.v |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/openlane/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/openlane/qspim_top/base.sdc |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/openlane/qspim_top/config.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/openlane/qspim_top/interactive.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/sdc/qspim_top.sdc |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/src/filelist.f |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/src/qspim_clkgen.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/src/qspim_ctrl.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/src/qspim_fifo.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/src/qspim_if.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/src/qspim_regs.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/src/qspim_rx.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/src/qspim_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/src/qspim_tx.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/synth/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/synth/synth.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/tb/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/tb/run_iverilog |
| /root/riscduino-qcore_q2_/verilog/rtl/qspim/tb/tb_top.v |
| /root/riscduino-qcore_q2_/verilog/rtl/sar_adc/ACMP.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/sar_adc/ACMP_HVL.v |
| /root/riscduino-qcore_q2_/verilog/rtl/sar_adc/DAC_8BIT.v |
| /root/riscduino-qcore_q2_/verilog/rtl/sar_adc/SAR.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/sar_adc/adc_reg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/sar_adc/sar_adc.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/sram_macros/sky130_sram_2kbyte_1rw1r_32x512_8.v |
| /root/riscduino-qcore_q2_/verilog/rtl/sspim/src/filelist_spi.f |
| /root/riscduino-qcore_q2_/verilog/rtl/sspim/src/sspim_cfg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/sspim/src/sspim_clkgen.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/sspim/src/sspim_ctl.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/sspim/src/sspim_if.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/sspim/src/sspim_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/sspis/src/spi2wb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/sspis/src/sspis_if.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/sspis/src/sspis_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/uart/src/uart_cfg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/uart/src/uart_core.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/uart/src/uart_rxfsm.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/uart/src/uart_txfsm.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/uart2wb/src/run_verilog |
| /root/riscduino-qcore_q2_/verilog/rtl/uart2wb/src/uart2_core.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/uart2wb/src/uart2wb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/uart2wb/src/uart_msg_handler.v |
| /root/riscduino-qcore_q2_/verilog/rtl/uart_i2c/src/uart_i2c_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/uart_i2c_usb/src/uart_i2c_usb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/uart_i2c_usb_spi/src/uart_i2c_usb_spi.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/usb1_host/src/filelist.f |
| /root/riscduino-qcore_q2_/verilog/rtl/usb1_host/src/core/usbh_core.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/usb1_host/src/core/usbh_crc16.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/usb1_host/src/core/usbh_crc5.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/usb1_host/src/core/usbh_fifo.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/usb1_host/src/core/usbh_sie.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/usb1_host/src/includes/usbh_host_defs.v |
| /root/riscduino-qcore_q2_/verilog/rtl/usb1_host/src/phy/usb_fs_phy.v |
| /root/riscduino-qcore_q2_/verilog/rtl/usb1_host/src/phy/usb_transceiver.v |
| /root/riscduino-qcore_q2_/verilog/rtl/usb1_host/src/top/usb1_host.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/wb_host/src/wb_host.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/wb_host/src/wbh_reg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/wb_host/src/wbh_reset_fsm.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/wb_interconnect/src/wb_arb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/wb_interconnect/src/wb_interconnect.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/wb_interconnect/src/wb_slave_port.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/run_iverilog |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/ycr2c/base.sdc |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/ycr2c/config.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/ycr2c/interactive.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/ycr2c/pdn.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/ycr2c/sta.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/ycr4_iconnect/base.sdc |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/ycr4_iconnect/config.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/ycr4_iconnect/drc_exclude.cells |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/ycr4_iconnect/pdn_cfg.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/ycr_core/base.sdc |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/ycr_core/config.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/ycr_intf/base.sdc |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/openlane/ycr_intf/config.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/iverilog_vpi/system.c |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/coremark/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/coremark/core_portme.c |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/coremark/core_portme.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/dhrystone21/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/dhrystone21/dhry.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/dhrystone21/dhry_1.c |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/benchmarks/dhrystone21/dhry_2.c |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/common/common.mk |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/common/crt.S |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/common/crt_tcm.S |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/common/csr.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/common/link.ld |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/common/link_tcm.ld |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/common/reloc.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/common/riscv_csr_encoding.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/common/riscv_macros.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/common/sc_print.c |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/common/sc_print.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/common/sc_test.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/common/ycr_specific.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/hello/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/hello/hello.c |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/isr_sample/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/isr_sample/isr_sample.S |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/isr_sample/timer.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/aw_test_macros.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/compliance_io.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/compliance_test.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/riscv_test.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/riscv_test_macros.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/riscv_compliance/test_macros.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/riscv_isa/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/riscv_isa/riscv_test.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/riscv_isa/rv32_tests.inc |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/tests/riscv_isa/test_macros.h |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/verilator_wrap/ycr_ahb_wrapper.c |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/verilator_wrap/ycr_axi_wrapper.c |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/sim/verilator_wrap/ycr_wb_wrapper.c |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core.files |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/run_modemsim |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/wb_top.files |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/cache/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/cache/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/cache/src/core/dcache_tag_fifo.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/cache/src/core/dcache_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/cache/src/core/icache_app_fsm.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/cache/src/core/icache_tag_fifo.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/cache/src/core/icache_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/cache/src/core/ycr_cache_defs.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/cache/src/model/sky130_sram_2kbyte_1rw1r_32x512_8.v |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/ycr_clk_ctrl.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/ycr_core_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/ycr_dm.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/ycr_dmi.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/ycr_scu.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/ycr_tapc.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/ycr_tapc_shift_reg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/ycr_tapc_synchronizer.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_ipic.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_csr.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_div.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_exu.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_hdu.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_ialu.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_idu.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_ifu.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_lsu.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_mprf.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_mul.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_tdu.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_pipe_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/pipeline/ycr_tracelog.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/primitives/ycr_cg.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/core/primitives/ycr_reset_cells.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_ahb.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_arch_description.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_arch_types.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_cache_defs.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_csr.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_dm.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_hdu.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_ipic.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_memif.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_riscv_isa_decoding.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_scu.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_search_ms1.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_tapc.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_tdu.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/includes/ycr_wb.svh |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/lib/async_fifo.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/lib/clk_skew_adjust.gv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/lib/ctech_cells.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/lib/sync_fifo.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/lib/sync_fifo2.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/lib/ycr_arb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/lib/ycr_async_wbb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr2_top_ahb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr2_top_axi.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr4_cross_bar.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr4_iconnect.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr4_router.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr4_top_wb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_cache_top.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_dcache_router.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_dmem_ahb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_dmem_router.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_dmem_wb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_dp_memory.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_icache_router.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_imem_ahb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_imem_router.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_imem_wb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_intf.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_mem_axi.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_req_retiming.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_sram_mux.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_tcm.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/src/top/ycr_timer.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/synth/Makefile |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/synth/base.sdc |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/synth/run_synth |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/synth/sta.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/synth/synth.tcl |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/synth/scripts/libtrim.pl |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/tb/ahb_tb.files |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/tb/axi_tb.files |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/tb/sky130_sram_2kbyte_1rw1r_32x512_8.v |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/tb/uprj_netlists.v |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/tb/wb_tb.files |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/tb/ycr_dmem_tb_wb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/tb/ycr_memory_tb_ahb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/tb/ycr_memory_tb_axi.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/tb/ycr_memory_tb_wb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/tb/ycr_top_tb_ahb.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/tb/ycr_top_tb_axi.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/tb/ycr_top_tb_runtests.sv |
| /root/riscduino-qcore_q2_/verilog/rtl/yifive/ycr4c/tb/ycr_top_tb_wb.sv |