clean up
diff --git a/openlane/io_place.py b/openlane/io_place.py deleted file mode 100755 index 86ac1f2..0000000 --- a/openlane/io_place.py +++ /dev/null
@@ -1,528 +0,0 @@ -# Copyright 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -""" -Places the IOs according to an input file. Supports regexes. -File format: -#N|#S|#E|#W -pin1_regex -pin2_regex -... - -#S|#N|#E|#W -... -... -""" -import odb - -import os -import re -import sys -import click -import random - - -@click.command() -@click.option("-l", "--input-lef", required=True, help="Input merged tlef/lef file.") -@click.option( - "-o", - "--output-def", - default="./output.def", - help="Output DEF file with newly placed pins", -) -@click.option("-c", "--config", required=False, help="Optional configuration file.") -@click.option( - "-r", - "--reverse", - default="", - type=str, - help="Reverse along comma,delimited,cardinals: e.g. N,E", -) -@click.option("-L", "--length", default=2, type=float, help="Pin length in microns.") -@click.option( - "-V", - "--ver-layer", - required=True, - help="Name of metal layer to place vertical pins on.", -) -@click.option( - "-H", - "--hor-layer", - required=True, - help="Name of metal layer to place horizontal pins on.", -) -@click.option( - "--hor-extension", - default=0, - type=float, - help="Extension for vertical pins in microns.", -) -@click.option( - "--ver-extension", - default=0, - type=float, - help="Extension for horizontal pins in microns.", -) -@click.option( - "--ver-width-mult", default=2, type=float, help="Multiplier for vertical pins." -) -@click.option( - "--hor-width-mult", default=2, type=float, help="Multiplier for horizontal pins." -) -@click.option( - "--bus-sort/--no-bus-sort", - default=False, - help="Misnomer: pins are grouped by index instead of bus, i.e. a[0] goes with b[0] instead of a[1].", -) -@click.argument("input_def") -def cli( - input_lef, - output_def, - config, - ver_layer, - hor_layer, - ver_width_mult, - hor_width_mult, - length, - hor_extension, - ver_extension, - reverse, - bus_sort, - input_def, -): - """ - Places the IOs in an input def with an optional config file that supports regexes. - - Config format: - #N|#S|#E|#W - pin1_regex (low co-ordinates to high co-ordinates; e.g., bottom to top and left to right) - pin2_regex - ... - - #S|#N|#E|#W - """ - - def_file_name = input_def - lef_file_name = input_lef - output_def_file_name = output_def - config_file_name = config - bus_sort_flag = bus_sort - - #1. Manual Pad Placement - Dinesh A - manual_place_flag = False - - h_layer_name = hor_layer - v_layer_name = ver_layer - - h_width_mult = float(hor_width_mult) - v_width_mult = float(ver_width_mult) - - # Initialize OpenDB - db_top = odb.dbDatabase.create() - odb.read_lef(db_top, lef_file_name) - odb.read_def(db_top, def_file_name) - block = db_top.getChip().getBlock() - - micron_in_units = block.getDefUnits() - - LENGTH = int(micron_in_units * length) - - H_EXTENSION = int(micron_in_units * hor_extension) - V_EXTENSION = int(micron_in_units * ver_extension) - - if H_EXTENSION < 0: - H_EXTENSION = 0 - - if V_EXTENSION < 0: - V_EXTENSION = 0 - - reverse_arr_raw = reverse.split(",") - reverse_arr = [] - for element in reverse_arr_raw: - if element.strip() != "": - reverse_arr.append(f"#{element}") - - def getGrid(origin, count, step): - tracks = [] - pos = origin - for i in range(count): - tracks.append(pos) - pos += step - assert len(tracks) > 0 - tracks.sort() - - return tracks - - def equallySpacedSeq(m, arr): - seq = [] - n = len(arr) - # Bresenham - indices = [i * n // m + n // (2 * m) for i in range(m)] - for i in indices: - seq.append(arr[i]) - return seq - - # HUMAN SORTING: https://stackoverflow.com/questions/5967500/how-to-correctly-sort-a-string-with-a-number-inside - def natural_keys(enum): - def atof(text): - try: - retval = float(text) - except ValueError: - retval = text - return retval - - text = enum[0] - text = re.sub(r"(\[|\]|\.|\$)", "", text) - """ - alist.sort(key=natural_keys) sorts in human order - http://nedbatchelder.com/blog/200712/human_sorting.html - (see toothy's implementation in the comments) - float regex comes from https://stackoverflow.com/a/12643073/190597 - """ - return [ - atof(c) for c in re.split(r"[+-]?([0-9]+(?:[.][0-9]*)?|[.][0-9]+)", text) - ] - - def bus_keys(enum): - text = enum[0] - m = re.match(r"^.*\[(\d+)\]$", text) - if not m: - return -1 - else: - return int(m.group(1)) - - #2. Find the Slot matching next nearest slot-DineshA - def findSlot(val, arr): - for i in arr: - if(i > val): - return i - print("ERROR: Next Valid Position not found :",val) - return -1 - - # read config - - pin_placement_cfg = {"#N": [], "#E": [], "#S": [], "#W": []} - cur_side = None - if config_file_name is not None and config_file_name != "": - with open(config_file_name, "r") as config_file: - for line in config_file: - line = line.split() - if len(line) == 0: - continue - - #3. Dinesh A - Start - if(manual_place_flag == False): - if len(line) > 1: - print("Only one entry allowed per line.") - sys.exit(1) - token = line[0] - else: - #During Manual Place we are allowing Four field - # <Pad Name> <Offset> <Position> <Multiplier> - # Causion: Make sure that you have given absolute name, else it will give issue - if len(line) > 4: - print("Only Four entry allowed per line.") - sys.exit(1) - if line[0] not in ["#N", "#E", "#S", "#W", "#NR", "#ER", "#SR", "#WR"]: - token = line - else: - token = line[0] - - if cur_side is not None and token[0] != "#": - pin_placement_cfg[cur_side].append(token) - elif token not in [ - "#N", - "#E", - "#S", - "#W", - "#NR", - "#ER", - "#SR", - "#WR", - "#BUS_SORT", - "#MANUAL_PLACE" - ]: - print( - "Valid directives are #N, #E, #S, or #W. Append R for reversing the default order.", - "Use #BUS_SORT to group 'bus bits' by index.", - "Please make sure you have set a valid side first before listing pins", - ) - sys.exit(1) - elif token == "#BUS_SORT": - bus_sort_flag = True - #4 - Dinesh A - elif token == "#MANUAL_PLACE": - print("Input token ",token) - manual_place_flag = True - else: - if len(token) == 3: - token = token[0:2] - reverse_arr.append(token) - cur_side = token - - # build a list of pins - - chip_top = db_top.getChip() - block_top = chip_top.getBlock() - top_design_name = block_top.getName() - tech = db_top.getTech() - - H_LAYER = tech.findLayer(h_layer_name) - V_LAYER = tech.findLayer(v_layer_name) - - H_WIDTH = int(h_width_mult * H_LAYER.getWidth()) - V_WIDTH = int(v_width_mult * V_LAYER.getWidth()) - - print("Top-level design name:", top_design_name) - - bterms = block_top.getBTerms() - bterms_enum = [] - for bterm in bterms: - pin_name = bterm.getName() - bterms_enum.append((pin_name, bterm)) - - # sort them "humanly" - bterms_enum.sort(key=natural_keys) - if bus_sort_flag: - bterms_enum.sort(key=bus_keys) - bterms = [bterm[1] for bterm in bterms_enum] - - pin_placement = {"#N": [], "#E": [], "#S": [], "#W": []} - bterm_regex_map = {} - #5. Dinesh A - if(manual_place_flag == False): - for side in pin_placement_cfg: - for regex in pin_placement_cfg[side]: # going through them in order - regex += "$" # anchor - for bterm in bterms: - # if a pin name matches multiple regexes, their order will be - # arbitrary. More refinement requires more strict regexes (or just - # the exact pin name). - pin_name = bterm.getName() - if re.match(regex, pin_name) is not None: - if bterm in bterm_regex_map: - print( - "Error: Multiple regexes matched", - pin_name, - ". Those are", - bterm_regex_map[bterm], - "and", - regex, - ) - sys.exit(os.EX_DATAERR) - bterm_regex_map[bterm] = regex - pin_placement[side].append(bterm) # to maintain the order - - unmatched_bterms = [bterm for bterm in bterms if bterm not in bterm_regex_map] - - if len(unmatched_bterms) > 0: - print("Warning: Some pins weren't matched by the config file") - print("Those are:", [bterm.getName() for bterm in unmatched_bterms]) - if True: - print("Assigning random sides to the above pins") - for bterm in unmatched_bterms: - random_side = random.choice(list(pin_placement.keys())) - pin_placement[random_side].append(bterm) - else: - sys.exit(1) - - #6 Dinesh A - else: - for side in pin_placement_cfg: - for regex in pin_placement_cfg[side]: # going through them in order - regex = regex[0] # take first value - regex += "$" # anchor - for bterm in bterms: - # if a pin name matches multiple regexes, their order will be - # arbitrary. More refinement requires more strict regexes (or just - # the exact pin name). - pin_name = bterm.getName() - if re.match(regex, pin_name) is not None: - print("Debug: Serching Pin match",regex) - if bterm in bterm_regex_map: - #print("Warning: Multiple regexes matched", pin_name) - # ". Those are", bterm_regex_map[bterm], "and", regex) - sys.exit(1) - bterm_regex_map[bterm] = regex - pin_placement[side].append(bterm) # to maintain the order - - unmatched_bterms = [bterm for bterm in bterms if bterm not in bterm_regex_map] - - if len(unmatched_bterms) > 0: - print("Warning: Some pins weren't matched by the config file") - print("Those are:", [bterm.getName() for bterm in unmatched_bterms]) - sys.exit(1) - - - assert len(block_top.getBTerms()) == len( - pin_placement["#N"] - + pin_placement["#E"] - + pin_placement["#S"] - + pin_placement["#W"] - ) - - # generate slots - - DIE_AREA = block_top.getDieArea() - BLOCK_LL_X = DIE_AREA.xMin() - BLOCK_LL_Y = DIE_AREA.yMin() - BLOCK_UR_X = DIE_AREA.xMax() - BLOCK_UR_Y = DIE_AREA.yMax() - - print("Block boundaries:", BLOCK_LL_X, BLOCK_LL_Y, BLOCK_UR_X, BLOCK_UR_Y) - - origin, count, step = block_top.findTrackGrid(H_LAYER).getGridPatternY(0) - - #7. Save the horizontal origin and step - DineshA - h_origin = origin - h_step = step - - h_tracks = getGrid(origin, count, step) - - origin, count, step = block_top.findTrackGrid(V_LAYER).getGridPatternX(0) - - #8. Save the horizontal origin and step - DineshA - v_origin = origin - v_step = step - - v_tracks = getGrid(origin, count, step) - - for rev in reverse_arr: - pin_placement[rev].reverse() - - # create the pins - #9. DineshA - if(manual_place_flag == False): - for side in pin_placement: - if side in ["#N", "#S"]: - slots = equallySpacedSeq(len(pin_placement[side]), v_tracks) - else: - slots = equallySpacedSeq(len(pin_placement[side]), h_tracks) - - assert len(slots) == len(pin_placement[side]) - - for i in range(len(pin_placement[side])): - bterm = pin_placement[side][i] - slot = slots[i] - - pin_name = bterm.getName() - pins = bterm.getBPins() - if len(pins) > 0: - print("Warning:", pin_name, "already has shapes. Modifying them") - assert len(pins) == 1 - pin_bpin = pins[0] - else: - pin_bpin = odb.dbBPin_create(bterm) - - pin_bpin.setPlacementStatus("PLACED") - - if side in ["#N", "#S"]: - rect = odb.Rect(0, 0, V_WIDTH, LENGTH + V_EXTENSION) - if side == "#N": - y = BLOCK_UR_Y - LENGTH - else: - y = BLOCK_LL_Y - V_EXTENSION - rect.moveTo(slot - V_WIDTH // 2, y) - odb.dbBox_create(pin_bpin, V_LAYER, *rect.ll(), *rect.ur()) - else: - rect = odb.Rect(0, 0, LENGTH + H_EXTENSION, H_WIDTH) - if side == "#E": - x = BLOCK_UR_X - LENGTH - else: - x = BLOCK_LL_X - H_EXTENSION - rect.moveTo(x, slot - H_WIDTH // 2) - odb.dbBox_create(pin_bpin, H_LAYER, *rect.ll(), *rect.ur()) - - else: - #10.New Logic, Manual Pin Placement - Dinesh A - #print("Allowed VTracks",v_tracks) - #print("Allowed hTracks",h_tracks) - - for side in pin_placement: - - if(len(pin_placement[side]) != len(pin_placement_cfg[side])): - print("ERROR : At Side:", side, " Total Pin Defined ",len(pin_placement_cfg[side]), "More than available:",len(pin_placement[side])) - - #check defined pad are more than avaibale one - assert len(pin_placement[side]) == len(pin_placement_cfg[side]) - start = 0 - - start_loc = 0 - pad_pos = 0 - slot_pre = 0 - #Dinesh: Give Step Multipler size *2 for better pad placement - multiplier= 2 - for i in range(len(pin_placement_cfg[side])): - #Dinesh: Multiply the offset by 1000 for micro conversion - if(len(pin_placement_cfg[side][i]) > 1): - start_loc = int(pin_placement_cfg[side][i][1]) - if(len(pin_placement_cfg[side][i]) > 2): - pad_pos = int(pin_placement_cfg[side][i][2]) - if(len(pin_placement_cfg[side][i]) > 3): - multiplier = int(pin_placement_cfg[side][i][3]) - - if side in ["#N", "#S"]: - slott = start_loc*1000+int(v_origin)+(int(v_step) * pad_pos * multiplier) - slot =findSlot(slott,v_tracks) - else: - slott = start_loc*1000+int(h_origin)+(int(h_step) * pad_pos * multiplier) - slot =findSlot(slott,h_tracks) - - pad_pos +=1 - bterm = pin_placement[side][i] - - pin_name = bterm.getName() - pins = bterm.getBPins() - if len(pins) > 0: - print("Warning:", pin_name, "already has shapes. Modifying them") - assert len(pins) == 1 - pin_bpin = pins[0] - else: - pin_bpin = odb.dbBPin_create(bterm) - - if(slot < slot_pre): - print("ERROR:", "Current Pad:", pin_name, " Slot:" , slot, " is less than Previous One:",slot_pre) - sys.exit(1) - - slot_pre = slot - - print("Dinesh: Placing Pad:" ,pin_name, " At Side: ", side, " Slot: ", slot) - pin_bpin.setPlacementStatus("PLACED") - - if side in ["#N", "#S"]: - rect = odb.Rect(0, 0, V_WIDTH, LENGTH+V_EXTENSION) - if side == "#N": - y = BLOCK_UR_Y-LENGTH - else: - y = BLOCK_LL_Y-V_EXTENSION - rect.moveTo(slot-V_WIDTH//2, y) - odb.dbBox_create(pin_bpin, V_LAYER, *rect.ll(), *rect.ur()) - else: - rect = odb.Rect(0, 0, LENGTH+H_EXTENSION, H_WIDTH) - if side == "#E": - x = BLOCK_UR_X-LENGTH - else: - x = BLOCK_LL_X-H_EXTENSION - rect.moveTo(x, slot-H_WIDTH//2) - odb.dbBox_create(pin_bpin, H_LAYER, *rect.ll(), *rect.ur()) - - - print( - f"Writing {output_def_file_name}...", - ) - odb.write_def(block_top, output_def_file_name) - - -if __name__ == "__main__": - cli()
diff --git a/openlane/mbist/base.sdc b/openlane/mbist/base.sdc deleted file mode 100644 index 26a1fe6..0000000 --- a/openlane/mbist/base.sdc +++ /dev/null
@@ -1,128 +0,0 @@ -############################################################################### -# Created by write_sdc -# Sun Nov 14 09:33:23 2021 -############################################################################### -current_design mbist_top -############################################################################### -# Timing Constraints -############################################################################### -create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}] -create_clock -name wb_clk2_i -period 10.0000 [get_ports {wb_clk2_i}] -create_generated_clock -name bist_mem_clk_a -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks wb_clk2_i] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a] -create_generated_clock -name bist_mem_clk_b -add -source [get_ports {wb_clk2_i}] -master_clock [get_clocks wb_clk2_i] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b] - -set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {bist_mem_clk_a bist_mem_clk_b}] -group [get_clocks {wb_clk_i }] -group [get_clocks {wb_clk2_i}] - -set_clock_transition 0.1500 [all_clocks] -set_clock_uncertainty -setup 0.2500 [all_clocks] -set_clock_uncertainty -hold 0.2500 [all_clocks] - -set ::env(SYNTH_TIMING_DERATE) 0.05 -puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" -set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] -set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] - -set_input_delay -max 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}] - -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}] - -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}] - -set_false_path -from [get_ports {bist_en}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}] - -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_en}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}] - -## Functional Inputs -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[*]}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbd_mbist1_dat_o[*]}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[*]}] - -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[*]}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbd_mbist1_dat_o[*]}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[*]}] - -set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[*]}] -set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}] -set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_err_o}] - -set_output_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[*]}] -set_output_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}] -set_output_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_err_o}] - -## Towards MEMORY from MBIST CLOCK -## PORT-A -set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}] - - -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}] -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}] - -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}] -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}] - - - -## PORT-B -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}] -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}] -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}] -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}] -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}] - -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}] -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}] -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}] -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}] -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}] - - -# Set max delay for clock skew - -set_max_delay 3.5 -from [get_ports {wbd_clk_int}] -set_max_delay 2 -to [get_ports {wbd_clk_mbist}] -set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_mbist - -############################################################################### -# Environment -############################################################################### -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] -set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] -puts "\[INFO\]: Setting load to: $cap_load" -set_load $cap_load [all_outputs] - -set_timing_derate -early 0.9500 -set_timing_derate -late 1.0500 -############################################################################### -# Design Rules -############################################################################### -set_max_fanout 4.0000 [current_design]
diff --git a/openlane/mbist/config.tcl b/openlane/mbist/config.tcl deleted file mode 100755 index 78cd955..0000000 --- a/openlane/mbist/config.tcl +++ /dev/null
@@ -1,123 +0,0 @@ -# SPDX-FileCopyrightText: 2021 , Dinesh Annayya -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 -# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> - -# Global -# ------ - -set script_dir [file dirname [file normalize [info script]]] -# Name - -set ::env(DESIGN_NAME) mbist_top - -set ::env(DESIGN_IS_CORE) "0" - -# Timing configuration -set ::env(CLOCK_PERIOD) "10" -#set ::env(CLOCK_PORT) "u_cts_wb_clk_b1.u_buf/X \ -# u_cts_wb_clk_b2.u_buf/X \ -# " -set ::env(CLOCK_PORT) { wb_clk_i mem_no\[3\].u_mem_sel.u_mem_clk_sel.u_mux/X mem_no\[2\].u_mem_sel.u_mem_clk_sel.u_mux/X mem_no\[1\].u_mem_sel.u_mem_clk_sel.u_mux/X mem_no\[0\].u_mem_sel.u_mem_clk_sel.u_mux/X } - -set ::env(SYNTH_MAX_FANOUT) 4 - -## CTS BUFFER -set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" -set ::env(CTS_SINK_CLUSTERING_SIZE) "16" -set ::env(CLOCK_BUFFER_FANOUT) "8" - - -# Sources -# ------- - -# Local sources + no2usb sources -set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_addr_gen.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_fsm.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_op_sel.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_repair_addr.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_sti_sel.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_pat_sel.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_mux.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_data_cmp.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv \ - $script_dir/../../verilog/rtl/mbist/src/top/mbist_top.sv \ - $script_dir/../../verilog/rtl/lib/ctech_cells.sv \ - $script_dir/../../verilog/rtl/lib/reset_sync.sv \ - $script_dir/../../verilog/rtl/lib/ser_shift.sv \ - " - -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/mbist/include ] -set ::env(SYNTH_DEFINES) [list SYNTHESIS ] - - -set ::env(SYNTH_PARAMS) "BIST_ADDR_WD 9,\ - BIST_DATA_WD 32,\ - BIST_ADDR_START 9'h000,\ - BIST_ADDR_END 9'h1FB,\ - BIST_REPAIR_ADDR_START 9'h1FC,\ - BIST_RAD_WD_I 9,\ - BIST_RAD_WD_O 9\ - " - -set ::env(SYNTH_READ_BLACKBOX_LIB) 1 -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" - -set ::env(LEC_ENABLE) 0 - -set ::env(VDD_PIN) [list {vccd1}] -set ::env(GND_PIN) [list {vssd1}] - - -# Floorplanning -# ------------- - -set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg - -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 1500 200" - - -# If you're going to use multiple power domains, then keep this disabled. -set ::env(RUN_CVC) 1 - -#set ::env(PDN_CFG) $script_dir/pdn.tcl - - -set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.30" - - - -set ::env(FP_IO_VEXTEND) 4 -set ::env(FP_IO_HEXTEND) 4 - -set ::env(FP_PDN_VPITCH) 140 -set ::env(FP_PDN_HPITCH) 140 -set ::env(FP_PDN_VWIDTH) 5 -set ::env(FP_PDN_HWIDTH) 5 - -set ::env(GLB_RT_MAXLAYER) 5 -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 - -set ::env(DIODE_INSERTION_STRATEGY) 4 - - -set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" -set ::env(QUIT_ON_MAGIC_DRC) "1" -set ::env(QUIT_ON_LVS_ERROR) "0" -set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/mbist/interactive.tcl b/openlane/mbist/interactive.tcl deleted file mode 100644 index f59586f..0000000 --- a/openlane/mbist/interactive.tcl +++ /dev/null
@@ -1,219 +0,0 @@ -#!/usr/bin/tclsh -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# Copyright 2020 Efabless Corporation -# Copyright 2020 Sylvain Munaut -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -package require openlane; - - -proc run_placement_step {args} { - # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def] - # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0] - # set_def $pdndef - if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } { - set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF) - } - - run_placement -} - -proc run_cts_step {args} { - # set_def $::env(opendp_result_file_tag).def - if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } { - set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF) - } - - run_cts - run_resizer_timing -} - -proc run_routing_step {args} { - # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def] - # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0] - # set_def $resizerdef - if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } { - set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF) - } - run_routing -} - -proc run_diode_insertion_2_5_step {args} { - # set_def $::env(tritonRoute_result_file_tag).def - if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } { - set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF) - } - if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } { - run_antenna_check - heal_antenna_violators; # modifies the routed DEF - } - -} - -proc run_power_pins_insertion_step {args} { - # set_def $::env(tritonRoute_result_file_tag).def - if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } { - set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF) - } - if { $::env(LVS_INSERT_POWER_PINS) } { - write_powered_verilog - set_netlist $::env(lvs_result_file_tag).powered.v - } - -} - -proc run_lvs_step {{ lvs_enabled 1 }} { - # set_def $::env(tritonRoute_result_file_tag).def - if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } { - set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF) - } - if { $lvs_enabled } { - run_magic_spice_export - run_lvs; # requires run_magic_spice_export - } - -} - -proc run_drc_step {{ drc_enabled 1 }} { - if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } { - set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF) - } - if { $drc_enabled } { - run_magic_drc - run_klayout_drc - } -} - -proc run_antenna_check_step {{ antenna_check_enabled 1 }} { - if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } { - set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF) - } - if { $antenna_check_enabled } { - run_antenna_check - } -} - -proc run_flow {args} { - set script_dir [file dirname [file normalize [info script]]] - - set options { - {-design required} - {-save_path optional} - {-no_lvs optional} - {-no_drc optional} - {-no_antennacheck optional} - } - set flags {-save} - parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume - - prep {*}$args - - set LVS_ENABLED 1 - set DRC_ENABLED 1 - set ANTENNACHECK_ENABLED 1 - - set steps [dict create "synthesis" {run_synthesis "" } \ - "floorplan" {run_floorplan ""} \ - "placement" {run_placement_step ""} \ - "cts" {run_cts_step ""} \ - "routing" {run_routing_step ""}\ - "diode_insertion" {run_diode_insertion_2_5_step ""} \ - "power_pins_insertion" {run_power_pins_insertion_step ""} \ - "gds_magic" {run_magic ""} \ - "gds_drc_klayout" {run_klayout ""} \ - "gds_xor_klayout" {run_klayout_gds_xor ""} \ - "lvs" "run_lvs_step $LVS_ENABLED" \ - "drc" "run_drc_step $DRC_ENABLED" \ - "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \ - "cvc" {run_lef_cvc} - ] - - set_if_unset arg_values(-to) "cvc"; - - if { [info exists ::env(CURRENT_STEP) ] } { - puts "\[INFO\]:Picking up where last execution left off" - puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)] - } else { - set ::env(CURRENT_STEP) "synthesis"; - } - set_if_unset arg_values(-from) $::env(CURRENT_STEP); - set exe 0; - dict for {step_name step_exe} $steps { - if { [ string equal $arg_values(-from) $step_name ] } { - set exe 1; - } - - if { $exe } { - # For when it fails - set ::env(CURRENT_STEP) $step_name - [lindex $step_exe 0] [lindex $step_exe 1] ; - } - - if { [ string equal $arg_values(-to) $step_name ] } { - set exe 0: - break; - } - - } - - # for when it resumes - set steps_as_list [dict keys $steps] - set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1] - set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx] - - if { [info exists flags_map(-save) ] } { - if { ! [info exists arg_values(-save_path)] } { - set arg_values(-save_path) "" - } - save_views -lef_path $::env(magic_result_file_tag).lef \ - -def_path $::env(CURRENT_DEF) \ - -gds_path $::env(magic_result_file_tag).gds \ - -mag_path $::env(magic_result_file_tag).mag \ - -maglef_path $::env(magic_result_file_tag).lef.mag \ - -spice_path $::env(magic_result_file_tag).spice \ - -spef_path $::env(CURRENT_SPEF) \ - -verilog_path $::env(CURRENT_NETLIST) \ - -save_path $arg_values(-save_path) \ - -tag $::env(RUN_TAG) - } - - - calc_total_runtime - save_state - generate_final_summary_report - - check_timing_violations - - puts_success "Flow Completed Without Fatal Errors." - -} - -run_flow {*}$argv
diff --git a/openlane/mbist/pin_order.cfg b/openlane/mbist/pin_order.cfg deleted file mode 100644 index 0416192..0000000 --- a/openlane/mbist/pin_order.cfg +++ /dev/null
@@ -1,527 +0,0 @@ -#BUS_SORT - -#MANUAL_PLACE - - -#S -rst_n 0000 0 - - - -#E -cfg_cska_mbist\[3\] 0000 0 4 -cfg_cska_mbist\[2\] -cfg_cska_mbist\[1\] -cfg_cska_mbist\[0\] -wb_clk2_i -wb_clk_i -wbd_clk_mbist -wbd_clk_int - -wb_cyc_i 0025 0 2 -wb_stb_i -wb_we_i -wb_cs_i\[1\] -wb_cs_i\[0\] -wb_adr_i\[8\] -wb_adr_i\[7\] -wb_adr_i\[6\] -wb_adr_i\[5\] -wb_adr_i\[4\] -wb_adr_i\[3\] -wb_adr_i\[2\] -wb_adr_i\[1\] -wb_adr_i\[0\] -wb_dat_i\[31\] -wb_dat_i\[30\] -wb_dat_i\[29\] -wb_dat_i\[28\] -wb_dat_i\[27\] -wb_dat_i\[26\] -wb_dat_i\[25\] -wb_dat_i\[24\] -wb_dat_i\[23\] -wb_dat_i\[22\] -wb_dat_i\[21\] -wb_dat_i\[20\] -wb_dat_i\[19\] -wb_dat_i\[18\] -wb_dat_i\[17\] -wb_dat_i\[16\] -wb_dat_i\[15\] -wb_dat_i\[14\] -wb_dat_i\[13\] -wb_dat_i\[12\] -wb_dat_i\[11\] -wb_dat_i\[10\] -wb_dat_i\[9\] -wb_dat_i\[8\] -wb_dat_i\[7\] -wb_dat_i\[6\] -wb_dat_i\[5\] -wb_dat_i\[4\] -wb_dat_i\[3\] -wb_dat_i\[2\] -wb_dat_i\[1\] -wb_dat_i\[0\] -wb_sel_i\[3\] -wb_sel_i\[2\] -wb_sel_i\[1\] -wb_sel_i\[0\] -wb_dat_o\[31\] -wb_dat_o\[30\] -wb_dat_o\[29\] -wb_dat_o\[28\] -wb_dat_o\[27\] -wb_dat_o\[26\] -wb_dat_o\[25\] -wb_dat_o\[24\] -wb_dat_o\[23\] -wb_dat_o\[22\] -wb_dat_o\[21\] -wb_dat_o\[20\] -wb_dat_o\[19\] -wb_dat_o\[18\] -wb_dat_o\[17\] -wb_dat_o\[16\] -wb_dat_o\[15\] -wb_dat_o\[14\] -wb_dat_o\[13\] -wb_dat_o\[12\] -wb_dat_o\[11\] -wb_dat_o\[10\] -wb_dat_o\[9\] -wb_dat_o\[8\] -wb_dat_o\[7\] -wb_dat_o\[6\] -wb_dat_o\[5\] -wb_dat_o\[4\] -wb_dat_o\[3\] -wb_dat_o\[2\] -wb_dat_o\[1\] -wb_dat_o\[0\] -wb_ack_o -wb_err_o - - -bist_error_cnt3\[3\] 0150 0 2 -bist_error_cnt3\[2\] -bist_error_cnt3\[1\] -bist_error_cnt3\[0\] -bist_correct\[3\] -bist_error\[3\] -bist_error_cnt2\[3\] -bist_error_cnt2\[2\] -bist_error_cnt2\[1\] -bist_error_cnt2\[0\] -bist_correct\[2\] -bist_error\[2\] -bist_error_cnt1\[3\] -bist_error_cnt1\[2\] -bist_error_cnt1\[1\] -bist_error_cnt1\[0\] -bist_correct\[1\] -bist_error\[1\] -bist_error_cnt0\[3\] -bist_error_cnt0\[2\] -bist_error_cnt0\[1\] -bist_error_cnt0\[0\] -bist_correct\[0\] -bist_error\[0\] -bist_done -bist_sdo -bist_shift -bist_sdi -bist_load -bist_run -bist_en - -#S -mem_clk_a\[0\] 250 0 2 -mem_cen_a\[0\] -mem_web_a\[0\] -mem_addr_a0\[0\] -mem_addr_a0\[1\] -mem_addr_a0\[2\] -mem_addr_a0\[3\] -mem_addr_a0\[4\] -mem_addr_a0\[5\] -mem_addr_a0\[6\] -mem_addr_a0\[7\] -mem_addr_a0\[8\] -mem_mask_a0\[0\] -mem_mask_a0\[1\] -mem_mask_a0\[2\] -mem_mask_a0\[3\] -mem_din_a0\[0\] -mem_din_a0\[1\] -mem_din_a0\[2\] -mem_din_a0\[3\] -mem_din_a0\[4\] -mem_din_a0\[5\] -mem_din_a0\[6\] -mem_din_a0\[7\] -mem_din_a0\[8\] -mem_din_a0\[9\] -mem_din_a0\[10\] -mem_din_a0\[11\] -mem_din_a0\[12\] -mem_din_a0\[13\] -mem_din_a0\[14\] -mem_din_a0\[15\] -mem_din_a0\[16\] -mem_din_a0\[17\] -mem_din_a0\[18\] -mem_din_a0\[19\] -mem_din_a0\[20\] -mem_din_a0\[21\] -mem_din_a0\[22\] -mem_din_a0\[23\] -mem_din_a0\[24\] -mem_din_a0\[25\] -mem_din_a0\[26\] -mem_din_a0\[27\] -mem_din_a0\[28\] -mem_din_a0\[29\] -mem_din_a0\[30\] -mem_din_a0\[31\] - - -mem_dout_a0\[0\] 350 0 2 -mem_dout_a0\[1\] -mem_dout_a0\[2\] -mem_dout_a0\[3\] -mem_dout_a0\[4\] -mem_dout_a0\[5\] -mem_dout_a0\[6\] -mem_dout_a0\[7\] -mem_dout_a0\[8\] -mem_dout_a0\[9\] -mem_dout_a0\[10\] -mem_dout_a0\[11\] -mem_dout_a0\[12\] -mem_dout_a0\[13\] -mem_dout_a0\[14\] -mem_dout_a0\[15\] -mem_dout_a0\[16\] -mem_dout_a0\[17\] -mem_dout_a0\[18\] -mem_dout_a0\[19\] -mem_dout_a0\[20\] -mem_dout_a0\[21\] -mem_dout_a0\[22\] -mem_dout_a0\[23\] -mem_dout_a0\[24\] -mem_dout_a0\[25\] -mem_dout_a0\[26\] -mem_dout_a0\[27\] -mem_dout_a0\[28\] -mem_dout_a0\[29\] -mem_dout_a0\[30\] -mem_dout_a0\[31\] - - -mem_clk_b\[0\] 0450 0 2 -mem_cen_b\[0\] -mem_addr_b0\[8\] -mem_addr_b0\[7\] -mem_addr_b0\[6\] -mem_addr_b0\[5\] -mem_addr_b0\[4\] -mem_addr_b0\[3\] -mem_addr_b0\[2\] -mem_addr_b0\[1\] -mem_addr_b0\[0\] - - -mem_clk_a\[1\] 1000 0 2 -mem_cen_a\[1\] -mem_web_a\[1\] -mem_addr_a1\[0\] -mem_addr_a1\[1\] -mem_addr_a1\[2\] -mem_addr_a1\[3\] -mem_addr_a1\[4\] -mem_addr_a1\[5\] -mem_addr_a1\[6\] -mem_addr_a1\[7\] -mem_addr_a1\[8\] -mem_mask_a1\[0\] -mem_mask_a1\[1\] -mem_mask_a1\[2\] -mem_mask_a1\[3\] -mem_din_a1\[0\] -mem_din_a1\[1\] -mem_din_a1\[2\] -mem_din_a1\[3\] -mem_din_a1\[4\] -mem_din_a1\[5\] -mem_din_a1\[6\] -mem_din_a1\[7\] -mem_din_a1\[8\] -mem_din_a1\[9\] -mem_din_a1\[10\] -mem_din_a1\[11\] -mem_din_a1\[12\] -mem_din_a1\[13\] -mem_din_a1\[14\] -mem_din_a1\[15\] -mem_din_a1\[16\] -mem_din_a1\[17\] -mem_din_a1\[18\] -mem_din_a1\[19\] -mem_din_a1\[20\] -mem_din_a1\[21\] -mem_din_a1\[22\] -mem_din_a1\[23\] -mem_din_a1\[24\] -mem_din_a1\[25\] -mem_din_a1\[26\] -mem_din_a1\[27\] -mem_din_a1\[28\] -mem_din_a1\[29\] -mem_din_a1\[30\] -mem_din_a1\[31\] - - -mem_dout_a1\[0\] 1100 0 2 -mem_dout_a1\[1\] -mem_dout_a1\[2\] -mem_dout_a1\[3\] -mem_dout_a1\[4\] -mem_dout_a1\[5\] -mem_dout_a1\[6\] -mem_dout_a1\[7\] -mem_dout_a1\[8\] -mem_dout_a1\[9\] -mem_dout_a1\[10\] -mem_dout_a1\[11\] -mem_dout_a1\[12\] -mem_dout_a1\[13\] -mem_dout_a1\[14\] -mem_dout_a1\[15\] -mem_dout_a1\[16\] -mem_dout_a1\[17\] -mem_dout_a1\[18\] -mem_dout_a1\[19\] -mem_dout_a1\[20\] -mem_dout_a1\[21\] -mem_dout_a1\[22\] -mem_dout_a1\[23\] -mem_dout_a1\[24\] -mem_dout_a1\[25\] -mem_dout_a1\[26\] -mem_dout_a1\[27\] -mem_dout_a1\[28\] -mem_dout_a1\[29\] -mem_dout_a1\[30\] -mem_dout_a1\[31\] - - -mem_clk_b\[1\] 1200 0 2 -mem_cen_b\[1\] -mem_addr_b1\[8\] -mem_addr_b1\[7\] -mem_addr_b1\[6\] -mem_addr_b1\[5\] -mem_addr_b1\[4\] -mem_addr_b1\[3\] -mem_addr_b1\[2\] -mem_addr_b1\[1\] -mem_addr_b1\[0\] - - -#N -mem_clk_a\[2\] 250 0 2 -mem_cen_a\[2\] -mem_web_a\[2\] -mem_addr_a2\[0\] -mem_addr_a2\[1\] -mem_addr_a2\[2\] -mem_addr_a2\[3\] -mem_addr_a2\[4\] -mem_addr_a2\[5\] -mem_addr_a2\[6\] -mem_addr_a2\[7\] -mem_addr_a2\[8\] -mem_mask_a2\[0\] -mem_mask_a2\[1\] -mem_mask_a2\[2\] -mem_mask_a2\[3\] -mem_din_a2\[0\] -mem_din_a2\[1\] -mem_din_a2\[2\] -mem_din_a2\[3\] -mem_din_a2\[4\] -mem_din_a2\[5\] -mem_din_a2\[6\] -mem_din_a2\[7\] -mem_din_a2\[8\] -mem_din_a2\[9\] -mem_din_a2\[10\] -mem_din_a2\[11\] -mem_din_a2\[12\] -mem_din_a2\[13\] -mem_din_a2\[14\] -mem_din_a2\[15\] -mem_din_a2\[16\] -mem_din_a2\[17\] -mem_din_a2\[18\] -mem_din_a2\[19\] -mem_din_a2\[20\] -mem_din_a2\[21\] -mem_din_a2\[22\] -mem_din_a2\[23\] -mem_din_a2\[24\] -mem_din_a2\[25\] -mem_din_a2\[26\] -mem_din_a2\[27\] -mem_din_a2\[28\] -mem_din_a2\[29\] -mem_din_a2\[30\] -mem_din_a2\[31\] - - -mem_dout_a2\[0\] 0350 0 2 -mem_dout_a2\[1\] -mem_dout_a2\[2\] -mem_dout_a2\[3\] -mem_dout_a2\[4\] -mem_dout_a2\[5\] -mem_dout_a2\[6\] -mem_dout_a2\[7\] -mem_dout_a2\[8\] -mem_dout_a2\[9\] -mem_dout_a2\[10\] -mem_dout_a2\[11\] -mem_dout_a2\[12\] -mem_dout_a2\[13\] -mem_dout_a2\[14\] -mem_dout_a2\[15\] -mem_dout_a2\[16\] -mem_dout_a2\[17\] -mem_dout_a2\[18\] -mem_dout_a2\[19\] -mem_dout_a2\[20\] -mem_dout_a2\[21\] -mem_dout_a2\[22\] -mem_dout_a2\[23\] -mem_dout_a2\[24\] -mem_dout_a2\[25\] -mem_dout_a2\[26\] -mem_dout_a2\[27\] -mem_dout_a2\[28\] -mem_dout_a2\[29\] -mem_dout_a2\[30\] -mem_dout_a2\[31\] - - -mem_clk_b\[2\] 0450 0 2 -mem_cen_b\[2\] -mem_addr_b2\[8\] -mem_addr_b2\[7\] -mem_addr_b2\[6\] -mem_addr_b2\[5\] -mem_addr_b2\[4\] -mem_addr_b2\[3\] -mem_addr_b2\[2\] -mem_addr_b2\[1\] -mem_addr_b2\[0\] - - -mem_clk_a\[3\] 1000 0 2 -mem_cen_a\[3\] -mem_web_a\[3\] -mem_addr_a3\[0\] -mem_addr_a3\[1\] -mem_addr_a3\[2\] -mem_addr_a3\[3\] -mem_addr_a3\[4\] -mem_addr_a3\[5\] -mem_addr_a3\[6\] -mem_addr_a3\[7\] -mem_addr_a3\[8\] -mem_mask_a3\[0\] -mem_mask_a3\[1\] -mem_mask_a3\[2\] -mem_mask_a3\[3\] -mem_din_a3\[0\] -mem_din_a3\[1\] -mem_din_a3\[2\] -mem_din_a3\[3\] -mem_din_a3\[4\] -mem_din_a3\[5\] -mem_din_a3\[6\] -mem_din_a3\[7\] -mem_din_a3\[8\] -mem_din_a3\[9\] -mem_din_a3\[10\] -mem_din_a3\[11\] -mem_din_a3\[12\] -mem_din_a3\[13\] -mem_din_a3\[14\] -mem_din_a3\[15\] -mem_din_a3\[16\] -mem_din_a3\[17\] -mem_din_a3\[18\] -mem_din_a3\[19\] -mem_din_a3\[20\] -mem_din_a3\[21\] -mem_din_a3\[22\] -mem_din_a3\[23\] -mem_din_a3\[24\] -mem_din_a3\[25\] -mem_din_a3\[26\] -mem_din_a3\[27\] -mem_din_a3\[28\] -mem_din_a3\[29\] -mem_din_a3\[30\] -mem_din_a3\[31\] - - -mem_dout_a3\[0\] 1100 0 2 -mem_dout_a3\[1\] -mem_dout_a3\[2\] -mem_dout_a3\[3\] -mem_dout_a3\[4\] -mem_dout_a3\[5\] -mem_dout_a3\[6\] -mem_dout_a3\[7\] -mem_dout_a3\[8\] -mem_dout_a3\[9\] -mem_dout_a3\[10\] -mem_dout_a3\[11\] -mem_dout_a3\[12\] -mem_dout_a3\[13\] -mem_dout_a3\[14\] -mem_dout_a3\[15\] -mem_dout_a3\[16\] -mem_dout_a3\[17\] -mem_dout_a3\[18\] -mem_dout_a3\[19\] -mem_dout_a3\[20\] -mem_dout_a3\[21\] -mem_dout_a3\[22\] -mem_dout_a3\[23\] -mem_dout_a3\[24\] -mem_dout_a3\[25\] -mem_dout_a3\[26\] -mem_dout_a3\[27\] -mem_dout_a3\[28\] -mem_dout_a3\[29\] -mem_dout_a3\[30\] -mem_dout_a3\[31\] - - -mem_clk_b\[3\] 1200 0 2 -mem_cen_b\[3\] -mem_addr_b3\[8\] -mem_addr_b3\[7\] -mem_addr_b3\[6\] -mem_addr_b3\[5\] -mem_addr_b3\[4\] -mem_addr_b3\[3\] -mem_addr_b3\[2\] -mem_addr_b3\[1\] -mem_addr_b3\[0\] -
diff --git a/openlane/mbist/sta.tcl b/openlane/mbist/sta.tcl deleted file mode 100644 index 57a6c35..0000000 --- a/openlane/mbist/sta.tcl +++ /dev/null
@@ -1,88 +0,0 @@ -# SPDX-FileCopyrightText: 2021 , Dinesh Annayya -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 -# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> - - -set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib" -set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib" -set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib" -set ::env(DESIGN_NAME) "mbist_top" -set ::env(BASE_SDC_FILE) "base.sdc" -set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8" -set ::env(SYNTH_DRIVING_CELL_PIN) "Y" -set ::env(SYNTH_CAP_LOAD) "17.65" -set ::env(WIRE_RC_LAYER) "met1" - -#To disable empty filler cell black box get created -#set link_make_black_boxes 0 - - -set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um -define_corners wc bc tt -read_liberty -corner bc $::env(LIB_FASTEST) -read_liberty -corner wc $::env(LIB_SLOWEST) -read_liberty -corner tt $::env(LIB_TYPICAL) - - -read_verilog ../user_project_wrapper/netlist/mbist.v -link_design $::env(DESIGN_NAME) - - -read_spef ../../spef/mbist_top.spef - - -read_sdc -echo $::env(BASE_SDC_FILE) - -# check for missing constraints -check_setup -verbose > unconstraints.rpt - -set_operating_conditions -analysis_type single -# Propgate the clock -set_propagated_clock [all_clocks] - -report_tns -report_wns -#report_power -echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_ss_max.rpt -report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc >> timing_ss_max.rpt -report_checks -group_count 100 -path_delay max -path_group bist_clk -corner wc >> timing_ss_max.rpt -report_checks -group_count 100 -path_delay max -path_group mem_clk_a -corner wc >> timing_ss_max.rpt -report_checks -group_count 100 -path_delay max -path_group mem_clk_b -corner wc >> timing_ss_max.rpt -report_checks -path_delay max -corner wc >> timing_ss_max.rpt - -echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_ff_min.rpt -report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc >> timing_ff_min.rpt -report_checks -group_count 100 -path_delay min -path_group bist_clk -corner bc >> timing_ff_min.rpt -report_checks -group_count 100 -path_delay min -path_group mem_clk_a -corner bc >> timing_ff_min.rpt -report_checks -group_count 100 -path_delay min -path_group mem_clk_b -corner bc >> timing_ff_min.rpt -report_checks -path_delay min -corner bc >> timing_ff_min.rpt - -echo "################ CORNER : TT (MAX) TIMING Report ###################" > timing_tt_max.rpt -report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_max.rpt -report_checks -group_count 100 -path_delay max -path_group bist_clk -corner tt >> timing_tt_max.rpt -report_checks -group_count 100 -path_delay max -path_group mem_clk_a -corner tt >> timing_tt_max.rpt -report_checks -group_count 100 -path_delay max -path_group mem_clk_b -corner tt >> timing_tt_max.rpt -report_checks -path_delay min -corner tt >> timing_tt_min.rpt - -echo "################ CORNER : TT (MIN) TIMING Report ###################" > timing_tt_min.rpt -report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_min.rpt -report_checks -group_count 100 -path_delay min -path_group bist_clk -corner tt >> timing_tt_min.rpt -report_checks -group_count 100 -path_delay min -path_group mem_clk_a -corner tt >> timing_tt_min.rpt -report_checks -group_count 100 -path_delay min -path_group mem_clk_b -corner tt >> timing_tt_min.rpt -report_checks -path_delay min -corner tt >> timing_tt_min.rpt - -report_checks -path_delay min - -#exit
diff --git a/openlane/mbist1/base.sdc b/openlane/mbist1/base.sdc deleted file mode 100644 index 8ae25b1..0000000 --- a/openlane/mbist1/base.sdc +++ /dev/null
@@ -1,163 +0,0 @@ -############################################################################### -# Created by write_sdc -# Sun Nov 14 09:33:23 2021 -############################################################################### -current_design mbist_top -############################################################################### -# Timing Constraints -############################################################################### -create_clock -name wb_clk_i -period 10.0000 [get_ports {wb_clk_i}] -create_generated_clock -name bist_mem_clk_a -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock A} [get_ports mem_clk_a] -create_generated_clock -name bist_mem_clk_b -add -source [get_ports {wb_clk_i}] -master_clock [get_clocks wb_clk_i] -divide_by 1 -comment {Mem Clock B} [get_ports mem_clk_b] - -set_clock_groups -name async_clock -asynchronous -comment "Async Clock group" -group [get_clocks {wb_clk_i bist_mem_clk_a bist_mem_clk_b}] - -set_clock_transition 0.1500 [get_clocks {wb_clk_i}] -set_clock_uncertainty -setup 0.2500 wb_clk_i -set_clock_uncertainty -setup 0.2500 mem_clk_a -set_clock_uncertainty -setup 0.2500 mem_clk_b - -set_clock_uncertainty -hold 0.2500 wb_clk_i -set_clock_uncertainty -hold 0.2500 mem_clk_a -set_clock_uncertainty -hold 0.2500 mem_clk_b - -set ::env(SYNTH_TIMING_DERATE) 0.05 -puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" -set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] -set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] - -set_input_delay -max 5.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {rst_n}] - -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}] - -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_correct}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_done}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[0]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[1]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[2]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_error_cnt[3]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdo}] - -set_false_path -from [get_ports {bist_en}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}] - -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_en}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_load}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_run}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_sdi}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {bist_shift}] - -## Functional Inputs -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[*]}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbd_mbist1_dat_o[*]}] -set_input_delay -max 4 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[*]}] - -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_adr_i[*]}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_stb_i}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_cyc_i}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_we_i}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wbd_mbist1_dat_o[*]}] -set_input_delay -min 2 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_sel_i[*]}] - -set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[*]}] -set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}] -set_output_delay -max 5 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_err_o}] - -set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_dat_o[*]}] -set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_ack_o}] -set_output_delay -min 1 -clock [get_clocks {wb_clk_i}] -add_delay [get_ports {wb_err_o}] - -## Towards MEMORY from MBIST CLOCK -## PORT-A -set_input_delay -max 4.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}] -set_input_delay -min 1.0000 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_dout_a[*]}] - - -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}] -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}] - -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_addr_a[*]}] -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_a}] -add_delay [get_ports {mem_cen_a}] - - - -## PORT-B -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}] -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}] -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}] -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}] -set_output_delay -max 4 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}] - -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_cen_b}] -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_din_b[*]}] -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_mask_b[*]}] -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_web_b}] -set_output_delay -min -0.5 -clock [get_clocks {bist_mem_clk_b}] -add_delay [get_ports {mem_addr_b[*]}] - - -# Set max delay for clock skew - -set_max_delay 3.5 -from [get_ports {wbd_clk_int}] -set_max_delay 2 -to [get_ports {wbd_clk_mbist}] -set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_mbist - -############################################################################### -# Environment -############################################################################### -set_load -pin_load 0.0334 [get_ports {bist_correct}] -set_load -pin_load 0.0334 [get_ports {bist_done}] -set_load -pin_load 0.0334 [get_ports {bist_error}] -set_load -pin_load 0.0334 [get_ports {bist_sdo}] -set_load -pin_load 0.0334 [get_ports {mem_cen_a}] -set_load -pin_load 0.0334 [get_ports {mem_cen_b}] -set_load -pin_load 0.0334 [get_ports {mem_clk_a}] -set_load -pin_load 0.0334 [get_ports {mem_clk_b}] -set_load -pin_load 0.0334 [get_ports {mem_web_b}] -set_load -pin_load 0.0334 [get_ports {bist_error_cnt[3]}] -set_load -pin_load 0.0334 [get_ports {bist_error_cnt[2]}] -set_load -pin_load 0.0334 [get_ports {bist_error_cnt[1]}] -set_load -pin_load 0.0334 [get_ports {bist_error_cnt[0]}] -set_load -pin_load 0.0334 [get_ports {wb_cyc_i}] -set_load -pin_load 0.0334 [get_ports {wb_stb_i}] -set_load -pin_load 0.0334 [get_ports {wb_adr_i[*]}] -set_load -pin_load 0.0334 [get_ports {wb_we_i}] -set_load -pin_load 0.0334 [get_ports {wb_dat_i[*]}] -set_load -pin_load 0.0334 [get_ports {wb_sel_i[*]}] -set_load -pin_load 0.0334 [get_ports {mem_addr_a[*]}] -set_load -pin_load 0.0334 [get_ports {mem_addr_b[*]}] -set_load -pin_load 0.0334 [get_ports {mem_din_b[*]}] -set_load -pin_load 0.0334 [get_ports {mem_mask_b[*]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_en}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_load}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_run}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_sdi}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {bist_shift}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_cyc_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_adr_i[*]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_we_i}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_dat_i[*]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {wb_sel_i[*]}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {rst_n}] -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mem_dout_a[*]}] -set_timing_derate -early 0.9500 -set_timing_derate -late 1.0500 -############################################################################### -# Design Rules -############################################################################### -set_max_fanout 4.0000 [current_design]
diff --git a/openlane/mbist1/config.tcl b/openlane/mbist1/config.tcl deleted file mode 100755 index 1876487..0000000 --- a/openlane/mbist1/config.tcl +++ /dev/null
@@ -1,113 +0,0 @@ -# SPDX-FileCopyrightText: 2021 , Dinesh Annayya -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 -# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> - -# Global -# ------ - -set script_dir [file dirname [file normalize [info script]]] -# Name - -set ::env(DESIGN_NAME) mbist_top1 - -set ::env(DESIGN_IS_CORE) "0" - -# Timing configuration -set ::env(CLOCK_PERIOD) "10" -set ::env(CLOCK_PORT) "u_cts_wb_clk_b1.u_buf/X u_cts_wb_clk_b2.u_buf/X u_mem_sel.u_cts_mem_clk_a.u_buf/X u_mem_sel.u_cts_mem_clk_b.u_buf/X" - -set ::env(SYNTH_MAX_FANOUT) 4 - -# Sources -# ------- - -# Local sources + no2usb sources -set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_addr_gen.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_fsm.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_op_sel.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_repair_addr.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_sti_sel.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_pat_sel.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_mux.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_data_cmp.sv \ - $script_dir/../../verilog/rtl/mbist/src/core/mbist_mem_wrapper.sv \ - $script_dir/../../verilog/rtl/mbist/src/top/mbist_top1.sv \ - $script_dir/../../verilog/rtl/lib/ctech_cells.sv \ - $script_dir/../../verilog/rtl/lib/reset_sync.sv \ - " - -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/mbist/include ] -set ::env(SYNTH_DEFINES) [list SYNTHESIS ] - - -set ::env(SYNTH_PARAMS) "BIST_ADDR_WD 9,\ - BIST_DATA_WD 32,\ - BIST_ADDR_START 9'h000,\ - BIST_ADDR_END 9'h1FB,\ - BIST_REPAIR_ADDR_START 9'h1FC,\ - BIST_RAD_WD_I 9,\ - BIST_RAD_WD_O 9\ - " - -set ::env(SYNTH_READ_BLACKBOX_LIB) 1 -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" - -set ::env(LEC_ENABLE) 0 - -set ::env(VDD_PIN) [list {vccd1}] -set ::env(GND_PIN) [list {vssd1}] - - -# Floorplanning -# ------------- - -set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg - -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 200 275" - - -# If you're going to use multiple power domains, then keep this disabled. -set ::env(RUN_CVC) 1 - -#set ::env(PDN_CFG) $script_dir/pdn.tcl - - -set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.35" - - - -set ::env(FP_IO_VEXTEND) 4 -set ::env(FP_IO_HEXTEND) 4 - -set ::env(FP_PDN_VPITCH) 100 -set ::env(FP_PDN_HPITCH) 100 -set ::env(FP_PDN_VWIDTH) 5 -set ::env(FP_PDN_HWIDTH) 5 - -set ::env(GLB_RT_MAXLAYER) 5 -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 - -set ::env(DIODE_INSERTION_STRATEGY) 4 - - -set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" -set ::env(QUIT_ON_MAGIC_DRC) "1" -set ::env(QUIT_ON_LVS_ERROR) "0" -set ::env(QUIT_ON_SLEW_VIOLATIONS) "0"
diff --git a/openlane/mbist1/interactive.tcl b/openlane/mbist1/interactive.tcl deleted file mode 100644 index f59586f..0000000 --- a/openlane/mbist1/interactive.tcl +++ /dev/null
@@ -1,219 +0,0 @@ -#!/usr/bin/tclsh -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# Copyright 2020 Efabless Corporation -# Copyright 2020 Sylvain Munaut -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -package require openlane; - - -proc run_placement_step {args} { - # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def] - # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0] - # set_def $pdndef - if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } { - set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF) - } - - run_placement -} - -proc run_cts_step {args} { - # set_def $::env(opendp_result_file_tag).def - if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } { - set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF) - } - - run_cts - run_resizer_timing -} - -proc run_routing_step {args} { - # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def] - # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0] - # set_def $resizerdef - if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } { - set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF) - } - run_routing -} - -proc run_diode_insertion_2_5_step {args} { - # set_def $::env(tritonRoute_result_file_tag).def - if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } { - set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF) - } - if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } { - run_antenna_check - heal_antenna_violators; # modifies the routed DEF - } - -} - -proc run_power_pins_insertion_step {args} { - # set_def $::env(tritonRoute_result_file_tag).def - if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } { - set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF) - } - if { $::env(LVS_INSERT_POWER_PINS) } { - write_powered_verilog - set_netlist $::env(lvs_result_file_tag).powered.v - } - -} - -proc run_lvs_step {{ lvs_enabled 1 }} { - # set_def $::env(tritonRoute_result_file_tag).def - if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } { - set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF) - } - if { $lvs_enabled } { - run_magic_spice_export - run_lvs; # requires run_magic_spice_export - } - -} - -proc run_drc_step {{ drc_enabled 1 }} { - if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } { - set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF) - } - if { $drc_enabled } { - run_magic_drc - run_klayout_drc - } -} - -proc run_antenna_check_step {{ antenna_check_enabled 1 }} { - if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } { - set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF) - } - if { $antenna_check_enabled } { - run_antenna_check - } -} - -proc run_flow {args} { - set script_dir [file dirname [file normalize [info script]]] - - set options { - {-design required} - {-save_path optional} - {-no_lvs optional} - {-no_drc optional} - {-no_antennacheck optional} - } - set flags {-save} - parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume - - prep {*}$args - - set LVS_ENABLED 1 - set DRC_ENABLED 1 - set ANTENNACHECK_ENABLED 1 - - set steps [dict create "synthesis" {run_synthesis "" } \ - "floorplan" {run_floorplan ""} \ - "placement" {run_placement_step ""} \ - "cts" {run_cts_step ""} \ - "routing" {run_routing_step ""}\ - "diode_insertion" {run_diode_insertion_2_5_step ""} \ - "power_pins_insertion" {run_power_pins_insertion_step ""} \ - "gds_magic" {run_magic ""} \ - "gds_drc_klayout" {run_klayout ""} \ - "gds_xor_klayout" {run_klayout_gds_xor ""} \ - "lvs" "run_lvs_step $LVS_ENABLED" \ - "drc" "run_drc_step $DRC_ENABLED" \ - "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \ - "cvc" {run_lef_cvc} - ] - - set_if_unset arg_values(-to) "cvc"; - - if { [info exists ::env(CURRENT_STEP) ] } { - puts "\[INFO\]:Picking up where last execution left off" - puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)] - } else { - set ::env(CURRENT_STEP) "synthesis"; - } - set_if_unset arg_values(-from) $::env(CURRENT_STEP); - set exe 0; - dict for {step_name step_exe} $steps { - if { [ string equal $arg_values(-from) $step_name ] } { - set exe 1; - } - - if { $exe } { - # For when it fails - set ::env(CURRENT_STEP) $step_name - [lindex $step_exe 0] [lindex $step_exe 1] ; - } - - if { [ string equal $arg_values(-to) $step_name ] } { - set exe 0: - break; - } - - } - - # for when it resumes - set steps_as_list [dict keys $steps] - set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1] - set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx] - - if { [info exists flags_map(-save) ] } { - if { ! [info exists arg_values(-save_path)] } { - set arg_values(-save_path) "" - } - save_views -lef_path $::env(magic_result_file_tag).lef \ - -def_path $::env(CURRENT_DEF) \ - -gds_path $::env(magic_result_file_tag).gds \ - -mag_path $::env(magic_result_file_tag).mag \ - -maglef_path $::env(magic_result_file_tag).lef.mag \ - -spice_path $::env(magic_result_file_tag).spice \ - -spef_path $::env(CURRENT_SPEF) \ - -verilog_path $::env(CURRENT_NETLIST) \ - -save_path $arg_values(-save_path) \ - -tag $::env(RUN_TAG) - } - - - calc_total_runtime - save_state - generate_final_summary_report - - check_timing_violations - - puts_success "Flow Completed Without Fatal Errors." - -} - -run_flow {*}$argv
diff --git a/openlane/mbist1/pin_order.cfg b/openlane/mbist1/pin_order.cfg deleted file mode 100644 index 82dd636..0000000 --- a/openlane/mbist1/pin_order.cfg +++ /dev/null
@@ -1,213 +0,0 @@ -#BUS_SORT - -#MANUAL_PLACE - - -#S -rst_n 0000 0 - - - -#E -cfg_cska_mbist\[3\] 0000 0 4 -cfg_cska_mbist\[2\] -cfg_cska_mbist\[1\] -cfg_cska_mbist\[0\] -wb_clk_i -wbd_clk_mbist -wbd_clk_int - -wb_cyc_i 0025 0 2 -wb_stb_i -wb_we_i -wb_adr_i\[8\] -wb_adr_i\[7\] -wb_adr_i\[6\] -wb_adr_i\[5\] -wb_adr_i\[4\] -wb_adr_i\[3\] -wb_adr_i\[2\] -wb_adr_i\[1\] -wb_adr_i\[0\] -wb_dat_i\[31\] -wb_dat_i\[30\] -wb_dat_i\[29\] -wb_dat_i\[28\] -wb_dat_i\[27\] -wb_dat_i\[26\] -wb_dat_i\[25\] -wb_dat_i\[24\] -wb_dat_i\[23\] -wb_dat_i\[22\] -wb_dat_i\[21\] -wb_dat_i\[20\] -wb_dat_i\[19\] -wb_dat_i\[18\] -wb_dat_i\[17\] -wb_dat_i\[16\] -wb_dat_i\[15\] -wb_dat_i\[14\] -wb_dat_i\[13\] -wb_dat_i\[12\] -wb_dat_i\[11\] -wb_dat_i\[10\] -wb_dat_i\[9\] -wb_dat_i\[8\] -wb_dat_i\[7\] -wb_dat_i\[6\] -wb_dat_i\[5\] -wb_dat_i\[4\] -wb_dat_i\[3\] -wb_dat_i\[2\] -wb_dat_i\[1\] -wb_dat_i\[0\] -wb_sel_i\[3\] -wb_sel_i\[2\] -wb_sel_i\[1\] -wb_sel_i\[0\] -wb_dat_o\[31\] -wb_dat_o\[30\] -wb_dat_o\[29\] -wb_dat_o\[28\] -wb_dat_o\[27\] -wb_dat_o\[26\] -wb_dat_o\[25\] -wb_dat_o\[24\] -wb_dat_o\[23\] -wb_dat_o\[22\] -wb_dat_o\[21\] -wb_dat_o\[20\] -wb_dat_o\[19\] -wb_dat_o\[18\] -wb_dat_o\[17\] -wb_dat_o\[16\] -wb_dat_o\[15\] -wb_dat_o\[14\] -wb_dat_o\[13\] -wb_dat_o\[12\] -wb_dat_o\[11\] -wb_dat_o\[10\] -wb_dat_o\[9\] -wb_dat_o\[8\] -wb_dat_o\[7\] -wb_dat_o\[6\] -wb_dat_o\[5\] -wb_dat_o\[4\] -wb_dat_o\[3\] -wb_dat_o\[2\] -wb_dat_o\[1\] -wb_dat_o\[0\] -wb_ack_o -wb_err_o - - -bist_error_cnt\[3\] 0150 0 2 -bist_error_cnt\[2\] -bist_error_cnt\[1\] -bist_error_cnt\[0\] -bist_correct -bist_error -bist_done -bist_sdo -bist_shift -bist_sdi -bist_load -bist_run -bist_en - -#W -mem_clk_b 0000 0 2 -mem_cen_b -mem_web_b -mem_mask_b\[0\] -mem_mask_b\[1\] -mem_mask_b\[2\] -mem_mask_b\[3\] -mem_addr_b\[0\] -mem_addr_b\[1\] -mem_addr_b\[2\] -mem_addr_b\[3\] -mem_addr_b\[4\] -mem_addr_b\[5\] -mem_addr_b\[6\] -mem_addr_b\[7\] -mem_addr_b\[8\] -mem_din_b\[0\] -mem_din_b\[1\] -mem_din_b\[2\] -mem_din_b\[3\] -mem_din_b\[4\] -mem_din_b\[5\] -mem_din_b\[6\] -mem_din_b\[7\] -mem_din_b\[8\] -mem_din_b\[9\] -mem_din_b\[10\] -mem_din_b\[11\] -mem_din_b\[12\] -mem_din_b\[13\] -mem_din_b\[14\] -mem_din_b\[15\] -mem_din_b\[16\] -mem_din_b\[17\] -mem_din_b\[18\] -mem_din_b\[19\] -mem_din_b\[20\] -mem_din_b\[21\] -mem_din_b\[22\] -mem_din_b\[23\] -mem_din_b\[24\] -mem_din_b\[25\] -mem_din_b\[26\] -mem_din_b\[27\] -mem_din_b\[28\] -mem_din_b\[29\] -mem_din_b\[30\] -mem_din_b\[31\] - - -mem_dout_a\[0\] 0100 0 2 -mem_dout_a\[1\] -mem_dout_a\[2\] -mem_dout_a\[3\] -mem_dout_a\[4\] -mem_dout_a\[5\] -mem_dout_a\[6\] -mem_dout_a\[7\] -mem_dout_a\[8\] -mem_dout_a\[9\] -mem_dout_a\[10\] -mem_dout_a\[11\] -mem_dout_a\[12\] -mem_dout_a\[13\] -mem_dout_a\[14\] -mem_dout_a\[15\] -mem_dout_a\[16\] -mem_dout_a\[17\] -mem_dout_a\[18\] -mem_dout_a\[19\] -mem_dout_a\[20\] -mem_dout_a\[21\] -mem_dout_a\[22\] -mem_dout_a\[23\] -mem_dout_a\[24\] -mem_dout_a\[25\] -mem_dout_a\[26\] -mem_dout_a\[27\] -mem_dout_a\[28\] -mem_dout_a\[29\] -mem_dout_a\[30\] -mem_dout_a\[31\] - - -mem_clk_a 0200 0 2 -mem_cen_a -mem_addr_a\[8\] -mem_addr_a\[7\] -mem_addr_a\[6\] -mem_addr_a\[5\] -mem_addr_a\[4\] -mem_addr_a\[3\] -mem_addr_a\[2\] -mem_addr_a\[1\] -mem_addr_a\[0\]
diff --git a/openlane/mbist1/sta.tcl b/openlane/mbist1/sta.tcl deleted file mode 100644 index 57a6c35..0000000 --- a/openlane/mbist1/sta.tcl +++ /dev/null
@@ -1,88 +0,0 @@ -# SPDX-FileCopyrightText: 2021 , Dinesh Annayya -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 -# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> - - -set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib" -set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib" -set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib" -set ::env(DESIGN_NAME) "mbist_top" -set ::env(BASE_SDC_FILE) "base.sdc" -set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8" -set ::env(SYNTH_DRIVING_CELL_PIN) "Y" -set ::env(SYNTH_CAP_LOAD) "17.65" -set ::env(WIRE_RC_LAYER) "met1" - -#To disable empty filler cell black box get created -#set link_make_black_boxes 0 - - -set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um -define_corners wc bc tt -read_liberty -corner bc $::env(LIB_FASTEST) -read_liberty -corner wc $::env(LIB_SLOWEST) -read_liberty -corner tt $::env(LIB_TYPICAL) - - -read_verilog ../user_project_wrapper/netlist/mbist.v -link_design $::env(DESIGN_NAME) - - -read_spef ../../spef/mbist_top.spef - - -read_sdc -echo $::env(BASE_SDC_FILE) - -# check for missing constraints -check_setup -verbose > unconstraints.rpt - -set_operating_conditions -analysis_type single -# Propgate the clock -set_propagated_clock [all_clocks] - -report_tns -report_wns -#report_power -echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_ss_max.rpt -report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc >> timing_ss_max.rpt -report_checks -group_count 100 -path_delay max -path_group bist_clk -corner wc >> timing_ss_max.rpt -report_checks -group_count 100 -path_delay max -path_group mem_clk_a -corner wc >> timing_ss_max.rpt -report_checks -group_count 100 -path_delay max -path_group mem_clk_b -corner wc >> timing_ss_max.rpt -report_checks -path_delay max -corner wc >> timing_ss_max.rpt - -echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_ff_min.rpt -report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc >> timing_ff_min.rpt -report_checks -group_count 100 -path_delay min -path_group bist_clk -corner bc >> timing_ff_min.rpt -report_checks -group_count 100 -path_delay min -path_group mem_clk_a -corner bc >> timing_ff_min.rpt -report_checks -group_count 100 -path_delay min -path_group mem_clk_b -corner bc >> timing_ff_min.rpt -report_checks -path_delay min -corner bc >> timing_ff_min.rpt - -echo "################ CORNER : TT (MAX) TIMING Report ###################" > timing_tt_max.rpt -report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_max.rpt -report_checks -group_count 100 -path_delay max -path_group bist_clk -corner tt >> timing_tt_max.rpt -report_checks -group_count 100 -path_delay max -path_group mem_clk_a -corner tt >> timing_tt_max.rpt -report_checks -group_count 100 -path_delay max -path_group mem_clk_b -corner tt >> timing_tt_max.rpt -report_checks -path_delay min -corner tt >> timing_tt_min.rpt - -echo "################ CORNER : TT (MIN) TIMING Report ###################" > timing_tt_min.rpt -report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt >> timing_tt_min.rpt -report_checks -group_count 100 -path_delay min -path_group bist_clk -corner tt >> timing_tt_min.rpt -report_checks -group_count 100 -path_delay min -path_group mem_clk_a -corner tt >> timing_tt_min.rpt -report_checks -group_count 100 -path_delay min -path_group mem_clk_b -corner tt >> timing_tt_min.rpt -report_checks -path_delay min -corner tt >> timing_tt_min.rpt - -report_checks -path_delay min - -#exit
diff --git a/openlane/yifive/base.sdc b/openlane/yifive/base.sdc deleted file mode 100644 index 375538d..0000000 --- a/openlane/yifive/base.sdc +++ /dev/null
@@ -1,321 +0,0 @@ -############################################################################### -# Timing Constraints -############################################################################### -create_clock -name core_clk -period 20.0000 [get_ports {core_clk}] -create_clock -name rtc_clk -period 40.0000 [get_ports {rtc_clk}] -create_clock -name wb_clk -period 10.0000 [get_ports {wb_clk}] - -create_generated_clock -name sram0_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {tcm sram clock0} [get_ports sram0_clk0] -create_generated_clock -name sram0_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {tcm sram clock1} [get_ports sram0_clk1] - -create_generated_clock -name icache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache clock0} [get_ports icache_mem_clk0] -create_generated_clock -name icache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {icache clock1} [get_ports icache_mem_clk1] - -create_generated_clock -name dcache_mem_clk0 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache clock0} [get_ports dcache_mem_clk0] -create_generated_clock -name dcache_mem_clk1 -add -source [get_ports {core_clk}] -master_clock [get_clocks core_clk] -divide_by 1 -comment {dcache clock1} [get_ports dcache_mem_clk1] - -set_clock_transition 0.1500 [all_clocks] -set_clock_uncertainty -setup 0.2500 [all_clocks] -set_clock_uncertainty -hold 0.2500 [all_clocks] - -set_propagated_clock [all_clocks] - - -set ::env(SYNTH_TIMING_DERATE) 0.05 -puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %" -set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}] -set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}] - -set_clock_groups -name async_clock -asynchronous \ - -group [get_clocks {core_clk sram0_clk0 sram0_clk1 icache_mem_clk0 icache_mem_clk1 dcache_mem_clk0 dcache_mem_clk1} ]\ - -group [get_clocks {rtc_clk}]\ - -group [get_clocks {wb_clk}] -comment {Async Clock group} - -### ClkSkew Adjust -set_case_analysis 0 [get_ports {cfg_cska_riscv[0]}] -set_case_analysis 0 [get_ports {cfg_cska_riscv[1]}] -set_case_analysis 0 [get_ports {cfg_cska_riscv[2]}] -set_case_analysis 0 [get_ports {cfg_cska_riscv[3]}] - - -set_max_delay 3.5 -from [get_ports {wbd_clk_int}] -set_max_delay 2 -to [get_ports {wbd_clk_riscv}] -set_max_delay 3.5 -from wbd_clk_int -to wbd_clk_riscv - -#TCM Memory -set_input_delay -max 6.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_dout0[*]}] -set_input_delay -min 3.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_dout0[*]}] - -set_input_delay -max 6.0000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_dout1[*]}] -set_input_delay -min 3.0000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_dout1[*]}] - -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_addr1[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_csb1}] - -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_addr1[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk1}] -add_delay [get_ports {sram0_csb1}] - -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_addr0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_csb0}] -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_din0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_web0}] -set_output_delay -max 4.5000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_wmask0[*]}] - -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_addr0[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_csb0}] -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_din0[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_web0}] -set_output_delay -min 2.0000 -clock [get_clocks {sram0_clk0}] -add_delay [get_ports {sram0_wmask0[*]}] - -#icache memory -set_input_delay -max 6.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_dout1[*]}] -set_input_delay -min 3.0000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_dout1[*]}] - -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_addr1[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_csb1}] - -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_addr1[*]}] -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk1}] -add_delay [get_ports {icache_mem_csb1}] - -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}] -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}] -set_output_delay -max 4.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}] - -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_addr0[*]}] -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_csb0}] -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_din0[*]}] -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_web0}] -set_output_delay -min -0.5000 -clock [get_clocks {icache_mem_clk0}] -add_delay [get_ports {icache_mem_wmask0[*]}] - -#dcache memory -set_input_delay -max 6.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_dout0[*]}] -set_input_delay -min 3.0000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_dout0[*]}] - -set_input_delay -max 6.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_dout1[*]}] -set_input_delay -min 3.0000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_dout1[*]}] - -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}] - -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_addr1[*]}] -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk1}] -add_delay [get_ports {dcache_mem_csb1}] - -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}] -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}] -set_output_delay -max 4.5000 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}] - -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_addr0[*]}] -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_csb0}] -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_din0[*]}] -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_web0}] -set_output_delay -min -0.500 -clock [get_clocks {dcache_mem_clk0}] -add_delay [get_ports {dcache_mem_wmask0[*]}] - -set_input_delay -max 5.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wb_rst_n}] - -#Wishbone DMEM -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_err_i}] - -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_ack_i}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_i[*]}] - -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}] - -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_adr_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_dat_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_sel_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_stb_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dmem_we_o}] - -#Wishbone icache -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_lack_i}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_ack_i}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_dat_i[*]}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_err_i}] - -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_lack_i}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_ack_i}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_dat_i[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_dat_i[*]}] - -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_adr_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_sel_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_bl_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_bry_o}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_stb_o}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_we_o}] - -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_adr_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_sel_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_bl_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_bry_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_stb_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_icache_we_o}] - -#Wishbone dcache -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_lack_i}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_ack_i}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_i[*]}] -set_input_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_err_i}] - -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_lack_i}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_ack_i}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_i[*]}] -set_input_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_i[*]}] - -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_adr_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_sel_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_bl_o[*]}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_bry_o}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_stb_o}] -set_output_delay -max 4.5000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_we_o}] - -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_adr_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_dat_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_sel_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_bl_o[*]}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_bry_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_stb_o}] -set_output_delay -min 2.0000 -clock [get_clocks {wb_clk}] -add_delay [get_ports {wbd_dcache_we_o}] - -set_false_path\ - -from [get_ports {soft_irq}] -set_false_path\ - -to [list [get_ports {riscv_debug[0]}]\ - [get_ports {riscv_debug[10]}]\ - [get_ports {riscv_debug[11]}]\ - [get_ports {riscv_debug[12]}]\ - [get_ports {riscv_debug[13]}]\ - [get_ports {riscv_debug[14]}]\ - [get_ports {riscv_debug[15]}]\ - [get_ports {riscv_debug[16]}]\ - [get_ports {riscv_debug[17]}]\ - [get_ports {riscv_debug[18]}]\ - [get_ports {riscv_debug[19]}]\ - [get_ports {riscv_debug[1]}]\ - [get_ports {riscv_debug[20]}]\ - [get_ports {riscv_debug[21]}]\ - [get_ports {riscv_debug[22]}]\ - [get_ports {riscv_debug[23]}]\ - [get_ports {riscv_debug[24]}]\ - [get_ports {riscv_debug[25]}]\ - [get_ports {riscv_debug[26]}]\ - [get_ports {riscv_debug[27]}]\ - [get_ports {riscv_debug[28]}]\ - [get_ports {riscv_debug[29]}]\ - [get_ports {riscv_debug[2]}]\ - [get_ports {riscv_debug[30]}]\ - [get_ports {riscv_debug[31]}]\ - [get_ports {riscv_debug[32]}]\ - [get_ports {riscv_debug[33]}]\ - [get_ports {riscv_debug[34]}]\ - [get_ports {riscv_debug[35]}]\ - [get_ports {riscv_debug[36]}]\ - [get_ports {riscv_debug[37]}]\ - [get_ports {riscv_debug[38]}]\ - [get_ports {riscv_debug[39]}]\ - [get_ports {riscv_debug[3]}]\ - [get_ports {riscv_debug[40]}]\ - [get_ports {riscv_debug[41]}]\ - [get_ports {riscv_debug[42]}]\ - [get_ports {riscv_debug[43]}]\ - [get_ports {riscv_debug[44]}]\ - [get_ports {riscv_debug[45]}]\ - [get_ports {riscv_debug[46]}]\ - [get_ports {riscv_debug[47]}]\ - [get_ports {riscv_debug[48]}]\ - [get_ports {riscv_debug[49]}]\ - [get_ports {riscv_debug[4]}]\ - [get_ports {riscv_debug[50]}]\ - [get_ports {riscv_debug[51]}]\ - [get_ports {riscv_debug[52]}]\ - [get_ports {riscv_debug[53]}]\ - [get_ports {riscv_debug[54]}]\ - [get_ports {riscv_debug[55]}]\ - [get_ports {riscv_debug[56]}]\ - [get_ports {riscv_debug[57]}]\ - [get_ports {riscv_debug[58]}]\ - [get_ports {riscv_debug[59]}]\ - [get_ports {riscv_debug[5]}]\ - [get_ports {riscv_debug[60]}]\ - [get_ports {riscv_debug[61]}]\ - [get_ports {riscv_debug[62]}]\ - [get_ports {riscv_debug[63]}]\ - [get_ports {riscv_debug[6]}]\ - [get_ports {riscv_debug[7]}]\ - [get_ports {riscv_debug[8]}]\ - [get_ports {riscv_debug[9]}]] - -set_false_path -from [get_ports {fuse_mhartid[0]}] -set_false_path -from [get_ports {fuse_mhartid[10]}] -set_false_path -from [get_ports {fuse_mhartid[11]}] -set_false_path -from [get_ports {fuse_mhartid[12]}] -set_false_path -from [get_ports {fuse_mhartid[13]}] -set_false_path -from [get_ports {fuse_mhartid[14]}] -set_false_path -from [get_ports {fuse_mhartid[15]}] -set_false_path -from [get_ports {fuse_mhartid[16]}] -set_false_path -from [get_ports {fuse_mhartid[17]}] -set_false_path -from [get_ports {fuse_mhartid[18]}] -set_false_path -from [get_ports {fuse_mhartid[19]}] -set_false_path -from [get_ports {fuse_mhartid[1]}] -set_false_path -from [get_ports {fuse_mhartid[20]}] -set_false_path -from [get_ports {fuse_mhartid[21]}] -set_false_path -from [get_ports {fuse_mhartid[22]}] -set_false_path -from [get_ports {fuse_mhartid[23]}] -set_false_path -from [get_ports {fuse_mhartid[24]}] -set_false_path -from [get_ports {fuse_mhartid[25]}] -set_false_path -from [get_ports {fuse_mhartid[26]}] -set_false_path -from [get_ports {fuse_mhartid[27]}] -set_false_path -from [get_ports {fuse_mhartid[28]}] -set_false_path -from [get_ports {fuse_mhartid[29]}] -set_false_path -from [get_ports {fuse_mhartid[2]}] -set_false_path -from [get_ports {fuse_mhartid[30]}] -set_false_path -from [get_ports {fuse_mhartid[31]}] -set_false_path -from [get_ports {fuse_mhartid[3]}] -set_false_path -from [get_ports {fuse_mhartid[4]}] -set_false_path -from [get_ports {fuse_mhartid[5]}] -set_false_path -from [get_ports {fuse_mhartid[6]}] -set_false_path -from [get_ports {fuse_mhartid[7]}] -set_false_path -from [get_ports {fuse_mhartid[8]}] -set_false_path -from [get_ports {fuse_mhartid[9]}] -set_false_path -from [get_ports {irq_lines[0]}] -set_false_path -from [get_ports {irq_lines[10]}] -set_false_path -from [get_ports {irq_lines[11]}] -set_false_path -from [get_ports {irq_lines[12]}] -set_false_path -from [get_ports {irq_lines[13]}] -set_false_path -from [get_ports {irq_lines[14]}] -set_false_path -from [get_ports {irq_lines[15]}] -set_false_path -from [get_ports {irq_lines[1]}] -set_false_path -from [get_ports {irq_lines[2]}] -set_false_path -from [get_ports {irq_lines[3]}] -set_false_path -from [get_ports {irq_lines[4]}] -set_false_path -from [get_ports {irq_lines[5]}] -set_false_path -from [get_ports {irq_lines[6]}] -set_false_path -from [get_ports {irq_lines[7]}] -set_false_path -from [get_ports {irq_lines[8]}] -set_false_path -from [get_ports {irq_lines[9]}] -set_false_path -from [get_ports {pwrup_rst_n}] -set_false_path -from [get_ports {rst_n}] -set_false_path -from [get_ports {soft_irq}] -############################################################################### -# Environment -############################################################################### -set_driving_cell -lib_cell sky130_fd_sc_hd__inv_8 -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs] -set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0] -puts "\[INFO\]: Setting load to: $cap_load" -set_load $cap_load [all_outputs] - -############################################################################### -# Design Rules -###############################################################################
diff --git a/openlane/yifive/config.tcl b/openlane/yifive/config.tcl deleted file mode 100755 index 1f117a8..0000000 --- a/openlane/yifive/config.tcl +++ /dev/null
@@ -1,145 +0,0 @@ -# SPDX-FileCopyrightText: 2021 , Dinesh Annayya -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 -# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> - -# Global -# ------ - -set script_dir [file dirname [file normalize [info script]]] -# Name -set ::env(DESIGN_NAME) ycr1_top_wb - -set ::env(DESIGN_IS_CORE) "0" -set ::env(FP_PDN_CORE_RING) "0" - -# Timing configuration -set ::env(CLOCK_PERIOD) "10" -set ::env(CLOCK_PORT) "wb_clk core_clk" - -set ::env(SYNTH_MAX_FANOUT) 4 - -## CTS BUFFER -set ::env(CTS_CLK_BUFFER_LIST) "sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_8" -set ::env(CTS_SINK_CLUSTERING_SIZE) "16" -set ::env(CLOCK_BUFFER_FANOUT) "8" - -# Sources -# ------- - -# Local sources + no2usb sources -set ::env(VERILOG_FILES) "\ - $script_dir/../../verilog/rtl/clk_skew_adjust/src/clk_skew_adjust.gv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_top.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_core_top.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_dm.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_tapc_synchronizer.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_clk_ctrl.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_scu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_tapc.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_tapc_shift_reg.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/ycr1_dmi.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/primitives/ycr1_reset_cells.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_ifu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_idu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_exu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_mprf.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_csr.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_ialu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_mul.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_div.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_lsu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_hdu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_pipe_tdu.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/core/pipeline/ycr1_ipic.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_dmem_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_imem_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_icache_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_dcache_router.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_tcm.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_timer.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_top_wb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_dmem_wb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_imem_wb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/top/ycr1_intf.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_top.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_app_fsm.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/icache_tag_fifo.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_tag_fifo.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/cache/src/core/dcache_top.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr1_async_wbb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ycr1_arb.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/sync_fifo.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/async_fifo.sv \ - $script_dir/../../verilog/rtl/yifive/ycr1c/src/lib/ctech_cells.sv \ - " - -set ::env(VERILOG_INCLUDE_DIRS) [glob $script_dir/../../verilog/rtl/yifive/ycr1c/src/includes ] -set ::env(SYNTH_READ_BLACKBOX_LIB) 1 -set ::env(SYNTH_DEFINES) [list SYNTHESIS ] - -set ::env(SDC_FILE) "$script_dir/base.sdc" -set ::env(BASE_SDC_FILE) "$script_dir/base.sdc" -#set ::env(SYNTH_DEFINES) [list SCR1_DBG_EN ] - -set ::env(LEC_ENABLE) 0 - -set ::env(VDD_PIN) [list {vccd1}] -set ::env(GND_PIN) [list {vssd1}] - - -# -------- -# Floorplanning -# ------------- - -set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg - -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) [list 0.0 0.0 725.0 1550.0] - - -# If you're going to use multiple power domains, then keep this disabled. -set ::env(RUN_CVC) 0 - -#set ::env(PDN_CFG) $script_dir/pdn.tcl - - -set ::env(PL_TIME_DRIVEN) 1 -set ::env(PL_TARGET_DENSITY) "0.35" -set ::env(FP_CORE_UTIL) "50" - -# helps in anteena fix -set ::env(USE_ARC_ANTENNA_CHECK) "0" - -set ::env(FP_IO_VEXTEND) 4 -set ::env(FP_IO_HEXTEND) 4 - -set ::env(FP_PDN_VPITCH) 100 -set ::env(FP_PDN_HPITCH) 100 -set ::env(FP_PDN_VWIDTH) 3 -set ::env(FP_PDN_HWIDTH) 3 - -set ::env(GLB_RT_MAXLAYER) 6 -set ::env(GLB_RT_MAX_DIODE_INS_ITERS) 10 -set ::env(DIODE_INSERTION_STRATEGY) 4 - - -set ::env(QUIT_ON_TIMING_VIOLATIONS) "0" -set ::env(QUIT_ON_MAGIC_DRC) "1" -set ::env(QUIT_ON_LVS_ERROR) "0" -set ::env(QUIT_ON_SLEW_VIOLATIONS) "0" - -#Need to cross-check why global timing opimization creating setup vio with hugh hold fix -set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) "0" -
diff --git a/openlane/yifive/interactive.tcl b/openlane/yifive/interactive.tcl deleted file mode 100644 index b44b517..0000000 --- a/openlane/yifive/interactive.tcl +++ /dev/null
@@ -1,219 +0,0 @@ -#!/usr/bin/tclsh -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# Copyright 2020 Efabless Corporation -# Copyright 2020 Sylvain Munaut -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -package require openlane; - - -proc run_placement_step {args} { - # set pdndef_dirname [file dirname $::env(pdn_tmp_file_tag).def] - # set pdndef [lindex [glob $pdndef_dirname/*pdn*] 0] - # set_def $pdndef - if { ! [ info exists ::env(PLACEMENT_CURRENT_DEF) ] } { - set ::env(PLACEMENT_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(PLACEMENT_CURRENT_DEF) - } - - run_placement -} - -proc run_cts_step {args} { - # set_def $::env(opendp_result_file_tag).def - if { ! [ info exists ::env(CTS_CURRENT_DEF) ] } { - set ::env(CTS_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(CTS_CURRENT_DEF) - } - - run_cts - run_resizer_timing -} - -proc run_routing_step {args} { - # set resizerdef_dirname [file dirname $::env(resizer_tmp_file_tag)_timing.def] - # set resizerdef [lindex [glob $resizerdef_dirname/*resizer*] 0] - # set_def $resizerdef - if { ! [ info exists ::env(ROUTING_CURRENT_DEF) ] } { - set ::env(ROUTING_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(ROUTING_CURRENT_DEF) - } - run_routing -} - -proc run_diode_insertion_2_5_step {args} { - # set_def $::env(tritonRoute_result_file_tag).def - if { ! [ info exists ::env(DIODE_INSERTION_CURRENT_DEF) ] } { - set ::env(DIODE_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(DIODE_INSERTION_CURRENT_DEF) - } - if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } { - run_antenna_check - heal_antenna_violators; # modifies the routed DEF - } - -} - -proc run_power_pins_insertion_step {args} { - # set_def $::env(tritonRoute_result_file_tag).def - if { ! [ info exists ::env(POWER_PINS_INSERTION_CURRENT_DEF) ] } { - set ::env(POWER_PINS_INSERTION_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(POWER_PINS_INSERTION_CURRENT_DEF) - } - if { $::env(LVS_INSERT_POWER_PINS) } { - write_powered_verilog - set_netlist $::env(lvs_result_file_tag).powered.v - } - -} - -proc run_lvs_step {{ lvs_enabled 1 }} { - # set_def $::env(tritonRoute_result_file_tag).def - if { ! [ info exists ::env(LVS_CURRENT_DEF) ] } { - set ::env(LVS_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(LVS_CURRENT_DEF) - } - if { $lvs_enabled } { - run_magic_spice_export - run_lvs; # requires run_magic_spice_export - } - -} - -proc run_drc_step {{ drc_enabled 1 }} { - if { ! [ info exists ::env(DRC_CURRENT_DEF) ] } { - set ::env(DRC_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(DRC_CURRENT_DEF) - } - if { $drc_enabled } { - run_magic_drc - run_klayout_drc - } -} - -proc run_antenna_check_step {{ antenna_check_enabled 1 }} { - if { ! [ info exists ::env(ANTENNA_CHECK_CURRENT_DEF) ] } { - set ::env(ANTENNA_CHECK_CURRENT_DEF) $::env(CURRENT_DEF) - } else { - set ::env(CURRENT_DEF) $::env(ANTENNA_CHECK_CURRENT_DEF) - } - if { $antenna_check_enabled } { - run_antenna_check - } -} - -proc run_flow {args} { - set script_dir [file dirname [file normalize [info script]]] - - set options { - {-design required} - {-save_path optional} - {-no_lvs optional} - {-no_drc optional} - {-no_antennacheck optional} - } - set flags {-save} - parse_key_args "run_flow" args arg_values $options flags_map $flags -no_consume - - prep {*}$args - - set LVS_ENABLED 1 - set DRC_ENABLED 0 - set ANTENNACHECK_ENABLED 1 - - set steps [dict create "synthesis" {run_synthesis "" } \ - "floorplan" {run_floorplan ""} \ - "placement" {run_placement_step ""} \ - "cts" {run_cts_step ""} \ - "routing" {run_routing_step ""}\ - "diode_insertion" {run_diode_insertion_2_5_step ""} \ - "power_pins_insertion" {run_power_pins_insertion_step ""} \ - "gds_magic" {run_magic ""} \ - "gds_drc_klayout" {run_klayout ""} \ - "gds_xor_klayout" {run_klayout_gds_xor ""} \ - "lvs" "run_lvs_step $LVS_ENABLED" \ - "drc" "run_drc_step $DRC_ENABLED" \ - "antenna_check" "run_antenna_check_step $ANTENNACHECK_ENABLED" \ - "cvc" {run_lef_cvc} - ] - - set_if_unset arg_values(-to) "cvc"; - - if { [info exists ::env(CURRENT_STEP) ] } { - puts "\[INFO\]:Picking up where last execution left off" - puts [format "\[INFO\]:Current stage is %s " $::env(CURRENT_STEP)] - } else { - set ::env(CURRENT_STEP) "synthesis"; - } - set_if_unset arg_values(-from) $::env(CURRENT_STEP); - set exe 0; - dict for {step_name step_exe} $steps { - if { [ string equal $arg_values(-from) $step_name ] } { - set exe 1; - } - - if { $exe } { - # For when it fails - set ::env(CURRENT_STEP) $step_name - [lindex $step_exe 0] [lindex $step_exe 1] ; - } - - if { [ string equal $arg_values(-to) $step_name ] } { - set exe 0: - break; - } - - } - - # for when it resumes - set steps_as_list [dict keys $steps] - set next_idx [expr [lsearch $steps_as_list $::env(CURRENT_STEP)] + 1] - set ::env(CURRENT_STEP) [lindex $steps_as_list $next_idx] - - if { [info exists flags_map(-save) ] } { - if { ! [info exists arg_values(-save_path)] } { - set arg_values(-save_path) "" - } - save_views -lef_path $::env(magic_result_file_tag).lef \ - -def_path $::env(CURRENT_DEF) \ - -gds_path $::env(magic_result_file_tag).gds \ - -mag_path $::env(magic_result_file_tag).mag \ - -maglef_path $::env(magic_result_file_tag).lef.mag \ - -spice_path $::env(magic_result_file_tag).spice \ - -spef_path $::env(CURRENT_SPEF) \ - -verilog_path $::env(CURRENT_NETLIST) \ - -save_path $arg_values(-save_path) \ - -tag $::env(RUN_TAG) - } - - - calc_total_runtime - save_state - generate_final_summary_report - - check_timing_violations - - puts_success "Flow Completed Without Fatal Errors." - -} - -run_flow {*}$argv
diff --git a/openlane/yifive/pdn.tcl b/openlane/yifive/pdn.tcl deleted file mode 100644 index 1fe689b..0000000 --- a/openlane/yifive/pdn.tcl +++ /dev/null
@@ -1,49 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -# Power nets -set ::power_nets $::env(VDD_PIN) -set ::ground_nets $::env(GND_PIN) - -set ::macro_blockage_layer_list "li1 met1 met2 met3 met4 met5" - -pdngen::specify_grid stdcell { - name grid - rails { - met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0} - } - straps { - met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)} - met5 {width 1.6 pitch $::env(FP_PDN_HPITCH) offset $::env(FP_PDN_HOFFSET)} - } - connect {{met1 met4} {met4 met5}} -} - -pdngen::specify_grid macro { - power_pins "VPWR" - ground_pins "VGND" - blockages "li1 met1 met2 met3 met4" - straps { - } - connect {{met4_PIN_ver met5}} -} - -set ::halo 5 - -# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area -set ::rails_start_with "POWER" ; - -# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area -set ::stripes_start_with "POWER" ;
diff --git a/openlane/yifive/pin_order.cfg b/openlane/yifive/pin_order.cfg deleted file mode 100644 index e168c5f..0000000 --- a/openlane/yifive/pin_order.cfg +++ /dev/null
@@ -1,796 +0,0 @@ -#BUS_SORT - -#MANUAL_PLACE - - -#E -soft_irq 0500 0 2 -irq_lines\[15\] -irq_lines\[14\] -irq_lines\[13\] -irq_lines\[12\] -irq_lines\[11\] -irq_lines\[10\] -irq_lines\[9\] -irq_lines\[8\] -irq_lines\[7\] -irq_lines\[6\] -irq_lines\[5\] -irq_lines\[4\] -irq_lines\[3\] -irq_lines\[2\] -irq_lines\[1\] -irq_lines\[0\] -fuse_mhartid\[31\] -fuse_mhartid\[30\] -fuse_mhartid\[29\] -fuse_mhartid\[28\] -fuse_mhartid\[27\] -fuse_mhartid\[26\] -fuse_mhartid\[25\] -fuse_mhartid\[24\] -fuse_mhartid\[23\] -fuse_mhartid\[22\] -fuse_mhartid\[21\] -fuse_mhartid\[20\] -fuse_mhartid\[19\] -fuse_mhartid\[18\] -fuse_mhartid\[17\] -fuse_mhartid\[16\] -fuse_mhartid\[15\] -fuse_mhartid\[14\] -fuse_mhartid\[13\] -fuse_mhartid\[12\] -fuse_mhartid\[11\] -fuse_mhartid\[10\] -fuse_mhartid\[9\] -fuse_mhartid\[8\] -fuse_mhartid\[7\] -fuse_mhartid\[6\] -fuse_mhartid\[5\] -fuse_mhartid\[4\] -fuse_mhartid\[3\] -fuse_mhartid\[2\] -fuse_mhartid\[1\] -fuse_mhartid\[0\] - -cfg_cska_riscv\[3\] -cfg_cska_riscv\[2\] -cfg_cska_riscv\[1\] -cfg_cska_riscv\[0\] -wbd_clk_int -wbd_clk_riscv -wb_clk - - -wbd_dmem_stb_o 0700 0 -wbd_dmem_we_o -wbd_dmem_adr_o\[31\] -wbd_dmem_adr_o\[30\] -wbd_dmem_adr_o\[29\] -wbd_dmem_adr_o\[28\] -wbd_dmem_adr_o\[27\] -wbd_dmem_adr_o\[26\] -wbd_dmem_adr_o\[25\] -wbd_dmem_adr_o\[24\] -wbd_dmem_adr_o\[23\] -wbd_dmem_adr_o\[22\] -wbd_dmem_adr_o\[21\] -wbd_dmem_adr_o\[20\] -wbd_dmem_adr_o\[19\] -wbd_dmem_adr_o\[18\] -wbd_dmem_adr_o\[17\] -wbd_dmem_adr_o\[16\] -wbd_dmem_adr_o\[15\] -wbd_dmem_adr_o\[14\] -wbd_dmem_adr_o\[13\] -wbd_dmem_adr_o\[12\] -wbd_dmem_adr_o\[11\] -wbd_dmem_adr_o\[10\] -wbd_dmem_adr_o\[9\] -wbd_dmem_adr_o\[8\] -wbd_dmem_adr_o\[7\] -wbd_dmem_adr_o\[6\] -wbd_dmem_adr_o\[5\] -wbd_dmem_adr_o\[4\] -wbd_dmem_adr_o\[3\] -wbd_dmem_adr_o\[2\] -wbd_dmem_adr_o\[1\] -wbd_dmem_adr_o\[0\] -wbd_dmem_sel_o\[3\] -wbd_dmem_sel_o\[2\] -wbd_dmem_sel_o\[1\] -wbd_dmem_sel_o\[0\] -wbd_dmem_dat_o\[31\] -wbd_dmem_dat_o\[30\] -wbd_dmem_dat_o\[29\] -wbd_dmem_dat_o\[28\] -wbd_dmem_dat_o\[27\] -wbd_dmem_dat_o\[26\] -wbd_dmem_dat_o\[25\] -wbd_dmem_dat_o\[24\] -wbd_dmem_dat_o\[23\] -wbd_dmem_dat_o\[22\] -wbd_dmem_dat_o\[21\] -wbd_dmem_dat_o\[20\] -wbd_dmem_dat_o\[19\] -wbd_dmem_dat_o\[18\] -wbd_dmem_dat_o\[17\] -wbd_dmem_dat_o\[16\] -wbd_dmem_dat_o\[15\] -wbd_dmem_dat_o\[14\] -wbd_dmem_dat_o\[13\] -wbd_dmem_dat_o\[12\] -wbd_dmem_dat_o\[11\] -wbd_dmem_dat_o\[10\] -wbd_dmem_dat_o\[9\] -wbd_dmem_dat_o\[8\] -wbd_dmem_dat_o\[7\] -wbd_dmem_dat_o\[6\] -wbd_dmem_dat_o\[5\] -wbd_dmem_dat_o\[4\] -wbd_dmem_dat_o\[3\] -wbd_dmem_dat_o\[2\] -wbd_dmem_dat_o\[1\] -wbd_dmem_dat_o\[0\] -wbd_dmem_dat_i\[31\] -wbd_dmem_dat_i\[30\] -wbd_dmem_dat_i\[29\] -wbd_dmem_dat_i\[28\] -wbd_dmem_dat_i\[27\] -wbd_dmem_dat_i\[26\] -wbd_dmem_dat_i\[25\] -wbd_dmem_dat_i\[24\] -wbd_dmem_dat_i\[23\] -wbd_dmem_dat_i\[22\] -wbd_dmem_dat_i\[21\] -wbd_dmem_dat_i\[20\] -wbd_dmem_dat_i\[19\] -wbd_dmem_dat_i\[18\] -wbd_dmem_dat_i\[17\] -wbd_dmem_dat_i\[16\] -wbd_dmem_dat_i\[15\] -wbd_dmem_dat_i\[14\] -wbd_dmem_dat_i\[13\] -wbd_dmem_dat_i\[12\] -wbd_dmem_dat_i\[11\] -wbd_dmem_dat_i\[10\] -wbd_dmem_dat_i\[9\] -wbd_dmem_dat_i\[8\] -wbd_dmem_dat_i\[7\] -wbd_dmem_dat_i\[6\] -wbd_dmem_dat_i\[5\] -wbd_dmem_dat_i\[4\] -wbd_dmem_dat_i\[3\] -wbd_dmem_dat_i\[2\] -wbd_dmem_dat_i\[1\] -wbd_dmem_dat_i\[0\] -wbd_dmem_ack_i -wbd_dmem_err_i - -wb_dcache_stb_o 0900 0 2 -wb_dcache_we_o -wb_dcache_adr_o\[31\] -wb_dcache_adr_o\[30\] -wb_dcache_adr_o\[29\] -wb_dcache_adr_o\[28\] -wb_dcache_adr_o\[27\] -wb_dcache_adr_o\[26\] -wb_dcache_adr_o\[25\] -wb_dcache_adr_o\[24\] -wb_dcache_adr_o\[23\] -wb_dcache_adr_o\[22\] -wb_dcache_adr_o\[21\] -wb_dcache_adr_o\[20\] -wb_dcache_adr_o\[19\] -wb_dcache_adr_o\[18\] -wb_dcache_adr_o\[17\] -wb_dcache_adr_o\[16\] -wb_dcache_adr_o\[15\] -wb_dcache_adr_o\[14\] -wb_dcache_adr_o\[13\] -wb_dcache_adr_o\[12\] -wb_dcache_adr_o\[11\] -wb_dcache_adr_o\[10\] -wb_dcache_adr_o\[9\] -wb_dcache_adr_o\[8\] -wb_dcache_adr_o\[7\] -wb_dcache_adr_o\[6\] -wb_dcache_adr_o\[5\] -wb_dcache_adr_o\[4\] -wb_dcache_adr_o\[3\] -wb_dcache_adr_o\[2\] -wb_dcache_adr_o\[1\] -wb_dcache_adr_o\[0\] -wb_dcache_sel_o\[3\] -wb_dcache_sel_o\[2\] -wb_dcache_sel_o\[1\] -wb_dcache_sel_o\[0\] -wb_dcache_bl_o\[9\] -wb_dcache_bl_o\[8\] -wb_dcache_bl_o\[7\] -wb_dcache_bl_o\[6\] -wb_dcache_bl_o\[5\] -wb_dcache_bl_o\[4\] -wb_dcache_bl_o\[3\] -wb_dcache_bl_o\[2\] -wb_dcache_bl_o\[1\] -wb_dcache_bl_o\[0\] -wb_dcache_bry_o -wb_dcache_dat_o\[31\] -wb_dcache_dat_o\[30\] -wb_dcache_dat_o\[29\] -wb_dcache_dat_o\[28\] -wb_dcache_dat_o\[27\] -wb_dcache_dat_o\[26\] -wb_dcache_dat_o\[25\] -wb_dcache_dat_o\[24\] -wb_dcache_dat_o\[23\] -wb_dcache_dat_o\[22\] -wb_dcache_dat_o\[21\] -wb_dcache_dat_o\[20\] -wb_dcache_dat_o\[19\] -wb_dcache_dat_o\[18\] -wb_dcache_dat_o\[17\] -wb_dcache_dat_o\[16\] -wb_dcache_dat_o\[15\] -wb_dcache_dat_o\[14\] -wb_dcache_dat_o\[13\] -wb_dcache_dat_o\[12\] -wb_dcache_dat_o\[11\] -wb_dcache_dat_o\[10\] -wb_dcache_dat_o\[9\] -wb_dcache_dat_o\[8\] -wb_dcache_dat_o\[7\] -wb_dcache_dat_o\[6\] -wb_dcache_dat_o\[5\] -wb_dcache_dat_o\[4\] -wb_dcache_dat_o\[3\] -wb_dcache_dat_o\[2\] -wb_dcache_dat_o\[1\] -wb_dcache_dat_o\[0\] -wb_dcache_dat_i\[31\] -wb_dcache_dat_i\[30\] -wb_dcache_dat_i\[29\] -wb_dcache_dat_i\[28\] -wb_dcache_dat_i\[27\] -wb_dcache_dat_i\[26\] -wb_dcache_dat_i\[25\] -wb_dcache_dat_i\[24\] -wb_dcache_dat_i\[23\] -wb_dcache_dat_i\[22\] -wb_dcache_dat_i\[21\] -wb_dcache_dat_i\[20\] -wb_dcache_dat_i\[19\] -wb_dcache_dat_i\[18\] -wb_dcache_dat_i\[17\] -wb_dcache_dat_i\[16\] -wb_dcache_dat_i\[15\] -wb_dcache_dat_i\[14\] -wb_dcache_dat_i\[13\] -wb_dcache_dat_i\[12\] -wb_dcache_dat_i\[11\] -wb_dcache_dat_i\[10\] -wb_dcache_dat_i\[9\] -wb_dcache_dat_i\[8\] -wb_dcache_dat_i\[7\] -wb_dcache_dat_i\[6\] -wb_dcache_dat_i\[5\] -wb_dcache_dat_i\[4\] -wb_dcache_dat_i\[3\] -wb_dcache_dat_i\[2\] -wb_dcache_dat_i\[1\] -wb_dcache_dat_i\[0\] -wb_dcache_ack_i -wb_dcache_lack_i -wb_dcache_err_i - -wb_icache_stb_o 1100 0 2 -wb_icache_we_o -wb_icache_adr_o\[31\] -wb_icache_adr_o\[30\] -wb_icache_adr_o\[29\] -wb_icache_adr_o\[28\] -wb_icache_adr_o\[27\] -wb_icache_adr_o\[26\] -wb_icache_adr_o\[25\] -wb_icache_adr_o\[24\] -wb_icache_adr_o\[23\] -wb_icache_adr_o\[22\] -wb_icache_adr_o\[21\] -wb_icache_adr_o\[20\] -wb_icache_adr_o\[19\] -wb_icache_adr_o\[18\] -wb_icache_adr_o\[17\] -wb_icache_adr_o\[16\] -wb_icache_adr_o\[15\] -wb_icache_adr_o\[14\] -wb_icache_adr_o\[13\] -wb_icache_adr_o\[12\] -wb_icache_adr_o\[11\] -wb_icache_adr_o\[10\] -wb_icache_adr_o\[9\] -wb_icache_adr_o\[8\] -wb_icache_adr_o\[7\] -wb_icache_adr_o\[6\] -wb_icache_adr_o\[5\] -wb_icache_adr_o\[4\] -wb_icache_adr_o\[3\] -wb_icache_adr_o\[2\] -wb_icache_adr_o\[1\] -wb_icache_adr_o\[0\] -wb_icache_sel_o\[3\] -wb_icache_sel_o\[2\] -wb_icache_sel_o\[1\] -wb_icache_sel_o\[0\] -wb_icache_bl_o\[9\] -wb_icache_bl_o\[8\] -wb_icache_bl_o\[7\] -wb_icache_bl_o\[6\] -wb_icache_bl_o\[5\] -wb_icache_bl_o\[4\] -wb_icache_bl_o\[3\] -wb_icache_bl_o\[2\] -wb_icache_bl_o\[1\] -wb_icache_bl_o\[0\] -wb_icache_bry_o -wb_icache_dat_i\[31\] -wb_icache_dat_i\[30\] -wb_icache_dat_i\[29\] -wb_icache_dat_i\[28\] -wb_icache_dat_i\[27\] -wb_icache_dat_i\[26\] -wb_icache_dat_i\[25\] -wb_icache_dat_i\[24\] -wb_icache_dat_i\[23\] -wb_icache_dat_i\[22\] -wb_icache_dat_i\[21\] -wb_icache_dat_i\[20\] -wb_icache_dat_i\[19\] -wb_icache_dat_i\[18\] -wb_icache_dat_i\[17\] -wb_icache_dat_i\[16\] -wb_icache_dat_i\[15\] -wb_icache_dat_i\[14\] -wb_icache_dat_i\[13\] -wb_icache_dat_i\[12\] -wb_icache_dat_i\[11\] -wb_icache_dat_i\[10\] -wb_icache_dat_i\[9\] -wb_icache_dat_i\[8\] -wb_icache_dat_i\[7\] -wb_icache_dat_i\[6\] -wb_icache_dat_i\[5\] -wb_icache_dat_i\[4\] -wb_icache_dat_i\[3\] -wb_icache_dat_i\[2\] -wb_icache_dat_i\[1\] -wb_icache_dat_i\[0\] -wb_icache_ack_i -wb_icache_lack_i -wb_icache_err_i - -#W -sram0_clk1 0000 0 2 -sram0_csb1 -sram0_addr1\[8\] -sram0_addr1\[7\] -sram0_addr1\[6\] -sram0_addr1\[5\] -sram0_addr1\[4\] -sram0_addr1\[3\] -sram0_addr1\[2\] -sram0_addr1\[1\] -sram0_addr1\[0\] - -sram0_dout1\[0\] 0200 0 2 -sram0_dout1\[1\] -sram0_dout1\[2\] -sram0_dout1\[3\] -sram0_dout1\[4\] -sram0_dout1\[5\] -sram0_dout1\[6\] -sram0_dout1\[7\] -sram0_dout1\[8\] -sram0_dout1\[9\] -sram0_dout1\[10\] -sram0_dout1\[11\] -sram0_dout1\[12\] -sram0_dout1\[13\] -sram0_dout1\[14\] -sram0_dout1\[15\] -sram0_dout1\[16\] -sram0_dout1\[17\] -sram0_dout1\[18\] -sram0_dout1\[19\] -sram0_dout1\[20\] -sram0_dout1\[21\] -sram0_dout1\[22\] -sram0_dout1\[23\] -sram0_dout1\[24\] -sram0_dout1\[25\] -sram0_dout1\[26\] -sram0_dout1\[27\] -sram0_dout1\[28\] -sram0_dout1\[29\] -sram0_dout1\[30\] -sram0_dout1\[31\] - -icache_mem_clk0 300 0 2 -icache_mem_csb0 -icache_mem_web0 -icache_mem_addr0\[0\] -icache_mem_addr0\[1\] -icache_mem_addr0\[2\] -icache_mem_addr0\[3\] -icache_mem_addr0\[4\] -icache_mem_addr0\[5\] -icache_mem_addr0\[6\] -icache_mem_addr0\[7\] -icache_mem_addr0\[8\] -icache_mem_wmask0\[0\] -icache_mem_wmask0\[1\] -icache_mem_wmask0\[2\] -icache_mem_wmask0\[3\] -icache_mem_din0\[0\] -icache_mem_din0\[1\] -icache_mem_din0\[2\] -icache_mem_din0\[3\] -icache_mem_din0\[4\] -icache_mem_din0\[5\] -icache_mem_din0\[6\] -icache_mem_din0\[7\] -icache_mem_din0\[8\] -icache_mem_din0\[9\] -icache_mem_din0\[10\] -icache_mem_din0\[11\] -icache_mem_din0\[12\] -icache_mem_din0\[13\] -icache_mem_din0\[14\] -icache_mem_din0\[15\] -icache_mem_din0\[16\] -icache_mem_din0\[17\] -icache_mem_din0\[18\] -icache_mem_din0\[19\] -icache_mem_din0\[20\] -icache_mem_din0\[21\] -icache_mem_din0\[22\] -icache_mem_din0\[23\] -icache_mem_din0\[24\] -icache_mem_din0\[25\] -icache_mem_din0\[26\] -icache_mem_din0\[27\] -icache_mem_din0\[28\] -icache_mem_din0\[29\] -icache_mem_din0\[30\] -icache_mem_din0\[31\] - -icache_mem_clk1 0400 0 2 -icache_mem_csb1 -icache_mem_addr1\[8\] -icache_mem_addr1\[7\] -icache_mem_addr1\[6\] -icache_mem_addr1\[5\] -icache_mem_addr1\[4\] -icache_mem_addr1\[3\] -icache_mem_addr1\[2\] -icache_mem_addr1\[1\] -icache_mem_addr1\[0\] - -icache_mem_dout1\[0\] 0450 0 2 -icache_mem_dout1\[1\] -icache_mem_dout1\[2\] -icache_mem_dout1\[3\] -icache_mem_dout1\[4\] -icache_mem_dout1\[5\] -icache_mem_dout1\[6\] -icache_mem_dout1\[7\] -icache_mem_dout1\[8\] -icache_mem_dout1\[9\] -icache_mem_dout1\[10\] -icache_mem_dout1\[11\] -icache_mem_dout1\[12\] -icache_mem_dout1\[13\] -icache_mem_dout1\[14\] -icache_mem_dout1\[15\] -icache_mem_dout1\[16\] -icache_mem_dout1\[17\] -icache_mem_dout1\[18\] -icache_mem_dout1\[19\] -icache_mem_dout1\[20\] -icache_mem_dout1\[21\] -icache_mem_dout1\[22\] -icache_mem_dout1\[23\] -icache_mem_dout1\[24\] -icache_mem_dout1\[25\] -icache_mem_dout1\[26\] -icache_mem_dout1\[27\] -icache_mem_dout1\[28\] -icache_mem_dout1\[29\] -icache_mem_dout1\[30\] -icache_mem_dout1\[31\] - -dcache_mem_clk0 850 0 2 -dcache_mem_csb0 -dcache_mem_web0 -dcache_mem_addr0\[0\] -dcache_mem_addr0\[1\] -dcache_mem_addr0\[2\] -dcache_mem_addr0\[3\] -dcache_mem_addr0\[4\] -dcache_mem_addr0\[5\] -dcache_mem_addr0\[6\] -dcache_mem_addr0\[7\] -dcache_mem_addr0\[8\] -dcache_mem_wmask0\[0\] -dcache_mem_wmask0\[1\] -dcache_mem_wmask0\[2\] -dcache_mem_wmask0\[3\] -dcache_mem_din0\[0\] -dcache_mem_din0\[1\] -dcache_mem_din0\[2\] -dcache_mem_din0\[3\] -dcache_mem_din0\[4\] -dcache_mem_din0\[5\] -dcache_mem_din0\[6\] -dcache_mem_din0\[7\] -dcache_mem_din0\[8\] -dcache_mem_din0\[9\] -dcache_mem_din0\[10\] -dcache_mem_din0\[11\] -dcache_mem_din0\[12\] -dcache_mem_din0\[13\] -dcache_mem_din0\[14\] -dcache_mem_din0\[15\] -dcache_mem_din0\[16\] -dcache_mem_din0\[17\] -dcache_mem_din0\[18\] -dcache_mem_din0\[19\] -dcache_mem_din0\[20\] -dcache_mem_din0\[21\] -dcache_mem_din0\[22\] -dcache_mem_din0\[23\] -dcache_mem_din0\[24\] -dcache_mem_din0\[25\] -dcache_mem_din0\[26\] -dcache_mem_din0\[27\] -dcache_mem_din0\[28\] -dcache_mem_din0\[29\] -dcache_mem_din0\[30\] -dcache_mem_din0\[31\] - - -dcache_mem_dout0\[0\] 950 0 2 -dcache_mem_dout0\[1\] -dcache_mem_dout0\[2\] -dcache_mem_dout0\[3\] -dcache_mem_dout0\[4\] -dcache_mem_dout0\[5\] -dcache_mem_dout0\[6\] -dcache_mem_dout0\[7\] -dcache_mem_dout0\[8\] -dcache_mem_dout0\[9\] -dcache_mem_dout0\[10\] -dcache_mem_dout0\[11\] -dcache_mem_dout0\[12\] -dcache_mem_dout0\[13\] -dcache_mem_dout0\[14\] -dcache_mem_dout0\[15\] -dcache_mem_dout0\[16\] -dcache_mem_dout0\[17\] -dcache_mem_dout0\[18\] -dcache_mem_dout0\[19\] -dcache_mem_dout0\[20\] -dcache_mem_dout0\[21\] -dcache_mem_dout0\[22\] -dcache_mem_dout0\[23\] -dcache_mem_dout0\[24\] -dcache_mem_dout0\[25\] -dcache_mem_dout0\[26\] -dcache_mem_dout0\[27\] -dcache_mem_dout0\[28\] -dcache_mem_dout0\[29\] -dcache_mem_dout0\[30\] -dcache_mem_dout0\[31\] - -dcache_mem_clk1 1000 0 2 -dcache_mem_csb1 -dcache_mem_addr1\[8\] -dcache_mem_addr1\[7\] -dcache_mem_addr1\[6\] -dcache_mem_addr1\[5\] -dcache_mem_addr1\[4\] -dcache_mem_addr1\[3\] -dcache_mem_addr1\[2\] -dcache_mem_addr1\[1\] -dcache_mem_addr1\[0\] - -dcache_mem_dout1\[0\] 1050 0 2 -dcache_mem_dout1\[1\] -dcache_mem_dout1\[2\] -dcache_mem_dout1\[3\] -dcache_mem_dout1\[4\] -dcache_mem_dout1\[5\] -dcache_mem_dout1\[6\] -dcache_mem_dout1\[7\] -dcache_mem_dout1\[8\] -dcache_mem_dout1\[9\] -dcache_mem_dout1\[10\] -dcache_mem_dout1\[11\] -dcache_mem_dout1\[12\] -dcache_mem_dout1\[13\] -dcache_mem_dout1\[14\] -dcache_mem_dout1\[15\] -dcache_mem_dout1\[16\] -dcache_mem_dout1\[17\] -dcache_mem_dout1\[18\] -dcache_mem_dout1\[19\] -dcache_mem_dout1\[20\] -dcache_mem_dout1\[21\] -dcache_mem_dout1\[22\] -dcache_mem_dout1\[23\] -dcache_mem_dout1\[24\] -dcache_mem_dout1\[25\] -dcache_mem_dout1\[26\] -dcache_mem_dout1\[27\] -dcache_mem_dout1\[28\] -dcache_mem_dout1\[29\] -dcache_mem_dout1\[30\] -dcache_mem_dout1\[31\] - -#S -sram0_clk0 0 0 2 -sram0_csb0 -sram0_web0 -sram0_addr0\[0\] -sram0_addr0\[1\] -sram0_addr0\[2\] -sram0_addr0\[3\] -sram0_addr0\[4\] -sram0_addr0\[5\] -sram0_addr0\[6\] -sram0_addr0\[7\] -sram0_addr0\[8\] -sram0_wmask0\[0\] -sram0_wmask0\[1\] -sram0_wmask0\[2\] -sram0_wmask0\[3\] -sram0_din0\[0\] -sram0_din0\[1\] -sram0_din0\[2\] -sram0_din0\[3\] -sram0_din0\[4\] -sram0_din0\[5\] -sram0_din0\[6\] -sram0_din0\[7\] -sram0_din0\[8\] -sram0_din0\[9\] -sram0_din0\[10\] -sram0_din0\[11\] -sram0_din0\[12\] -sram0_din0\[13\] -sram0_din0\[14\] -sram0_din0\[15\] -sram0_din0\[16\] -sram0_din0\[17\] -sram0_din0\[18\] -sram0_din0\[19\] -sram0_din0\[20\] -sram0_din0\[21\] -sram0_din0\[22\] -sram0_din0\[23\] -sram0_din0\[24\] -sram0_din0\[25\] -sram0_din0\[26\] -sram0_din0\[27\] -sram0_din0\[28\] -sram0_din0\[29\] -sram0_din0\[30\] -sram0_din0\[31\] - - -sram0_dout0\[0\] 0100 0 2 -sram0_dout0\[1\] -sram0_dout0\[2\] -sram0_dout0\[3\] -sram0_dout0\[4\] -sram0_dout0\[5\] -sram0_dout0\[6\] -sram0_dout0\[7\] -sram0_dout0\[8\] -sram0_dout0\[9\] -sram0_dout0\[10\] -sram0_dout0\[11\] -sram0_dout0\[12\] -sram0_dout0\[13\] -sram0_dout0\[14\] -sram0_dout0\[15\] -sram0_dout0\[16\] -sram0_dout0\[17\] -sram0_dout0\[18\] -sram0_dout0\[19\] -sram0_dout0\[20\] -sram0_dout0\[21\] -sram0_dout0\[22\] -sram0_dout0\[23\] -sram0_dout0\[24\] -sram0_dout0\[25\] -sram0_dout0\[26\] -sram0_dout0\[27\] -sram0_dout0\[28\] -sram0_dout0\[29\] -sram0_dout0\[30\] -sram0_dout0\[31\] - -riscv_debug\[0\] 300 0 2 -riscv_debug\[1\] -riscv_debug\[2\] -riscv_debug\[3\] -riscv_debug\[4\] -riscv_debug\[5\] -riscv_debug\[6\] -riscv_debug\[7\] -riscv_debug\[8\] -riscv_debug\[9\] -riscv_debug\[10\] -riscv_debug\[11\] -riscv_debug\[12\] -riscv_debug\[13\] -riscv_debug\[14\] -riscv_debug\[15\] -riscv_debug\[16\] -riscv_debug\[17\] -riscv_debug\[18\] -riscv_debug\[19\] -riscv_debug\[20\] -riscv_debug\[21\] -riscv_debug\[22\] -riscv_debug\[23\] -riscv_debug\[24\] -riscv_debug\[25\] -riscv_debug\[26\] -riscv_debug\[27\] -riscv_debug\[28\] -riscv_debug\[29\] -riscv_debug\[30\] -riscv_debug\[31\] -riscv_debug\[32\] -riscv_debug\[33\] -riscv_debug\[34\] -riscv_debug\[35\] -riscv_debug\[36\] -riscv_debug\[37\] -riscv_debug\[38\] -riscv_debug\[39\] -riscv_debug\[40\] -riscv_debug\[41\] -riscv_debug\[42\] -riscv_debug\[43\] -riscv_debug\[44\] -riscv_debug\[45\] -riscv_debug\[46\] -riscv_debug\[47\] -riscv_debug\[48\] -riscv_debug\[49\] -riscv_debug\[50\] -riscv_debug\[51\] -riscv_debug\[52\] -riscv_debug\[53\] -riscv_debug\[54\] -riscv_debug\[55\] -riscv_debug\[56\] -riscv_debug\[57\] -riscv_debug\[58\] -riscv_debug\[59\] -riscv_debug\[60\] -riscv_debug\[61\] -riscv_debug\[62\] -riscv_debug\[63\] - - -wb_rst_n 500 0 2 -pwrup_rst_n -rst_n -core_clk -rtc_clk -cpu_rst_n
diff --git a/openlane/yifive/sta.tcl b/openlane/yifive/sta.tcl deleted file mode 100644 index 8168d16..0000000 --- a/openlane/yifive/sta.tcl +++ /dev/null
@@ -1,95 +0,0 @@ -# SPDX-FileCopyrightText: 2021 , Dinesh Annayya -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 -# SPDX-FileContributor: Modified by Dinesh Annayya <dinesha@opencores.org> - -set ::env(LIB_FASTEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib" -set ::env(LIB_TYPICAL) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib" -set ::env(LIB_SLOWEST) "$::env(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib" -set ::env(CURRENT_NETLIST) ../user_project_wrapper/netlist/syntacore.v -set ::env(DESIGN_NAME) "scr1_top_wb" -set ::env(CURRENT_SPEF) ../../spef/scr1_top_wb.spef -set ::env(BASE_SDC_FILE) "base.sdc" -set ::env(SYNTH_DRIVING_CELL) "sky130_fd_sc_hd__inv_8" -set ::env(SYNTH_DRIVING_CELL_PIN) "Y" -set ::env(SYNTH_CAP_LOAD) "17.65" -set ::env(WIRE_RC_LAYER) "met1" - - -set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um -define_corners wc bc tt -read_liberty -corner bc $::env(LIB_FASTEST) -read_liberty -corner wc $::env(LIB_SLOWEST) -read_liberty -corner tt $::env(LIB_TYPICAL) - -read_verilog $::env(CURRENT_NETLIST) -link_design $::env(DESIGN_NAME) - -read_spef $::env(CURRENT_SPEF) - -read_sdc -echo $::env(BASE_SDC_FILE) - -# check for missing constraints -check_setup -verbose > unconstraints.rpt - -set_operating_conditions -analysis_type single -# Propgate the clock -set_propagated_clock [all_clocks] - -report_tns -report_wns -#report_power - -echo "################ CORNER : WC (SLOW) TIMING Report ###################" > timing_ss_max.rpt -report_checks -unique -path_delay max -slack_max -0.0 -group_count 100 -corner wc -format full_clock_expanded >> timing_ss_max.rpt -report_checks -group_count 100 -path_delay max -path_group wbm_clk_i -corner wc -format full_clock_expanded >> timing_ss_max.rpt -report_checks -group_count 100 -path_delay max -path_group wbs_clk_i -corner wc -format full_clock_expanded >> timing_ss_max.rpt -report_checks -group_count 100 -path_delay max -path_group cpu_clk -corner wc -format full_clock_expanded >> timing_ss_max.rpt -report_checks -group_count 100 -path_delay max -path_group rtc_clk -corner wc -format full_clock_expanded >> timing_ss_max.rpt -report_checks -group_count 100 -path_delay max -path_group line_clk -corner wc -format full_clock_expanded >> timing_ss_max.rpt -report_checks -path_delay max -corner wc >> timing_ff_max.rpt - -echo "################ CORNER : BC (SLOW) TIMING Report ###################" > timing_ff_min.rpt -report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner bc -format full_clock_expanded >> timing_ff_min.rpt -report_checks -group_count 100 -path_delay min -path_group wbm_clk_i -corner bc -format full_clock_expanded >> timing_ff_min.rpt -report_checks -group_count 100 -path_delay min -path_group wbs_clk_i -corner bc -format full_clock_expanded >> timing_ff_min.rpt -report_checks -group_count 100 -path_delay min -path_group cpu_clk -corner bc -format full_clock_expanded >> timing_ff_min.rpt -report_checks -group_count 100 -path_delay min -path_group rtc_clk -corner bc -format full_clock_expanded >> timing_ff_min.rpt -report_checks -group_count 100 -path_delay min -path_group line_clk -corner bc -format full_clock_expanded >> timing_ff_min.rpt -report_checks -path_delay min -corner bc >> timing_min.rpt - -echo "################ CORNER : TT (MAX) TIMING Report ###################" > timing_tt_max.rpt -report_checks -unique -path_delay max -slack_min -0.0 -group_count 100 -corner tt -format full_clock_expanded >> timing_tt_max.rpt -report_checks -group_count 100 -path_delay max -path_group wbm_clk_i -corner tt -format full_clock_expanded >> timing_tt_max.rpt -report_checks -group_count 100 -path_delay max -path_group wbs_clk_i -corner tt -format full_clock_expanded >> timing_tt_max.rpt -report_checks -group_count 100 -path_delay max -path_group cpu_clk -corner tt -format full_clock_expanded >> timing_tt_max.rpt -report_checks -group_count 100 -path_delay max -path_group rtc_clk -corner tt -format full_clock_expanded >> timing_tt_max.rpt -report_checks -group_count 100 -path_delay max -path_group line_clk -corner tt -format full_clock_expanded >> timing_tt_max.rpt -report_checks -path_delay max -corner tt >> timing_tt_max.rpt - -echo "################ CORNER : TT (MIN) TIMING Report ###################" > timing_tt_min.rpt -report_checks -unique -path_delay min -slack_min -0.0 -group_count 100 -corner tt -format full_clock_expanded >> timing_tt_min.rpt -report_checks -group_count 100 -path_delay min -path_group wbm_clk_i -corner tt -format full_clock_expanded >> timing_tt_min.rpt -report_checks -group_count 100 -path_delay min -path_group wbs_clk_i -corner tt -format full_clock_expanded >> timing_tt_min.rpt -report_checks -group_count 100 -path_delay min -path_group cpu_clk -corner tt -format full_clock_expanded >> timing_tt_min.rpt -report_checks -group_count 100 -path_delay min -path_group rtc_clk -corner tt -format full_clock_expanded >> timing_tt_min.rpt -report_checks -group_count 100 -path_delay min -path_group line_clk -corner tt -format full_clock_expanded >> timing_tt_min.rpt -report_checks -path_delay min -corner tt >> timing_tt_min.rpt - - - - -report_checks -path_delay min_max - -#exit