| ////////////////////////////////////////////////////////////////////////////// |
| // SPDX-FileCopyrightText: 2021, Dinesh Annayya //// |
| // //// |
| // Licensed under the Apache License, Version 2.0 (the "License"); //// |
| // you may not use this file except in compliance with the License. //// |
| // You may obtain a copy of the License at //// |
| // //// |
| // http://www.apache.org/licenses/LICENSE-2.0 //// |
| // //// |
| // Unless required by applicable law or agreed to in writing, software //// |
| // distributed under the License is distributed on an "AS IS" BASIS, //// |
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied./// |
| // See the License for the specific language governing permissions and //// |
| // limitations under the License. //// |
| // SPDX-License-Identifier: Apache-2.0 //// |
| // SPDX-FileContributor: Dinesh Annayya <dinesha@opencores.org> //// |
| ////////////////////////////////////////////////////////////////////////////// |
| |
| #ifndef __RISCV_MACROS_H |
| #define __RISCV_MACROS_H |
| |
| #include "riscv_csr_encoding.h" |
| #include "sc_test.h" |
| |
| //----------------------------------------------------------------------- |
| // Begin Macro |
| //----------------------------------------------------------------------- |
| |
| #define RVTEST_RV64U \ |
| .macro init; \ |
| .endm |
| |
| #define RVTEST_RV64UF \ |
| .macro init; \ |
| RVTEST_FP_ENABLE; \ |
| .endm |
| |
| #define RVTEST_RV32U \ |
| .macro init; \ |
| .endm |
| |
| #define RVTEST_RV32UF \ |
| .macro init; \ |
| RVTEST_FP_ENABLE; \ |
| .endm |
| |
| #define RVTEST_RV64M \ |
| .macro init; \ |
| RVTEST_ENABLE_MACHINE; \ |
| .endm |
| |
| #define RVTEST_RV64S \ |
| .macro init; \ |
| RVTEST_ENABLE_SUPERVISOR; \ |
| .endm |
| |
| #define RVTEST_RV32M \ |
| .macro init; \ |
| RVTEST_ENABLE_MACHINE; \ |
| .endm |
| |
| #define RVTEST_RV32S \ |
| .macro init; \ |
| RVTEST_ENABLE_SUPERVISOR; \ |
| .endm |
| |
| #if __riscv_xlen == 64 |
| # define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1: |
| #else |
| # define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: |
| #endif |
| |
| #define INIT_PMP \ |
| la t0, 1f; \ |
| csrw mtvec, t0; \ |
| li t0, -1; /* Set up a PMP to permit all accesses */ \ |
| csrw pmpaddr0, t0; \ |
| li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \ |
| csrw pmpcfg0, t0; \ |
| .balign 4; \ |
| 1: |
| |
| #define INIT_SPTBR \ |
| la t0, 1f; \ |
| csrw mtvec, t0; \ |
| csrwi sptbr, 0; \ |
| .balign 4; \ |
| 1: |
| |
| #define DELEGATE_NO_TRAPS |
| |
| #define RVTEST_ENABLE_SUPERVISOR \ |
| li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \ |
| csrs mstatus, a0; \ |
| li a0, SIP_SSIP | SIP_STIP; \ |
| csrs mideleg, a0; \ |
| |
| #define RVTEST_ENABLE_MACHINE \ |
| li a0, MSTATUS_MPP; \ |
| csrs mstatus, a0; \ |
| |
| #define RVTEST_FP_ENABLE \ |
| li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \ |
| csrs mstatus, a0; \ |
| csrwi fcsr, 0 |
| |
| #define RISCV_MULTICORE_DISABLE \ |
| csrr a0, mhartid; \ |
| 1: bnez a0, 1b |
| |
| #define EXTRA_TVEC_USER |
| #define EXTRA_TVEC_SUPERVISOR |
| #define EXTRA_TVEC_HYPERVISOR |
| #define EXTRA_TVEC_MACHINE |
| #define EXTRA_INIT |
| #define EXTRA_INIT_TIMER |
| |
| #define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */ |
| |
| #define RVTEST_CODE_BEGIN \ |
| .section .text.init; \ |
| .org 0xC0, 0x00; \ |
| .balign 64; \ |
| .weak stvec_handler; \ |
| .weak mtvec_handler; \ |
| trap_vector: \ |
| /* test whether the test came from pass/fail */ \ |
| csrr a4, mcause; \ |
| li a5, CAUSE_USER_ECALL; \ |
| beq a4, a5, _report; \ |
| li a5, CAUSE_SUPERVISOR_ECALL; \ |
| beq a4, a5, _report; \ |
| li a5, CAUSE_MACHINE_ECALL; \ |
| beq a4, a5, _report; \ |
| /* if an mtvec_handler is defined, jump to it */ \ |
| la a4, mtvec_handler; \ |
| beqz a4, 1f; \ |
| jr a4; \ |
| /* was it an interrupt or an exception? */ \ |
| 1: csrr a4, mcause; \ |
| bgez a4, handle_exception; \ |
| INTERRUPT_HANDLER; \ |
| handle_exception: \ |
| /* we don't know how to handle whatever the exception was */ \ |
| other_exception: \ |
| /* some unhandlable exception occurred */ \ |
| li a0, 0x1; \ |
| _report: \ |
| j sc_exit; \ |
| .balign 64; \ |
| .globl _start; \ |
| _start: \ |
| RISCV_MULTICORE_DISABLE; \ |
| /*INIT_SPTBR;*/ \ |
| /*INIT_PMP;*/ \ |
| DELEGATE_NO_TRAPS; \ |
| li TESTNUM, 0; \ |
| la t0, trap_vector; \ |
| csrw mtvec, t0; \ |
| CHECK_XLEN; \ |
| /* if an stvec_handler is defined, delegate exceptions to it */ \ |
| la t0, stvec_handler; \ |
| beqz t0, 1f; \ |
| csrw stvec, t0; \ |
| li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \ |
| (1 << CAUSE_STORE_PAGE_FAULT) | \ |
| (1 << CAUSE_FETCH_PAGE_FAULT) | \ |
| (1 << CAUSE_MISALIGNED_FETCH) | \ |
| (1 << CAUSE_USER_ECALL) | \ |
| (1 << CAUSE_BREAKPOINT); \ |
| csrw medeleg, t0; \ |
| csrr t1, medeleg; \ |
| bne t0, t1, other_exception; \ |
| 1: csrwi mstatus, 0; \ |
| init; \ |
| EXTRA_INIT; \ |
| EXTRA_INIT_TIMER; \ |
| la t0, _run_test; \ |
| csrw mepc, t0; \ |
| csrr a0, mhartid; \ |
| mret; \ |
| .section .text; \ |
| _run_test: |
| |
| //----------------------------------------------------------------------- |
| // End Macro |
| //----------------------------------------------------------------------- |
| |
| #define RVTEST_CODE_END ecall: ecall |
| |
| //----------------------------------------------------------------------- |
| // Pass/Fail Macro |
| //----------------------------------------------------------------------- |
| |
| #define RVTEST_PASS \ |
| fence; \ |
| mv a1, TESTNUM; \ |
| li a0, 0x0; \ |
| ecall |
| |
| #define TESTNUM x28 |
| #define RVTEST_FAIL \ |
| fence; \ |
| mv a1, TESTNUM; \ |
| li a0, 0x1; \ |
| ecall |
| |
| //----------------------------------------------------------------------- |
| // Data Section Macro |
| //----------------------------------------------------------------------- |
| |
| #define EXTRA_DATA |
| |
| #define RVTEST_DATA_BEGIN \ |
| EXTRA_DATA \ |
| .pushsection .tohost,"aw",@progbits; \ |
| .balign 64; .global tohost; tohost: .dword 0; \ |
| .balign 64; .global fromhost; fromhost: .dword 0; \ |
| .popsection; \ |
| .balign 16; \ |
| .global begin_regstate; begin_regstate: .dword 0; .dword 0; .dword 0; \ |
| .balign 16; \ |
| .global begin_signature; begin_signature: |
| |
| #define RVTEST_DATA_END .balign 16; .global end_signature; end_signature: |
| |
| #----------------------------------------------------------------------- |
| # Helper macros |
| #----------------------------------------------------------------------- |
| |
| #define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1)) |
| |
| #define TEST_CASE( testnum, testreg, correctval, code... ) \ |
| test_ ## testnum: \ |
| code; \ |
| li x29, MASK_XLEN(correctval); \ |
| li TESTNUM, testnum; \ |
| bne testreg, x29, fail; |
| |
| # We use a macro hack to simpify code generation for various numbers |
| # of bubble cycles. |
| |
| #define TEST_INSERT_NOPS_0 |
| #define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0 |
| #define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1 |
| #define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2 |
| #define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3 |
| #define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4 |
| #define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5 |
| #define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6 |
| #define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7 |
| #define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8 |
| #define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9 |
| |
| |
| #----------------------------------------------------------------------- |
| # RV64UI MACROS |
| #----------------------------------------------------------------------- |
| |
| #----------------------------------------------------------------------- |
| # Tests for instructions with immediate operand |
| #----------------------------------------------------------------------- |
| |
| #define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) |
| |
| #define TEST_IMM_OP( testnum, inst, result, val1, imm ) \ |
| TEST_CASE( testnum, x3, result, \ |
| li x1, MASK_XLEN(val1); \ |
| inst x3, x1, SEXT_IMM(imm); \ |
| ) |
| |
| #define TEST_IMM_OP_RVC( testnum, inst, result, val1, imm ) \ |
| TEST_CASE( testnum, x1, result, \ |
| li x1, val1; \ |
| inst x1, imm; \ |
| ) |
| |
| #define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \ |
| TEST_CASE( testnum, x1, result, \ |
| li x1, MASK_XLEN(val1); \ |
| inst x1, x1, SEXT_IMM(imm); \ |
| ) |
| |
| #define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ |
| TEST_CASE( testnum, x6, result, \ |
| li x4, 0; \ |
| 1: li x1, MASK_XLEN(val1); \ |
| inst x3, x1, SEXT_IMM(imm); \ |
| TEST_INSERT_NOPS_ ## nop_cycles \ |
| addi x6, x3, 0; \ |
| addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| ) |
| |
| #define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ |
| TEST_CASE( testnum, x3, result, \ |
| li x4, 0; \ |
| 1: li x1, MASK_XLEN(val1); \ |
| TEST_INSERT_NOPS_ ## nop_cycles \ |
| inst x3, x1, SEXT_IMM(imm); \ |
| addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| ) |
| |
| #define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \ |
| TEST_CASE( testnum, x1, result, \ |
| inst x1, x0, SEXT_IMM(imm); \ |
| ) |
| |
| #define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \ |
| TEST_CASE( testnum, x0, 0, \ |
| li x1, MASK_XLEN(val1); \ |
| inst x0, x1, SEXT_IMM(imm); \ |
| ) |
| |
| #----------------------------------------------------------------------- |
| # Tests for vector config instructions |
| #----------------------------------------------------------------------- |
| |
| #define TEST_VSETCFGIVL( testnum, nxpr, nfpr, bank, vl, result ) \ |
| TEST_CASE( testnum, x1, result, \ |
| li x1, (bank << 12); \ |
| vsetcfg x1,nxpr,nfpr; \ |
| li x1, vl; \ |
| vsetvl x1,x1; \ |
| ) |
| |
| #define TEST_VVCFG( testnum, nxpr, nfpr, bank, vl, result ) \ |
| TEST_CASE( testnum, x1, result, \ |
| li x1, (bank << 12) | (nfpr << 6) | nxpr; \ |
| vsetcfg x1; \ |
| li x1, vl; \ |
| vsetvl x1,x1; \ |
| ) |
| |
| #define TEST_VSETVL( testnum, nxpr, nfpr, bank, vl, result ) \ |
| TEST_CASE( testnum, x1, result, \ |
| li x1, (bank << 12); \ |
| vsetcfg x1,nxpr,nfpr; \ |
| li x1, vl; \ |
| vsetvl x1, x1; \ |
| ) |
| |
| #----------------------------------------------------------------------- |
| # Tests for an instruction with register operands |
| #----------------------------------------------------------------------- |
| |
| #define TEST_R_OP( testnum, inst, result, val1 ) \ |
| TEST_CASE( testnum, x3, result, \ |
| li x1, val1; \ |
| inst x3, x1; \ |
| ) |
| |
| #define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \ |
| TEST_CASE( testnum, x1, result, \ |
| li x1, val1; \ |
| inst x1, x1; \ |
| ) |
| |
| #define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \ |
| TEST_CASE( testnum, x6, result, \ |
| li x4, 0; \ |
| 1: li x1, val1; \ |
| inst x3, x1; \ |
| TEST_INSERT_NOPS_ ## nop_cycles \ |
| addi x6, x3, 0; \ |
| addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| ) |
| |
| #----------------------------------------------------------------------- |
| # Tests for an instruction with register-register operands |
| #----------------------------------------------------------------------- |
| |
| #define TEST_RR_OP( testnum, inst, result, val1, val2 ) \ |
| TEST_CASE( testnum, x3, result, \ |
| li x1, MASK_XLEN(val1); \ |
| li x2, MASK_XLEN(val2); \ |
| inst x3, x1, x2; \ |
| ) |
| |
| #define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \ |
| TEST_CASE( testnum, x1, result, \ |
| li x1, MASK_XLEN(val1); \ |
| li x2, MASK_XLEN(val2); \ |
| inst x1, x1, x2; \ |
| ) |
| |
| #define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \ |
| TEST_CASE( testnum, x2, result, \ |
| li x1, MASK_XLEN(val1); \ |
| li x2, MASK_XLEN(val2); \ |
| inst x2, x1, x2; \ |
| ) |
| |
| #define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \ |
| TEST_CASE( testnum, x1, result, \ |
| li x1, MASK_XLEN(val1); \ |
| inst x1, x1, x1; \ |
| ) |
| |
| #define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \ |
| TEST_CASE( testnum, x6, result, \ |
| li x4, 0; \ |
| 1: li x1, MASK_XLEN(val1); \ |
| li x2, MASK_XLEN(val2); \ |
| inst x3, x1, x2; \ |
| TEST_INSERT_NOPS_ ## nop_cycles \ |
| addi x6, x3, 0; \ |
| addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| ) |
| |
| #define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ |
| TEST_CASE( testnum, x3, result, \ |
| li x4, 0; \ |
| 1: li x1, MASK_XLEN(val1); \ |
| TEST_INSERT_NOPS_ ## src1_nops \ |
| li x2, MASK_XLEN(val2); \ |
| TEST_INSERT_NOPS_ ## src2_nops \ |
| inst x3, x1, x2; \ |
| addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| ) |
| |
| #define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ |
| TEST_CASE( testnum, x3, result, \ |
| li x4, 0; \ |
| 1: li x2, MASK_XLEN(val2); \ |
| TEST_INSERT_NOPS_ ## src1_nops \ |
| li x1, MASK_XLEN(val1); \ |
| TEST_INSERT_NOPS_ ## src2_nops \ |
| inst x3, x1, x2; \ |
| addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| ) |
| |
| #define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \ |
| TEST_CASE( testnum, x2, result, \ |
| li x1, MASK_XLEN(val); \ |
| inst x2, x0, x1; \ |
| ) |
| |
| #define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \ |
| TEST_CASE( testnum, x2, result, \ |
| li x1, MASK_XLEN(val); \ |
| inst x2, x1, x0; \ |
| ) |
| |
| #define TEST_RR_ZEROSRC12( testnum, inst, result ) \ |
| TEST_CASE( testnum, x1, result, \ |
| inst x1, x0, x0; \ |
| ) |
| |
| #define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \ |
| TEST_CASE( testnum, x0, 0, \ |
| li x1, MASK_XLEN(val1); \ |
| li x2, MASK_XLEN(val2); \ |
| inst x0, x1, x2; \ |
| ) |
| |
| #----------------------------------------------------------------------- |
| # Test memory instructions |
| #----------------------------------------------------------------------- |
| |
| #define TEST_LD_OP( testnum, inst, result, offset, base ) \ |
| TEST_CASE( testnum, x3, result, \ |
| la x1, base; \ |
| inst x3, offset(x1); \ |
| ) |
| |
| #define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \ |
| TEST_CASE( testnum, x3, result, \ |
| la x1, base; \ |
| li x2, result; \ |
| store_inst x2, offset(x1); \ |
| load_inst x3, offset(x1); \ |
| ) |
| |
| #define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| li x4, 0; \ |
| 1: la x1, base; \ |
| inst x3, offset(x1); \ |
| TEST_INSERT_NOPS_ ## nop_cycles \ |
| addi x6, x3, 0; \ |
| li x29, result; \ |
| bne x6, x29, fail; \ |
| addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b; \ |
| |
| #define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| li x4, 0; \ |
| 1: la x1, base; \ |
| TEST_INSERT_NOPS_ ## nop_cycles \ |
| inst x3, offset(x1); \ |
| li x29, result; \ |
| bne x3, x29, fail; \ |
| addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| |
| #define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| li x4, 0; \ |
| 1: li x1, result; \ |
| TEST_INSERT_NOPS_ ## src1_nops \ |
| la x2, base; \ |
| TEST_INSERT_NOPS_ ## src2_nops \ |
| store_inst x1, offset(x2); \ |
| load_inst x3, offset(x2); \ |
| li x29, result; \ |
| bne x3, x29, fail; \ |
| addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| |
| #define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| li x4, 0; \ |
| 1: la x2, base; \ |
| TEST_INSERT_NOPS_ ## src1_nops \ |
| li x1, result; \ |
| TEST_INSERT_NOPS_ ## src2_nops \ |
| store_inst x1, offset(x2); \ |
| load_inst x3, offset(x2); \ |
| li x29, result; \ |
| bne x3, x29, fail; \ |
| addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| |
| #----------------------------------------------------------------------- |
| # Test branch instructions |
| #----------------------------------------------------------------------- |
| |
| #define TEST_BR1_OP_TAKEN( testnum, inst, val1 ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| li x1, val1; \ |
| inst x1, 2f; \ |
| bne x0, TESTNUM, fail; \ |
| 1: bne x0, TESTNUM, 3f; \ |
| 2: inst x1, 1b; \ |
| bne x0, TESTNUM, fail; \ |
| 3: |
| |
| #define TEST_BR1_OP_NOTTAKEN( testnum, inst, val1 ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| li x1, val1; \ |
| inst x1, 1f; \ |
| bne x0, TESTNUM, 2f; \ |
| 1: bne x0, TESTNUM, fail; \ |
| 2: inst x1, 1b; \ |
| 3: |
| |
| #define TEST_BR1_SRC1_BYPASS( testnum, nop_cycles, inst, val1 ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| li x4, 0; \ |
| 1: li x1, val1; \ |
| TEST_INSERT_NOPS_ ## nop_cycles \ |
| inst x1, fail; \ |
| addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| |
| #define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| li x1, val1; \ |
| li x2, val2; \ |
| inst x1, x2, 2f; \ |
| bne x0, TESTNUM, fail; \ |
| 1: bne x0, TESTNUM, 3f; \ |
| 2: inst x1, x2, 1b; \ |
| bne x0, TESTNUM, fail; \ |
| 3: |
| |
| #define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| li x1, val1; \ |
| li x2, val2; \ |
| inst x1, x2, 1f; \ |
| bne x0, TESTNUM, 2f; \ |
| 1: bne x0, TESTNUM, fail; \ |
| 2: inst x1, x2, 1b; \ |
| 3: |
| |
| #define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| li x4, 0; \ |
| 1: li x1, val1; \ |
| TEST_INSERT_NOPS_ ## src1_nops \ |
| li x2, val2; \ |
| TEST_INSERT_NOPS_ ## src2_nops \ |
| inst x1, x2, fail; \ |
| addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| |
| #define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| li x4, 0; \ |
| 1: li x2, val2; \ |
| TEST_INSERT_NOPS_ ## src1_nops \ |
| li x1, val1; \ |
| TEST_INSERT_NOPS_ ## src2_nops \ |
| inst x1, x2, fail; \ |
| addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| |
| #----------------------------------------------------------------------- |
| # Test jump instructions |
| #----------------------------------------------------------------------- |
| |
| #define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| li x4, 0; \ |
| 1: la x6, 2f; \ |
| TEST_INSERT_NOPS_ ## nop_cycles \ |
| inst x6; \ |
| bne x0, TESTNUM, fail; \ |
| 2: addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| |
| #define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| li x4, 0; \ |
| 1: la x6, 2f; \ |
| TEST_INSERT_NOPS_ ## nop_cycles \ |
| inst x19, x6, 0; \ |
| bne x0, TESTNUM, fail; \ |
| 2: addi x4, x4, 1; \ |
| li x5, 2; \ |
| bne x4, x5, 1b \ |
| |
| |
| #----------------------------------------------------------------------- |
| # RV64UF MACROS |
| #----------------------------------------------------------------------- |
| |
| #----------------------------------------------------------------------- |
| # Tests floating-point instructions |
| #----------------------------------------------------------------------- |
| |
| #define qNaNf 0f:7fc00000 |
| #define sNaNf 0f:7f800001 |
| #define qNaN 0d:7ff8000000000000 |
| #define sNaN 0d:7ff0000000000001 |
| |
| #define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| la a0, test_ ## testnum ## _data ;\ |
| flw f0, 0(a0); \ |
| flw f1, 4(a0); \ |
| flw f2, 8(a0); \ |
| lw a3, 12(a0); \ |
| code; \ |
| fsflags a1, x0; \ |
| li a2, flags; \ |
| bne a0, a3, fail; \ |
| bne a1, a2, fail; \ |
| j 2f; \ |
| .balign 4; \ |
| .data; \ |
| test_ ## testnum ## _data: \ |
| .float val1; \ |
| .float val2; \ |
| .float val3; \ |
| .result; \ |
| .text; \ |
| 2: |
| |
| #define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| la a0, test_ ## testnum ## _data ;\ |
| fld f0, 0(a0); \ |
| fld f1, 8(a0); \ |
| fld f2, 16(a0); \ |
| ld a3, 24(a0); \ |
| code; \ |
| fsflags a1, x0; \ |
| li a2, flags; \ |
| bne a0, a3, fail; \ |
| bne a1, a2, fail; \ |
| j 2f; \ |
| .data; \ |
| .balign 8; \ |
| test_ ## testnum ## _data: \ |
| .double val1; \ |
| .double val2; \ |
| .double val3; \ |
| .result; \ |
| .text; \ |
| 2: |
| |
| #define TEST_FCVT_S_D( testnum, result, val1 ) \ |
| TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ |
| fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3) |
| |
| #define TEST_FCVT_D_S( testnum, result, val1 ) \ |
| TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \ |
| fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3) |
| |
| #define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \ |
| TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \ |
| inst f3, f0; fmv.x.s a0, f3) |
| |
| #define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \ |
| TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ |
| inst f3, f0; fmv.x.d a0, f3) |
| |
| #define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ |
| TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ |
| inst f3, f0; fmv.x.s a0, f3) |
| |
| #define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ |
| TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ |
| inst f3, f0; fmv.x.d a0, f3) |
| |
| #define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \ |
| TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \ |
| inst f3, f0, f1; fmv.x.s a0, f3) |
| |
| #define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \ |
| TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ |
| inst f3, f0, f1; fmv.x.d a0, f3) |
| |
| #define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \ |
| TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \ |
| inst f3, f0, f1, f2; fmv.x.s a0, f3) |
| |
| #define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \ |
| TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \ |
| inst f3, f0, f1, f2; fmv.x.d a0, f3) |
| |
| #define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \ |
| TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ |
| inst a0, f0, rm) |
| |
| #define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \ |
| TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ |
| inst a0, f0, rm) |
| |
| #define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \ |
| TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \ |
| inst a0, f0, f1) |
| |
| #define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \ |
| TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ |
| inst a0, f0, f1) |
| |
| #define TEST_FCLASS_S(testnum, correct, input) \ |
| TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \ |
| fclass.s a0, fa0) |
| |
| #define TEST_FCLASS_D(testnum, correct, input) \ |
| TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \ |
| fclass.d a0, fa0) |
| |
| #define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| la a0, test_ ## testnum ## _data ;\ |
| lw a3, 0(a0); \ |
| li a0, val1; \ |
| inst f0, a0; \ |
| fsflags x0; \ |
| fmv.x.s a0, f0; \ |
| bne a0, a3, fail; \ |
| j 1f; \ |
| .balign 4; \ |
| test_ ## testnum ## _data: \ |
| .float result; \ |
| 1: |
| |
| #define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \ |
| test_ ## testnum: \ |
| li TESTNUM, testnum; \ |
| la a0, test_ ## testnum ## _data ;\ |
| ld a3, 0(a0); \ |
| li a0, val1; \ |
| inst f0, a0; \ |
| fsflags x0; \ |
| fmv.x.d a0, f0; \ |
| bne a0, a3, fail; \ |
| j 1f; \ |
| .balign 8; \ |
| test_ ## testnum ## _data: \ |
| .double result; \ |
| 1: |
| |
| #----------------------------------------------------------------------- |
| # Pass and fail code (assumes test num is in TESTNUM) |
| #----------------------------------------------------------------------- |
| |
| #define TEST_PASSFAIL \ |
| bne x0, TESTNUM, pass; \ |
| fail: \ |
| RVTEST_FAIL; \ |
| pass: \ |
| RVTEST_PASS \ |
| |
| |
| #----------------------------------------------------------------------- |
| # Test data section |
| #----------------------------------------------------------------------- |
| |
| #define TEST_DATA |
| |
| #endif |
| |
