statistic updated
diff --git a/README.md b/README.md
index 5a02926..995e370 100644
--- a/README.md
+++ b/README.md
@@ -206,6 +206,15 @@
<tr align="center"> <td> usb1.1 </td> <td> usb_dp </td> <td> </td> <td> digital_io[36] </td></tr>
<tr align="center"> <td> usb1.1 </td> <td> usb_dn </td> <td> </td> <td> digital_io[37] </td></tr>
</table>
+
+
+# Riscduino documentation
+* Riscduino documentation available at : <https://riscduino.readthedocs.io/en/latest/>
+
+# Arduino ide integration
+* We are in initial phase of Riscduino board integration into arduino and integration details are available at : <https://github.com/dineshannayya/riscduino_board/>
+
+
# Sub IP features
## RISC V Core
@@ -342,18 +351,16 @@
# SOC Size
-| Block | Total Cell | Seq | Combo |
-| ------ | --------- | -------- | ----- |
-| RISC | 20982 | 3164 | 17818 |
-| PINMUX | 5693 | 1022 | 4671 |
-| SPI | 7120 | 1281 | 5839 |
-| UART_I2C_USB_SPI | 11196 | 2448 | 8748 |
-| WB_HOST | 2796 | 588 | 2208 |
-| WB_INTC | 1878 | 108 | 1770 |
-| SAR_ADC | 118 | 18 | 100 |
-| MBIST | 3125 | 543 | 2582 |
-| | | | |
-| TOTAL | 52908 | 9172 | 43736 |
+| Block | Total Cell | Combo | Seq |
+| ------ | --------- | ----- | -------- |
+| RISC | 52527 | 46858 | 5669 |
+| QSPI | 8654 | 7149 | 1505 |
+| UART_I2C_USB_SPI | 15926 | 13061 | 2865 |
+| WB_HOST | 5800 | 4701 | 1099 |
+| WB_INTC | 11477 | 10081 | 1396 |
+| PINMUX | 6746 | 5574 | 1172 |
+| | | | |
+| TOTAL | 120381 | 103826 | 16555 |
@@ -753,14 +760,9 @@
3. `Netgen` - Performs LVS Checks
4. `CVC` - Performs Circuit Validity Checks
-# Riscduino documentation
- Riscduino documentation available at <https://riscduino.readthedocs.io/en/latest/>
-
-# Arduino ide integration
- We are in initial phase of Riscduino board integration into arduino and integration details are available at <https://github.com/dineshannayya/riscduino_board/>
# News
-* **Riscduino Aim** - https://www.youtube.com/watch?v=lFVnicPhTI0
+* **Riscduino Aim** - <https://www.youtube.com/watch?v=lFVnicPhTI0>
# How To Contribute
diff --git a/sta/scripts/riscdunio.tcl b/sta/scripts/riscdunio.tcl
new file mode 100644
index 0000000..7fe97c6
--- /dev/null
+++ b/sta/scripts/riscdunio.tcl
@@ -0,0 +1,142 @@
+
+ set ::env(USER_ROOT) ".."
+ set ::env(CARAVEL_ROOT) "/home/dinesha/workarea/efabless/MPW-6/caravel"
+ set ::env(CARAVEL_PDK_ROOT) "/opt/pdk_mpw6"
+
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hvl/lib/sky130_fd_sc_hvl__tt_025C_3v30_lv1v80.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_gpiov2_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_hvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_ground_lvc_wpad_tt_100C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_power_lvc_wpad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_fd_io__top_xres4v2_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__gpiov2_pad_tt_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vdda_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssa_hvc_clamped_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped3_pad_tt_025C_1v80_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vccd_lvc_clamped3_pad_tt_025C_1v80_3v30_3v30.lib
+ read_liberty $::env(CARAVEL_PDK_ROOT)/sky130A/libs.ref/sky130_fd_io/lib/sky130_ef_io__vssd_lvc_clamped_pad_tt_025C_1v80_3v30.lib
+
+ source scripts/statistic.tcl
+ set c_seq_cnt 0
+ set c_comb_cnt 0
+ set c_total_cnt 0
+
+ read_verilog $::env(USER_ROOT)/verilog/gl/qspim_top.v
+ link_design qspim_top
+ puts "IP :: Total Cell :: Total Combo :: Total Sequential"
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "qspim_top :: $tcell :: $tregs "
+ lassign [get_statistic qspim_top] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
+
+ #Variable for Risc Area
+ set r_seq_cnt 0
+ set r_comb_cnt 0
+ set r_total_cnt 0
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr2_iconnect.v
+ link_design ycr2_iconnect
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_iconnect :: $tcell :: $tregs "
+ lassign [get_statistic ycr2_iconnect] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
+ set r_total_cnt [expr {$r_total_cnt + $a }]
+ set r_comb_cnt [expr {$r_comb_cnt + $b }]
+ set r_seq_cnt [expr {$r_seq_cnt + $c }]
+
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_intf.v
+ link_design ycr_intf
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_intf :: $tcell :: $tregs "
+ lassign [get_statistic ycr_intf] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
+
+ read_verilog $::env(USER_ROOT)/verilog/gl/ycr_core_top.v
+ link_design ycr_core_top
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_intf :: $tcell :: $tregs "
+ lassign [get_statistic ycr_core_top] a b c
+ #2 core in riscduino_dcore
+ set c_total_cnt [expr {$c_total_cnt + ($a *2) }]
+ set c_comb_cnt [expr {$c_comb_cnt + ($b *2) }]
+ set c_seq_cnt [expr {$c_seq_cnt + ($c *2) }]
+ set r_total_cnt [expr {$r_total_cnt + ($a *2) }]
+ set r_comb_cnt [expr {$r_comb_cnt + ($b *2) }]
+ set r_seq_cnt [expr {$r_seq_cnt + ($c *2) }]
+ puts "RISC :: $r_total_cnt :: $r_comb_cnt :: $r_seq_cnt"
+
+ read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2c_usb_spi_top.v
+ link_design uart_i2c_usb_spi_top
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_intf :: $tcell :: $tregs "
+ lassign [get_statistic uart_i2c_usb_spi_top] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
+
+ read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v
+ link_design wb_host
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_intf :: $tcell :: $tregs "
+ lassign [get_statistic wb_host] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
+
+ read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
+ link_design wb_interconnect
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_intf :: $tcell :: $tregs "
+ lassign [get_statistic wb_interconnect] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
+
+ read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v
+ link_design pinmux
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "ycr_intf :: $tcell :: $tregs "
+ lassign [get_statistic pinmux] a b c
+ set c_total_cnt [expr {$c_total_cnt + $a }]
+ set c_comb_cnt [expr {$c_comb_cnt + $b }]
+ set c_seq_cnt [expr {$c_seq_cnt + $c }]
+
+ puts "digital_top :: $c_total_cnt :: $c_comb_cnt :: $c_seq_cnt"
+ # read_verilog $::env(USER_ROOT)/verilog/gl/user_project_wrapper.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/DFFRAM.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/pinmux.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/wb_interconnect.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/wb_host.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/uart_i2cm_usb_spi.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/qspim.v
+ # read_verilog $::env(USER_ROOT)/verilog/gl/yifive.v
+
+ #link_design user_project_wrapper
+ #set tcell [llength [get_cell -hier *]]
+ #set tregs [llength [all_registers]]
+ #puts "user_project_wrapper :: $tcell :: $tregs "
+
+
+
+
+
diff --git a/sta/scripts/statistic.tcl b/sta/scripts/statistic.tcl
new file mode 100644
index 0000000..343a4e1
--- /dev/null
+++ b/sta/scripts/statistic.tcl
@@ -0,0 +1,86 @@
+########################################
+# Get the Cell wise statistic
+#########################################
+
+proc get_statistic {design_name } {
+
+ #puts "Analysising the Statistic ..."
+
+ #To get all the lib cells and initialise the counter
+ array set libArray {}
+ set mylist [get_lib_cells *]
+ set lib_cnt 0
+ foreach elem $mylist {
+ #puts [get_full_name $elem]
+ #set libArray($lib_cnt,0) [get_full_name $elem]
+ set libArray($lib_cnt) 0
+ #puts "$libArray($lib_cnt)"
+ set lib_cnt [expr {$lib_cnt + 1}]
+ }
+
+
+ #################################################
+ # Accumlate the lib count
+ ################################################
+ set mylist1 [get_cells]
+ foreach elem1 $mylist1 {
+ set Inst [get_full_name $elem1]
+ #puts "Searching: ..:: $Inst .."
+ if ([string match "*ANTENNA*" $Inst]) {
+ continue
+ }
+ if ([string match "*FILLER*" $Inst]) {
+ continue
+ }
+ if ([string match "*TAP_*" $Inst]) {
+ continue
+ }
+ set lib [get_lib_cells -of_objects [get_cells $Inst]]
+ set lib_name [get_full_name $lib]
+ #puts "Searching: ..:: $lib_name .."
+
+ if ([string match "*decap*" $lib_name]) {
+ continue
+ }
+ set lib_cnt 0
+ set mylist2 [get_lib_cells *]
+ foreach elem2 $mylist2 {
+ set ref_lib_name [get_full_name $elem2]
+ if { [expr {$ref_lib_name eq $lib_name}] == 1 } {
+ set c_lib_cnt $libArray($lib_cnt)
+ set libArray($lib_cnt) [expr {$c_lib_cnt + 1}]
+ #puts "Lib Matched : $Inst: $lib_name :: $ref_lib_name :: cnt: $libArray($lib_cnt)"
+ break
+ }
+ set lib_cnt [expr {$lib_cnt + 1}]
+ }
+ }
+
+
+ ##################################################
+ ## lib count > 0
+ #################################################
+ set mylist [get_lib_cells *]
+ set lib_cnt 0
+ set seq_cnt 0
+ set comb_cnt 0
+ set total_cnt 0
+ foreach elem $mylist {
+ set ref_lib_name [get_full_name $elem]
+ if {$libArray($lib_cnt) > 0} {
+ #puts "Lib Name: $ref_lib_name :: Count: $libArray($lib_cnt)"
+ }
+ # Check cell is Sequential OR Combo
+ if ([string match "*__df*" $ref_lib_name]) {
+ set seq_cnt [expr {$seq_cnt + $libArray($lib_cnt) }]
+ } else {
+ set comb_cnt [expr {$comb_cnt + $libArray($lib_cnt) }]
+ }
+
+ set total_cnt [expr {$total_cnt + $libArray($lib_cnt) }]
+ set lib_cnt [expr {$lib_cnt + 1}]
+ }
+ puts "$design_name :: $total_cnt :: $comb_cnt :: $seq_cnt"
+ return "$total_cnt $comb_cnt $seq_cnt"
+}
+
