pre-check DRC fix
diff --git a/Makefile b/Makefile
index 09c44b5..53869ec 100644
--- a/Makefile
+++ b/Makefile
@@ -200,21 +200,15 @@
fi
zip:
- gzip -f def/*
gzip -f lef/*
gzip -f gds/*
- gzip -f mag/*
- gzip -f maglef/*
gzip -f spef/*
gzip -f spi/lvs/*
gzip -f verilog/gl/*
unzip:
- gzip -d def/*
gzip -d lef/*
gzip -d gds/*
- gzip -d mag/*
- gzip -d maglef/*
gzip -d spef/*
gzip -d spi/lvs/*
gzip -d verilog/gl/*
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index e58ee59..1c6fc4f 100644
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -144,6 +144,9 @@
met3 150 750 833.1 1166.54,\
met1 950 650 1760 660 ,\
met3 950 650 1760 660 ,\
+ met1 2250 2150 2800 2600,\
+ met2 2250 2150 2800 2600,\
+ met3 2250 2150 2800 2600,\
met5 0 0 2920 3520"
set ::env(FP_PDN_POWER_STRAPS) "vccd1 vssd1 1, vccd2 vssd2 0, vdda1 vssa1 0, vdda2 vssa2 0"
diff --git a/signoff/user_project_wrapper/final_summary_report.csv b/signoff/user_project_wrapper/final_summary_report.csv
index d4326b1..9645d12 100644
--- a/signoff/user_project_wrapper/final_summary_report.csv
+++ b/signoff/user_project_wrapper/final_summary_report.csv
@@ -1,2 +1,2 @@
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/home/dinesha/workarea/opencore/git/riscduino_dcore/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,1h43m41s0ms,0h4m1s0ms,-2.0,-1,-1,-1,594.3,13,0,0,0,0,0,0,-1,0,0,-1,-1,1415412,10457,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.37,6.22,1.45,2.47,0.0,367,3710,367,3710,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
+0,/home/dinesha/workarea/opencore/git/riscduino_dcore/openlane/user_project_wrapper,user_project_wrapper,user_project_wrapper,flow completed,0h53m42s0ms,0h3m56s0ms,-2.0,-1,-1,-1,578.62,13,0,0,0,0,0,0,-1,0,0,-1,-1,1415980,10509,0.0,-1,-1,0.0,0.0,0.0,-1,-1,0.0,0.0,-1,0.0,5.37,6.1,1.48,2.78,0.0,367,3710,367,3710,0,0,0,13,0,0,0,0,0,0,0,0,-1,-1,-1,0,0,0,0,100.0,10.0,10,AREA 0,5,50,1,80,90,0.55,0.3,sky130_fd_sc_hd,4,0
