| design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY | |
| /scratch/mpw6/caravel_user_project/openlane/Microwatt_FP_DFFRFile,Microwatt_FP_DFFRFile,Microwatt_FP_DFFRFile,flow completed,0h29m58s0ms,0h13m49s0ms,-2.0,1.3225,-1,31.25,9032.99,-1,0,0,0,0,0,0,0,479,0,-1,-1,2910997,340731,0.0,-2.48,0.0,0.0,-1,0.0,-336.58,0.0,0.0,-1,2113732045.0,0.0,56.93,57.84,18.39,43.2,-1,18378,24702,106,6430,0,0,0,24608,0,0,2,0,119,0,0,18240,6237,6336,11,828,18304,0,19132,1285020.2303999998,0.0414,0.0115,0.00031,0.052,0.0149,3.14e-07,0.0598,0.0178,4.58e-07,6.59,11.0,90.9090909090909,10,DELAY 4,10,50,1,180,180,0.33,0.3,sky130_fd_sc_hd,4,3 |