| |
| library (Microwatt_FP_DFFRFile_lib) { |
| delay_model : "table_lookup"; |
| time_unit : "1ns"; |
| voltage_unit : "1V"; |
| current_unit : "1mA"; |
| pulling_resistance_unit : "1kohm"; |
| leakage_power_unit : "1nW"; |
| capacitive_load_unit (1.0, pf); |
| |
| input_threshold_pct_fall : 50; |
| output_threshold_pct_fall : 50; |
| input_threshold_pct_rise : 50; |
| output_threshold_pct_rise : 50; |
| slew_derate_from_library : 1.0; |
| slew_lower_threshold_pct_fall : 20; |
| slew_lower_threshold_pct_rise : 20; |
| slew_upper_threshold_pct_fall : 80; |
| slew_upper_threshold_pct_rise : 80; |
| |
| default_max_transition : 1.5; |
| default_cell_leakage_power : 0.0; |
| default_fanout_load : 1.0; |
| default_inout_pin_cap : 0.0; |
| default_input_pin_cap : 0.0; |
| default_output_pin_cap : 0.0; |
| |
| nom_process : 1.0; |
| nom_temperature : 25.0; |
| nom_voltage : 1.8; |
| |
| default_operating_conditions : "tt_025C_1v80"; |
| operating_conditions ("tt_025C_1v80") { |
| voltage : 1.8; |
| process : 1.0; |
| temperature : 25.0; |
| tree_type : "balanced_tree"; |
| } |
| |
| type (bits_64) { |
| base_type : array; |
| data_type : bit; |
| bit_width : 64; |
| bit_from : 63; |
| bit_to : 0; |
| } |
| |
| type (bits_7) { |
| base_type : array; |
| data_type : bit; |
| bit_width : 7; |
| bit_from : 6; |
| bit_to : 0; |
| } |
| |
| cell (Microwatt_FP_DFFRFile) { |
| interface_timing : true; |
| |
| pg_pin ("VPWR") { |
| pg_type : "primary_power"; |
| voltage_name : "VPWR"; |
| } |
| |
| pg_pin ("VGND") { |
| pg_type : "primary_ground"; |
| voltage_name : "VGND"; |
| } |
| |
| bus(R1) { |
| bus_type : bits_7; |
| clock : false; |
| direction : input; |
| related_ground_pin : "VGND"; |
| related_power_pin : "VPWR"; |
| |
| capacitance : 0.002103; |
| rise_capacitance : 0.002191; |
| fall_capacitance : 0.002015; |
| max_transition : 1.5; |
| } |
| |
| bus(R2) { |
| bus_type : bits_7; |
| clock : false; |
| direction : input; |
| related_ground_pin : "VGND"; |
| related_power_pin : "VPWR"; |
| |
| capacitance : 0.002103; |
| rise_capacitance : 0.002191; |
| fall_capacitance : 0.002015; |
| max_transition : 1.5; |
| } |
| |
| bus(R3) { |
| bus_type : bits_7; |
| clock : false; |
| direction : input; |
| related_ground_pin : "VGND"; |
| related_power_pin : "VPWR"; |
| |
| capacitance : 0.002103; |
| rise_capacitance : 0.002191; |
| fall_capacitance : 0.002015; |
| max_transition : 1.5; |
| } |
| |
| bus(D1) { |
| bus_type : bits_64; |
| direction : output; |
| related_ground_pin : "VGND"; |
| related_power_pin : "VPWR"; |
| |
| max_capacitance : 0.130015; |
| max_transition : 1.5; |
| timing() { |
| related_pin : "D1"; |
| timing_type : rising_edge |
| cell_rise(scalar) { |
| values("3.2700"); |
| } |
| cell_fall(scalar) { |
| values("3.2700"); |
| } |
| rise_transition(scalar) { |
| values("0.7500"); |
| } |
| fall_transition(scalar) { |
| values("0.7500"); |
| } |
| } |
| |
| } |
| |
| bus(D2) { |
| bus_type : bits_64; |
| direction : output; |
| related_ground_pin : "VGND"; |
| related_power_pin : "VPWR"; |
| |
| max_capacitance : 0.130015; |
| max_transition : 1.5; |
| timing() { |
| related_pin : "D1"; |
| timing_type : rising_edge |
| cell_rise(scalar) { |
| values("3.4100"); |
| } |
| cell_fall(scalar) { |
| values("3.4100"); |
| } |
| rise_transition(scalar) { |
| values("0.7500"); |
| } |
| fall_transition(scalar) { |
| values("0.7500"); |
| } |
| } |
| |
| } |
| |
| bus(D3) { |
| bus_type : bits_64; |
| direction : output; |
| related_ground_pin : "VGND"; |
| related_power_pin : "VPWR"; |
| |
| max_capacitance : 0.130015; |
| max_transition : 1.5; |
| timing() { |
| related_pin : "D1"; |
| timing_type : rising_edge |
| cell_rise(scalar) { |
| values("3.3000"); |
| } |
| cell_fall(scalar) { |
| values("3.3000"); |
| } |
| rise_transition(scalar) { |
| values("0.7500"); |
| } |
| fall_transition(scalar) { |
| values("0.7500"); |
| } |
| } |
| |
| } |
| |
| bus(RW) { |
| bus_type : bits_7; |
| clock : false; |
| direction : input; |
| related_ground_pin : "VGND"; |
| related_power_pin : "VPWR"; |
| |
| capacitance : 0.002103; |
| rise_capacitance : 0.002191; |
| fall_capacitance : 0.002015; |
| max_transition : 1.5; |
| timing() { |
| timing_type : setup_rising; |
| related_pin : "CLK"; |
| rise_constraint(scalar) { |
| values("1.3300"); |
| } |
| fall_constraint(scalar) { |
| values("1.3300"); |
| } |
| } |
| |
| timing() { |
| timing_type : hold_rising; |
| related_pin : "CLK"; |
| rise_constraint(scalar) { |
| values("1.6800"); |
| } |
| fall_constraint(scalar) { |
| values("1.6800"); |
| } |
| } |
| |
| } |
| |
| pin(WE) { |
| clock : false; |
| direction : input; |
| related_ground_pin : "VGND"; |
| related_power_pin : "VPWR"; |
| |
| capacitance : 0.002103; |
| rise_capacitance : 0.002191; |
| fall_capacitance : 0.002015; |
| max_transition : 1.5; |
| timing() { |
| timing_type : setup_rising; |
| related_pin : "CLK"; |
| rise_constraint(scalar) { |
| values("1.2800"); |
| } |
| fall_constraint(scalar) { |
| values("1.2800"); |
| } |
| } |
| |
| timing() { |
| timing_type : hold_rising; |
| related_pin : "CLK"; |
| rise_constraint(scalar) { |
| values("1.7000"); |
| } |
| fall_constraint(scalar) { |
| values("1.7000"); |
| } |
| } |
| |
| } |
| |
| bus(DW) { |
| bus_type : bits_64; |
| clock : false; |
| direction : input; |
| related_ground_pin : "VGND"; |
| related_power_pin : "VPWR"; |
| |
| capacitance : 0.002103; |
| rise_capacitance : 0.002191; |
| fall_capacitance : 0.002015; |
| max_transition : 1.5; |
| timing() { |
| timing_type : setup_rising; |
| related_pin : "CLK"; |
| rise_constraint(scalar) { |
| values("-0.3400"); |
| } |
| fall_constraint(scalar) { |
| values("-0.3400"); |
| } |
| } |
| |
| timing() { |
| timing_type : hold_rising; |
| related_pin : "CLK"; |
| rise_constraint(scalar) { |
| values("1.6700"); |
| } |
| fall_constraint(scalar) { |
| values("1.6700"); |
| } |
| } |
| |
| } |
| |
| pin(CLK) { |
| clock : true; |
| direction : input; |
| related_ground_pin : "VGND"; |
| related_power_pin : "VPWR"; |
| |
| capacitance : 0.002103; |
| rise_capacitance : 0.002191; |
| fall_capacitance : 0.002015; |
| max_transition : 1.5; |
| } |
| } |
| } |