removed fake register
diff --git a/env.sh b/env.sh
deleted file mode 100755
index ba4f223..0000000
--- a/env.sh
+++ /dev/null
@@ -1,5 +0,0 @@
-
- # you need to export this whenever you start a new shell
-export OPENLANE_ROOT=../openlane
-
-export PDK_ROOT=../pdks
diff --git a/verilog/rtl/aes/generated/aes.v b/verilog/rtl/aes/generated/aes.v
index 10f1d9e..709bda1 100644
--- a/verilog/rtl/aes/generated/aes.v
+++ b/verilog/rtl/aes/generated/aes.v
@@ -1108,7 +1108,6 @@
reg [31:0] _RAND_22;
reg [31:0] _RAND_23;
reg [31:0] _RAND_24;
- reg [31:0] _RAND_25;
`endif // RANDOMIZE_REG_INIT
wire [31:0] moduloSbox_io_msg; // @[aes.scala 105:32]
wire [31:0] moduloSbox_io_msg_out; // @[aes.scala 105:32]
@@ -1204,7 +1203,6 @@
wire [31:0] _T_55 = _T_54 ? rego_3 : 32'h0; // @[Mux.scala 98:16]
wire [31:0] _T_56 = _T_53 ? rego_2 : _T_55; // @[Mux.scala 98:16]
wire [31:0] _T_57 = _T_52 ? rego_1 : _T_56; // @[Mux.scala 98:16]
- reg [31:0] cumbia; // @[aes.scala 110:29]
wire [7:0] _GEN_50 = 4'h1 == ronda ? 8'h2 : 8'h1; // @[Cat.scala 30:58 Cat.scala 30:58]
wire [7:0] _GEN_51 = 4'h2 == ronda ? 8'h4 : _GEN_50; // @[Cat.scala 30:58 Cat.scala 30:58]
wire [7:0] _GEN_52 = 4'h3 == ronda ? 8'h8 : _GEN_51; // @[Cat.scala 30:58 Cat.scala 30:58]
@@ -1221,8 +1219,8 @@
wire [7:0] _GEN_63 = 4'he == ronda ? 8'h0 : _GEN_62; // @[Cat.scala 30:58 Cat.scala 30:58]
wire [7:0] _GEN_64 = 4'hf == ronda ? 8'h0 : _GEN_63; // @[Cat.scala 30:58 Cat.scala 30:58]
wire [31:0] _T_58 = {_GEN_64,24'h0}; // @[Cat.scala 30:58]
- wire [31:0] _T_59 = _T_58 ^ cumbia; // @[aes.scala 115:50]
- wire [31:0] put0 = _T_59 ^ reg1K0; // @[aes.scala 115:59]
+ wire [31:0] _T_59 = _T_58 ^ moduloSbox_io_msg_out; // @[aes.scala 115:50]
+ wire [31:0] put0 = _T_59 ^ reg1K0; // @[aes.scala 115:74]
wire [31:0] put1 = put0 ^ reg1K1; // @[aes.scala 116:25]
wire [31:0] put2 = put1 ^ reg1K2; // @[aes.scala 117:25]
wire [31:0] put3 = put2 ^ reg1K3; // @[aes.scala 118:25]
@@ -1665,7 +1663,6 @@
end else begin
reg1K3 <= rego_7;
end
- cumbia <= moduloSbox_io_msg_out; // @[aes.scala 110:29]
if (reset) begin // @[aes.scala 176:46]
REG_1 <= 1'h0; // @[aes.scala 176:46]
end else begin
@@ -1757,9 +1754,7 @@
_RAND_23 = {1{`RANDOM}};
reg1K3 = _RAND_23[31:0];
_RAND_24 = {1{`RANDOM}};
- cumbia = _RAND_24[31:0];
- _RAND_25 = {1{`RANDOM}};
- REG_1 = _RAND_25[0:0];
+ REG_1 = _RAND_24[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
diff --git a/verilog/rtl/aes/src/main/scala/aes.scala b/verilog/rtl/aes/src/main/scala/aes.scala
index dc2c281..6e8f7c4 100644
--- a/verilog/rtl/aes/src/main/scala/aes.scala
+++ b/verilog/rtl/aes/src/main/scala/aes.scala
@@ -107,12 +107,12 @@
val moduloMix = Module(new mix)
moduloMix.io.msg := mux2MixARK
- val cumbia = RegNext(moduloSbox.io.msg_out)
+ //val cumbia = RegNext(moduloSbox.io.msg_out)
val rcon_pure: Seq[Int] = Seq(
0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1B, 0x36, 0x6C, 0xD8, 0x00, 0x00, 0x00, 0x00)
val rcon_hw = VecInit(rcon_pure.map(_.U(8.W)))
- val put0 = Cat(rcon_hw(ronda),0.U(24.W)) ^ cumbia ^ reg1K0
+ val put0 = Cat(rcon_hw(ronda),0.U(24.W)) ^ moduloSbox.io.msg_out ^ reg1K0
val put1 = put0 ^ reg1K1
val put2 = put1 ^ reg1K2
val put3 = put2 ^ reg1K3
diff --git a/verilog/rtl/aes/target/scala-2.12/arcabuco_2.12-1.0.jar b/verilog/rtl/aes/target/scala-2.12/arcabuco_2.12-1.0.jar
index 194be5b..2456df7 100644
--- a/verilog/rtl/aes/target/scala-2.12/arcabuco_2.12-1.0.jar
+++ b/verilog/rtl/aes/target/scala-2.12/arcabuco_2.12-1.0.jar
Binary files differ
diff --git a/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aes.class b/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aes.class
index d23f17c..d081987 100644
--- a/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aes.class
+++ b/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aes.class
Binary files differ
diff --git a/verilog/rtl/aes/target/streams/compile/compileIncSetup/$global/streams/inc_compile_2.12.zip b/verilog/rtl/aes/target/streams/compile/compileIncSetup/$global/streams/inc_compile_2.12.zip
index 114f857..64e5e4e 100644
--- a/verilog/rtl/aes/target/streams/compile/compileIncSetup/$global/streams/inc_compile_2.12.zip
+++ b/verilog/rtl/aes/target/streams/compile/compileIncSetup/$global/streams/inc_compile_2.12.zip
Binary files differ
diff --git a/verilog/rtl/aes/target/streams/compile/compileIncremental/$global/streams/out b/verilog/rtl/aes/target/streams/compile/compileIncremental/$global/streams/out
index 6ffdb13..fe4aa64 100644
--- a/verilog/rtl/aes/target/streams/compile/compileIncremental/$global/streams/out
+++ b/verilog/rtl/aes/target/streams/compile/compileIncremental/$global/streams/out
@@ -17,7 +17,7 @@
[0m[[0m[0minfo[0m] [0m[0mCompiling 1 Scala source to /home/askartos/sandbox/caravel_tutorial/fossiAES/verilog/rtl/aes/target/scala-2.12/classes ...[0m
[0m[[0m[0mdebug[0m] [0m[0mGetting org.scala-sbt:compiler-bridge_2.12:1.1.1:compile for Scala 2.12.6[0m
[0m[[0m[0mdebug[0m] [0m[0mGetting org.scala-sbt:compiler-bridge_2.12:1.1.1:compile for Scala 2.12.6[0m
-[0m[[0m[0mdebug[0m] [0m[0m[zinc] Running cached compiler 78994af3 for Scala compiler version 2.12.6[0m
+[0m[[0m[0mdebug[0m] [0m[0m[zinc] Running cached compiler 700041dc for Scala compiler version 2.12.6[0m
[0m[[0m[0mdebug[0m] [0m[0m[zinc] The Scala compiler is invoked with:[0m
[0m[[0m[0mdebug[0m] [0m[0m -Xsource:2.11[0m
[0m[[0m[0mdebug[0m] [0m[0m -language:reflectiveCalls[0m
@@ -30,8 +30,17 @@
[0m[[0m[0mdebug[0m] [0m[0m /usr/lib/jvm/java-8-oracle/jre/lib/resources.jar:/usr/lib/jvm/java-8-oracle/jre/lib/rt.jar:/usr/lib/jvm/java-8-oracle/jre/lib/sunrsasign.jar:/usr/lib/jvm/java-8-oracle/jre/lib/jsse.jar:/usr/lib/jvm/java-8-oracle/jre/lib/jce.jar:/usr/lib/jvm/java-8-oracle/jre/lib/charsets.jar:/usr/lib/jvm/java-8-oracle/jre/lib/jfr.jar:/usr/lib/jvm/java-8-oracle/jre/classes:/home/askartos/.ivy2/cache/org.scala-lang/scala-library/jars/scala-library-2.12.6.jar[0m
[0m[[0m[0mdebug[0m] [0m[0m -classpath[0m
[0m[[0m[0mdebug[0m] [0m[0m /home/askartos/sandbox/caravel_tutorial/fossiAES/verilog/rtl/aes/target/scala-2.12/classes:/home/askartos/.ivy2/cache/edu.berkeley.cs/chisel3_2.12/jars/chisel3_2.12-3.4.4.jar:/home/askartos/.ivy2/cache/edu.berkeley.cs/chisel3-macros_2.12/jars/chisel3-macros_2.12-3.4.4.jar:/home/askartos/.ivy2/cache/org.scala-lang/scala-reflect/jars/scala-reflect-2.12.6.jar:/home/askartos/.ivy2/cache/edu.berkeley.cs/chisel3-core_2.12/jars/chisel3-core_2.12-3.4.4.jar:/home/askartos/.ivy2/cache/edu.berkeley.cs/firrtl_2.12/jars/firrtl_2.12-1.4.4.jar:/home/askartos/.ivy2/cache/org.antlr/antlr4-runtime/jars/antlr4-runtime-4.7.1.jar:/home/askartos/.ivy2/cache/com.google.protobuf/protobuf-java/bundles/protobuf-java-3.9.0.jar:/home/askartos/.ivy2/cache/com.github.scopt/scopt_2.12/jars/scopt_2.12-3.7.1.jar:/home/askartos/.ivy2/cache/net.jcazevedo/moultingyaml_2.12/jars/moultingyaml_2.12-0.4.2.jar:/home/askartos/.ivy2/cache/com.github.nscala-time/nscala-time_2.12/jars/nscala-time_2.12-2.22.0.jar:/home/askartos/.ivy2/cache/joda-time/joda-time/jars/joda-time-2.10.1.jar:/home/askartos/.ivy2/cache/org.joda/joda-convert/jars/joda-convert-2.2.0.jar:/home/askartos/.ivy2/cache/org.yaml/snakeyaml/bundles/snakeyaml-1.26.jar:/home/askartos/.ivy2/cache/org.json4s/json4s-native_2.12/jars/json4s-native_2.12-3.6.9.jar:/home/askartos/.ivy2/cache/org.json4s/json4s-core_2.12/jars/json4s-core_2.12-3.6.9.jar:/home/askartos/.ivy2/cache/org.json4s/json4s-ast_2.12/jars/json4s-ast_2.12-3.6.9.jar:/home/askartos/.ivy2/cache/org.json4s/json4s-scalap_2.12/jars/json4s-scalap_2.12-3.6.9.jar:/home/askartos/.ivy2/cache/com.thoughtworks.paranamer/paranamer/bundles/paranamer-2.8.jar:/home/askartos/.ivy2/cache/org.apache.commons/commons-text/jars/commons-text-1.8.jar:/home/askartos/.ivy2/cache/org.apache.commons/commons-lang3/jars/commons-lang3-3.9.jar[0m
-[0m[[0m[0mdebug[0m] [0m[0mScala compilation took 6.243932755 s[0m
+[0m[[0m[0mdebug[0m] [0m[0mScala compilation took 7.722830117 s[0m
[0m[[0m[0minfo[0m] [0m[0mDone compiling.[0m
+[0m[[0m[0mdebug[0m] [0m[0mInvalidating (transitively) by inheritance from fossiAES.aes...[0m
+[0m[[0m[0mdebug[0m] [0m[0mInitial set of included nodes: Set(fossiAES.aes)[0m
+[0m[[0m[0mdebug[0m] [0m[0mInvalidated by transitive inheritance dependency: Set(fossiAES.aes)[0m
+[0m[[0m[0mdebug[0m] [0m[0mChange NamesChange(fossiAES.aes,ModifiedNames(changes = UsedName(cumbia,[Default]))) invalidates 1 classes due to The fossiAES.aes has the following regular definitions changed:[0m
+[0m[[0m[0mdebug[0m] [0m[0m UsedName(cumbia,[Default]).[0m
+[0m[[0m[0mdebug[0m] [0m[0m > by transitive inheritance: Set(fossiAES.aes)[0m
+[0m[[0m[0mdebug[0m] [0m[0m > [0m
+[0m[[0m[0mdebug[0m] [0m[0m > [0m
+[0m[[0m[0mdebug[0m] [0m[0m [0m
[0m[[0m[0mdebug[0m] [0m[0mNew invalidations:[0m
[0m[[0m[0mdebug[0m] [0m[0m Set()[0m
[0m[[0m[0mdebug[0m] [0m[0mInitial set of included nodes: Set()[0m
diff --git a/verilog/rtl/aes/target/streams/compile/packageBin/$global/streams/inputs b/verilog/rtl/aes/target/streams/compile/packageBin/$global/streams/inputs
index b1c0187..99213fd 100644
--- a/verilog/rtl/aes/target/streams/compile/packageBin/$global/streams/inputs
+++ b/verilog/rtl/aes/target/streams/compile/packageBin/$global/streams/inputs
@@ -1 +1 @@
--400517001
\ No newline at end of file
+1634551659
\ No newline at end of file
