commit 5ffeb9f2526e12ebff744da1b8c7c04948239671
author Hanssel <hanssel1301@hotmail.com> Thu Jun 02 21:05:06 2022 -0500
committer Hanssel <hanssel1301@hotmail.com> Thu Jun 02 21:05:06 2022 -0500
tree 9b092a3d7f00d33bfd395b753d9c0ade3e45903c
parent fcb04ec2a88e86df987a8333489ca8c1e5ba9d29

aest_test makefile issue

verilog/dv/aes_test/Makefile

diff --git a/verilog/dv/aes_test/Makefile b/verilog/dv/aes_test/Makefile
index 70ad30a..483de8e 100644
--- a/verilog/dv/aes_test/Makefile
+++ b/verilog/dv/aes_test/Makefile
@@ -27,8 +27,6 @@
 include $(MCW_ROOT)/verilog/dv/make/env.makefile
 include $(MCW_ROOT)/verilog/dv/make/var.makefile
 include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
-$(info ============= compiling =================)
-$(info SOURCE_FILES=$(SOURCE_FILES) )
 SOURCE_FILES := $(SOURCE_FILES) $(shell pwd)/tiny-AES-c/aes.c
 $(info SOURCE_FILES=$(SOURCE_FILES) )
 include $(MCW_ROOT)/verilog/dv/make/sim.makefile