wb its alive
diff --git a/verilog/rtl/aes/generated/aes.v b/verilog/rtl/aes/generated/aes.v index 339b246..071dcf8 100644 --- a/verilog/rtl/aes/generated/aes.v +++ b/verilog/rtl/aes/generated/aes.v
@@ -1121,9 +1121,9 @@ reg [31:0] rego_8; // @[aes.scala 25:26] reg [3:0] state; // @[aes.scala 34:28] wire busy = state != 4'h0; // @[aes.scala 35:33] - wire _T_167 = ~busy; // @[aes.scala 190:34] - wire [30:0] _T_168 = {30'h0,_T_167}; // @[Cat.scala 30:58] - wire [31:0] regi_0 = {{1'd0}, _T_168}; // @[aes.scala 26:24 aes.scala 190:17] + wire _T_166 = ~busy; // @[aes.scala 190:34] + wire [30:0] _T_167 = {30'h0,_T_166}; // @[Cat.scala 30:58] + wire [31:0] regi_0 = {{1'd0}, _T_167}; // @[aes.scala 26:24 aes.scala 190:17] wire [319:0] _T_1 = {regi_0,rego_8,rego_7,rego_6,rego_5,rego_4,rego_3,rego_2,rego_1,rego_0}; // @[Cat.scala 30:58] wire [415:0] _WIRE_2 = {{96'd0}, _T_1}; wire [31:0] full_regs_0 = _WIRE_2[31:0]; // @[aes.scala 30:65] @@ -1143,11 +1143,10 @@ wire [7:0] mask_1 = io_wbs_sel_i[1] ? 8'hff : 8'h0; // @[aes.scala 39:39 aes.scala 40:24 aes.scala 42:32] wire [7:0] mask_2 = io_wbs_sel_i[2] ? 8'hff : 8'h0; // @[aes.scala 39:39 aes.scala 40:24 aes.scala 42:32] wire [7:0] mask_3 = io_wbs_sel_i[3] ? 8'hff : 8'h0; // @[aes.scala 39:39 aes.scala 40:24 aes.scala 42:32] - wire [31:0] _T_20 = io_wbs_adr_i - 32'h20000080; // @[aes.scala 48:29] - wire [31:0] _T_25 = io_wbs_adr_i & 32'hff000000; // @[aes.scala 50:60] - wire valid = io_wbs_stb_i & _T_167 & _T_25 == 32'h20000000; // @[aes.scala 50:42] + wire [31:0] _T_20 = io_wbs_adr_i - 32'h30000000; // @[aes.scala 48:29] + wire [31:0] _T_26 = io_wbs_adr_i & 32'hff000000; // @[aes.scala 50:75] + wire valid = io_wbs_stb_i & io_wbs_cyc_i & _T_166 & _T_26 == 32'h30000000; // @[aes.scala 50:57] reg ack; // @[aes.scala 52:26] - wire _T_29 = valid & io_wbs_cyc_i; // @[aes.scala 56:14] wire [31:0] _T_31 = {mask_3,mask_2,mask_1,mask_0}; // @[aes.scala 57:69] wire [3:0] addr = _T_20[5:2]; // @[aes.scala 47:18 aes.scala 48:13] wire [31:0] _GEN_5 = 4'h1 == addr ? rego_1 : rego_0; // @[aes.scala 57:59 aes.scala 57:59] @@ -1180,23 +1179,23 @@ reg [2:0] selMuxSbox; // @[aes.scala 78:34] reg [1:0] selMuxMixARK; // @[aes.scala 79:34] reg [1:0] selKey; // @[aes.scala 80:50] - wire _T_40 = selMuxSbox == 3'h0; // @[aes.scala 94:29] - wire _T_41 = selMuxSbox == 3'h1; // @[aes.scala 95:29] - wire _T_42 = selMuxSbox == 3'h2; // @[aes.scala 96:29] - wire _T_43 = selMuxSbox == 3'h3; // @[aes.scala 97:29] - wire _T_44 = selMuxSbox == 3'h4; // @[aes.scala 98:29] - wire [31:0] _T_47 = {rego_7[23:0],rego_7[31:24]}; // @[Cat.scala 30:58] - wire [31:0] _T_48 = _T_44 ? _T_47 : 32'h0; // @[Mux.scala 98:16] - wire [31:0] _T_49 = _T_43 ? rego_3 : _T_48; // @[Mux.scala 98:16] - wire [31:0] _T_50 = _T_42 ? rego_2 : _T_49; // @[Mux.scala 98:16] - wire [31:0] _T_51 = _T_41 ? rego_1 : _T_50; // @[Mux.scala 98:16] - wire _T_52 = selMuxMixARK == 2'h0; // @[aes.scala 100:31] - wire _T_53 = selMuxMixARK == 2'h1; // @[aes.scala 101:31] - wire _T_54 = selMuxMixARK == 2'h2; // @[aes.scala 102:31] - wire _T_55 = selMuxMixARK == 2'h3; // @[aes.scala 103:31] - wire [31:0] _T_56 = _T_55 ? rego_3 : 32'h0; // @[Mux.scala 98:16] - wire [31:0] _T_57 = _T_54 ? rego_2 : _T_56; // @[Mux.scala 98:16] - wire [31:0] _T_58 = _T_53 ? rego_1 : _T_57; // @[Mux.scala 98:16] + wire _T_39 = selMuxSbox == 3'h0; // @[aes.scala 94:29] + wire _T_40 = selMuxSbox == 3'h1; // @[aes.scala 95:29] + wire _T_41 = selMuxSbox == 3'h2; // @[aes.scala 96:29] + wire _T_42 = selMuxSbox == 3'h3; // @[aes.scala 97:29] + wire _T_43 = selMuxSbox == 3'h4; // @[aes.scala 98:29] + wire [31:0] _T_46 = {rego_7[23:0],rego_7[31:24]}; // @[Cat.scala 30:58] + wire [31:0] _T_47 = _T_43 ? _T_46 : 32'h0; // @[Mux.scala 98:16] + wire [31:0] _T_48 = _T_42 ? rego_3 : _T_47; // @[Mux.scala 98:16] + wire [31:0] _T_49 = _T_41 ? rego_2 : _T_48; // @[Mux.scala 98:16] + wire [31:0] _T_50 = _T_40 ? rego_1 : _T_49; // @[Mux.scala 98:16] + wire _T_51 = selMuxMixARK == 2'h0; // @[aes.scala 100:31] + wire _T_52 = selMuxMixARK == 2'h1; // @[aes.scala 101:31] + wire _T_53 = selMuxMixARK == 2'h2; // @[aes.scala 102:31] + wire _T_54 = selMuxMixARK == 2'h3; // @[aes.scala 103:31] + wire [31:0] _T_55 = _T_54 ? rego_3 : 32'h0; // @[Mux.scala 98:16] + wire [31:0] _T_56 = _T_53 ? rego_2 : _T_55; // @[Mux.scala 98:16] + wire [31:0] _T_57 = _T_52 ? rego_1 : _T_56; // @[Mux.scala 98:16] reg [31:0] cumbia; // @[aes.scala 110:29] wire [7:0] _GEN_46 = 4'h1 == ronda ? 8'h2 : 8'h1; // @[Cat.scala 30:58 Cat.scala 30:58] wire [7:0] _GEN_47 = 4'h2 == ronda ? 8'h4 : _GEN_46; // @[Cat.scala 30:58 Cat.scala 30:58] @@ -1213,158 +1212,158 @@ wire [7:0] _GEN_58 = 4'hd == ronda ? 8'h0 : _GEN_57; // @[Cat.scala 30:58 Cat.scala 30:58] wire [7:0] _GEN_59 = 4'he == ronda ? 8'h0 : _GEN_58; // @[Cat.scala 30:58 Cat.scala 30:58] wire [7:0] _GEN_60 = 4'hf == ronda ? 8'h0 : _GEN_59; // @[Cat.scala 30:58 Cat.scala 30:58] - wire [31:0] _T_59 = {_GEN_60,24'h0}; // @[Cat.scala 30:58] - wire [31:0] _T_60 = _T_59 ^ cumbia; // @[aes.scala 115:50] - wire [31:0] put0 = _T_60 ^ rego_4; // @[aes.scala 115:59] + wire [31:0] _T_58 = {_GEN_60,24'h0}; // @[Cat.scala 30:58] + wire [31:0] _T_59 = _T_58 ^ cumbia; // @[aes.scala 115:50] + wire [31:0] put0 = _T_59 ^ rego_4; // @[aes.scala 115:59] wire [31:0] put1 = put0 ^ rego_5; // @[aes.scala 116:25] wire [31:0] put2 = put1 ^ rego_6; // @[aes.scala 117:25] wire [31:0] put3 = put2 ^ rego_7; // @[aes.scala 118:25] - wire _T_61 = selKey == 2'h0; // @[aes.scala 121:31] - wire _T_62 = selKey == 2'h1; // @[aes.scala 122:43] - wire [31:0] _T_77 = _T_55 ? rego_7 : 32'h0; // @[Mux.scala 98:16] - wire [31:0] _T_78 = _T_54 ? rego_6 : _T_77; // @[Mux.scala 98:16] - wire [31:0] _T_79 = _T_53 ? rego_5 : _T_78; // @[Mux.scala 98:16] - wire [31:0] key_out = _T_52 ? rego_4 : _T_79; // @[Mux.scala 98:16] + wire _T_60 = selKey == 2'h0; // @[aes.scala 121:31] + wire _T_61 = selKey == 2'h1; // @[aes.scala 122:43] + wire [31:0] _T_76 = _T_54 ? rego_7 : 32'h0; // @[Mux.scala 98:16] + wire [31:0] _T_77 = _T_53 ? rego_6 : _T_76; // @[Mux.scala 98:16] + wire [31:0] _T_78 = _T_52 ? rego_5 : _T_77; // @[Mux.scala 98:16] + wire [31:0] key_out = _T_51 ? rego_4 : _T_78; // @[Mux.scala 98:16] wire [31:0] moduloARK = moduloMix_io_msg_out ^ key_out; // @[aes.scala 138:46] wire [31:0] arkW0 = rego_0 ^ rego_4; // @[aes.scala 140:28] wire [31:0] arkW1 = rego_1 ^ rego_5; // @[aes.scala 141:28] wire [31:0] arkW2 = rego_2 ^ rego_6; // @[aes.scala 142:28] wire [31:0] arkW3 = rego_3 ^ rego_7; // @[aes.scala 143:28] wire [31:0] auxiliary = key_out ^ moduloSbox_io_msg_out; // @[aes.scala 145:33] - wire _T_80 = selMux1W0 == 3'h0; // @[aes.scala 148:28] - wire _T_81 = selMux1W0 == 3'h1; // @[aes.scala 149:28] - wire _T_82 = selMux1W0 == 3'h2; // @[aes.scala 150:28] - wire _T_83 = selMux1W0 == 3'h3; // @[aes.scala 151:28] - wire [31:0] _T_88 = {rego_0[31:24],rego_1[23:16],rego_2[15:8],moduloARK[7:0]}; // @[Cat.scala 30:58] - wire _T_89 = selMux1W0 == 3'h4; // @[aes.scala 152:28] - wire [31:0] _T_94 = {arkW0[31:24],arkW1[23:16],arkW2[15:8],arkW3[7:0]}; // @[Cat.scala 30:58] - wire _T_95 = selMux1W0 == 3'h5; // @[aes.scala 153:28] - wire [31:0] _T_96 = _T_95 ? auxiliary : 32'h0; // @[Mux.scala 98:16] - wire [31:0] _T_97 = _T_89 ? _T_94 : _T_96; // @[Mux.scala 98:16] - wire [31:0] _T_98 = _T_83 ? _T_88 : _T_97; // @[Mux.scala 98:16] - wire [31:0] _T_99 = _T_82 ? moduloARK : _T_98; // @[Mux.scala 98:16] - wire _T_101 = selMux1W1 == 3'h0; // @[aes.scala 155:28] - wire _T_102 = selMux1W1 == 3'h1; // @[aes.scala 156:28] - wire _T_103 = selMux1W1 == 3'h2; // @[aes.scala 157:28] - wire _T_104 = selMux1W1 == 3'h3; // @[aes.scala 158:28] - wire [31:0] _T_109 = {rego_1[31:24],rego_2[23:16],moduloARK[15:8],rego_0[7:0]}; // @[Cat.scala 30:58] - wire [31:0] _T_115 = {arkW1[31:24],arkW2[23:16],arkW3[15:8],arkW0[7:0]}; // @[Cat.scala 30:58] - wire _T_116 = selMux1W1 == 3'h5; // @[aes.scala 160:28] - wire [31:0] _T_117 = _T_116 ? auxiliary : 32'h0; // @[Mux.scala 98:16] - wire [31:0] _T_118 = _T_89 ? _T_115 : _T_117; // @[Mux.scala 98:16] - wire [31:0] _T_119 = _T_104 ? _T_109 : _T_118; // @[Mux.scala 98:16] - wire [31:0] _T_120 = _T_103 ? moduloARK : _T_119; // @[Mux.scala 98:16] - wire _T_122 = selMux1W2 == 3'h0; // @[aes.scala 162:28] - wire _T_123 = selMux1W2 == 3'h1; // @[aes.scala 163:28] - wire _T_124 = selMux1W2 == 3'h2; // @[aes.scala 164:28] - wire _T_125 = selMux1W2 == 3'h3; // @[aes.scala 165:28] - wire [31:0] _T_130 = {rego_2[31:24],moduloARK[23:16],rego_0[15:8],rego_1[7:0]}; // @[Cat.scala 30:58] - wire [31:0] _T_136 = {arkW2[31:24],arkW3[23:16],arkW0[15:8],arkW1[7:0]}; // @[Cat.scala 30:58] - wire _T_137 = selMux1W2 == 3'h5; // @[aes.scala 167:28] - wire [31:0] _T_138 = _T_137 ? auxiliary : 32'h0; // @[Mux.scala 98:16] - wire [31:0] _T_139 = _T_89 ? _T_136 : _T_138; // @[Mux.scala 98:16] - wire [31:0] _T_140 = _T_125 ? _T_130 : _T_139; // @[Mux.scala 98:16] - wire [31:0] _T_141 = _T_124 ? moduloARK : _T_140; // @[Mux.scala 98:16] - wire _T_143 = selMux1W3 == 3'h0; // @[aes.scala 169:28] - wire _T_144 = selMux1W3 == 3'h1; // @[aes.scala 170:28] - wire _T_145 = selMux1W3 == 3'h2; // @[aes.scala 171:28] - wire _T_146 = selMux1W3 == 3'h3; // @[aes.scala 172:28] - wire [31:0] _T_151 = {moduloARK[31:24],rego_0[23:16],rego_1[15:8],rego_2[7:0]}; // @[Cat.scala 30:58] - wire [31:0] _T_157 = {arkW3[31:24],arkW0[23:16],arkW1[15:8],arkW2[7:0]}; // @[Cat.scala 30:58] - wire _T_158 = selMux1W3 == 3'h5; // @[aes.scala 174:28] - wire [31:0] _T_159 = _T_158 ? auxiliary : 32'h0; // @[Mux.scala 98:16] - wire [31:0] _T_160 = _T_89 ? _T_157 : _T_159; // @[Mux.scala 98:16] - wire [31:0] _T_161 = _T_146 ? _T_151 : _T_160; // @[Mux.scala 98:16] - wire [31:0] _T_162 = _T_145 ? moduloARK : _T_161; // @[Mux.scala 98:16] + wire _T_79 = selMux1W0 == 3'h0; // @[aes.scala 148:28] + wire _T_80 = selMux1W0 == 3'h1; // @[aes.scala 149:28] + wire _T_81 = selMux1W0 == 3'h2; // @[aes.scala 150:28] + wire _T_82 = selMux1W0 == 3'h3; // @[aes.scala 151:28] + wire [31:0] _T_87 = {rego_0[31:24],rego_1[23:16],rego_2[15:8],moduloARK[7:0]}; // @[Cat.scala 30:58] + wire _T_88 = selMux1W0 == 3'h4; // @[aes.scala 152:28] + wire [31:0] _T_93 = {arkW0[31:24],arkW1[23:16],arkW2[15:8],arkW3[7:0]}; // @[Cat.scala 30:58] + wire _T_94 = selMux1W0 == 3'h5; // @[aes.scala 153:28] + wire [31:0] _T_95 = _T_94 ? auxiliary : 32'h0; // @[Mux.scala 98:16] + wire [31:0] _T_96 = _T_88 ? _T_93 : _T_95; // @[Mux.scala 98:16] + wire [31:0] _T_97 = _T_82 ? _T_87 : _T_96; // @[Mux.scala 98:16] + wire [31:0] _T_98 = _T_81 ? moduloARK : _T_97; // @[Mux.scala 98:16] + wire _T_100 = selMux1W1 == 3'h0; // @[aes.scala 155:28] + wire _T_101 = selMux1W1 == 3'h1; // @[aes.scala 156:28] + wire _T_102 = selMux1W1 == 3'h2; // @[aes.scala 157:28] + wire _T_103 = selMux1W1 == 3'h3; // @[aes.scala 158:28] + wire [31:0] _T_108 = {rego_1[31:24],rego_2[23:16],moduloARK[15:8],rego_0[7:0]}; // @[Cat.scala 30:58] + wire [31:0] _T_114 = {arkW1[31:24],arkW2[23:16],arkW3[15:8],arkW0[7:0]}; // @[Cat.scala 30:58] + wire _T_115 = selMux1W1 == 3'h5; // @[aes.scala 160:28] + wire [31:0] _T_116 = _T_115 ? auxiliary : 32'h0; // @[Mux.scala 98:16] + wire [31:0] _T_117 = _T_88 ? _T_114 : _T_116; // @[Mux.scala 98:16] + wire [31:0] _T_118 = _T_103 ? _T_108 : _T_117; // @[Mux.scala 98:16] + wire [31:0] _T_119 = _T_102 ? moduloARK : _T_118; // @[Mux.scala 98:16] + wire _T_121 = selMux1W2 == 3'h0; // @[aes.scala 162:28] + wire _T_122 = selMux1W2 == 3'h1; // @[aes.scala 163:28] + wire _T_123 = selMux1W2 == 3'h2; // @[aes.scala 164:28] + wire _T_124 = selMux1W2 == 3'h3; // @[aes.scala 165:28] + wire [31:0] _T_129 = {rego_2[31:24],moduloARK[23:16],rego_0[15:8],rego_1[7:0]}; // @[Cat.scala 30:58] + wire [31:0] _T_135 = {arkW2[31:24],arkW3[23:16],arkW0[15:8],arkW1[7:0]}; // @[Cat.scala 30:58] + wire _T_136 = selMux1W2 == 3'h5; // @[aes.scala 167:28] + wire [31:0] _T_137 = _T_136 ? auxiliary : 32'h0; // @[Mux.scala 98:16] + wire [31:0] _T_138 = _T_88 ? _T_135 : _T_137; // @[Mux.scala 98:16] + wire [31:0] _T_139 = _T_124 ? _T_129 : _T_138; // @[Mux.scala 98:16] + wire [31:0] _T_140 = _T_123 ? moduloARK : _T_139; // @[Mux.scala 98:16] + wire _T_142 = selMux1W3 == 3'h0; // @[aes.scala 169:28] + wire _T_143 = selMux1W3 == 3'h1; // @[aes.scala 170:28] + wire _T_144 = selMux1W3 == 3'h2; // @[aes.scala 171:28] + wire _T_145 = selMux1W3 == 3'h3; // @[aes.scala 172:28] + wire [31:0] _T_150 = {moduloARK[31:24],rego_0[23:16],rego_1[15:8],rego_2[7:0]}; // @[Cat.scala 30:58] + wire [31:0] _T_156 = {arkW3[31:24],arkW0[23:16],arkW1[15:8],arkW2[7:0]}; // @[Cat.scala 30:58] + wire _T_157 = selMux1W3 == 3'h5; // @[aes.scala 174:28] + wire [31:0] _T_158 = _T_157 ? auxiliary : 32'h0; // @[Mux.scala 98:16] + wire [31:0] _T_159 = _T_88 ? _T_156 : _T_158; // @[Mux.scala 98:16] + wire [31:0] _T_160 = _T_145 ? _T_150 : _T_159; // @[Mux.scala 98:16] + wire [31:0] _T_161 = _T_144 ? moduloARK : _T_160; // @[Mux.scala 98:16] reg REG_1; // @[aes.scala 176:46] wire start = rego_8[0] & ~REG_1; // @[aes.scala 176:35] - wire _T_169 = 4'h0 == state; // @[Conditional.scala 37:30] - wire _T_170 = 4'h1 == state; // @[Conditional.scala 37:30] - wire _T_171 = 4'h2 == state; // @[Conditional.scala 37:30] - wire _T_172 = 4'h3 == state; // @[Conditional.scala 37:30] - wire _T_173 = 4'h4 == state; // @[Conditional.scala 37:30] - wire _T_174 = 4'h5 == state; // @[Conditional.scala 37:30] - wire [3:0] _T_176 = ronda + 4'h1; // @[aes.scala 262:50] - wire _T_177 = 4'h6 == state; // @[Conditional.scala 37:30] + wire _T_168 = 4'h0 == state; // @[Conditional.scala 37:30] + wire _T_169 = 4'h1 == state; // @[Conditional.scala 37:30] + wire _T_170 = 4'h2 == state; // @[Conditional.scala 37:30] + wire _T_171 = 4'h3 == state; // @[Conditional.scala 37:30] + wire _T_172 = 4'h4 == state; // @[Conditional.scala 37:30] + wire _T_173 = 4'h5 == state; // @[Conditional.scala 37:30] + wire [3:0] _T_175 = ronda + 4'h1; // @[aes.scala 262:50] + wire _T_176 = 4'h6 == state; // @[Conditional.scala 37:30] wire [3:0] _GEN_75 = ronda <= 4'h8 ? 4'h2 : 4'h7; // @[aes.scala 272:45 aes.scala 273:41 aes.scala 283:41] wire [3:0] _GEN_76 = ronda <= 4'h8 ? ronda : 4'h0; // @[aes.scala 272:45 aes.scala 274:41 aes.scala 284:49] wire [2:0] _GEN_77 = ronda <= 4'h8 ? 3'h1 : 3'h5; // @[aes.scala 272:45 aes.scala 275:49 aes.scala 285:49] - wire _T_179 = 4'h7 == state; // @[Conditional.scala 37:30] - wire _T_180 = 4'h8 == state; // @[Conditional.scala 37:30] - wire _T_181 = 4'h9 == state; // @[Conditional.scala 37:30] - wire _T_182 = 4'ha == state; // @[Conditional.scala 37:30] - wire [3:0] _GEN_79 = _T_182 ? 4'h0 : state; // @[Conditional.scala 39:67 aes.scala 328:33 aes.scala 34:28] - wire [3:0] _GEN_80 = _T_182 ? 4'h0 : ronda; // @[Conditional.scala 39:67 aes.scala 329:41 aes.scala 73:50] - wire [2:0] _GEN_81 = _T_182 ? 3'h0 : selMux1W0; // @[Conditional.scala 39:67 aes.scala 330:41 aes.scala 74:34] - wire [2:0] _GEN_82 = _T_182 ? 3'h0 : selMux1W1; // @[Conditional.scala 39:67 aes.scala 331:41 aes.scala 75:34] - wire [2:0] _GEN_83 = _T_182 ? 3'h0 : selMux1W2; // @[Conditional.scala 39:67 aes.scala 332:41 aes.scala 76:34] - wire [2:0] _GEN_84 = _T_182 ? 3'h0 : selMux1W3; // @[Conditional.scala 39:67 aes.scala 333:41 aes.scala 77:34] - wire [2:0] _GEN_85 = _T_182 ? 3'h4 : selMuxSbox; // @[Conditional.scala 39:67 aes.scala 334:41 aes.scala 78:34] - wire [1:0] _GEN_86 = _T_182 ? 2'h0 : selMuxMixARK; // @[Conditional.scala 39:67 aes.scala 335:37 aes.scala 79:34] - wire [1:0] _GEN_87 = _T_182 ? 2'h0 : selKey; // @[Conditional.scala 39:67 aes.scala 336:41 aes.scala 80:50] - wire [3:0] _GEN_88 = _T_181 ? 4'ha : _GEN_79; // @[Conditional.scala 39:67 aes.scala 317:41] - wire [3:0] _GEN_89 = _T_181 ? 4'h0 : _GEN_80; // @[Conditional.scala 39:67 aes.scala 318:41] - wire [2:0] _GEN_90 = _T_181 ? 3'h0 : _GEN_81; // @[Conditional.scala 39:67 aes.scala 319:41] - wire [2:0] _GEN_91 = _T_181 ? 3'h0 : _GEN_82; // @[Conditional.scala 39:67 aes.scala 320:41] - wire [2:0] _GEN_92 = _T_181 ? 3'h0 : _GEN_83; // @[Conditional.scala 39:67 aes.scala 321:41] - wire [2:0] _GEN_93 = _T_181 ? 3'h5 : _GEN_84; // @[Conditional.scala 39:67 aes.scala 322:41] - wire [2:0] _GEN_94 = _T_181 ? 3'h3 : _GEN_85; // @[Conditional.scala 39:67 aes.scala 323:41] - wire [1:0] _GEN_95 = _T_181 ? 2'h3 : _GEN_86; // @[Conditional.scala 39:67 aes.scala 324:37] - wire [1:0] _GEN_96 = _T_181 ? 2'h0 : _GEN_87; // @[Conditional.scala 39:67 aes.scala 325:41] - wire [3:0] _GEN_97 = _T_180 ? 4'h9 : _GEN_88; // @[Conditional.scala 39:67 aes.scala 306:41] - wire [3:0] _GEN_98 = _T_180 ? 4'h0 : _GEN_89; // @[Conditional.scala 39:67 aes.scala 307:41] - wire [2:0] _GEN_99 = _T_180 ? 3'h0 : _GEN_90; // @[Conditional.scala 39:67 aes.scala 308:41] - wire [2:0] _GEN_100 = _T_180 ? 3'h0 : _GEN_91; // @[Conditional.scala 39:67 aes.scala 309:41] - wire [2:0] _GEN_101 = _T_180 ? 3'h5 : _GEN_92; // @[Conditional.scala 39:67 aes.scala 310:41] - wire [2:0] _GEN_102 = _T_180 ? 3'h0 : _GEN_93; // @[Conditional.scala 39:67 aes.scala 311:41] - wire [2:0] _GEN_103 = _T_180 ? 3'h2 : _GEN_94; // @[Conditional.scala 39:67 aes.scala 312:41] - wire [1:0] _GEN_104 = _T_180 ? 2'h2 : _GEN_95; // @[Conditional.scala 39:67 aes.scala 313:37] - wire [1:0] _GEN_105 = _T_180 ? 2'h0 : _GEN_96; // @[Conditional.scala 39:67 aes.scala 314:41] - wire [3:0] _GEN_106 = _T_179 ? 4'h8 : _GEN_97; // @[Conditional.scala 39:67 aes.scala 295:41] - wire [3:0] _GEN_107 = _T_179 ? 4'h0 : _GEN_98; // @[Conditional.scala 39:67 aes.scala 296:41] - wire [2:0] _GEN_108 = _T_179 ? 3'h0 : _GEN_99; // @[Conditional.scala 39:67 aes.scala 297:41] - wire [2:0] _GEN_109 = _T_179 ? 3'h5 : _GEN_100; // @[Conditional.scala 39:67 aes.scala 298:41] - wire [2:0] _GEN_110 = _T_179 ? 3'h0 : _GEN_101; // @[Conditional.scala 39:67 aes.scala 299:41] - wire [2:0] _GEN_111 = _T_179 ? 3'h0 : _GEN_102; // @[Conditional.scala 39:67 aes.scala 300:41] - wire [2:0] _GEN_112 = _T_179 ? 3'h1 : _GEN_103; // @[Conditional.scala 39:67 aes.scala 301:41] - wire [1:0] _GEN_113 = _T_179 ? 2'h1 : _GEN_104; // @[Conditional.scala 39:67 aes.scala 302:37] - wire [1:0] _GEN_114 = _T_179 ? 2'h0 : _GEN_105; // @[Conditional.scala 39:67 aes.scala 303:41] - wire [3:0] _GEN_115 = _T_177 ? _GEN_75 : _GEN_106; // @[Conditional.scala 39:67] - wire [3:0] _GEN_116 = _T_177 ? _GEN_76 : _GEN_107; // @[Conditional.scala 39:67] - wire [2:0] _GEN_117 = _T_177 ? _GEN_77 : _GEN_108; // @[Conditional.scala 39:67] - wire [2:0] _GEN_118 = _T_177 ? 3'h0 : _GEN_109; // @[Conditional.scala 39:67] - wire [2:0] _GEN_119 = _T_177 ? 3'h0 : _GEN_110; // @[Conditional.scala 39:67] - wire [2:0] _GEN_120 = _T_177 ? 3'h0 : _GEN_111; // @[Conditional.scala 39:67] - wire [2:0] _GEN_121 = _T_177 ? 3'h0 : _GEN_112; // @[Conditional.scala 39:67] - wire [1:0] _GEN_122 = _T_177 ? 2'h0 : _GEN_113; // @[Conditional.scala 39:67] - wire [1:0] _GEN_123 = _T_177 ? 2'h0 : _GEN_114; // @[Conditional.scala 39:67] - wire [3:0] _GEN_124 = _T_174 ? 4'h6 : _GEN_115; // @[Conditional.scala 39:67 aes.scala 261:41] - wire [3:0] _GEN_125 = _T_174 ? _T_176 : _GEN_116; // @[Conditional.scala 39:67 aes.scala 262:41] - wire [2:0] _GEN_126 = _T_174 ? 3'h3 : _GEN_117; // @[Conditional.scala 39:67 aes.scala 263:41] - wire [2:0] _GEN_127 = _T_174 ? 3'h3 : _GEN_118; // @[Conditional.scala 39:67 aes.scala 264:41] - wire [2:0] _GEN_128 = _T_174 ? 3'h3 : _GEN_119; // @[Conditional.scala 39:67 aes.scala 265:41] - wire [2:0] _GEN_129 = _T_174 ? 3'h3 : _GEN_120; // @[Conditional.scala 39:67 aes.scala 266:41] - wire [2:0] _GEN_130 = _T_174 ? 3'h4 : _GEN_121; // @[Conditional.scala 39:67 aes.scala 267:41] - wire [1:0] _GEN_131 = _T_174 ? 2'h3 : _GEN_122; // @[Conditional.scala 39:67 aes.scala 268:37] - wire [1:0] _GEN_132 = _T_174 ? 2'h1 : _GEN_123; // @[Conditional.scala 39:67 aes.scala 269:41] - wire [3:0] _GEN_133 = _T_173 ? 4'h5 : _GEN_124; // @[Conditional.scala 39:67 aes.scala 250:41] - wire [3:0] _GEN_134 = _T_173 ? ronda : _GEN_125; // @[Conditional.scala 39:67 aes.scala 251:41] - wire [2:0] _GEN_135 = _T_173 ? 3'h0 : _GEN_126; // @[Conditional.scala 39:67 aes.scala 252:41] - wire [2:0] _GEN_136 = _T_173 ? 3'h0 : _GEN_127; // @[Conditional.scala 39:67 aes.scala 253:41] - wire [2:0] _GEN_137 = _T_173 ? 3'h2 : _GEN_128; // @[Conditional.scala 39:67 aes.scala 254:41] - wire [2:0] _GEN_138 = _T_173 ? 3'h1 : _GEN_129; // @[Conditional.scala 39:67 aes.scala 255:41] - wire [2:0] _GEN_139 = _T_173 ? 3'h3 : _GEN_130; // @[Conditional.scala 39:67 aes.scala 256:41] - wire [1:0] _GEN_140 = _T_173 ? 2'h2 : _GEN_131; // @[Conditional.scala 39:67 aes.scala 257:37] - wire [1:0] _GEN_141 = _T_173 ? 2'h0 : _GEN_132; // @[Conditional.scala 39:67 aes.scala 258:41] - wire [3:0] _GEN_142 = _T_172 ? 4'h4 : _GEN_133; // @[Conditional.scala 39:67 aes.scala 239:41] - wire [3:0] _GEN_143 = _T_172 ? ronda : _GEN_134; // @[Conditional.scala 39:67 aes.scala 240:41] - wire [2:0] _GEN_144 = _T_172 ? 3'h0 : _GEN_135; // @[Conditional.scala 39:67 aes.scala 241:41] - wire [2:0] _GEN_145 = _T_172 ? 3'h2 : _GEN_136; // @[Conditional.scala 39:67 aes.scala 242:41] - wire [2:0] _GEN_146 = _T_172 ? 3'h1 : _GEN_137; // @[Conditional.scala 39:67 aes.scala 243:41] - wire [2:0] _GEN_147 = _T_172 ? 3'h0 : _GEN_138; // @[Conditional.scala 39:67 aes.scala 244:41] - wire [2:0] _GEN_148 = _T_172 ? 3'h2 : _GEN_139; // @[Conditional.scala 39:67 aes.scala 245:41] - wire [1:0] _GEN_149 = _T_172 ? 2'h1 : _GEN_140; // @[Conditional.scala 39:67 aes.scala 246:37] - wire [1:0] _GEN_150 = _T_172 ? 2'h0 : _GEN_141; // @[Conditional.scala 39:67 aes.scala 247:41] + wire _T_178 = 4'h7 == state; // @[Conditional.scala 37:30] + wire _T_179 = 4'h8 == state; // @[Conditional.scala 37:30] + wire _T_180 = 4'h9 == state; // @[Conditional.scala 37:30] + wire _T_181 = 4'ha == state; // @[Conditional.scala 37:30] + wire [3:0] _GEN_79 = _T_181 ? 4'h0 : state; // @[Conditional.scala 39:67 aes.scala 328:33 aes.scala 34:28] + wire [3:0] _GEN_80 = _T_181 ? 4'h0 : ronda; // @[Conditional.scala 39:67 aes.scala 329:41 aes.scala 73:50] + wire [2:0] _GEN_81 = _T_181 ? 3'h0 : selMux1W0; // @[Conditional.scala 39:67 aes.scala 330:41 aes.scala 74:34] + wire [2:0] _GEN_82 = _T_181 ? 3'h0 : selMux1W1; // @[Conditional.scala 39:67 aes.scala 331:41 aes.scala 75:34] + wire [2:0] _GEN_83 = _T_181 ? 3'h0 : selMux1W2; // @[Conditional.scala 39:67 aes.scala 332:41 aes.scala 76:34] + wire [2:0] _GEN_84 = _T_181 ? 3'h0 : selMux1W3; // @[Conditional.scala 39:67 aes.scala 333:41 aes.scala 77:34] + wire [2:0] _GEN_85 = _T_181 ? 3'h4 : selMuxSbox; // @[Conditional.scala 39:67 aes.scala 334:41 aes.scala 78:34] + wire [1:0] _GEN_86 = _T_181 ? 2'h0 : selMuxMixARK; // @[Conditional.scala 39:67 aes.scala 335:37 aes.scala 79:34] + wire [1:0] _GEN_87 = _T_181 ? 2'h0 : selKey; // @[Conditional.scala 39:67 aes.scala 336:41 aes.scala 80:50] + wire [3:0] _GEN_88 = _T_180 ? 4'ha : _GEN_79; // @[Conditional.scala 39:67 aes.scala 317:41] + wire [3:0] _GEN_89 = _T_180 ? 4'h0 : _GEN_80; // @[Conditional.scala 39:67 aes.scala 318:41] + wire [2:0] _GEN_90 = _T_180 ? 3'h0 : _GEN_81; // @[Conditional.scala 39:67 aes.scala 319:41] + wire [2:0] _GEN_91 = _T_180 ? 3'h0 : _GEN_82; // @[Conditional.scala 39:67 aes.scala 320:41] + wire [2:0] _GEN_92 = _T_180 ? 3'h0 : _GEN_83; // @[Conditional.scala 39:67 aes.scala 321:41] + wire [2:0] _GEN_93 = _T_180 ? 3'h5 : _GEN_84; // @[Conditional.scala 39:67 aes.scala 322:41] + wire [2:0] _GEN_94 = _T_180 ? 3'h3 : _GEN_85; // @[Conditional.scala 39:67 aes.scala 323:41] + wire [1:0] _GEN_95 = _T_180 ? 2'h3 : _GEN_86; // @[Conditional.scala 39:67 aes.scala 324:37] + wire [1:0] _GEN_96 = _T_180 ? 2'h0 : _GEN_87; // @[Conditional.scala 39:67 aes.scala 325:41] + wire [3:0] _GEN_97 = _T_179 ? 4'h9 : _GEN_88; // @[Conditional.scala 39:67 aes.scala 306:41] + wire [3:0] _GEN_98 = _T_179 ? 4'h0 : _GEN_89; // @[Conditional.scala 39:67 aes.scala 307:41] + wire [2:0] _GEN_99 = _T_179 ? 3'h0 : _GEN_90; // @[Conditional.scala 39:67 aes.scala 308:41] + wire [2:0] _GEN_100 = _T_179 ? 3'h0 : _GEN_91; // @[Conditional.scala 39:67 aes.scala 309:41] + wire [2:0] _GEN_101 = _T_179 ? 3'h5 : _GEN_92; // @[Conditional.scala 39:67 aes.scala 310:41] + wire [2:0] _GEN_102 = _T_179 ? 3'h0 : _GEN_93; // @[Conditional.scala 39:67 aes.scala 311:41] + wire [2:0] _GEN_103 = _T_179 ? 3'h2 : _GEN_94; // @[Conditional.scala 39:67 aes.scala 312:41] + wire [1:0] _GEN_104 = _T_179 ? 2'h2 : _GEN_95; // @[Conditional.scala 39:67 aes.scala 313:37] + wire [1:0] _GEN_105 = _T_179 ? 2'h0 : _GEN_96; // @[Conditional.scala 39:67 aes.scala 314:41] + wire [3:0] _GEN_106 = _T_178 ? 4'h8 : _GEN_97; // @[Conditional.scala 39:67 aes.scala 295:41] + wire [3:0] _GEN_107 = _T_178 ? 4'h0 : _GEN_98; // @[Conditional.scala 39:67 aes.scala 296:41] + wire [2:0] _GEN_108 = _T_178 ? 3'h0 : _GEN_99; // @[Conditional.scala 39:67 aes.scala 297:41] + wire [2:0] _GEN_109 = _T_178 ? 3'h5 : _GEN_100; // @[Conditional.scala 39:67 aes.scala 298:41] + wire [2:0] _GEN_110 = _T_178 ? 3'h0 : _GEN_101; // @[Conditional.scala 39:67 aes.scala 299:41] + wire [2:0] _GEN_111 = _T_178 ? 3'h0 : _GEN_102; // @[Conditional.scala 39:67 aes.scala 300:41] + wire [2:0] _GEN_112 = _T_178 ? 3'h1 : _GEN_103; // @[Conditional.scala 39:67 aes.scala 301:41] + wire [1:0] _GEN_113 = _T_178 ? 2'h1 : _GEN_104; // @[Conditional.scala 39:67 aes.scala 302:37] + wire [1:0] _GEN_114 = _T_178 ? 2'h0 : _GEN_105; // @[Conditional.scala 39:67 aes.scala 303:41] + wire [3:0] _GEN_115 = _T_176 ? _GEN_75 : _GEN_106; // @[Conditional.scala 39:67] + wire [3:0] _GEN_116 = _T_176 ? _GEN_76 : _GEN_107; // @[Conditional.scala 39:67] + wire [2:0] _GEN_117 = _T_176 ? _GEN_77 : _GEN_108; // @[Conditional.scala 39:67] + wire [2:0] _GEN_118 = _T_176 ? 3'h0 : _GEN_109; // @[Conditional.scala 39:67] + wire [2:0] _GEN_119 = _T_176 ? 3'h0 : _GEN_110; // @[Conditional.scala 39:67] + wire [2:0] _GEN_120 = _T_176 ? 3'h0 : _GEN_111; // @[Conditional.scala 39:67] + wire [2:0] _GEN_121 = _T_176 ? 3'h0 : _GEN_112; // @[Conditional.scala 39:67] + wire [1:0] _GEN_122 = _T_176 ? 2'h0 : _GEN_113; // @[Conditional.scala 39:67] + wire [1:0] _GEN_123 = _T_176 ? 2'h0 : _GEN_114; // @[Conditional.scala 39:67] + wire [3:0] _GEN_124 = _T_173 ? 4'h6 : _GEN_115; // @[Conditional.scala 39:67 aes.scala 261:41] + wire [3:0] _GEN_125 = _T_173 ? _T_175 : _GEN_116; // @[Conditional.scala 39:67 aes.scala 262:41] + wire [2:0] _GEN_126 = _T_173 ? 3'h3 : _GEN_117; // @[Conditional.scala 39:67 aes.scala 263:41] + wire [2:0] _GEN_127 = _T_173 ? 3'h3 : _GEN_118; // @[Conditional.scala 39:67 aes.scala 264:41] + wire [2:0] _GEN_128 = _T_173 ? 3'h3 : _GEN_119; // @[Conditional.scala 39:67 aes.scala 265:41] + wire [2:0] _GEN_129 = _T_173 ? 3'h3 : _GEN_120; // @[Conditional.scala 39:67 aes.scala 266:41] + wire [2:0] _GEN_130 = _T_173 ? 3'h4 : _GEN_121; // @[Conditional.scala 39:67 aes.scala 267:41] + wire [1:0] _GEN_131 = _T_173 ? 2'h3 : _GEN_122; // @[Conditional.scala 39:67 aes.scala 268:37] + wire [1:0] _GEN_132 = _T_173 ? 2'h1 : _GEN_123; // @[Conditional.scala 39:67 aes.scala 269:41] + wire [3:0] _GEN_133 = _T_172 ? 4'h5 : _GEN_124; // @[Conditional.scala 39:67 aes.scala 250:41] + wire [3:0] _GEN_134 = _T_172 ? ronda : _GEN_125; // @[Conditional.scala 39:67 aes.scala 251:41] + wire [2:0] _GEN_135 = _T_172 ? 3'h0 : _GEN_126; // @[Conditional.scala 39:67 aes.scala 252:41] + wire [2:0] _GEN_136 = _T_172 ? 3'h0 : _GEN_127; // @[Conditional.scala 39:67 aes.scala 253:41] + wire [2:0] _GEN_137 = _T_172 ? 3'h2 : _GEN_128; // @[Conditional.scala 39:67 aes.scala 254:41] + wire [2:0] _GEN_138 = _T_172 ? 3'h1 : _GEN_129; // @[Conditional.scala 39:67 aes.scala 255:41] + wire [2:0] _GEN_139 = _T_172 ? 3'h3 : _GEN_130; // @[Conditional.scala 39:67 aes.scala 256:41] + wire [1:0] _GEN_140 = _T_172 ? 2'h2 : _GEN_131; // @[Conditional.scala 39:67 aes.scala 257:37] + wire [1:0] _GEN_141 = _T_172 ? 2'h0 : _GEN_132; // @[Conditional.scala 39:67 aes.scala 258:41] + wire [3:0] _GEN_142 = _T_171 ? 4'h4 : _GEN_133; // @[Conditional.scala 39:67 aes.scala 239:41] + wire [3:0] _GEN_143 = _T_171 ? ronda : _GEN_134; // @[Conditional.scala 39:67 aes.scala 240:41] + wire [2:0] _GEN_144 = _T_171 ? 3'h0 : _GEN_135; // @[Conditional.scala 39:67 aes.scala 241:41] + wire [2:0] _GEN_145 = _T_171 ? 3'h2 : _GEN_136; // @[Conditional.scala 39:67 aes.scala 242:41] + wire [2:0] _GEN_146 = _T_171 ? 3'h1 : _GEN_137; // @[Conditional.scala 39:67 aes.scala 243:41] + wire [2:0] _GEN_147 = _T_171 ? 3'h0 : _GEN_138; // @[Conditional.scala 39:67 aes.scala 244:41] + wire [2:0] _GEN_148 = _T_171 ? 3'h2 : _GEN_139; // @[Conditional.scala 39:67 aes.scala 245:41] + wire [1:0] _GEN_149 = _T_171 ? 2'h1 : _GEN_140; // @[Conditional.scala 39:67 aes.scala 246:37] + wire [1:0] _GEN_150 = _T_171 ? 2'h0 : _GEN_141; // @[Conditional.scala 39:67 aes.scala 247:41] sbox moduloSbox ( // @[aes.scala 105:32] .io_msg(moduloSbox_io_msg), .io_msg_out(moduloSbox_io_msg_out) @@ -1375,20 +1374,20 @@ ); assign io_wbs_dat_o = REG; // @[aes.scala 70:22] assign io_wbs_ack_o = ack; // @[aes.scala 54:14] - assign moduloSbox_io_msg = _T_40 ? rego_0 : _T_51; // @[Mux.scala 98:16] - assign moduloMix_io_msg = _T_52 ? rego_0 : _T_58; // @[Mux.scala 98:16] + assign moduloSbox_io_msg = _T_39 ? rego_0 : _T_50; // @[Mux.scala 98:16] + assign moduloMix_io_msg = _T_51 ? rego_0 : _T_57; // @[Mux.scala 98:16] always @(posedge clock) begin if (reset) begin // @[aes.scala 25:26] rego_0 <= 32'h0; // @[aes.scala 25:26] end else if (busy) begin // @[aes.scala 178:19] - if (!(_T_80)) begin // @[Mux.scala 98:16] - if (_T_81) begin // @[Mux.scala 98:16] + if (!(_T_79)) begin // @[Mux.scala 98:16] + if (_T_80) begin // @[Mux.scala 98:16] rego_0 <= moduloSbox_io_msg_out; end else begin - rego_0 <= _T_99; + rego_0 <= _T_98; end end - end else if (valid & io_wbs_cyc_i & io_wbs_we_i) begin // @[aes.scala 56:44] + end else if (valid & io_wbs_we_i) begin // @[aes.scala 56:30] if (4'h0 == addr) begin // @[aes.scala 57:44] rego_0 <= _T_36; // @[aes.scala 57:44] end @@ -1396,14 +1395,14 @@ if (reset) begin // @[aes.scala 25:26] rego_1 <= 32'h0; // @[aes.scala 25:26] end else if (busy) begin // @[aes.scala 178:19] - if (!(_T_101)) begin // @[Mux.scala 98:16] - if (_T_102) begin // @[Mux.scala 98:16] + if (!(_T_100)) begin // @[Mux.scala 98:16] + if (_T_101) begin // @[Mux.scala 98:16] rego_1 <= moduloSbox_io_msg_out; end else begin - rego_1 <= _T_120; + rego_1 <= _T_119; end end - end else if (valid & io_wbs_cyc_i & io_wbs_we_i) begin // @[aes.scala 56:44] + end else if (valid & io_wbs_we_i) begin // @[aes.scala 56:30] if (4'h1 == addr) begin // @[aes.scala 57:44] rego_1 <= _T_36; // @[aes.scala 57:44] end @@ -1411,14 +1410,14 @@ if (reset) begin // @[aes.scala 25:26] rego_2 <= 32'h0; // @[aes.scala 25:26] end else if (busy) begin // @[aes.scala 178:19] - if (!(_T_122)) begin // @[Mux.scala 98:16] - if (_T_123) begin // @[Mux.scala 98:16] + if (!(_T_121)) begin // @[Mux.scala 98:16] + if (_T_122) begin // @[Mux.scala 98:16] rego_2 <= moduloSbox_io_msg_out; end else begin - rego_2 <= _T_141; + rego_2 <= _T_140; end end - end else if (valid & io_wbs_cyc_i & io_wbs_we_i) begin // @[aes.scala 56:44] + end else if (valid & io_wbs_we_i) begin // @[aes.scala 56:30] if (4'h2 == addr) begin // @[aes.scala 57:44] rego_2 <= _T_36; // @[aes.scala 57:44] end @@ -1426,14 +1425,14 @@ if (reset) begin // @[aes.scala 25:26] rego_3 <= 32'h0; // @[aes.scala 25:26] end else if (busy) begin // @[aes.scala 178:19] - if (!(_T_143)) begin // @[Mux.scala 98:16] - if (_T_144) begin // @[Mux.scala 98:16] + if (!(_T_142)) begin // @[Mux.scala 98:16] + if (_T_143) begin // @[Mux.scala 98:16] rego_3 <= moduloSbox_io_msg_out; end else begin - rego_3 <= _T_162; + rego_3 <= _T_161; end end - end else if (valid & io_wbs_cyc_i & io_wbs_we_i) begin // @[aes.scala 56:44] + end else if (valid & io_wbs_we_i) begin // @[aes.scala 56:30] if (4'h3 == addr) begin // @[aes.scala 57:44] rego_3 <= _T_36; // @[aes.scala 57:44] end @@ -1441,14 +1440,14 @@ if (reset) begin // @[aes.scala 25:26] rego_4 <= 32'h0; // @[aes.scala 25:26] end else if (busy) begin // @[aes.scala 178:19] - if (!(_T_61)) begin // @[Mux.scala 98:16] - if (_T_62) begin // @[Mux.scala 98:16] + if (!(_T_60)) begin // @[Mux.scala 98:16] + if (_T_61) begin // @[Mux.scala 98:16] rego_4 <= put0; end else begin rego_4 <= 32'h0; end end - end else if (valid & io_wbs_cyc_i & io_wbs_we_i) begin // @[aes.scala 56:44] + end else if (valid & io_wbs_we_i) begin // @[aes.scala 56:30] if (4'h4 == addr) begin // @[aes.scala 57:44] rego_4 <= _T_36; // @[aes.scala 57:44] end @@ -1456,14 +1455,14 @@ if (reset) begin // @[aes.scala 25:26] rego_5 <= 32'h0; // @[aes.scala 25:26] end else if (busy) begin // @[aes.scala 178:19] - if (!(_T_61)) begin // @[Mux.scala 98:16] - if (_T_62) begin // @[Mux.scala 98:16] + if (!(_T_60)) begin // @[Mux.scala 98:16] + if (_T_61) begin // @[Mux.scala 98:16] rego_5 <= put1; end else begin rego_5 <= 32'h0; end end - end else if (valid & io_wbs_cyc_i & io_wbs_we_i) begin // @[aes.scala 56:44] + end else if (valid & io_wbs_we_i) begin // @[aes.scala 56:30] if (4'h5 == addr) begin // @[aes.scala 57:44] rego_5 <= _T_36; // @[aes.scala 57:44] end @@ -1471,14 +1470,14 @@ if (reset) begin // @[aes.scala 25:26] rego_6 <= 32'h0; // @[aes.scala 25:26] end else if (busy) begin // @[aes.scala 178:19] - if (!(_T_61)) begin // @[Mux.scala 98:16] - if (_T_62) begin // @[Mux.scala 98:16] + if (!(_T_60)) begin // @[Mux.scala 98:16] + if (_T_61) begin // @[Mux.scala 98:16] rego_6 <= put2; end else begin rego_6 <= 32'h0; end end - end else if (valid & io_wbs_cyc_i & io_wbs_we_i) begin // @[aes.scala 56:44] + end else if (valid & io_wbs_we_i) begin // @[aes.scala 56:30] if (4'h6 == addr) begin // @[aes.scala 57:44] rego_6 <= _T_36; // @[aes.scala 57:44] end @@ -1486,14 +1485,14 @@ if (reset) begin // @[aes.scala 25:26] rego_7 <= 32'h0; // @[aes.scala 25:26] end else if (busy) begin // @[aes.scala 178:19] - if (!(_T_61)) begin // @[Mux.scala 98:16] - if (_T_62) begin // @[Mux.scala 98:16] + if (!(_T_60)) begin // @[Mux.scala 98:16] + if (_T_61) begin // @[Mux.scala 98:16] rego_7 <= put3; end else begin rego_7 <= 32'h0; end end - end else if (valid & io_wbs_cyc_i & io_wbs_we_i) begin // @[aes.scala 56:44] + end else if (valid & io_wbs_we_i) begin // @[aes.scala 56:30] if (4'h7 == addr) begin // @[aes.scala 57:44] rego_7 <= _T_36; // @[aes.scala 57:44] end @@ -1502,28 +1501,28 @@ rego_8 <= 32'h0; // @[aes.scala 25:26] end else if (busy) begin // @[aes.scala 178:19] rego_8 <= 32'h0; // @[aes.scala 187:28] - end else if (valid & io_wbs_cyc_i & io_wbs_we_i) begin // @[aes.scala 56:44] + end else if (valid & io_wbs_we_i) begin // @[aes.scala 56:30] if (4'h8 == addr) begin // @[aes.scala 57:44] rego_8 <= _T_36; // @[aes.scala 57:44] end end if (reset) begin // @[aes.scala 34:28] state <= 4'h0; // @[aes.scala 34:28] - end else if (_T_169) begin // @[Conditional.scala 40:58] + end else if (_T_168) begin // @[Conditional.scala 40:58] if (start) begin // @[aes.scala 194:32] state <= 4'h1; // @[aes.scala 195:41] end else begin state <= 4'h0; // @[aes.scala 205:41] end - end else if (_T_170) begin // @[Conditional.scala 39:67] + end else if (_T_169) begin // @[Conditional.scala 39:67] state <= 4'h2; // @[aes.scala 217:41] - end else if (_T_171) begin // @[Conditional.scala 39:67] + end else if (_T_170) begin // @[Conditional.scala 39:67] state <= 4'h3; // @[aes.scala 228:41] end else begin state <= _GEN_142; end - ack <= io_wbs_stb_i & _T_167 & _T_25 == 32'h20000000; // @[aes.scala 50:42] - if (_T_29 & ~io_wbs_we_i) begin // @[aes.scala 63:46] + ack <= io_wbs_stb_i & io_wbs_cyc_i & _T_166 & _T_26 == 32'h30000000; // @[aes.scala 50:57] + if (valid & ~io_wbs_we_i) begin // @[aes.scala 63:31] if (4'hc == addr) begin // @[aes.scala 64:23] REG <= full_regs_12; // @[aes.scala 64:23] end else if (4'hb == addr) begin // @[aes.scala 64:23] @@ -1538,102 +1537,102 @@ end if (reset) begin // @[aes.scala 73:50] ronda <= 4'h0; // @[aes.scala 73:50] - end else if (_T_169) begin // @[Conditional.scala 40:58] + end else if (_T_168) begin // @[Conditional.scala 40:58] ronda <= 4'h0; - end else if (!(_T_170)) begin // @[Conditional.scala 39:67] - if (!(_T_171)) begin // @[Conditional.scala 39:67] + end else if (!(_T_169)) begin // @[Conditional.scala 39:67] + if (!(_T_170)) begin // @[Conditional.scala 39:67] ronda <= _GEN_143; end end if (reset) begin // @[aes.scala 74:34] selMux1W0 <= 3'h5; // @[aes.scala 74:34] - end else if (_T_169) begin // @[Conditional.scala 40:58] + end else if (_T_168) begin // @[Conditional.scala 40:58] if (start) begin // @[aes.scala 194:32] selMux1W0 <= 3'h4; // @[aes.scala 197:49] end else begin selMux1W0 <= 3'h0; // @[aes.scala 207:49] end - end else if (_T_170) begin // @[Conditional.scala 39:67] + end else if (_T_169) begin // @[Conditional.scala 39:67] selMux1W0 <= 3'h1; // @[aes.scala 219:41] - end else if (_T_171) begin // @[Conditional.scala 39:67] + end else if (_T_170) begin // @[Conditional.scala 39:67] selMux1W0 <= 3'h2; // @[aes.scala 230:41] end else begin selMux1W0 <= _GEN_144; end if (reset) begin // @[aes.scala 75:34] selMux1W1 <= 3'h5; // @[aes.scala 75:34] - end else if (_T_169) begin // @[Conditional.scala 40:58] + end else if (_T_168) begin // @[Conditional.scala 40:58] if (start) begin // @[aes.scala 194:32] selMux1W1 <= 3'h4; // @[aes.scala 197:49] end else begin selMux1W1 <= 3'h0; // @[aes.scala 207:49] end - end else if (_T_170) begin // @[Conditional.scala 39:67] + end else if (_T_169) begin // @[Conditional.scala 39:67] selMux1W1 <= 3'h0; // @[aes.scala 220:41] - end else if (_T_171) begin // @[Conditional.scala 39:67] + end else if (_T_170) begin // @[Conditional.scala 39:67] selMux1W1 <= 3'h1; // @[aes.scala 231:41] end else begin selMux1W1 <= _GEN_145; end if (reset) begin // @[aes.scala 76:34] selMux1W2 <= 3'h5; // @[aes.scala 76:34] - end else if (_T_169) begin // @[Conditional.scala 40:58] + end else if (_T_168) begin // @[Conditional.scala 40:58] if (start) begin // @[aes.scala 194:32] selMux1W2 <= 3'h4; // @[aes.scala 197:49] end else begin selMux1W2 <= 3'h0; // @[aes.scala 207:49] end - end else if (_T_170) begin // @[Conditional.scala 39:67] + end else if (_T_169) begin // @[Conditional.scala 39:67] selMux1W2 <= 3'h0; // @[aes.scala 221:41] - end else if (_T_171) begin // @[Conditional.scala 39:67] + end else if (_T_170) begin // @[Conditional.scala 39:67] selMux1W2 <= 3'h0; // @[aes.scala 232:41] end else begin selMux1W2 <= _GEN_146; end if (reset) begin // @[aes.scala 77:34] selMux1W3 <= 3'h5; // @[aes.scala 77:34] - end else if (_T_169) begin // @[Conditional.scala 40:58] + end else if (_T_168) begin // @[Conditional.scala 40:58] if (start) begin // @[aes.scala 194:32] selMux1W3 <= 3'h4; // @[aes.scala 197:49] end else begin selMux1W3 <= 3'h0; // @[aes.scala 207:49] end - end else if (_T_170) begin // @[Conditional.scala 39:67] + end else if (_T_169) begin // @[Conditional.scala 39:67] selMux1W3 <= 3'h0; // @[aes.scala 222:41] - end else if (_T_171) begin // @[Conditional.scala 39:67] + end else if (_T_170) begin // @[Conditional.scala 39:67] selMux1W3 <= 3'h0; // @[aes.scala 233:41] end else begin selMux1W3 <= _GEN_147; end if (reset) begin // @[aes.scala 78:34] selMuxSbox <= 3'h4; // @[aes.scala 78:34] - end else if (_T_169) begin // @[Conditional.scala 40:58] + end else if (_T_168) begin // @[Conditional.scala 40:58] selMuxSbox <= 3'h4; - end else if (_T_170) begin // @[Conditional.scala 39:67] + end else if (_T_169) begin // @[Conditional.scala 39:67] selMuxSbox <= 3'h0; // @[aes.scala 223:41] - end else if (_T_171) begin // @[Conditional.scala 39:67] + end else if (_T_170) begin // @[Conditional.scala 39:67] selMuxSbox <= 3'h1; // @[aes.scala 234:41] end else begin selMuxSbox <= _GEN_148; end if (reset) begin // @[aes.scala 79:34] selMuxMixARK <= 2'h0; // @[aes.scala 79:34] - end else if (_T_169) begin // @[Conditional.scala 40:58] + end else if (_T_168) begin // @[Conditional.scala 40:58] selMuxMixARK <= 2'h0; - end else if (_T_170) begin // @[Conditional.scala 39:67] + end else if (_T_169) begin // @[Conditional.scala 39:67] selMuxMixARK <= 2'h0; // @[aes.scala 224:37] - end else if (_T_171) begin // @[Conditional.scala 39:67] + end else if (_T_170) begin // @[Conditional.scala 39:67] selMuxMixARK <= 2'h0; // @[aes.scala 235:37] end else begin selMuxMixARK <= _GEN_149; end if (reset) begin // @[aes.scala 80:50] selKey <= 2'h0; // @[aes.scala 80:50] - end else if (_T_169) begin // @[Conditional.scala 40:58] + end else if (_T_168) begin // @[Conditional.scala 40:58] selKey <= {{1'd0}, start}; - end else if (_T_170) begin // @[Conditional.scala 39:67] + end else if (_T_169) begin // @[Conditional.scala 39:67] selKey <= 2'h0; // @[aes.scala 225:41] - end else if (_T_171) begin // @[Conditional.scala 39:67] + end else if (_T_170) begin // @[Conditional.scala 39:67] selKey <= 2'h0; // @[aes.scala 236:41] end else begin selKey <= _GEN_150;
diff --git a/verilog/rtl/aes/src/main/scala/aes.scala b/verilog/rtl/aes/src/main/scala/aes.scala index 9b32dfa..77bcf67 100644 --- a/verilog/rtl/aes/src/main/scala/aes.scala +++ b/verilog/rtl/aes/src/main/scala/aes.scala
@@ -47,20 +47,20 @@ val addr = Wire(UInt((log2Ceil(1+nrego)).W)) addr:= (io.wbs_adr_i-base.U) >>2 - val valid = io.wbs_stb_i & !busy & ( (io.wbs_adr_i & (0xFF.U <<24) ) === ( base.U & (0xFF.U <<24)) ) + val valid = io.wbs_stb_i & io.wbs_cyc_i & !busy & ( (io.wbs_adr_i & (0xFF.U <<24) ) === ( base.U & (0xFF.U <<24)) ) val ack = RegNext(valid) io.wbs_ack_o:=ack //write - when( valid & io.wbs_cyc_i & io.wbs_we_i ){ + when( valid & io.wbs_we_i ){ rego(addr) := (rego(addr) & ! (mask.asUInt)) | ( io.wbs_dat_i & mask.asUInt ) } //read val readed = Wire(UInt(32.W)) - when( valid & io.wbs_cyc_i & ! io.wbs_we_i ){ + when( valid & ! io.wbs_we_i ){ readed:=full_regs(addr) }.otherwise { readed:=0.U @@ -340,5 +340,5 @@ //fossiAES.aesMain object aesMain extends App { - (new chisel3.stage.ChiselStage).emitVerilog(new aes(32,BigInt(0x20000080)) ,args) + (new chisel3.stage.ChiselStage).emitVerilog(new aes(32,BigInt(0x30000000)) ,args) }
diff --git a/verilog/rtl/aes/target/scala-2.12/arcabuco_2.12-1.0.jar b/verilog/rtl/aes/target/scala-2.12/arcabuco_2.12-1.0.jar index 1b9d2ac..efae6dd 100644 --- a/verilog/rtl/aes/target/scala-2.12/arcabuco_2.12-1.0.jar +++ b/verilog/rtl/aes/target/scala-2.12/arcabuco_2.12-1.0.jar Binary files differ
diff --git a/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aes.class b/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aes.class index 4eae093..c874978 100644 --- a/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aes.class +++ b/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aes.class Binary files differ
diff --git a/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aesMain$.class b/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aesMain$.class index 5424681..21cdfb0 100644 --- a/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aesMain$.class +++ b/verilog/rtl/aes/target/scala-2.12/classes/fossiAES/aesMain$.class Binary files differ
diff --git a/verilog/rtl/aes/target/streams/compile/compileIncSetup/$global/streams/inc_compile_2.12.zip b/verilog/rtl/aes/target/streams/compile/compileIncSetup/$global/streams/inc_compile_2.12.zip index afebd55..9a97f4a 100644 --- a/verilog/rtl/aes/target/streams/compile/compileIncSetup/$global/streams/inc_compile_2.12.zip +++ b/verilog/rtl/aes/target/streams/compile/compileIncSetup/$global/streams/inc_compile_2.12.zip Binary files differ
diff --git a/verilog/rtl/aes/target/streams/compile/compileIncremental/$global/streams/out b/verilog/rtl/aes/target/streams/compile/compileIncremental/$global/streams/out index d88c41e..4dad3aa 100644 --- a/verilog/rtl/aes/target/streams/compile/compileIncremental/$global/streams/out +++ b/verilog/rtl/aes/target/streams/compile/compileIncremental/$global/streams/out
@@ -17,7 +17,7 @@ [0m[[0m[0minfo[0m] [0m[0mCompiling 1 Scala source to /home/askartos/sandbox/caravel_tutorial/fossiAES/verilog/rtl/aes/target/scala-2.12/classes ...[0m [0m[[0m[0mdebug[0m] [0m[0mGetting org.scala-sbt:compiler-bridge_2.12:1.1.1:compile for Scala 2.12.6[0m [0m[[0m[0mdebug[0m] [0m[0mGetting org.scala-sbt:compiler-bridge_2.12:1.1.1:compile for Scala 2.12.6[0m -[0m[[0m[0mdebug[0m] [0m[0m[zinc] Running cached compiler 6321e45d for Scala compiler version 2.12.6[0m +[0m[[0m[0mdebug[0m] [0m[0m[zinc] Running cached compiler 27d5bc7b for Scala compiler version 2.12.6[0m [0m[[0m[0mdebug[0m] [0m[0m[zinc] The Scala compiler is invoked with:[0m [0m[[0m[0mdebug[0m] [0m[0m -Xsource:2.11[0m [0m[[0m[0mdebug[0m] [0m[0m -language:reflectiveCalls[0m @@ -30,7 +30,7 @@ [0m[[0m[0mdebug[0m] [0m[0m /usr/lib/jvm/java-8-oracle/jre/lib/resources.jar:/usr/lib/jvm/java-8-oracle/jre/lib/rt.jar:/usr/lib/jvm/java-8-oracle/jre/lib/sunrsasign.jar:/usr/lib/jvm/java-8-oracle/jre/lib/jsse.jar:/usr/lib/jvm/java-8-oracle/jre/lib/jce.jar:/usr/lib/jvm/java-8-oracle/jre/lib/charsets.jar:/usr/lib/jvm/java-8-oracle/jre/lib/jfr.jar:/usr/lib/jvm/java-8-oracle/jre/classes:/home/askartos/.ivy2/cache/org.scala-lang/scala-library/jars/scala-library-2.12.6.jar[0m [0m[[0m[0mdebug[0m] [0m[0m -classpath[0m [0m[[0m[0mdebug[0m] [0m[0m /home/askartos/sandbox/caravel_tutorial/fossiAES/verilog/rtl/aes/target/scala-2.12/classes:/home/askartos/.ivy2/cache/edu.berkeley.cs/chisel3_2.12/jars/chisel3_2.12-3.4.4.jar:/home/askartos/.ivy2/cache/edu.berkeley.cs/chisel3-macros_2.12/jars/chisel3-macros_2.12-3.4.4.jar:/home/askartos/.ivy2/cache/org.scala-lang/scala-reflect/jars/scala-reflect-2.12.6.jar:/home/askartos/.ivy2/cache/edu.berkeley.cs/chisel3-core_2.12/jars/chisel3-core_2.12-3.4.4.jar:/home/askartos/.ivy2/cache/edu.berkeley.cs/firrtl_2.12/jars/firrtl_2.12-1.4.4.jar:/home/askartos/.ivy2/cache/org.antlr/antlr4-runtime/jars/antlr4-runtime-4.7.1.jar:/home/askartos/.ivy2/cache/com.google.protobuf/protobuf-java/bundles/protobuf-java-3.9.0.jar:/home/askartos/.ivy2/cache/com.github.scopt/scopt_2.12/jars/scopt_2.12-3.7.1.jar:/home/askartos/.ivy2/cache/net.jcazevedo/moultingyaml_2.12/jars/moultingyaml_2.12-0.4.2.jar:/home/askartos/.ivy2/cache/com.github.nscala-time/nscala-time_2.12/jars/nscala-time_2.12-2.22.0.jar:/home/askartos/.ivy2/cache/joda-time/joda-time/jars/joda-time-2.10.1.jar:/home/askartos/.ivy2/cache/org.joda/joda-convert/jars/joda-convert-2.2.0.jar:/home/askartos/.ivy2/cache/org.yaml/snakeyaml/bundles/snakeyaml-1.26.jar:/home/askartos/.ivy2/cache/org.json4s/json4s-native_2.12/jars/json4s-native_2.12-3.6.9.jar:/home/askartos/.ivy2/cache/org.json4s/json4s-core_2.12/jars/json4s-core_2.12-3.6.9.jar:/home/askartos/.ivy2/cache/org.json4s/json4s-ast_2.12/jars/json4s-ast_2.12-3.6.9.jar:/home/askartos/.ivy2/cache/org.json4s/json4s-scalap_2.12/jars/json4s-scalap_2.12-3.6.9.jar:/home/askartos/.ivy2/cache/com.thoughtworks.paranamer/paranamer/bundles/paranamer-2.8.jar:/home/askartos/.ivy2/cache/org.apache.commons/commons-text/jars/commons-text-1.8.jar:/home/askartos/.ivy2/cache/org.apache.commons/commons-lang3/jars/commons-lang3-3.9.jar[0m -[0m[[0m[0mdebug[0m] [0m[0mScala compilation took 6.196713579 s[0m +[0m[[0m[0mdebug[0m] [0m[0mScala compilation took 6.253367337 s[0m [0m[[0m[0minfo[0m] [0m[0mDone compiling.[0m [0m[[0m[0mdebug[0m] [0m[0mNew invalidations:[0m [0m[[0m[0mdebug[0m] [0m[0m Set()[0m
diff --git a/verilog/rtl/aes/target/streams/compile/packageBin/$global/streams/inputs b/verilog/rtl/aes/target/streams/compile/packageBin/$global/streams/inputs index 6353d4d..43bee6a 100644 --- a/verilog/rtl/aes/target/streams/compile/packageBin/$global/streams/inputs +++ b/verilog/rtl/aes/target/streams/compile/packageBin/$global/streams/inputs
@@ -1 +1 @@ -673532377 \ No newline at end of file +1507277370 \ No newline at end of file