MERGE: TRNG to master
diff --git a/README.md b/README.md
index 3077244..a12ad0e 100644
--- a/README.md
+++ b/README.md
@@ -1,12 +1,141 @@
-# Caravel User Project
+# Secure Memory
-[](https://opensource.org/licenses/Apache-2.0) [](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)
+[](https://opensource.org/licenses/Apache-2.0)
-| :exclamation: Important Note |
-|-----------------------------------------|
+## Table of contents
+- [Secure Memory](#secure-memory)
+ - [Table of contents](#table-of-contents)
+ - [Overview](#overview)
+ - [Basic Macros](#basic-macros)
+ - [Prerequisites](#prerequisites)
+ - [Step-1: Docker in ubuntu 20.04 version](#step-1-docker-in-ubuntu-2004-version)
+ - [Step-2: Clone caravel user project](#step-2-clone-caravel-user-project)
+ - [Step-3: Setup your local environment](#step-3-setup-your-local-environment)
+ - [Step-4: To install required repos](#step-4-to-install-required-repos)
+ - [Step-5: Harden design](#step-5-harden-design)
+ - [Step-6 Simulation](#step-6-simulation)
+ - [Step-7 Precheck](#step-7-precheck)
+ - [Openlane Flow](#openlane-flow)
-## Please fill in your project documentation in this README.md file
+## Overview
-Refer to [README](docs/source/quickstart.rst) for a quick start of how to use caravel_user_project
+Keeping your data secure. This project aims to secure data from adversaries. It has inherent SRAM to keep the data safe and they are kept as not plaintext but ciphered. We got 5 macros inherently in order to accomplish our goal. Below section will be described those macros briefly.
-Refer to [README](docs/source/index.rst) for this sample project documentation.
+<table>
+ <tr>
+ <td align="center"><img src="./docs/source/_static/secure_memory.png" ></td>
+ </tr>
+</table>
+
+## Basic Macros
+
+- `TRNG` - True random number generator. Ring oscillator macro which is one of the inner macros of caravel core, is used. In this macro, delay buffers are used instead of not gates. It can be also used as key generator for AES.
+
+<table>
+ <tr>
+ <td align="center"><img src="./docs/source/_static/trng.png" ></td>
+ </tr>
+</table>
+
+- `SPI` - SPI pins are connected to GPIO pins which is spared for user project. User can read/write data from/to SRAM via SPI.
+- `UART` - UART pins are connected to GPIO pins which is spared for user project. User can read/write data from/to SRAM via UART.
+- `AES` - Cipher plaintext to keep data safe in SRAM.
+- `SRAM` - Our precious. Its 1KB.
+
+All these macros are in located in the `verilog/rtl/` directory.
+
+## Prerequisites
+ - Docker (ensure docker daemon is running) -- tested with version 19.03.12, but any recent version should suffice.
+### Step-1: Docker in ubuntu 20.04 version
+```bash
+ sudo apt update
+ sudo apt-get install apt-transport-https curl rtificates -agent software-properties-common
+ curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo apt-key add -
+ sudo add-apt-repository "deb [arch=amd64] https://download.docker.com/linux/ubuntu focal stable"
+ sudo apt update
+ apt-cache policy docker-ce
+ sudo apt install docker-ce
+
+ #Add User Name to docker
+ sudo usermod -aG docker <your user name>
+ # Reboot the system to enable the docker setup
+```
+### Step-2: Clone caravel user project
+```bash
+ git clone -b mpw-5c https://github.com/efabless/caravel_user_project
+```
+### Step-3: Setup your local environment
+```bash
+ export CARAVEL_ROOT=<Caravel Installed Path>
+ export PDK_ROOT=<PDK Installed PATH>
+ export UPRJ_ROOT=<Caravel User Project Installed Path>
+ export OPENLANE_ROOT=<OpenLane Installed Path>
+ export OPENLANE_IMAGE_NAME=efabless/openlane:2022.02.23_02.50.41
+```
+
+### Step-4: To install required repos
+```bash
+ source ~/.bashrc
+ cd $UPRJ_ROOT
+ make install # install pdk. pdk with sram, openlane. caravel and mgmt core
+```
+
+### Step-5: Harden design
+A subdirectory for each macro in your project under openlane/ directory, each subdirectory should include openlane configuration files for the macro
+```bash
+ make <module_name>
+ make user_project_wrapper
+```
+
+### Step-6 Simulation
+Examples:
+``` sh
+ # you can then run RTL simulations using
+ make verify-<testbench-name>-rtl
+
+ # or GL simulation using
+ make verify-<testbench-name>-gl
+
+ # for example
+ make verify-wb_port-rtl
+```
+
+### Step-7 Precheck
+``` sh
+ make precheck
+ make run-precheck
+```
+
+## Openlane Flow
+
+Mbist Controller flow uses Openlane tool sets.
+
+1. **Synthesis**
+ 1. `yosys` - Performs RTL synthesis
+ 2. `abc` - Performs technology mapping
+ 3. `OpenSTA` - Pefroms static timing analysis on the resulting netlist to generate timing reports
+2. **Floorplan and PDN**
+ 1. `init_fp` - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)
+ 2. `ioplacer` - Places the macro input and output ports
+ 3. `pdn` - Generates the power distribution network
+ 4. `tapcell` - Inserts welltap and decap cells in the floorplan
+3. **Placement**
+ 1. `RePLace` - Performs global placement
+ 2. `Resizer` - Performs optional optimizations on the design
+ 3. `OpenPhySyn` - Performs timing optimizations on the design
+ 4. `OpenDP` - Perfroms detailed placement to legalize the globally placed components
+4. **CTS**
+ 1. `TritonCTS` - Synthesizes the clock distribution network (the clock tree)
+5. **Routing**
+ 1. `FastRoute` - Performs global routing to generate a guide file for the detailed router
+ 2. `CU-GR` - Another option for performing global routing.
+ 3. `TritonRoute` - Performs detailed routing
+ 4. `SPEF-Extractor` - Performs SPEF extraction
+6. **GDSII Generation**
+ 1. `Magic` - Streams out the final GDSII layout file from the routed def
+ 2. `Klayout` - Streams out the final GDSII layout file from the routed def as a back-up
+7. **Checks**
+ 1. `Magic` - Performs DRC Checks & Antenna Checks
+ 2. `Klayout` - Performs DRC Checks
+ 3. `Netgen` - Performs LVS Checks
+ 4. `CVC` - Performs Circuit Validity Checks
\ No newline at end of file
diff --git a/gds/trng2_wb_wrapper.gds b/gds/trng2_wb_wrapper.gds
new file mode 100644
index 0000000..9e1bf13
--- /dev/null
+++ b/gds/trng2_wb_wrapper.gds
Binary files differ
diff --git a/gds/trng3_wb_wrapper.gds b/gds/trng3_wb_wrapper.gds
new file mode 100644
index 0000000..dd460a7
--- /dev/null
+++ b/gds/trng3_wb_wrapper.gds
Binary files differ
diff --git a/lef/trng2_wb_wrapper.lef b/lef/trng2_wb_wrapper.lef
new file mode 100644
index 0000000..33b37a0
--- /dev/null
+++ b/lef/trng2_wb_wrapper.lef
@@ -0,0 +1,1143 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO trng_wb_wrapper
+ CLASS BLOCK ;
+ FOREIGN trng_wb_wrapper ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 750.000 BY 1000.000 ;
+ PIN rst_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 455.640 750.000 456.240 ;
+ END
+ END rst_i
+ PIN trng_buffer_o[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 202.950 996.000 203.230 1000.000 ;
+ END
+ END trng_buffer_o[0]
+ PIN trng_buffer_o[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 285.640 4.000 286.240 ;
+ END
+ END trng_buffer_o[10]
+ PIN trng_buffer_o[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 415.470 996.000 415.750 1000.000 ;
+ END
+ END trng_buffer_o[11]
+ PIN trng_buffer_o[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 734.440 4.000 735.040 ;
+ END
+ END trng_buffer_o[12]
+ PIN trng_buffer_o[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 95.240 4.000 95.840 ;
+ END
+ END trng_buffer_o[13]
+ PIN trng_buffer_o[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 574.640 4.000 575.240 ;
+ END
+ END trng_buffer_o[14]
+ PIN trng_buffer_o[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 380.840 4.000 381.440 ;
+ END
+ END trng_buffer_o[15]
+ PIN trng_buffer_o[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 173.970 996.000 174.250 1000.000 ;
+ END
+ END trng_buffer_o[16]
+ PIN trng_buffer_o[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 209.390 0.000 209.670 4.000 ;
+ END
+ END trng_buffer_o[17]
+ PIN trng_buffer_o[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 512.070 0.000 512.350 4.000 ;
+ END
+ END trng_buffer_o[18]
+ PIN trng_buffer_o[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 656.970 996.000 657.250 1000.000 ;
+ END
+ END trng_buffer_o[19]
+ PIN trng_buffer_o[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 71.440 750.000 72.040 ;
+ END
+ END trng_buffer_o[1]
+ PIN trng_buffer_o[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 901.040 750.000 901.640 ;
+ END
+ END trng_buffer_o[20]
+ PIN trng_buffer_o[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 605.450 0.000 605.730 4.000 ;
+ END
+ END trng_buffer_o[21]
+ PIN trng_buffer_o[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 166.640 750.000 167.240 ;
+ END
+ END trng_buffer_o[22]
+ PIN trng_buffer_o[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 836.440 750.000 837.040 ;
+ END
+ END trng_buffer_o[23]
+ PIN trng_buffer_o[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 325.310 996.000 325.590 1000.000 ;
+ END
+ END trng_buffer_o[24]
+ PIN trng_buffer_o[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 22.630 996.000 22.910 1000.000 ;
+ END
+ END trng_buffer_o[25]
+ PIN trng_buffer_o[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 935.040 750.000 935.640 ;
+ END
+ END trng_buffer_o[26]
+ PIN trng_buffer_o[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 112.790 996.000 113.070 1000.000 ;
+ END
+ END trng_buffer_o[27]
+ PIN trng_buffer_o[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 540.640 4.000 541.240 ;
+ END
+ END trng_buffer_o[28]
+ PIN trng_buffer_o[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 37.440 750.000 38.040 ;
+ END
+ END trng_buffer_o[29]
+ PIN trng_buffer_o[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 180.410 0.000 180.690 4.000 ;
+ END
+ END trng_buffer_o[2]
+ PIN trng_buffer_o[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 354.290 996.000 354.570 1000.000 ;
+ END
+ END trng_buffer_o[30]
+ PIN trng_buffer_o[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 695.610 0.000 695.890 4.000 ;
+ END
+ END trng_buffer_o[31]
+ PIN trng_buffer_o[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 119.230 0.000 119.510 4.000 ;
+ END
+ END trng_buffer_o[3]
+ PIN trng_buffer_o[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 264.130 996.000 264.410 1000.000 ;
+ END
+ END trng_buffer_o[4]
+ PIN trng_buffer_o[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 326.440 750.000 327.040 ;
+ END
+ END trng_buffer_o[5]
+ PIN trng_buffer_o[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 30.640 4.000 31.240 ;
+ END
+ END trng_buffer_o[6]
+ PIN trng_buffer_o[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 863.640 4.000 864.240 ;
+ END
+ END trng_buffer_o[7]
+ PIN trng_buffer_o[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 639.240 4.000 639.840 ;
+ END
+ END trng_buffer_o[8]
+ PIN trng_buffer_o[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 595.790 996.000 596.070 1000.000 ;
+ END
+ END trng_buffer_o[9]
+ PIN trng_valid_o
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 421.910 0.000 422.190 4.000 ;
+ END
+ END trng_valid_o
+ PIN vccd1
+ DIRECTION INPUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 21.040 10.640 22.640 987.600 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 174.640 10.640 176.240 987.600 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 328.240 10.640 329.840 987.600 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 481.840 10.640 483.440 987.600 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 635.440 10.640 637.040 987.600 ;
+ END
+ END vccd1
+ PIN vssd1
+ DIRECTION INPUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 97.840 10.640 99.440 987.600 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 251.440 10.640 253.040 987.600 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 405.040 10.640 406.640 987.600 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 558.640 10.640 560.240 987.600 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 712.240 10.640 713.840 987.600 ;
+ END
+ END vssd1
+ PIN wb_ack_o
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 357.040 750.000 357.640 ;
+ END
+ END wb_ack_o
+ PIN wb_adr_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 870.440 750.000 871.040 ;
+ END
+ END wb_adr_i[0]
+ PIN wb_adr_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 775.240 750.000 775.840 ;
+ END
+ END wb_adr_i[1]
+ PIN wb_adr_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 710.640 750.000 711.240 ;
+ END
+ END wb_adr_i[2]
+ PIN wb_adr_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 676.640 750.000 677.240 ;
+ END
+ END wb_adr_i[3]
+ PIN wb_adr_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 360.730 0.000 361.010 4.000 ;
+ END
+ END wb_adr_i[4]
+ PIN wb_adr_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 61.240 4.000 61.840 ;
+ END
+ END wb_adr_i[5]
+ PIN wb_adr_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 965.640 750.000 966.240 ;
+ END
+ END wb_adr_i[6]
+ PIN wb_adr_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 605.240 4.000 605.840 ;
+ END
+ END wb_adr_i[7]
+ PIN wb_adr_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 293.110 996.000 293.390 1000.000 ;
+ END
+ END wb_adr_i[8]
+ PIN wb_clk_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 550.840 750.000 551.440 ;
+ END
+ END wb_clk_i
+ PIN wb_cyc_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 581.440 750.000 582.040 ;
+ END
+ END wb_cyc_i
+ PIN wb_dat_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 141.770 996.000 142.050 1000.000 ;
+ END
+ END wb_dat_i[0]
+ PIN wb_dat_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 386.490 996.000 386.770 1000.000 ;
+ END
+ END wb_dat_i[10]
+ PIN wb_dat_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 689.170 996.000 689.450 1000.000 ;
+ END
+ END wb_dat_i[11]
+ PIN wb_dat_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 241.590 0.000 241.870 4.000 ;
+ END
+ END wb_dat_i[12]
+ PIN wb_dat_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 292.440 750.000 293.040 ;
+ END
+ END wb_dat_i[13]
+ PIN wb_dat_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 197.240 750.000 197.840 ;
+ END
+ END wb_dat_i[14]
+ PIN wb_dat_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 445.440 4.000 446.040 ;
+ END
+ END wb_dat_i[15]
+ PIN wb_dat_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 58.050 0.000 58.330 4.000 ;
+ END
+ END wb_dat_i[16]
+ PIN wb_dat_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 6.840 750.000 7.440 ;
+ END
+ END wb_dat_i[17]
+ PIN wb_dat_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 261.840 750.000 262.440 ;
+ END
+ END wb_dat_i[18]
+ PIN wb_dat_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 747.130 996.000 747.410 1000.000 ;
+ END
+ END wb_dat_i[19]
+ PIN wb_dat_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 221.040 4.000 221.640 ;
+ END
+ END wb_dat_i[1]
+ PIN wb_dat_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 666.630 0.000 666.910 4.000 ;
+ END
+ END wb_dat_i[20]
+ PIN wb_dat_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 331.750 0.000 332.030 4.000 ;
+ END
+ END wb_dat_i[21]
+ PIN wb_dat_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 391.040 750.000 391.640 ;
+ END
+ END wb_dat_i[22]
+ PIN wb_dat_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 80.590 996.000 80.870 1000.000 ;
+ END
+ END wb_dat_i[23]
+ PIN wb_dat_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 703.840 4.000 704.440 ;
+ END
+ END wb_dat_i[24]
+ PIN wb_dat_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 132.640 750.000 133.240 ;
+ END
+ END wb_dat_i[25]
+ PIN wb_dat_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 829.640 4.000 830.240 ;
+ END
+ END wb_dat_i[26]
+ PIN wb_dat_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 159.840 4.000 160.440 ;
+ END
+ END wb_dat_i[27]
+ PIN wb_dat_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 476.650 996.000 476.930 1000.000 ;
+ END
+ END wb_dat_i[28]
+ PIN wb_dat_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 125.840 4.000 126.440 ;
+ END
+ END wb_dat_i[29]
+ PIN wb_dat_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 90.250 0.000 90.530 4.000 ;
+ END
+ END wb_dat_i[2]
+ PIN wb_dat_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 270.570 0.000 270.850 4.000 ;
+ END
+ END wb_dat_i[30]
+ PIN wb_dat_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 102.040 750.000 102.640 ;
+ END
+ END wb_dat_i[31]
+ PIN wb_dat_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 615.440 750.000 616.040 ;
+ END
+ END wb_dat_i[3]
+ PIN wb_dat_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 421.640 750.000 422.240 ;
+ END
+ END wb_dat_i[4]
+ PIN wb_dat_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 634.430 0.000 634.710 4.000 ;
+ END
+ END wb_dat_i[5]
+ PIN wb_dat_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 669.840 4.000 670.440 ;
+ END
+ END wb_dat_i[6]
+ PIN wb_dat_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 510.040 4.000 510.640 ;
+ END
+ END wb_dat_i[7]
+ PIN wb_dat_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 479.440 4.000 480.040 ;
+ END
+ END wb_dat_i[8]
+ PIN wb_dat_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 486.240 750.000 486.840 ;
+ END
+ END wb_dat_i[9]
+ PIN wb_dat_o[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 741.240 750.000 741.840 ;
+ END
+ END wb_dat_o[0]
+ PIN wb_dat_o[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 724.590 0.000 724.870 4.000 ;
+ END
+ END wb_dat_o[10]
+ PIN wb_dat_o[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 805.840 750.000 806.440 ;
+ END
+ END wb_dat_o[11]
+ PIN wb_dat_o[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 190.440 4.000 191.040 ;
+ END
+ END wb_dat_o[12]
+ PIN wb_dat_o[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 958.840 4.000 959.440 ;
+ END
+ END wb_dat_o[13]
+ PIN wb_dat_o[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 350.240 4.000 350.840 ;
+ END
+ END wb_dat_o[14]
+ PIN wb_dat_o[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 0.090 0.000 0.370 4.000 ;
+ END
+ END wb_dat_o[15]
+ PIN wb_dat_o[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 544.270 0.000 544.550 4.000 ;
+ END
+ END wb_dat_o[16]
+ PIN wb_dat_o[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 989.440 4.000 990.040 ;
+ END
+ END wb_dat_o[17]
+ PIN wb_dat_o[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 235.150 996.000 235.430 1000.000 ;
+ END
+ END wb_dat_o[18]
+ PIN wb_dat_o[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 505.630 996.000 505.910 1000.000 ;
+ END
+ END wb_dat_o[19]
+ PIN wb_dat_o[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 799.040 4.000 799.640 ;
+ END
+ END wb_dat_o[1]
+ PIN wb_dat_o[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 414.840 4.000 415.440 ;
+ END
+ END wb_dat_o[20]
+ PIN wb_dat_o[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 29.070 0.000 29.350 4.000 ;
+ END
+ END wb_dat_o[21]
+ PIN wb_dat_o[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 627.990 996.000 628.270 1000.000 ;
+ END
+ END wb_dat_o[22]
+ PIN wb_dat_o[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 444.450 996.000 444.730 1000.000 ;
+ END
+ END wb_dat_o[23]
+ PIN wb_dat_o[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 392.930 0.000 393.210 4.000 ;
+ END
+ END wb_dat_o[24]
+ PIN wb_dat_o[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 718.150 996.000 718.430 1000.000 ;
+ END
+ END wb_dat_o[25]
+ PIN wb_dat_o[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 231.240 750.000 231.840 ;
+ END
+ END wb_dat_o[26]
+ PIN wb_dat_o[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 894.240 4.000 894.840 ;
+ END
+ END wb_dat_o[27]
+ PIN wb_dat_o[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 319.640 4.000 320.240 ;
+ END
+ END wb_dat_o[28]
+ PIN wb_dat_o[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 151.430 0.000 151.710 4.000 ;
+ END
+ END wb_dat_o[29]
+ PIN wb_dat_o[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 302.770 0.000 303.050 4.000 ;
+ END
+ END wb_dat_o[2]
+ PIN wb_dat_o[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 454.110 0.000 454.390 4.000 ;
+ END
+ END wb_dat_o[30]
+ PIN wb_dat_o[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 646.040 750.000 646.640 ;
+ END
+ END wb_dat_o[31]
+ PIN wb_dat_o[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 483.090 0.000 483.370 4.000 ;
+ END
+ END wb_dat_o[3]
+ PIN wb_dat_o[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 566.810 996.000 567.090 1000.000 ;
+ END
+ END wb_dat_o[4]
+ PIN wb_dat_o[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 537.830 996.000 538.110 1000.000 ;
+ END
+ END wb_dat_o[5]
+ PIN wb_dat_o[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 924.840 4.000 925.440 ;
+ END
+ END wb_dat_o[6]
+ PIN wb_dat_o[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 51.610 996.000 51.890 1000.000 ;
+ END
+ END wb_dat_o[7]
+ PIN wb_dat_o[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 573.250 0.000 573.530 4.000 ;
+ END
+ END wb_dat_o[8]
+ PIN wb_dat_o[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 255.040 4.000 255.640 ;
+ END
+ END wb_dat_o[9]
+ PIN wb_stb_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 765.040 4.000 765.640 ;
+ END
+ END wb_stb_i
+ PIN wb_we_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 746.000 516.840 750.000 517.440 ;
+ END
+ END wb_we_i
+ OBS
+ LAYER li1 ;
+ RECT 5.520 10.795 744.280 987.445 ;
+ LAYER met1 ;
+ RECT 0.070 10.640 749.730 987.600 ;
+ LAYER met2 ;
+ RECT 0.100 995.720 22.350 996.610 ;
+ RECT 23.190 995.720 51.330 996.610 ;
+ RECT 52.170 995.720 80.310 996.610 ;
+ RECT 81.150 995.720 112.510 996.610 ;
+ RECT 113.350 995.720 141.490 996.610 ;
+ RECT 142.330 995.720 173.690 996.610 ;
+ RECT 174.530 995.720 202.670 996.610 ;
+ RECT 203.510 995.720 234.870 996.610 ;
+ RECT 235.710 995.720 263.850 996.610 ;
+ RECT 264.690 995.720 292.830 996.610 ;
+ RECT 293.670 995.720 325.030 996.610 ;
+ RECT 325.870 995.720 354.010 996.610 ;
+ RECT 354.850 995.720 386.210 996.610 ;
+ RECT 387.050 995.720 415.190 996.610 ;
+ RECT 416.030 995.720 444.170 996.610 ;
+ RECT 445.010 995.720 476.370 996.610 ;
+ RECT 477.210 995.720 505.350 996.610 ;
+ RECT 506.190 995.720 537.550 996.610 ;
+ RECT 538.390 995.720 566.530 996.610 ;
+ RECT 567.370 995.720 595.510 996.610 ;
+ RECT 596.350 995.720 627.710 996.610 ;
+ RECT 628.550 995.720 656.690 996.610 ;
+ RECT 657.530 995.720 688.890 996.610 ;
+ RECT 689.730 995.720 717.870 996.610 ;
+ RECT 718.710 995.720 746.850 996.610 ;
+ RECT 747.690 995.720 749.700 996.610 ;
+ RECT 0.100 4.280 749.700 995.720 ;
+ RECT 0.650 4.000 28.790 4.280 ;
+ RECT 29.630 4.000 57.770 4.280 ;
+ RECT 58.610 4.000 89.970 4.280 ;
+ RECT 90.810 4.000 118.950 4.280 ;
+ RECT 119.790 4.000 151.150 4.280 ;
+ RECT 151.990 4.000 180.130 4.280 ;
+ RECT 180.970 4.000 209.110 4.280 ;
+ RECT 209.950 4.000 241.310 4.280 ;
+ RECT 242.150 4.000 270.290 4.280 ;
+ RECT 271.130 4.000 302.490 4.280 ;
+ RECT 303.330 4.000 331.470 4.280 ;
+ RECT 332.310 4.000 360.450 4.280 ;
+ RECT 361.290 4.000 392.650 4.280 ;
+ RECT 393.490 4.000 421.630 4.280 ;
+ RECT 422.470 4.000 453.830 4.280 ;
+ RECT 454.670 4.000 482.810 4.280 ;
+ RECT 483.650 4.000 511.790 4.280 ;
+ RECT 512.630 4.000 543.990 4.280 ;
+ RECT 544.830 4.000 572.970 4.280 ;
+ RECT 573.810 4.000 605.170 4.280 ;
+ RECT 606.010 4.000 634.150 4.280 ;
+ RECT 634.990 4.000 666.350 4.280 ;
+ RECT 667.190 4.000 695.330 4.280 ;
+ RECT 696.170 4.000 724.310 4.280 ;
+ RECT 725.150 4.000 749.700 4.280 ;
+ LAYER met3 ;
+ RECT 4.400 989.040 748.815 989.905 ;
+ RECT 4.000 966.640 748.815 989.040 ;
+ RECT 4.000 965.240 745.600 966.640 ;
+ RECT 4.000 959.840 748.815 965.240 ;
+ RECT 4.400 958.440 748.815 959.840 ;
+ RECT 4.000 936.040 748.815 958.440 ;
+ RECT 4.000 934.640 745.600 936.040 ;
+ RECT 4.000 925.840 748.815 934.640 ;
+ RECT 4.400 924.440 748.815 925.840 ;
+ RECT 4.000 902.040 748.815 924.440 ;
+ RECT 4.000 900.640 745.600 902.040 ;
+ RECT 4.000 895.240 748.815 900.640 ;
+ RECT 4.400 893.840 748.815 895.240 ;
+ RECT 4.000 871.440 748.815 893.840 ;
+ RECT 4.000 870.040 745.600 871.440 ;
+ RECT 4.000 864.640 748.815 870.040 ;
+ RECT 4.400 863.240 748.815 864.640 ;
+ RECT 4.000 837.440 748.815 863.240 ;
+ RECT 4.000 836.040 745.600 837.440 ;
+ RECT 4.000 830.640 748.815 836.040 ;
+ RECT 4.400 829.240 748.815 830.640 ;
+ RECT 4.000 806.840 748.815 829.240 ;
+ RECT 4.000 805.440 745.600 806.840 ;
+ RECT 4.000 800.040 748.815 805.440 ;
+ RECT 4.400 798.640 748.815 800.040 ;
+ RECT 4.000 776.240 748.815 798.640 ;
+ RECT 4.000 774.840 745.600 776.240 ;
+ RECT 4.000 766.040 748.815 774.840 ;
+ RECT 4.400 764.640 748.815 766.040 ;
+ RECT 4.000 742.240 748.815 764.640 ;
+ RECT 4.000 740.840 745.600 742.240 ;
+ RECT 4.000 735.440 748.815 740.840 ;
+ RECT 4.400 734.040 748.815 735.440 ;
+ RECT 4.000 711.640 748.815 734.040 ;
+ RECT 4.000 710.240 745.600 711.640 ;
+ RECT 4.000 704.840 748.815 710.240 ;
+ RECT 4.400 703.440 748.815 704.840 ;
+ RECT 4.000 677.640 748.815 703.440 ;
+ RECT 4.000 676.240 745.600 677.640 ;
+ RECT 4.000 670.840 748.815 676.240 ;
+ RECT 4.400 669.440 748.815 670.840 ;
+ RECT 4.000 647.040 748.815 669.440 ;
+ RECT 4.000 645.640 745.600 647.040 ;
+ RECT 4.000 640.240 748.815 645.640 ;
+ RECT 4.400 638.840 748.815 640.240 ;
+ RECT 4.000 616.440 748.815 638.840 ;
+ RECT 4.000 615.040 745.600 616.440 ;
+ RECT 4.000 606.240 748.815 615.040 ;
+ RECT 4.400 604.840 748.815 606.240 ;
+ RECT 4.000 582.440 748.815 604.840 ;
+ RECT 4.000 581.040 745.600 582.440 ;
+ RECT 4.000 575.640 748.815 581.040 ;
+ RECT 4.400 574.240 748.815 575.640 ;
+ RECT 4.000 551.840 748.815 574.240 ;
+ RECT 4.000 550.440 745.600 551.840 ;
+ RECT 4.000 541.640 748.815 550.440 ;
+ RECT 4.400 540.240 748.815 541.640 ;
+ RECT 4.000 517.840 748.815 540.240 ;
+ RECT 4.000 516.440 745.600 517.840 ;
+ RECT 4.000 511.040 748.815 516.440 ;
+ RECT 4.400 509.640 748.815 511.040 ;
+ RECT 4.000 487.240 748.815 509.640 ;
+ RECT 4.000 485.840 745.600 487.240 ;
+ RECT 4.000 480.440 748.815 485.840 ;
+ RECT 4.400 479.040 748.815 480.440 ;
+ RECT 4.000 456.640 748.815 479.040 ;
+ RECT 4.000 455.240 745.600 456.640 ;
+ RECT 4.000 446.440 748.815 455.240 ;
+ RECT 4.400 445.040 748.815 446.440 ;
+ RECT 4.000 422.640 748.815 445.040 ;
+ RECT 4.000 421.240 745.600 422.640 ;
+ RECT 4.000 415.840 748.815 421.240 ;
+ RECT 4.400 414.440 748.815 415.840 ;
+ RECT 4.000 392.040 748.815 414.440 ;
+ RECT 4.000 390.640 745.600 392.040 ;
+ RECT 4.000 381.840 748.815 390.640 ;
+ RECT 4.400 380.440 748.815 381.840 ;
+ RECT 4.000 358.040 748.815 380.440 ;
+ RECT 4.000 356.640 745.600 358.040 ;
+ RECT 4.000 351.240 748.815 356.640 ;
+ RECT 4.400 349.840 748.815 351.240 ;
+ RECT 4.000 327.440 748.815 349.840 ;
+ RECT 4.000 326.040 745.600 327.440 ;
+ RECT 4.000 320.640 748.815 326.040 ;
+ RECT 4.400 319.240 748.815 320.640 ;
+ RECT 4.000 293.440 748.815 319.240 ;
+ RECT 4.000 292.040 745.600 293.440 ;
+ RECT 4.000 286.640 748.815 292.040 ;
+ RECT 4.400 285.240 748.815 286.640 ;
+ RECT 4.000 262.840 748.815 285.240 ;
+ RECT 4.000 261.440 745.600 262.840 ;
+ RECT 4.000 256.040 748.815 261.440 ;
+ RECT 4.400 254.640 748.815 256.040 ;
+ RECT 4.000 232.240 748.815 254.640 ;
+ RECT 4.000 230.840 745.600 232.240 ;
+ RECT 4.000 222.040 748.815 230.840 ;
+ RECT 4.400 220.640 748.815 222.040 ;
+ RECT 4.000 198.240 748.815 220.640 ;
+ RECT 4.000 196.840 745.600 198.240 ;
+ RECT 4.000 191.440 748.815 196.840 ;
+ RECT 4.400 190.040 748.815 191.440 ;
+ RECT 4.000 167.640 748.815 190.040 ;
+ RECT 4.000 166.240 745.600 167.640 ;
+ RECT 4.000 160.840 748.815 166.240 ;
+ RECT 4.400 159.440 748.815 160.840 ;
+ RECT 4.000 133.640 748.815 159.440 ;
+ RECT 4.000 132.240 745.600 133.640 ;
+ RECT 4.000 126.840 748.815 132.240 ;
+ RECT 4.400 125.440 748.815 126.840 ;
+ RECT 4.000 103.040 748.815 125.440 ;
+ RECT 4.000 101.640 745.600 103.040 ;
+ RECT 4.000 96.240 748.815 101.640 ;
+ RECT 4.400 94.840 748.815 96.240 ;
+ RECT 4.000 72.440 748.815 94.840 ;
+ RECT 4.000 71.040 745.600 72.440 ;
+ RECT 4.000 62.240 748.815 71.040 ;
+ RECT 4.400 60.840 748.815 62.240 ;
+ RECT 4.000 38.440 748.815 60.840 ;
+ RECT 4.000 37.040 745.600 38.440 ;
+ RECT 4.000 31.640 748.815 37.040 ;
+ RECT 4.400 30.240 748.815 31.640 ;
+ RECT 4.000 10.715 748.815 30.240 ;
+ LAYER met4 ;
+ RECT 495.255 351.735 558.240 760.065 ;
+ RECT 560.640 351.735 635.040 760.065 ;
+ RECT 637.440 351.735 711.840 760.065 ;
+ RECT 714.240 351.735 748.585 760.065 ;
+ END
+END trng_wb_wrapper
+END LIBRARY
+
diff --git a/lef/trng3_wb_wrapper.lef b/lef/trng3_wb_wrapper.lef
new file mode 100644
index 0000000..abfcbca
--- /dev/null
+++ b/lef/trng3_wb_wrapper.lef
@@ -0,0 +1,1151 @@
+VERSION 5.7 ;
+ NOWIREEXTENSIONATPIN ON ;
+ DIVIDERCHAR "/" ;
+ BUSBITCHARS "[]" ;
+MACRO trng_wb_wrapper
+ CLASS BLOCK ;
+ FOREIGN trng_wb_wrapper ;
+ ORIGIN 0.000 0.000 ;
+ SIZE 900.000 BY 1200.000 ;
+ PIN rst_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 544.040 900.000 544.640 ;
+ END
+ END rst_i
+ PIN trng_buffer_o[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 244.810 1196.000 245.090 1200.000 ;
+ END
+ END trng_buffer_o[0]
+ PIN trng_buffer_o[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 343.440 4.000 344.040 ;
+ END
+ END trng_buffer_o[10]
+ PIN trng_buffer_o[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 499.190 1196.000 499.470 1200.000 ;
+ END
+ END trng_buffer_o[11]
+ PIN trng_buffer_o[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 880.640 4.000 881.240 ;
+ END
+ END trng_buffer_o[12]
+ PIN trng_buffer_o[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 112.240 4.000 112.840 ;
+ END
+ END trng_buffer_o[13]
+ PIN trng_buffer_o[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 690.240 4.000 690.840 ;
+ END
+ END trng_buffer_o[14]
+ PIN trng_buffer_o[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 459.040 4.000 459.640 ;
+ END
+ END trng_buffer_o[15]
+ PIN trng_buffer_o[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 209.390 1196.000 209.670 1200.000 ;
+ END
+ END trng_buffer_o[16]
+ PIN trng_buffer_o[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 254.470 0.000 254.750 4.000 ;
+ END
+ END trng_buffer_o[17]
+ PIN trng_buffer_o[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 618.330 0.000 618.610 4.000 ;
+ END
+ END trng_buffer_o[18]
+ PIN trng_buffer_o[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 792.210 1196.000 792.490 1200.000 ;
+ END
+ END trng_buffer_o[19]
+ PIN trng_buffer_o[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 85.040 900.000 85.640 ;
+ END
+ END trng_buffer_o[1]
+ PIN trng_buffer_o[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 1084.640 900.000 1085.240 ;
+ END
+ END trng_buffer_o[20]
+ PIN trng_buffer_o[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 727.810 0.000 728.090 4.000 ;
+ END
+ END trng_buffer_o[21]
+ PIN trng_buffer_o[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 200.640 900.000 201.240 ;
+ END
+ END trng_buffer_o[22]
+ PIN trng_buffer_o[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 1006.440 900.000 1007.040 ;
+ END
+ END trng_buffer_o[23]
+ PIN trng_buffer_o[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 389.710 1196.000 389.990 1200.000 ;
+ END
+ END trng_buffer_o[24]
+ PIN trng_buffer_o[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 25.850 1196.000 26.130 1200.000 ;
+ END
+ END trng_buffer_o[25]
+ PIN trng_buffer_o[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 1122.040 900.000 1122.640 ;
+ END
+ END trng_buffer_o[26]
+ PIN trng_buffer_o[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 135.330 1196.000 135.610 1200.000 ;
+ END
+ END trng_buffer_o[27]
+ PIN trng_buffer_o[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 652.840 4.000 653.440 ;
+ END
+ END trng_buffer_o[28]
+ PIN trng_buffer_o[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 44.240 900.000 44.840 ;
+ END
+ END trng_buffer_o[29]
+ PIN trng_buffer_o[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 215.830 0.000 216.110 4.000 ;
+ END
+ END trng_buffer_o[2]
+ PIN trng_buffer_o[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 428.350 1196.000 428.630 1200.000 ;
+ END
+ END trng_buffer_o[30]
+ PIN trng_buffer_o[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 834.070 0.000 834.350 4.000 ;
+ END
+ END trng_buffer_o[31]
+ PIN trng_buffer_o[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 144.990 0.000 145.270 4.000 ;
+ END
+ END trng_buffer_o[3]
+ PIN trng_buffer_o[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 318.870 1196.000 319.150 1200.000 ;
+ END
+ END trng_buffer_o[4]
+ PIN trng_buffer_o[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 391.040 900.000 391.640 ;
+ END
+ END trng_buffer_o[5]
+ PIN trng_buffer_o[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 37.440 4.000 38.040 ;
+ END
+ END trng_buffer_o[6]
+ PIN trng_buffer_o[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1037.040 4.000 1037.640 ;
+ END
+ END trng_buffer_o[7]
+ PIN trng_buffer_o[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 768.440 4.000 769.040 ;
+ END
+ END trng_buffer_o[8]
+ PIN trng_buffer_o[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 718.150 1196.000 718.430 1200.000 ;
+ END
+ END trng_buffer_o[9]
+ PIN trng_valid_o
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 508.850 0.000 509.130 4.000 ;
+ END
+ END trng_valid_o
+ PIN vccd1
+ DIRECTION INPUT ;
+ USE POWER ;
+ PORT
+ LAYER met4 ;
+ RECT 21.040 10.640 22.640 1188.880 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 174.640 10.640 176.240 1188.880 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 328.240 10.640 329.840 1188.880 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 481.840 10.640 483.440 1188.880 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 635.440 10.640 637.040 1188.880 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 789.040 10.640 790.640 1188.880 ;
+ END
+ END vccd1
+ PIN vssd1
+ DIRECTION INPUT ;
+ USE GROUND ;
+ PORT
+ LAYER met4 ;
+ RECT 97.840 10.640 99.440 1188.880 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 251.440 10.640 253.040 1188.880 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 405.040 10.640 406.640 1188.880 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 558.640 10.640 560.240 1188.880 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 712.240 10.640 713.840 1188.880 ;
+ END
+ PORT
+ LAYER met4 ;
+ RECT 865.840 10.640 867.440 1188.880 ;
+ END
+ END vssd1
+ PIN wb_ack_o
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 428.440 900.000 429.040 ;
+ END
+ END wb_ack_o
+ PIN wb_adr_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 1043.840 900.000 1044.440 ;
+ END
+ END wb_adr_i[0]
+ PIN wb_adr_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 928.240 900.000 928.840 ;
+ END
+ END wb_adr_i[1]
+ PIN wb_adr_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 853.440 900.000 854.040 ;
+ END
+ END wb_adr_i[2]
+ PIN wb_adr_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 812.640 900.000 813.240 ;
+ END
+ END wb_adr_i[3]
+ PIN wb_adr_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 434.790 0.000 435.070 4.000 ;
+ END
+ END wb_adr_i[4]
+ PIN wb_adr_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 74.840 4.000 75.440 ;
+ END
+ END wb_adr_i[5]
+ PIN wb_adr_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 1159.440 900.000 1160.040 ;
+ END
+ END wb_adr_i[6]
+ PIN wb_adr_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 727.640 4.000 728.240 ;
+ END
+ END wb_adr_i[7]
+ PIN wb_adr_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 354.290 1196.000 354.570 1200.000 ;
+ END
+ END wb_adr_i[8]
+ PIN wb_clk_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 659.640 900.000 660.240 ;
+ END
+ END wb_clk_i
+ PIN wb_cyc_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 700.440 900.000 701.040 ;
+ END
+ END wb_cyc_i
+ PIN wb_dat_i[0]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 170.750 1196.000 171.030 1200.000 ;
+ END
+ END wb_dat_i[0]
+ PIN wb_dat_i[10]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 463.770 1196.000 464.050 1200.000 ;
+ END
+ END wb_dat_i[10]
+ PIN wb_dat_i[11]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 827.630 1196.000 827.910 1200.000 ;
+ END
+ END wb_dat_i[11]
+ PIN wb_dat_i[12]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 289.890 0.000 290.170 4.000 ;
+ END
+ END wb_dat_i[12]
+ PIN wb_dat_i[13]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 353.640 900.000 354.240 ;
+ END
+ END wb_dat_i[13]
+ PIN wb_dat_i[14]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 238.040 900.000 238.640 ;
+ END
+ END wb_dat_i[14]
+ PIN wb_dat_i[15]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 537.240 4.000 537.840 ;
+ END
+ END wb_dat_i[15]
+ PIN wb_dat_i[16]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 70.930 0.000 71.210 4.000 ;
+ END
+ END wb_dat_i[16]
+ PIN wb_dat_i[17]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 6.840 900.000 7.440 ;
+ END
+ END wb_dat_i[17]
+ PIN wb_dat_i[18]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 316.240 900.000 316.840 ;
+ END
+ END wb_dat_i[18]
+ PIN wb_dat_i[19]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 898.470 1196.000 898.750 1200.000 ;
+ END
+ END wb_dat_i[19]
+ PIN wb_dat_i[1]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 268.640 4.000 269.240 ;
+ END
+ END wb_dat_i[1]
+ PIN wb_dat_i[20]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 798.650 0.000 798.930 4.000 ;
+ END
+ END wb_dat_i[20]
+ PIN wb_dat_i[21]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 399.370 0.000 399.650 4.000 ;
+ END
+ END wb_dat_i[21]
+ PIN wb_dat_i[22]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 469.240 900.000 469.840 ;
+ END
+ END wb_dat_i[22]
+ PIN wb_dat_i[23]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 99.910 1196.000 100.190 1200.000 ;
+ END
+ END wb_dat_i[23]
+ PIN wb_dat_i[24]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 843.240 4.000 843.840 ;
+ END
+ END wb_dat_i[24]
+ PIN wb_dat_i[25]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 159.840 900.000 160.440 ;
+ END
+ END wb_dat_i[25]
+ PIN wb_dat_i[26]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 996.240 4.000 996.840 ;
+ END
+ END wb_dat_i[26]
+ PIN wb_dat_i[27]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 190.440 4.000 191.040 ;
+ END
+ END wb_dat_i[27]
+ PIN wb_dat_i[28]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 573.250 1196.000 573.530 1200.000 ;
+ END
+ END wb_dat_i[28]
+ PIN wb_dat_i[29]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 153.040 4.000 153.640 ;
+ END
+ END wb_dat_i[29]
+ PIN wb_dat_i[2]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 106.350 0.000 106.630 4.000 ;
+ END
+ END wb_dat_i[2]
+ PIN wb_dat_i[30]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 325.310 0.000 325.590 4.000 ;
+ END
+ END wb_dat_i[30]
+ PIN wb_dat_i[31]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 122.440 900.000 123.040 ;
+ END
+ END wb_dat_i[31]
+ PIN wb_dat_i[3]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 737.840 900.000 738.440 ;
+ END
+ END wb_dat_i[3]
+ PIN wb_dat_i[4]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 506.640 900.000 507.240 ;
+ END
+ END wb_dat_i[4]
+ PIN wb_dat_i[5]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 763.230 0.000 763.510 4.000 ;
+ END
+ END wb_dat_i[5]
+ PIN wb_dat_i[6]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 805.840 4.000 806.440 ;
+ END
+ END wb_dat_i[6]
+ PIN wb_dat_i[7]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 612.040 4.000 612.640 ;
+ END
+ END wb_dat_i[7]
+ PIN wb_dat_i[8]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 574.640 4.000 575.240 ;
+ END
+ END wb_dat_i[8]
+ PIN wb_dat_i[9]
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 584.840 900.000 585.440 ;
+ END
+ END wb_dat_i[9]
+ PIN wb_dat_o[0]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 890.840 900.000 891.440 ;
+ END
+ END wb_dat_o[0]
+ PIN wb_dat_o[10]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 872.710 0.000 872.990 4.000 ;
+ END
+ END wb_dat_o[10]
+ PIN wb_dat_o[11]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 969.040 900.000 969.640 ;
+ END
+ END wb_dat_o[11]
+ PIN wb_dat_o[12]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 227.840 4.000 228.440 ;
+ END
+ END wb_dat_o[12]
+ PIN wb_dat_o[13]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1152.640 4.000 1153.240 ;
+ END
+ END wb_dat_o[13]
+ PIN wb_dat_o[14]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 421.640 4.000 422.240 ;
+ END
+ END wb_dat_o[14]
+ PIN wb_dat_o[15]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 0.090 0.000 0.370 4.000 ;
+ END
+ END wb_dat_o[15]
+ PIN wb_dat_o[16]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 653.750 0.000 654.030 4.000 ;
+ END
+ END wb_dat_o[16]
+ PIN wb_dat_o[17]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1190.040 4.000 1190.640 ;
+ END
+ END wb_dat_o[17]
+ PIN wb_dat_o[18]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 280.230 1196.000 280.510 1200.000 ;
+ END
+ END wb_dat_o[18]
+ PIN wb_dat_o[19]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 608.670 1196.000 608.950 1200.000 ;
+ END
+ END wb_dat_o[19]
+ PIN wb_dat_o[1]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 958.840 4.000 959.440 ;
+ END
+ END wb_dat_o[1]
+ PIN wb_dat_o[20]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 496.440 4.000 497.040 ;
+ END
+ END wb_dat_o[20]
+ PIN wb_dat_o[21]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 35.510 0.000 35.790 4.000 ;
+ END
+ END wb_dat_o[21]
+ PIN wb_dat_o[22]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 753.570 1196.000 753.850 1200.000 ;
+ END
+ END wb_dat_o[22]
+ PIN wb_dat_o[23]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 534.610 1196.000 534.890 1200.000 ;
+ END
+ END wb_dat_o[23]
+ PIN wb_dat_o[24]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 470.210 0.000 470.490 4.000 ;
+ END
+ END wb_dat_o[24]
+ PIN wb_dat_o[25]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 863.050 1196.000 863.330 1200.000 ;
+ END
+ END wb_dat_o[25]
+ PIN wb_dat_o[26]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 275.440 900.000 276.040 ;
+ END
+ END wb_dat_o[26]
+ PIN wb_dat_o[27]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1074.440 4.000 1075.040 ;
+ END
+ END wb_dat_o[27]
+ PIN wb_dat_o[28]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 384.240 4.000 384.840 ;
+ END
+ END wb_dat_o[28]
+ PIN wb_dat_o[29]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 180.410 0.000 180.690 4.000 ;
+ END
+ END wb_dat_o[29]
+ PIN wb_dat_o[2]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 363.950 0.000 364.230 4.000 ;
+ END
+ END wb_dat_o[2]
+ PIN wb_dat_o[30]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 544.270 0.000 544.550 4.000 ;
+ END
+ END wb_dat_o[30]
+ PIN wb_dat_o[31]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 775.240 900.000 775.840 ;
+ END
+ END wb_dat_o[31]
+ PIN wb_dat_o[3]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 579.690 0.000 579.970 4.000 ;
+ END
+ END wb_dat_o[3]
+ PIN wb_dat_o[4]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 682.730 1196.000 683.010 1200.000 ;
+ END
+ END wb_dat_o[4]
+ PIN wb_dat_o[5]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 644.090 1196.000 644.370 1200.000 ;
+ END
+ END wb_dat_o[5]
+ PIN wb_dat_o[6]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 1111.840 4.000 1112.440 ;
+ END
+ END wb_dat_o[6]
+ PIN wb_dat_o[7]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 64.490 1196.000 64.770 1200.000 ;
+ END
+ END wb_dat_o[7]
+ PIN wb_dat_o[8]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met2 ;
+ RECT 689.170 0.000 689.450 4.000 ;
+ END
+ END wb_dat_o[8]
+ PIN wb_dat_o[9]
+ DIRECTION OUTPUT TRISTATE ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 306.040 4.000 306.640 ;
+ END
+ END wb_dat_o[9]
+ PIN wb_stb_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 0.000 921.440 4.000 922.040 ;
+ END
+ END wb_stb_i
+ PIN wb_we_i
+ DIRECTION INPUT ;
+ USE SIGNAL ;
+ PORT
+ LAYER met3 ;
+ RECT 896.000 622.240 900.000 622.840 ;
+ END
+ END wb_we_i
+ OBS
+ LAYER li1 ;
+ RECT 5.520 10.795 894.240 1188.725 ;
+ LAYER met1 ;
+ RECT 0.070 10.640 899.690 1188.880 ;
+ LAYER met2 ;
+ RECT 0.100 1195.720 25.570 1196.530 ;
+ RECT 26.410 1195.720 64.210 1196.530 ;
+ RECT 65.050 1195.720 99.630 1196.530 ;
+ RECT 100.470 1195.720 135.050 1196.530 ;
+ RECT 135.890 1195.720 170.470 1196.530 ;
+ RECT 171.310 1195.720 209.110 1196.530 ;
+ RECT 209.950 1195.720 244.530 1196.530 ;
+ RECT 245.370 1195.720 279.950 1196.530 ;
+ RECT 280.790 1195.720 318.590 1196.530 ;
+ RECT 319.430 1195.720 354.010 1196.530 ;
+ RECT 354.850 1195.720 389.430 1196.530 ;
+ RECT 390.270 1195.720 428.070 1196.530 ;
+ RECT 428.910 1195.720 463.490 1196.530 ;
+ RECT 464.330 1195.720 498.910 1196.530 ;
+ RECT 499.750 1195.720 534.330 1196.530 ;
+ RECT 535.170 1195.720 572.970 1196.530 ;
+ RECT 573.810 1195.720 608.390 1196.530 ;
+ RECT 609.230 1195.720 643.810 1196.530 ;
+ RECT 644.650 1195.720 682.450 1196.530 ;
+ RECT 683.290 1195.720 717.870 1196.530 ;
+ RECT 718.710 1195.720 753.290 1196.530 ;
+ RECT 754.130 1195.720 791.930 1196.530 ;
+ RECT 792.770 1195.720 827.350 1196.530 ;
+ RECT 828.190 1195.720 862.770 1196.530 ;
+ RECT 863.610 1195.720 898.190 1196.530 ;
+ RECT 899.030 1195.720 899.670 1196.530 ;
+ RECT 0.100 4.280 899.670 1195.720 ;
+ RECT 0.650 3.670 35.230 4.280 ;
+ RECT 36.070 3.670 70.650 4.280 ;
+ RECT 71.490 3.670 106.070 4.280 ;
+ RECT 106.910 3.670 144.710 4.280 ;
+ RECT 145.550 3.670 180.130 4.280 ;
+ RECT 180.970 3.670 215.550 4.280 ;
+ RECT 216.390 3.670 254.190 4.280 ;
+ RECT 255.030 3.670 289.610 4.280 ;
+ RECT 290.450 3.670 325.030 4.280 ;
+ RECT 325.870 3.670 363.670 4.280 ;
+ RECT 364.510 3.670 399.090 4.280 ;
+ RECT 399.930 3.670 434.510 4.280 ;
+ RECT 435.350 3.670 469.930 4.280 ;
+ RECT 470.770 3.670 508.570 4.280 ;
+ RECT 509.410 3.670 543.990 4.280 ;
+ RECT 544.830 3.670 579.410 4.280 ;
+ RECT 580.250 3.670 618.050 4.280 ;
+ RECT 618.890 3.670 653.470 4.280 ;
+ RECT 654.310 3.670 688.890 4.280 ;
+ RECT 689.730 3.670 727.530 4.280 ;
+ RECT 728.370 3.670 762.950 4.280 ;
+ RECT 763.790 3.670 798.370 4.280 ;
+ RECT 799.210 3.670 833.790 4.280 ;
+ RECT 834.630 3.670 872.430 4.280 ;
+ RECT 873.270 3.670 899.670 4.280 ;
+ LAYER met3 ;
+ RECT 4.400 1189.640 899.695 1190.505 ;
+ RECT 4.000 1160.440 899.695 1189.640 ;
+ RECT 4.000 1159.040 895.600 1160.440 ;
+ RECT 4.000 1153.640 899.695 1159.040 ;
+ RECT 4.400 1152.240 899.695 1153.640 ;
+ RECT 4.000 1123.040 899.695 1152.240 ;
+ RECT 4.000 1121.640 895.600 1123.040 ;
+ RECT 4.000 1112.840 899.695 1121.640 ;
+ RECT 4.400 1111.440 899.695 1112.840 ;
+ RECT 4.000 1085.640 899.695 1111.440 ;
+ RECT 4.000 1084.240 895.600 1085.640 ;
+ RECT 4.000 1075.440 899.695 1084.240 ;
+ RECT 4.400 1074.040 899.695 1075.440 ;
+ RECT 4.000 1044.840 899.695 1074.040 ;
+ RECT 4.000 1043.440 895.600 1044.840 ;
+ RECT 4.000 1038.040 899.695 1043.440 ;
+ RECT 4.400 1036.640 899.695 1038.040 ;
+ RECT 4.000 1007.440 899.695 1036.640 ;
+ RECT 4.000 1006.040 895.600 1007.440 ;
+ RECT 4.000 997.240 899.695 1006.040 ;
+ RECT 4.400 995.840 899.695 997.240 ;
+ RECT 4.000 970.040 899.695 995.840 ;
+ RECT 4.000 968.640 895.600 970.040 ;
+ RECT 4.000 959.840 899.695 968.640 ;
+ RECT 4.400 958.440 899.695 959.840 ;
+ RECT 4.000 929.240 899.695 958.440 ;
+ RECT 4.000 927.840 895.600 929.240 ;
+ RECT 4.000 922.440 899.695 927.840 ;
+ RECT 4.400 921.040 899.695 922.440 ;
+ RECT 4.000 891.840 899.695 921.040 ;
+ RECT 4.000 890.440 895.600 891.840 ;
+ RECT 4.000 881.640 899.695 890.440 ;
+ RECT 4.400 880.240 899.695 881.640 ;
+ RECT 4.000 854.440 899.695 880.240 ;
+ RECT 4.000 853.040 895.600 854.440 ;
+ RECT 4.000 844.240 899.695 853.040 ;
+ RECT 4.400 842.840 899.695 844.240 ;
+ RECT 4.000 813.640 899.695 842.840 ;
+ RECT 4.000 812.240 895.600 813.640 ;
+ RECT 4.000 806.840 899.695 812.240 ;
+ RECT 4.400 805.440 899.695 806.840 ;
+ RECT 4.000 776.240 899.695 805.440 ;
+ RECT 4.000 774.840 895.600 776.240 ;
+ RECT 4.000 769.440 899.695 774.840 ;
+ RECT 4.400 768.040 899.695 769.440 ;
+ RECT 4.000 738.840 899.695 768.040 ;
+ RECT 4.000 737.440 895.600 738.840 ;
+ RECT 4.000 728.640 899.695 737.440 ;
+ RECT 4.400 727.240 899.695 728.640 ;
+ RECT 4.000 701.440 899.695 727.240 ;
+ RECT 4.000 700.040 895.600 701.440 ;
+ RECT 4.000 691.240 899.695 700.040 ;
+ RECT 4.400 689.840 899.695 691.240 ;
+ RECT 4.000 660.640 899.695 689.840 ;
+ RECT 4.000 659.240 895.600 660.640 ;
+ RECT 4.000 653.840 899.695 659.240 ;
+ RECT 4.400 652.440 899.695 653.840 ;
+ RECT 4.000 623.240 899.695 652.440 ;
+ RECT 4.000 621.840 895.600 623.240 ;
+ RECT 4.000 613.040 899.695 621.840 ;
+ RECT 4.400 611.640 899.695 613.040 ;
+ RECT 4.000 585.840 899.695 611.640 ;
+ RECT 4.000 584.440 895.600 585.840 ;
+ RECT 4.000 575.640 899.695 584.440 ;
+ RECT 4.400 574.240 899.695 575.640 ;
+ RECT 4.000 545.040 899.695 574.240 ;
+ RECT 4.000 543.640 895.600 545.040 ;
+ RECT 4.000 538.240 899.695 543.640 ;
+ RECT 4.400 536.840 899.695 538.240 ;
+ RECT 4.000 507.640 899.695 536.840 ;
+ RECT 4.000 506.240 895.600 507.640 ;
+ RECT 4.000 497.440 899.695 506.240 ;
+ RECT 4.400 496.040 899.695 497.440 ;
+ RECT 4.000 470.240 899.695 496.040 ;
+ RECT 4.000 468.840 895.600 470.240 ;
+ RECT 4.000 460.040 899.695 468.840 ;
+ RECT 4.400 458.640 899.695 460.040 ;
+ RECT 4.000 429.440 899.695 458.640 ;
+ RECT 4.000 428.040 895.600 429.440 ;
+ RECT 4.000 422.640 899.695 428.040 ;
+ RECT 4.400 421.240 899.695 422.640 ;
+ RECT 4.000 392.040 899.695 421.240 ;
+ RECT 4.000 390.640 895.600 392.040 ;
+ RECT 4.000 385.240 899.695 390.640 ;
+ RECT 4.400 383.840 899.695 385.240 ;
+ RECT 4.000 354.640 899.695 383.840 ;
+ RECT 4.000 353.240 895.600 354.640 ;
+ RECT 4.000 344.440 899.695 353.240 ;
+ RECT 4.400 343.040 899.695 344.440 ;
+ RECT 4.000 317.240 899.695 343.040 ;
+ RECT 4.000 315.840 895.600 317.240 ;
+ RECT 4.000 307.040 899.695 315.840 ;
+ RECT 4.400 305.640 899.695 307.040 ;
+ RECT 4.000 276.440 899.695 305.640 ;
+ RECT 4.000 275.040 895.600 276.440 ;
+ RECT 4.000 269.640 899.695 275.040 ;
+ RECT 4.400 268.240 899.695 269.640 ;
+ RECT 4.000 239.040 899.695 268.240 ;
+ RECT 4.000 237.640 895.600 239.040 ;
+ RECT 4.000 228.840 899.695 237.640 ;
+ RECT 4.400 227.440 899.695 228.840 ;
+ RECT 4.000 201.640 899.695 227.440 ;
+ RECT 4.000 200.240 895.600 201.640 ;
+ RECT 4.000 191.440 899.695 200.240 ;
+ RECT 4.400 190.040 899.695 191.440 ;
+ RECT 4.000 160.840 899.695 190.040 ;
+ RECT 4.000 159.440 895.600 160.840 ;
+ RECT 4.000 154.040 899.695 159.440 ;
+ RECT 4.400 152.640 899.695 154.040 ;
+ RECT 4.000 123.440 899.695 152.640 ;
+ RECT 4.000 122.040 895.600 123.440 ;
+ RECT 4.000 113.240 899.695 122.040 ;
+ RECT 4.400 111.840 899.695 113.240 ;
+ RECT 4.000 86.040 899.695 111.840 ;
+ RECT 4.000 84.640 895.600 86.040 ;
+ RECT 4.000 75.840 899.695 84.640 ;
+ RECT 4.400 74.440 899.695 75.840 ;
+ RECT 4.000 45.240 899.695 74.440 ;
+ RECT 4.000 43.840 895.600 45.240 ;
+ RECT 4.000 38.440 899.695 43.840 ;
+ RECT 4.400 37.040 899.695 38.440 ;
+ RECT 4.000 10.715 899.695 37.040 ;
+ LAYER met4 ;
+ RECT 647.055 262.655 711.840 760.745 ;
+ RECT 714.240 262.655 788.640 760.745 ;
+ RECT 791.040 262.655 865.440 760.745 ;
+ RECT 867.840 262.655 895.785 760.745 ;
+ END
+END trng_wb_wrapper
+END LIBRARY
+
diff --git a/openlane/trng_wb_wrapper/base.sdc b/openlane/trng_wb_wrapper/base.sdc
new file mode 100644
index 0000000..ecb2b02
--- /dev/null
+++ b/openlane/trng_wb_wrapper/base.sdc
@@ -0,0 +1,74 @@
+# Randsack digital top macro timing constraints.
+#
+# SPDX-FileCopyrightText: (c) 2021 Harrison Pham <harrison@harrisonpham.com>
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+set ::env(WB_CLOCK_PERIOD) "25"
+set ::env(WB_CLOCK_PORT) "wb_clk_i"
+
+set ::env(RING0_CLOCK_PERIOD) "10"
+set ::env(RING0_CLOCK_PORT) "clockp[0]"
+
+set ::env(RING1_CLOCK_PERIOD) "10"
+set ::env(RING1_CLOCK_PORT) "clockp[1]"
+
+set ::env(RING2_CLOCK_PERIOD) "10"
+set ::env(RING2_CLOCK_PORT) "clockp[2]"
+
+set ::env(RING3_CLOCK_PERIOD) "10"
+set ::env(RING3_CLOCK_PORT) "clockp[3]"
+
+# if {[info exists ::env(WB_CLOCK_PORT)] && $::env(WB_CLOCK_PORT) != ""} {
+# create_clock [get_ports $::env(WB_CLOCK_PORT)] -name $::env(WB_CLOCK_PORT) -period $::env(CLOCK_PERIOD)
+# } else {
+# create_clock -name VIRTUAL_CLK -period $::env(CLOCK_PERIOD)
+# set ::env(WB_CLOCK_PORT) VIRTUAL_CLK
+# }
+
+# set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+# set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_PCT)]
+# puts "\[INFO\]: Setting output delay to: $output_delay_value"
+# puts "\[INFO\]: Setting input delay to: $input_delay_value"
+
+# set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
+
+# set clk_indx [lsearch [all_inputs] [get_port $::env(WB_CLOCK_PORT)]]
+#set rst_indx [lsearch [all_inputs] [get_port resetn]]
+# set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
+#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
+# set all_inputs_wo_clk_rst $all_inputs_wo_clk
+
+# TODO set this as parameter
+# set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
+# set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
+# puts "\[INFO\]: Setting load to: $cap_load"
+# set_load $cap_load [all_outputs]
+
+# Extra clocks for macros.
+# NOTE: These don't need any input/output delays since this design just uses it for clock counting.
+create_clock [get_ports $::env(RING0_CLOCK_PORT)] -name $::env(RING0_CLOCK_PORT) -period $::env(RING0_CLOCK_PERIOD)
+create_clock [get_ports $::env(RING1_CLOCK_PORT)] -name $::env(RING1_CLOCK_PORT) -period $::env(RING1_CLOCK_PERIOD)
+create_clock [get_ports $::env(RING2_CLOCK_PORT)] -name $::env(RING2_CLOCK_PORT) -period $::env(RING2_CLOCK_PERIOD)
+create_clock [get_ports $::env(RING3_CLOCK_PORT)] -name $::env(RING3_CLOCK_PORT) -period $::env(RING3_CLOCK_PERIOD)
+
+set_false_path -from [get_clocks $::env(WB_CLOCK_PORT)] -to [get_clocks $::env(RING0_CLOCK_PORT)]
+set_false_path -from [get_clocks $::env(WB_CLOCK_PORT)] -to [get_clocks $::env(RING1_CLOCK_PORT)]
+set_false_path -from [get_clocks $::env(WB_CLOCK_PORT)] -to [get_clocks $::env(RING2_CLOCK_PORT)]
+set_false_path -from [get_clocks $::env(WB_CLOCK_PORT)] -to [get_clocks $::env(RING3_CLOCK_PORT)]
+
+set_false_path -from [get_clocks $::env(RING0_CLOCK_PORT)] -to [get_clocks $::env(WB_CLOCK_PORT)]
+set_false_path -from [get_clocks $::env(RING1_CLOCK_PORT)] -to [get_clocks $::env(WB_CLOCK_PORT)]
+set_false_path -from [get_clocks $::env(RING2_CLOCK_PORT)] -to [get_clocks $::env(WB_CLOCK_PORT)]
+set_false_path -from [get_clocks $::env(RING3_CLOCK_PORT)] -to [get_clocks $::env(WB_CLOCK_PORT)]
diff --git a/openlane/trng_wb_wrapper/config.tcl b/openlane/trng_wb_wrapper/config.tcl
new file mode 100644
index 0000000..00cc361
--- /dev/null
+++ b/openlane/trng_wb_wrapper/config.tcl
@@ -0,0 +1,62 @@
+# User config
+set ::env(DESIGN_NAME) trng_wb_wrapper
+
+# Change if needed
+set ::env(VERILOG_FILES) "\
+ $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/trng/trng_wb_wrapper.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/trng/ringosc_macro.v \
+ $::env(DESIGN_DIR)/../../verilog/rtl/trng/ring_osc2x13.v"
+
+# Black-box verilog and views
+# set ::env(VERILOG_FILES_BLACKBOX) "\
+# $::env(DESIGN_DIR)/../../verilog/rtl/trng/ringosc_macro.v"
+
+# set ::env(EXTRA_LEFS) "\
+# $::env(DESIGN_DIR)/../../lef/ringosc_macro.lef"
+
+# set ::env(EXTRA_GDS_FILES) "\
+# $::env(DESIGN_DIR)/../../gds/ringosc_macro.gds"
+
+# Fill this
+set ::env(CLOCK_PERIOD) "25.0"
+set ::env(CLOCK_PORT) "wb_clk_i"
+
+set ::env(PDK) "sky130A"
+set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
+
+# set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+# if { [file exists $filename] == 1} {
+# source $filename
+# }
+
+# set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
+
+# Preserve manually instantiated stdcells.
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+# Disable optimizations and CTS to preserve our hand picked stdcells.
+set ::env(SYNTH_BUFFERING) 0
+set ::env(SYNTH_SIZING) 0
+set ::env(SYNTH_SHARE_RESOURCES) 0
+set ::env(CLOCK_TREE_SYNTH) 0
+set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
+set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
+
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 750 1000"
+
+set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_TARGET_DENSITY) 0.40
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
+set ::env(RT_MAX_LAYER) {met4}
+set ::env(DIODE_INSERTION_STRATEGY) 4
diff --git a/openlane/trng_wb_wrapper/pin_order.cfg b/openlane/trng_wb_wrapper/pin_order.cfg
new file mode 100644
index 0000000..e0572f1
--- /dev/null
+++ b/openlane/trng_wb_wrapper/pin_order.cfg
@@ -0,0 +1,11 @@
+#BUS_SORT
+
+#S
+*._i
+
+#N
+*._o
+
+#E
+
+#W
\ No newline at end of file
diff --git a/verilog/dv/wb_trng/Makefile b/verilog/dv/wb_trng/Makefile
new file mode 100644
index 0000000..0121c39
--- /dev/null
+++ b/verilog/dv/wb_trng/Makefile
@@ -0,0 +1,31 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+
+PWDD := $(shell pwd)
+BLOCKS := $(shell basename $(PWDD))
+
+# ---- Include Partitioned Makefiles ----
+
+CONFIG = caravel_user_project
+
+
+include $(MCW_ROOT)/verilog/dv/make/env.makefile
+include $(MCW_ROOT)/verilog/dv/make/var.makefile
+include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
+include $(MCW_ROOT)/verilog/dv/make/sim.makefile
+
diff --git a/verilog/dv/wb_trng/wb_trng.c b/verilog/dv/wb_trng/wb_trng.c
new file mode 100644
index 0000000..94e64a0
--- /dev/null
+++ b/verilog/dv/wb_trng/wb_trng.c
@@ -0,0 +1,95 @@
+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This include is relative to $CARAVEL_PATH (see Makefile)
+#include <defs.h>
+#include <stub.c>
+
+// User Project Slaves (0x3000_0000)
+#define trng_offset (*(volatile uint32_t*)0x30002000)
+
+/*
+ Wishbone Test:
+ - Configures MPRJ lower 8-IO pins as outputs
+ - Checks counter value through the wishbone port
+*/
+
+void main()
+{
+ int trng_buffer = 0;
+
+ /*
+ IO Control Registers
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
+ Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
+
+
+ Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
+ | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
+ | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
+ */
+
+ /* Set up the housekeeping SPI to be connected internally so */
+ /* that external pin changes don't affect it. */
+ reg_spi_enable = 1;
+ reg_wb_enable = 1;
+ // reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
+ // connect to housekeeping SPI
+
+ // Connect the housekeeping SPI to the SPI master
+ // so that the CSB line is not left floating. This allows
+ // all of the GPIO pins to be used for user functions.
+
+ reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
+ reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ /* Apply configuration */
+ reg_mprj_xfer = 1;
+ while (reg_mprj_xfer == 1);
+
+ reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
+
+ // Flag start of the test
+ reg_mprj_datal = 0xAB600000;
+
+ // change trim
+ trng_offset = 0x00000037;
+ *((&trng_offset)+1) = 0x00000001;
+
+ // read buffer
+ trng_buffer = trng_offset;
+
+ // Flag finish of the test
+ reg_mprj_datal = 0xAB610000;
+}
\ No newline at end of file
diff --git a/verilog/dv/wb_trng/wb_trng_tb.v b/verilog/dv/wb_trng/wb_trng_tb.v
new file mode 100644
index 0000000..eb580b0
--- /dev/null
+++ b/verilog/dv/wb_trng/wb_trng_tb.v
@@ -0,0 +1,147 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+module wb_trng_tb;
+ reg clock;
+ reg RSTB;
+ reg CSB;
+ reg power1, power2;
+ reg power3, power4;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+ wire [15:0] checkbits;
+ wire [7:0] result;
+
+ assign checkbits = mprj_io[31:16];
+
+ assign mprj_io[3] = 1'b1;
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #10.0 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("wb_trng.vcd");
+ $dumpvars(0, wb_trng_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (50) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ `ifdef GL
+ $display ("Monitor: Timeout, Test Mega-Project WB Port (GL) Failed");
+ `else
+ $display ("Monitor: Timeout, Test Mega-Project WB Port (RTL) Failed");
+ `endif
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ wait(checkbits == 16'hAB60);
+ $display("Monitor: MPRJ-Logic WB Started");
+ wait(checkbits == 16'hAB61);
+ `ifdef GL
+ $display("Monitor: Mega-Project WB (GL) Passed");
+ `else
+ $display("Monitor: Mega-Project WB (RTL) Passed");
+ `endif
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ CSB <= 1'b1; // Force CSB high
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ #100000;
+ CSB = 1'b0; // CSB can be released
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+
+ wire VDD3V3 = power1;
+ wire VDD1V8 = power2;
+ wire USER_VDD3V3 = power3;
+ wire USER_VDD1V8 = power4;
+ wire VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vddio_2 (VDD3V3),
+ .vssio (VSS),
+ .vssio_2 (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda1_2 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa1_2 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("wb_trng.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+endmodule
+`default_nettype wire
\ No newline at end of file
diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project
index e2dafde..d0827e5 100644
--- a/verilog/includes/includes.rtl.caravel_user_project
+++ b/verilog/includes/includes.rtl.caravel_user_project
@@ -15,3 +15,5 @@
-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/skidbuffer.v
-v $(USER_PROJECT_VERILOG)/rtl/wbuart32/wbuart.v
-v $(USER_PROJECT_VERILOG)/rtl/sram/sky130_sram_1kbyte_1rw1r_32x256_8.v
+-v $(USER_PROJECT_VERILOG)/rtl/trng/ringosc_macro.v
+-v $(USER_PROJECT_VERILOG)/rtl/trng/trng_wb_wrapper.v
diff --git a/verilog/rtl/trng/ring_osc2x13.v b/verilog/rtl/trng/ring_osc2x13.v
new file mode 100644
index 0000000..da85b09
--- /dev/null
+++ b/verilog/rtl/trng/ring_osc2x13.v
@@ -0,0 +1,246 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+// Tunable ring oscillator---synthesizable (physical) version.
+//
+// NOTE: This netlist cannot be simulated correctly due to lack
+// of accurate timing in the digital cell verilog models.
+
+module delay_stage(in, trim, out);
+ input in;
+ input [1:0] trim;
+ output out;
+
+ wire d0, d1, d2, ts;
+
+ sky130_fd_sc_hd__clkbuf_2 delaybuf0 (
+ .A(in),
+ .X(ts)
+ );
+
+ sky130_fd_sc_hd__clkbuf_1 delaybuf1 (
+ .A(ts),
+ .X(d0)
+ );
+
+ sky130_fd_sc_hd__einvp_2 delayen1 (
+ .A(d0),
+ .TE(trim[1]),
+ .Z(d1)
+ );
+
+ sky130_fd_sc_hd__einvn_4 delayenb1 (
+ .A(ts),
+ .TE_B(trim[1]),
+ .Z(d1)
+ );
+
+ sky130_fd_sc_hd__clkinv_1 delayint0 (
+ .A(d1),
+ .Y(d2)
+ );
+
+ sky130_fd_sc_hd__einvp_2 delayen0 (
+ .A(d2),
+ .TE(trim[0]),
+ .Z(out)
+ );
+
+ sky130_fd_sc_hd__einvn_8 delayenb0 (
+ .A(ts),
+ .TE_B(trim[0]),
+ .Z(out)
+ );
+
+endmodule
+
+module start_stage(in, trim, reset, out);
+ input in;
+ input [1:0] trim;
+ input reset;
+ output out;
+
+ wire d0, d1, d2, ctrl0, one;
+
+ sky130_fd_sc_hd__clkbuf_1 delaybuf0 (
+ .A(in),
+ .X(d0)
+ );
+
+ sky130_fd_sc_hd__einvp_2 delayen1 (
+ .A(d0),
+ .TE(trim[1]),
+ .Z(d1)
+ );
+
+ sky130_fd_sc_hd__einvn_4 delayenb1 (
+ .A(in),
+ .TE_B(trim[1]),
+ .Z(d1)
+ );
+
+ sky130_fd_sc_hd__clkinv_1 delayint0 (
+ .A(d1),
+ .Y(d2)
+ );
+
+ sky130_fd_sc_hd__einvp_2 delayen0 (
+ .A(d2),
+ .TE(trim[0]),
+ .Z(out)
+ );
+
+ sky130_fd_sc_hd__einvn_8 delayenb0 (
+ .A(in),
+ .TE_B(ctrl0),
+ .Z(out)
+ );
+
+ sky130_fd_sc_hd__einvp_1 reseten0 (
+ .A(one),
+ .TE(reset),
+ .Z(out)
+ );
+
+ sky130_fd_sc_hd__or2_2 ctrlen0 (
+ .A(reset),
+ .B(trim[0]),
+ .X(ctrl0)
+ );
+
+ sky130_fd_sc_hd__conb_1 const1 (
+ .HI(one),
+ .LO()
+ );
+
+endmodule
+
+// Ring oscillator with 13 stages, each with two trim bits delay
+// (see above). Trim is not binary: For trim[1:0], lower bit
+// trim[0] is primary trim and must be applied first; upper
+// bit trim[1] is secondary trim and should only be applied
+// after the primary trim is applied, or it has no effect.
+//
+// Total effective number of inverter stages in this oscillator
+// ranges from 13 at trim 0 to 65 at trim 24. The intention is
+// to cover a range greater than 2x so that the midrange can be
+// reached over all PVT conditions.
+//
+// Frequency of this ring oscillator under SPICE simulations at
+// nominal PVT is maximum 214 MHz (trim 0), minimum 90 MHz (trim 24).
+
+module ring_osc2x13(reset, trim, clockp);
+ input reset;
+ input [25:0] trim;
+ output[1:0] clockp;
+
+`ifdef FUNCTIONAL // i.e., behavioral model below
+
+ reg [1:0] clockp;
+ reg hiclock;
+ integer i;
+ real delay;
+ wire [5:0] bcount;
+
+ assign bcount = trim[0] + trim[1] + trim[2]
+ + trim[3] + trim[4] + trim[5] + trim[6] + trim[7]
+ + trim[8] + trim[9] + trim[10] + trim[11] + trim[12]
+ + trim[13] + trim[14] + trim[15] + trim[16] + trim[17]
+ + trim[18] + trim[19] + trim[20] + trim[21] + trim[22]
+ + trim[23] + trim[24] + trim[25];
+
+ initial begin
+ hiclock <= 1'b0;
+ delay = 3.0;
+ end
+
+ // Fastest operation is 214 MHz = 4.67ns
+ // Delay per trim is 0.02385
+ // Run "hiclock" at 2x this rate, then use positive and negative
+ // edges to derive the 0 and 90 degree phase clocks.
+ always #delay begin
+ hiclock <= (hiclock === 1'b0);
+ end
+
+ always @(trim) begin
+ // Implement trim as a variable delay, one delay per trim bit
+ delay = 1.168 + 0.012 * $itor(bcount);
+ end
+
+ always @(posedge hiclock or posedge reset) begin
+ if (reset == 1'b1) begin
+ clockp[0] <= 1'b0;
+ end else begin
+ clockp[0] <= (clockp[0] === 1'b0);
+ end
+ end
+
+ always @(negedge hiclock or posedge reset) begin
+ if (reset == 1'b1) begin
+ clockp[1] <= 1'b0;
+ end else begin
+ clockp[1] <= (clockp[1] === 1'b0);
+ end
+ end
+
+`else // gate level netlist below
+
+ wire [1:0] clockp;
+ wire [12:0] d;
+ wire [1:0] c;
+
+ // Main oscillator loop stages
+ genvar i;
+ generate
+ for (i = 0; i < 12; i = i + 1) begin : dstage
+ delay_stage id (
+ .in(d[i]),
+ .trim({trim[i+13], trim[i]}),
+ .out(d[i+1])
+ );
+ end
+ endgenerate
+
+ // Reset/startup stage
+ start_stage iss (
+ .in(d[12]),
+ .trim({trim[25], trim[12]}),
+ .reset(reset),
+ .out(d[0])
+ );
+
+ // Buffered outputs a 0 and 90 degrees phase (approximately)
+ sky130_fd_sc_hd__clkinv_2 ibufp00 (
+ .A(d[0]),
+ .Y(c[0])
+ );
+ sky130_fd_sc_hd__clkinv_8 ibufp01 (
+ .A(c[0]),
+ .Y(clockp[0])
+ );
+ sky130_fd_sc_hd__clkinv_2 ibufp10 (
+ .A(d[6]),
+ .Y(c[1])
+ );
+ sky130_fd_sc_hd__clkinv_8 ibufp11 (
+ .A(c[1]),
+ .Y(clockp[1])
+ );
+
+`endif
+
+endmodule
+`default_nettype wire
diff --git a/verilog/rtl/trng/ringosc_macro.v b/verilog/rtl/trng/ringosc_macro.v
new file mode 100644
index 0000000..ddb235f
--- /dev/null
+++ b/verilog/rtl/trng/ringosc_macro.v
@@ -0,0 +1,64 @@
+// SPDX-FileCopyrightText: 2021 Harrison Pham
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+module ringosc_macro #(
+ parameter TRIM_BITS = 26
+) (
+`ifdef USE_POWER_PINS
+ inout vccd1,
+ inout vssd1,
+`endif
+ input rst_i,
+ input [TRIM_BITS-1:0] trim_fast,
+ input [TRIM_BITS-1:0] trim_slow,
+ output trng_o
+);
+
+wire [2:0] clockp, clockn;
+wire [2:0] temp;
+wire [2:0] entropy_next;
+reg [2:0] entropy_reg;
+wire trng_o;
+
+genvar i;
+generate
+ for (i = 0; i < 3; i = i + 1) begin : rings
+ ring_osc2x13 trng_ring_fast (
+ .reset(rst_i),
+ .trim(trim_fast),
+ .clockp({temp[i],entropy_next[i]})
+ );
+
+ ring_osc2x13 trng_ring_slow (
+ .reset(rst_i),
+ .trim(trim_slow),
+ .clockp({clockn[i],clockp[i]})
+ );
+
+ always @(posedge clockp[i])
+ begin
+ if (rst_i == 1'b1) begin
+ entropy_reg[i] <= 1'b0;
+ end
+ else begin
+ entropy_reg[i] <= entropy_next[i];
+ end
+ end
+ end
+endgenerate
+
+assign trng_o = entropy_reg[0] ^ entropy_reg[1] ^ entropy_reg[2];
+
+endmodule
diff --git a/verilog/rtl/trng/trng_wb_wrapper.v b/verilog/rtl/trng/trng_wb_wrapper.v
new file mode 100644
index 0000000..1650c39
--- /dev/null
+++ b/verilog/rtl/trng/trng_wb_wrapper.v
@@ -0,0 +1,178 @@
+//-----------------------------------------------------------------------------
+// @file trng_wb_wrapper.vhd
+//
+// @brief This block is a wishbone wrapper for TRNG macro
+//
+// @details This wrapper gets signal from master if it is selected
+// and convey to the TRNG module and vice versa.
+//
+// @author Sukru Uzun <sukru.uzun@procenne.com>
+// @date 19.03.2022
+//
+// @todo TRNG buffer size can be changed.
+// @warning Wrapper should not convey data unless buffer is full.
+//
+// @project https://github.com/Procenne-Digital-Design/secure-memory.git
+//
+// @revision :
+// 0.1 - 19 March 2022, Sukru Uzun
+// initial version
+//-----------------------------------------------------------------------------
+
+module trng_wb_wrapper #(
+ parameter BUFFER_SIZE = 32
+ ) (
+ `ifdef USE_POWER_PINS
+ input wire vccd1,
+ input wire vssd1,
+ `endif
+ input wire rst_i,
+ // Wishbone Interface
+ input wire wb_clk_i,
+ input wire wb_cyc_i,
+ input wire wb_stb_i,
+ input wire [8:0] wb_adr_i,
+ input wire wb_we_i,
+ input wire [31:0] wb_dat_i,
+ // input wire [3:0] wb_sel_i,
+ output wire [31:0] wb_dat_o,
+ output reg wb_ack_o,
+ output reg trng_valid_o,
+ output reg [BUFFER_SIZE-1:0] trng_buffer_o
+);
+
+wire read_trng;
+wire trim_select;
+wire trim_write_en;
+reg [25:0] trim_fast, trim_slow;
+reg [5:0] trng_counter;
+wire trng_o;
+
+// Wishbone to TRNG signalization and vice versa.
+assign read_trng = (wb_stb_i == 1'b1 && wb_we_i == 1'b0 && wb_cyc_i == 1'b1) ? 1'b1 : 1'b0;
+assign wb_dat_o = (trng_valid_o == 1'b1 && read_trng == 1'b1) ? trng_buffer : 'h0;
+
+ringosc_macro #(.TRIM_BITS(26))
+ringosc_macro_dut (
+`ifdef USE_POWER_PINS
+ .vccd1 (vccd1),
+ .vssd1 (vssd1),
+`endif
+ .rst_i (rst_i),
+ .trim_fast (trim_fast),
+ .trim_slow (trim_slow),
+ .trng_o (trng_o)
+);
+
+assign trim_select = wb_dat_i[5];
+assign trim_write_en = (wb_stb_i == 1'b1 && wb_we_i == 1'b1 && wb_cyc_i == 1'b1) ? 1'b1 : 1'b0;
+
+always @(posedge wb_clk_i)
+begin
+ if (rst_i == 1'b1) begin
+ trim_slow <= 26'b11111111111111111111111111;
+ trim_fast <= 26'b00000000000000000000000000;
+ end
+ else begin
+ if (trim_write_en) begin
+ if(trim_select)
+ case(wb_dat_i[4:0])
+ 5'b00000: trim_fast = 26'b00000000000000000000000000;
+ 5'b00001: trim_fast = 26'b00000000000000000000000001;
+ 5'b00010: trim_fast = 26'b00000000000000000000000011;
+ 5'b00011: trim_fast = 26'b00000000000000000000000111;
+ 5'b00100: trim_fast = 26'b00000000000000000000001111;
+ 5'b00101: trim_fast = 26'b00000000000000000000011111;
+ 5'b00110: trim_fast = 26'b00000000000000000000111111;
+ 5'b00111: trim_fast = 26'b00000000000000000001111111;
+ 5'b01000: trim_fast = 26'b00000000000000000011111111;
+ 5'b01001: trim_fast = 26'b00000000000000000111111111;
+ 5'b01010: trim_fast = 26'b00000000000000001111111111;
+ 5'b01011: trim_fast = 26'b00000000000000011111111111;
+ 5'b01100: trim_fast = 26'b00000000000000111111111111;
+ 5'b01101: trim_fast = 26'b00000000000001111111111111;
+ 5'b01110: trim_fast = 26'b00000000000011111111111111;
+ 5'b01111: trim_fast = 26'b00000000000111111111111111;
+ 5'b10000: trim_fast = 26'b00000000001111111111111111;
+ 5'b10001: trim_fast = 26'b00000000011111111111111111;
+ 5'b10010: trim_fast = 26'b00000000111111111111111111;
+ 5'b10011: trim_fast = 26'b00000001111111111111111111;
+ 5'b10100: trim_fast = 26'b00000011111111111111111111;
+ 5'b10101: trim_fast = 26'b00000111111111111111111111;
+ 5'b10110: trim_fast = 26'b00001111111111111111111111;
+ 5'b10111: trim_fast = 26'b00011111111111111111111111;
+ 5'b11000: trim_fast = 26'b00111111111111111111111111;
+ 5'b11001: trim_fast = 26'b01111111111111111111111111;
+ 5'b11010: trim_fast = 26'b11111111111111111111111111;
+ default: trim_fast = 26'b11111111111111111111111111;
+ endcase
+ else begin
+ case(wb_adr_i[4:0])
+ 5'b00000: trim_slow = 26'b00000000000000000000000000;
+ 5'b00001: trim_slow = 26'b00000000000000000000000001;
+ 5'b00010: trim_slow = 26'b00000000000000000000000011;
+ 5'b00011: trim_slow = 26'b00000000000000000000000111;
+ 5'b00100: trim_slow = 26'b00000000000000000000001111;
+ 5'b00101: trim_slow = 26'b00000000000000000000011111;
+ 5'b00110: trim_slow = 26'b00000000000000000000111111;
+ 5'b00111: trim_slow = 26'b00000000000000000001111111;
+ 5'b01000: trim_slow = 26'b00000000000000000011111111;
+ 5'b01001: trim_slow = 26'b00000000000000000111111111;
+ 5'b01010: trim_slow = 26'b00000000000000001111111111;
+ 5'b01011: trim_slow = 26'b00000000000000011111111111;
+ 5'b01100: trim_slow = 26'b00000000000000111111111111;
+ 5'b01101: trim_slow = 26'b00000000000001111111111111;
+ 5'b01110: trim_slow = 26'b00000000000011111111111111;
+ 5'b01111: trim_slow = 26'b00000000000111111111111111;
+ 5'b10000: trim_slow = 26'b00000000001111111111111111;
+ 5'b10001: trim_slow = 26'b00000000011111111111111111;
+ 5'b10010: trim_slow = 26'b00000000111111111111111111;
+ 5'b10011: trim_slow = 26'b00000001111111111111111111;
+ 5'b10100: trim_slow = 26'b00000011111111111111111111;
+ 5'b10101: trim_slow = 26'b00000111111111111111111111;
+ 5'b10110: trim_slow = 26'b00001111111111111111111111;
+ 5'b10111: trim_slow = 26'b00011111111111111111111111;
+ 5'b11000: trim_slow = 26'b00111111111111111111111111;
+ 5'b11001: trim_slow = 26'b01111111111111111111111111;
+ 5'b11010: trim_slow = 26'b11111111111111111111111111;
+ default: trim_slow = 26'b00000000000000000000000000;
+ endcase
+ end
+ end
+ end
+end
+
+always @(posedge wb_clk_i)
+begin
+ if (rst_i == 1'b1) begin
+ wb_ack_o <= 1'b0;
+ trng_valid_o <= 1'b0;
+ trng_counter <= 'h0;
+ trng_buffer <= 'h0;
+ end
+ else begin
+ // TRNG signalization
+ wb_ack_o <= 1'b0;
+ trng_counter <= trng_counter + 1;
+ trng_valid_o <= trng_valid_o;
+
+ if(trim_write_en == 1'b1 && wb_ack_o == 1'b0) begin
+ wb_ack_o <= 1'b1;
+ end
+
+ if(trng_counter == 6'b100000) begin
+ trng_counter <= 'h0;
+ trng_valid_o <= 1'b1;
+ end
+
+ if(read_trng == 1'b1 && trng_valid_o == 1'b1) begin
+ wb_ack_o <= 1'b1;
+ trng_counter <= 'h0;
+ trng_valid_o <= 1'b0;
+ end
+
+ trng_buffer <= {trng_buffer[30:0],trng_o};
+ end
+end
+
+endmodule
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 9a427be..3942d06 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -70,7 +70,17 @@
output sram_web_b ,
output [ 3:0] sram_mask_b,
output [ 8:0] sram_addr_b,
- output [ 31:0] sram_din_b
+ output [ 31:0] sram_din_b,
+ //TRNG
+ output trng_wb_cyc_o,
+ output trng_wb_stb_o,
+ output [8:0] trng_wb_adr_o,
+ output trng_wb_we_o ,
+ input [31:0] trng_wb_dat_i,
+ output [31:0] trng_wb_dat_o,
+ input trng_wb_ack_i,
+ input [31:0] trng_buffer_i
+
);
/*--------------------------------------*/
/* User project is instantiated here */
@@ -175,14 +185,14 @@
.s1_wb_stb_o(s1_wb_stb_i),
// Slave 2 Interface
- // .s2_wb_dat_i(),
- // .s2_wb_ack_i(),
- // .s2_wb_dat_o(),
- // .s2_wb_adr_o(),
- // .s2_wb_sel_o(),
- // .s2_wb_we_o (),
- // .s2_wb_cyc_o(),
- // .s2_wb_stb_o(),
+ .s2_wb_dat_i(trng_wb_dat_i),
+ .s2_wb_ack_i(trng_wb_ack_i),
+ .s2_wb_dat_o(trng_wb_dat_o),
+ .s2_wb_adr_o(trng_wb_adr_o),
+ .s2_wb_sel_o(),
+ .s2_wb_we_o (trng_wb_we_o),
+ .s2_wb_cyc_o(trng_wb_cyc_o),
+ .s2_wb_stb_o(trng_wb_cyc_o),
// Slave 3 Interface
.s3_wb_dat_i(s3_wb_dat_o),
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index aa0deb5..f61c19e 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -85,6 +85,21 @@
+
+
+ wire wb_clk_i;
+ wire wb_cyc_i;
+ wire wb_stb_i;
+ wire [8:0] wb_adr_i;
+ wire wb_we_i ;
+ wire [31:0] wb_dat_i;
+ wire [31:0] wb_dat_o;
+ wire wb_ack_o;
+ wire [31:0] trng_buffer_o;
+
+
+
+
user_proj_example mprj (
`ifdef USE_POWER_PINS
.vccd1 (vccd1 ), // User area 1 1.8V power
@@ -114,10 +129,40 @@
.sram_web_b (sram_web_b ),
.sram_mask_b(sram_mask_b),
.sram_addr_b(sram_addr_b),
- .sram_din_b (sram_din_b )
+ .sram_din_b (sram_din_b ),
+ .trng_wb_cyc_o(wb_cyc_i),
+ .trng_wb_stb_o(wb_stb_i),
+ .trng_wb_adr_o(wb_adr_i),
+ .trng_wb_we_o (wb_we_i ),
+ .trng_wb_dat_i(wb_dat_o),
+ .trng_wb_dat_o(wb_dat_i),
+ .trng_wb_ack_i(wb_ack_o),
+ .trng_buffer_i (trng_buffer_o)
);
+ trng_wb_wrapper
+ #(
+ .BUFFER_SIZE (BITS )
+ )
+ trng_wb_wrapper_dut (
+ .vccd1 (vccd1 ),
+ .vssd1 (vssd1 ),
+ .rst_i (rst_i ),
+ .wb_clk_i (wb_clk_i ),
+ .wb_cyc_i (wb_cyc_i ),
+ .wb_stb_i (wb_stb_i ),
+ .wb_adr_i (wb_adr_i ),
+ .wb_we_i (wb_we_i ),
+ .wb_dat_i (wb_dat_i ),
+ .wb_dat_o (wb_dat_o ),
+ .wb_ack_o (wb_ack_o ),
+ .trng_valid_o (trng_valid_o ),
+ .trng_buffer_o ( trng_buffer_o)
+ );
+
+
+
sky130_sram_2kbyte_1rw1r_32x512_8 u_sram1_2kb (
`ifdef USE_POWER_PINS
diff --git a/verilog/rtl/wb_interconnect/wb_interconnect.sv b/verilog/rtl/wb_interconnect/wb_interconnect.sv
index ad0ab15..204375b 100644
--- a/verilog/rtl/wb_interconnect/wb_interconnect.sv
+++ b/verilog/rtl/wb_interconnect/wb_interconnect.sv
@@ -58,14 +58,14 @@
output wire s1_wb_cyc_o,
output wire s1_wb_stb_o,
// Slave 2 Interface
- // input logic [31:0] s2_wb_dat_i,
- // input logic s2_wb_ack_i,
- // output wire [31:0] s2_wb_dat_o,
- // output wire [8:0] s2_wb_adr_o,
- // output wire [3:0] s2_wb_sel_o,
- // output wire s2_wb_we_o,
- // output wire s2_wb_cyc_o,
- // output wire s2_wb_stb_o,
+ input logic [31:0] s2_wb_dat_i,
+ input logic s2_wb_ack_i,
+ output wire [31:0] s2_wb_dat_o,
+ output wire [8:0] s2_wb_adr_o,
+ output wire [3:0] s2_wb_sel_o,
+ output wire s2_wb_we_o,
+ output wire s2_wb_cyc_o,
+ output wire s2_wb_stb_o,
// Slave 3 Interface
input logic [31:0] s3_wb_dat_i,
input logic s3_wb_ack_i,
@@ -93,12 +93,12 @@
wire [31:0] s_bus_rd_wb_dat = (m0_wb_adr_i[13:12] == 2'b00) ? s0_wb_dat_i :
(m0_wb_adr_i[13:12] == 2'b01) ? s1_wb_dat_i :
+ (m0_wb_adr_i[13:12] == 2'b10) ? s2_wb_dat_i :
(m0_wb_adr_i[13:12] == 2'b11) ? s3_wb_dat_i : 32'd0;
- //s3_wb_dat_i;
wire s_bus_rd_wb_ack = (m0_wb_adr_i[13:12] == 2'b00) ? s0_wb_ack_i :
(m0_wb_adr_i[13:12] == 2'b01) ? s1_wb_ack_i :
+ (m0_wb_adr_i[13:12] == 2'b10) ? s2_wb_ack_i :
(m0_wb_adr_i[13:12] == 2'b11) ? s3_wb_ack_i : 1'b0 ; // :
- //s3_wb_ack_i;
//wire [31:0] s_bus_rd_wb_dat = s0_wb_dat_i;
//wire s_bus_rd_wb_ack = s0_wb_ack_i;
@@ -136,12 +136,12 @@
assign s1_wb_cyc_o = (m0_wb_tid_reg == 2'b01) ? m0_wb_cyc_reg : 1'b0;
assign s1_wb_stb_o = (m0_wb_tid_reg == 2'b01) ? m0_wb_stb_reg : 1'b0;
- // assign s2_wb_dat_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_dat_i_reg : 2'b00;
- // assign s2_wb_adr_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_adr_reg : 2'b00;
- // assign s2_wb_sel_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_sel_reg : 2'b00;
- // assign s2_wb_we_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_we_reg : 2'b00;
- // assign s2_wb_cyc_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_cyc_reg : 2'b00;
- // assign s2_wb_stb_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_stb_reg : 2'b00;
+ assign s2_wb_dat_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_dat_i_reg : 'h0;
+ assign s2_wb_adr_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_adr_reg : 'h0;
+ assign s2_wb_sel_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_sel_reg : 'h0;
+ assign s2_wb_we_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_we_reg : 'h0;
+ assign s2_wb_cyc_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_cyc_reg : 'h0;
+ assign s2_wb_stb_o = (m0_wb_tid_reg == 2'b10) ? m0_wb_stb_reg : 'h0;
assign s3_wb_dat_o = (m0_wb_tid_reg == 2'b11) ? m0_wb_dat_i_reg : 32'd0;
assign s3_wb_adr_o = (m0_wb_tid_reg == 2'b11) ? m0_wb_adr_reg : 9'd0;
