submodule configs

openlane/sram_wb_wrapper/config.tcl

diff --git a/openlane/sram_wb_wrapper/config.tcl b/openlane/sram_wb_wrapper/config.tcl
new file mode 100644
index 0000000..302c217
--- /dev/null
+++ b/openlane/sram_wb_wrapper/config.tcl
@@ -0,0 +1,38 @@
+# User config
+set ::env(DESIGN_NAME) sram_wb_wrapper
+
+# Change if needed
+set ::env(VERILOG_FILES) "\
+	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/sram/sram_wb_wrapper.sv"
+
+# Fill this
+set ::env(CLOCK_PERIOD) "10.0"
+set ::env(CLOCK_PORT) "wb_clk_i"
+
+set filename $::env(DESIGN_DIR)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
+if { [file exists $filename] == 1} {
+	source $filename
+}
+
+# Black-box verilog and views
+# set ::env(VERILOG_FILES_BLACKBOX) "\
+# 	$::env(DESIGN_DIR)/../../verilog/rtl/sram/sky130_sram_1kbyte_1rw1r_32x256_8.v"
+
+# set ::env(EXTRA_LEFS) "\
+# 	$::env(DESIGN_DIR)/../../lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef"
+
+# set ::env(EXTRA_GDS_FILES) "\
+# 	$::env(DESIGN_DIR)/../../gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds"
+
+# Preserve gate instances in the rtl of the design.
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 400 600"
+
+set ::env(PL_BASIC_PLACEMENT) 1
+set ::env(PL_TARGET_DENSITY) 0.50
+
+set ::env(VDD_PIN) [list {vccd1}]
+set ::env(GND_PIN) [list {vssd1}]
\ No newline at end of file

openlane/user_project_wrapper/config.tcl

diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl
index f720e39..256cddd 100755
--- a/openlane/user_project_wrapper/config.tcl
+++ b/openlane/user_project_wrapper/config.tcl
@@ -31,36 +31,46 @@
 #section end
 
 # User Configurations
+set ::env(DESIGN_IS_CORE) 1
+set ::env(FP_PDN_CORE_RING) 1
 
 ## Source Verilog Files
 set ::env(VERILOG_FILES) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_project_wrapper.v"
+	$::env(DESIGN_DIR)/../../verilog/rtl/user_project_wrapper.v"
 
 ## Clock configurations
-set ::env(CLOCK_PORT) "user_clock2"
-set ::env(CLOCK_NET) "mprj.clk"
+set ::env(CLOCK_PORT) "wb_clk_i"
+set ::env(CLOCK_NET) "wb_clk_i"
 
-set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PERIOD) "20"
 
 ## Internal Macros
 ### Macro PDN Connections
 set ::env(FP_PDN_MACRO_HOOKS) "\
-	mprj vccd1 vssd1"
+	interconnect vccd1 vssd1 \
+	wb_wrapper0  vccd1 vssd1 \
+	u_sram1_1kb  vccd1 vssd1"
 
 ### Macro Placement
-set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg
+set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro.cfg
 
 ### Black-box verilog and views
 set ::env(VERILOG_FILES_BLACKBOX) "\
 	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
-	$script_dir/../../verilog/rtl/user_proj_example.v"
+	$::env(DESIGN_DIR)/../../verilog/rtl/sram/sky130_sram_1kbyte_1rw1r_32x256_8.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/sram/sram_wb_wrapper.sv \
+	$::env(DESIGN_DIR)/../../verilog/rtl/wb_interconnect/wb_interconnect.sv"
 
 set ::env(EXTRA_LEFS) "\
-	$script_dir/../../lef/user_proj_example.lef"
+	$::env(DESIGN_DIR)/../../lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef \
+	$::env(DESIGN_DIR)/../../lef/sram_wb_wrapper.lef \
+	$::env(DESIGN_DIR)/../../lef/wb_interconnect.lef"
 
 set ::env(EXTRA_GDS_FILES) "\
-	$script_dir/../../gds/user_proj_example.gds"
+	$::env(DESIGN_DIR)/../../gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds \
+	$::env(DESIGN_DIR)/../../gds/sram_wb_wrapper.gds \
+	$::env(DESIGN_DIR)/../../gds/wb_interconnect.gds"
 
 # set ::env(GLB_RT_MAXLAYER) 5
 set ::env(RT_MAX_LAYER) {met4}