remove example proj
diff --git a/verilog/rtl/uprj_netlists.v b/verilog/rtl/uprj_netlists.v
index 4a1dec9..bfbc580 100644
--- a/verilog/rtl/uprj_netlists.v
+++ b/verilog/rtl/uprj_netlists.v
@@ -21,10 +21,8 @@
// Assume default net type to be wire because GL netlists don't have the wire definitions
`default_nettype wire
`include "gl/user_project_wrapper.v"
- `include "gl/user_proj_example.v"
`else
`include "user_project_wrapper.v"
- `include "user_proj_example.v"
`include "wb_interconnect/wb_interconnect.sv"
`include "wb_interconnect/wb_signal_reg.sv"
`include "sram/sram_wb_wrapper.sv"
