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foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-036 / f7ea7f35268b4e5895263b26ccb867b21bac9d88 / . / Intermediate / Motor_Top / runs / Motor_Top / logs / routing / 21-detailed.log
blob: 06bc62924bed19e5ac10716f86a27e6361986252 [file] [log] [blame]
OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/ali11-2000/FYP/mpw/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/merged_unpadded.lef
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/ali11-2000/FYP/mpw/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/merged_unpadded.lef
[INFO ODB-0127] Reading DEF file: /home/ali11-2000/FYP/mpw/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/routing/19-global.def
[INFO ODB-0128] Design: Motor_Top
[INFO ODB-0130] Created 97 pins.
[INFO ODB-0131] Created 32552 components and 145377 component-terminals.
[INFO ODB-0132] Created 2 special nets and 123660 connections.
[INFO ODB-0133] Created 5997 nets and 21717 connections.
[INFO ODB-0134] Finished DEF file: /home/ali11-2000/FYP/mpw/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/routing/19-global.def
[INFO ORD-0030] Using 2 thread(s).
[INFO DRT-0149] Reading tech and libs.
Units: 1000
Number of layers: 13
Number of macros: 441
Number of vias: 25
Number of viarulegen: 25
[INFO DRT-0150] Reading design.
Design: Motor_Top
Die area: ( 0 0 ) ( 500000 500000 )
Number of track patterns: 12
Number of DEF vias: 3
Number of components: 32552
Number of terminals: 97
Number of snets: 2
Number of nets: 5997
[INFO DRT-0167] List of default vias:
Layer mcon
default via: L1M1_PR
Layer via
default via: M1M2_PR
Layer via2
default via: M2M3_PR
Layer via3
default via: M3M4_PR
Layer via4
default via: M4M5_PR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
Complete 10000 instances.
Complete 20000 instances.
Complete 30000 instances.
[INFO DRT-0164] Number of unique instances = 427.
[INFO DRT-0168] Init region query.
[INFO DRT-0018] Complete 10000 insts.
[INFO DRT-0018] Complete 20000 insts.
[INFO DRT-0018] Complete 30000 insts.
[INFO DRT-0024] Complete FR_MASTERSLICE.
[INFO DRT-0024] Complete FR_VIA.
[INFO DRT-0024] Complete li1.
[INFO DRT-0024] Complete mcon.
[INFO DRT-0024] Complete met1.
[INFO DRT-0024] Complete via.
[INFO DRT-0024] Complete met2.
[INFO DRT-0024] Complete via2.
[INFO DRT-0024] Complete met3.
[INFO DRT-0024] Complete via3.
[INFO DRT-0024] Complete met4.
[INFO DRT-0024] Complete via4.
[INFO DRT-0024] Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] FR_VIA shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 276585.
[INFO DRT-0033] mcon shape region query size = 374878.
[INFO DRT-0033] met1 shape region query size = 73583.
[INFO DRT-0033] via shape region query size = 3080.
[INFO DRT-0033] met2 shape region query size = 1285.
[INFO DRT-0033] via2 shape region query size = 2464.
[INFO DRT-0033] met3 shape region query size = 1274.
[INFO DRT-0033] via3 shape region query size = 2464.
[INFO DRT-0033] met4 shape region query size = 630.
[INFO DRT-0033] via4 shape region query size = 0.
[INFO DRT-0033] met5 shape region query size = 0.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076] Complete 100 pins.
[INFO DRT-0076] Complete 200 pins.
[INFO DRT-0076] Complete 300 pins.
[INFO DRT-0076] Complete 400 pins.
[INFO DRT-0076] Complete 500 pins.
[INFO DRT-0076] Complete 600 pins.
[INFO DRT-0076] Complete 700 pins.
[INFO DRT-0076] Complete 800 pins.
[INFO DRT-0076] Complete 900 pins.
[INFO DRT-0077] Complete 1000 pins.
[INFO DRT-0078] Complete 1615 pins.
[INFO DRT-0079] Complete 100 unique inst patterns.
[INFO DRT-0079] Complete 200 unique inst patterns.
[INFO DRT-0079] Complete 300 unique inst patterns.
[INFO DRT-0079] Complete 400 unique inst patterns.
[INFO DRT-0081] Complete 421 unique inst patterns.
[INFO DRT-0082] Complete 1000 groups.
[INFO DRT-0082] Complete 2000 groups.
[INFO DRT-0082] Complete 3000 groups.
[INFO DRT-0082] Complete 4000 groups.
[INFO DRT-0082] Complete 5000 groups.
[INFO DRT-0082] Complete 6000 groups.
[INFO DRT-0082] Complete 7000 groups.
[INFO DRT-0084] Complete 7891 groups.
#scanned instances = 32552
#unique instances = 427
#stdCellGenAp = 12282
#stdCellValidPlanarAp = 36
#stdCellValidViaAp = 9553
#stdCellPinNoAp = 0
#stdCellPinCnt = 21717
#instTermValidViaApCnt = 0
#macroGenAp = 0
#macroValidPlanarAp = 0
#macroValidViaAp = 0
#macroNoAp = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:17, elapsed time = 00:00:08, memory = 219.62 (MB), peak = 228.14 (MB)
[INFO DRT-0151] Reading guide.
Number of guides: 43913
[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 72 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 72 STEP 6900 ;
[INFO DRT-0026] Complete 10000 origin guides.
[INFO DRT-0026] Complete 20000 origin guides.
[INFO DRT-0026] Complete 30000 origin guides.
[INFO DRT-0026] Complete 40000 origin guides.
[INFO DRT-0028] Complete FR_MASTERSLICE.
[INFO DRT-0028] Complete FR_VIA.
[INFO DRT-0028] Complete li1.
[INFO DRT-0028] Complete mcon.
[INFO DRT-0028] Complete met1.
[INFO DRT-0028] Complete via.
[INFO DRT-0028] Complete met2.
[INFO DRT-0028] Complete via2.
[INFO DRT-0028] Complete met3.
[INFO DRT-0028] Complete via3.
[INFO DRT-0028] Complete met4.
[INFO DRT-0028] Complete via4.
[INFO DRT-0028] Complete met5.
[INFO DRT-0178] Init guide query.
[INFO DRT-0035] Complete FR_MASTERSLICE (guide).
[INFO DRT-0035] Complete FR_VIA (guide).
[INFO DRT-0035] Complete li1 (guide).
[INFO DRT-0035] Complete mcon (guide).
[INFO DRT-0035] Complete met1 (guide).
[INFO DRT-0035] Complete via (guide).
[INFO DRT-0035] Complete met2 (guide).
[INFO DRT-0035] Complete via2 (guide).
[INFO DRT-0035] Complete met3 (guide).
[INFO DRT-0035] Complete via3 (guide).
[INFO DRT-0035] Complete met4 (guide).
[INFO DRT-0035] Complete via4 (guide).
[INFO DRT-0035] Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] FR_VIA guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 16786.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 12987.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 6807.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 465.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 103.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 0.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 23696 vertical wires in 2 frboxes and 13452 horizontal wires in 2 frboxes.
[INFO DRT-0186] Done with 2709 vertical wires in 2 frboxes and 3827 horizontal wires in 2 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:00:03, elapsed time = 00:00:02, memory = 347.29 (MB), peak = 347.29 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 347.50 (MB), peak = 347.50 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:01, memory = 590.84 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:09, memory = 978.96 (MB).
Completing 30% with 407 violations.
elapsed time = 00:00:11, memory = 813.76 (MB).
Completing 40% with 407 violations.
elapsed time = 00:00:16, memory = 907.40 (MB).
Completing 50% with 407 violations.
elapsed time = 00:00:22, memory = 1122.83 (MB).
Completing 60% with 901 violations.
elapsed time = 00:00:24, memory = 997.32 (MB).
Completing 70% with 901 violations.
elapsed time = 00:00:33, memory = 1098.96 (MB).
Completing 80% with 1365 violations.
elapsed time = 00:00:37, memory = 1179.42 (MB).
Completing 90% with 1365 violations.
elapsed time = 00:00:49, memory = 1179.68 (MB).
Completing 100% with 2039 violations.
elapsed time = 00:00:54, memory = 1186.15 (MB).
[INFO DRT-0199] Number of violations = 3070.
[INFO DRT-0267] cpu time = 00:01:46, elapsed time = 00:00:54, memory = 1186.23 (MB), peak = 1186.23 (MB)
Total wire length = 224344 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 99508 um.
Total wire length on LAYER met2 = 97156 um.
Total wire length on LAYER met3 = 19852 um.
Total wire length on LAYER met4 = 7827 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44690.
Up-via summary (total 44690):.
------------------------
FR_MASTERSLICE 0
li1 21660
met1 22091
met2 746
met3 193
met4 0
------------------------
44690
[INFO DRT-0195] Start 1st optimization iteration.
Completing 10% with 3070 violations.
elapsed time = 00:00:01, memory = 1186.23 (MB).
Completing 20% with 3070 violations.
elapsed time = 00:00:09, memory = 1186.23 (MB).
Completing 30% with 2549 violations.
elapsed time = 00:00:11, memory = 1186.28 (MB).
Completing 40% with 2549 violations.
elapsed time = 00:00:15, memory = 1203.28 (MB).
Completing 50% with 2549 violations.
elapsed time = 00:00:24, memory = 1203.58 (MB).
Completing 60% with 1969 violations.
elapsed time = 00:00:25, memory = 1209.57 (MB).
Completing 70% with 1969 violations.
elapsed time = 00:00:34, memory = 1209.57 (MB).
Completing 80% with 1425 violations.
elapsed time = 00:00:37, memory = 1209.34 (MB).
Completing 90% with 1425 violations.
elapsed time = 00:00:44, memory = 1209.57 (MB).
Completing 100% with 990 violations.
elapsed time = 00:00:50, memory = 1209.55 (MB).
[INFO DRT-0199] Number of violations = 990.
[INFO DRT-0267] cpu time = 00:01:39, elapsed time = 00:00:51, memory = 1209.55 (MB), peak = 1254.95 (MB)
Total wire length = 223013 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 98887 um.
Total wire length on LAYER met2 = 96461 um.
Total wire length on LAYER met3 = 19819 um.
Total wire length on LAYER met4 = 7844 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44275.
Up-via summary (total 44275):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21685
met2 755
met3 195
met4 0
------------------------
44275
[INFO DRT-0195] Start 2nd optimization iteration.
Completing 10% with 990 violations.
elapsed time = 00:00:00, memory = 1209.55 (MB).
Completing 20% with 990 violations.
elapsed time = 00:00:10, memory = 1209.55 (MB).
Completing 30% with 979 violations.
elapsed time = 00:00:11, memory = 1209.57 (MB).
Completing 40% with 979 violations.
elapsed time = 00:00:14, memory = 1209.57 (MB).
Completing 50% with 979 violations.
elapsed time = 00:00:22, memory = 1209.57 (MB).
Completing 60% with 971 violations.
elapsed time = 00:00:24, memory = 1209.57 (MB).
Completing 70% with 971 violations.
elapsed time = 00:00:32, memory = 1209.57 (MB).
Completing 80% with 996 violations.
elapsed time = 00:00:35, memory = 1209.59 (MB).
Completing 90% with 996 violations.
elapsed time = 00:00:39, memory = 1209.59 (MB).
Completing 100% with 877 violations.
elapsed time = 00:00:47, memory = 1209.59 (MB).
[INFO DRT-0199] Number of violations = 877.
[INFO DRT-0267] cpu time = 00:01:31, elapsed time = 00:00:47, memory = 1209.59 (MB), peak = 1254.95 (MB)
Total wire length = 222358 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 98586 um.
Total wire length on LAYER met2 = 96143 um.
Total wire length on LAYER met3 = 19818 um.
Total wire length on LAYER met4 = 7810 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44123.
Up-via summary (total 44123):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21554
met2 734
met3 195
met4 0
------------------------
44123
[INFO DRT-0195] Start 3rd optimization iteration.
Completing 10% with 877 violations.
elapsed time = 00:00:00, memory = 1209.59 (MB).
Completing 20% with 877 violations.
elapsed time = 00:00:10, memory = 1209.59 (MB).
Completing 30% with 668 violations.
elapsed time = 00:00:11, memory = 1209.59 (MB).
Completing 40% with 668 violations.
elapsed time = 00:00:14, memory = 1209.59 (MB).
Completing 50% with 668 violations.
elapsed time = 00:00:21, memory = 1209.59 (MB).
Completing 60% with 450 violations.
elapsed time = 00:00:25, memory = 1209.59 (MB).
Completing 70% with 450 violations.
elapsed time = 00:00:38, memory = 1209.59 (MB).
Completing 80% with 302 violations.
elapsed time = 00:00:49, memory = 1209.40 (MB).
Completing 90% with 302 violations.
elapsed time = 00:01:00, memory = 1209.40 (MB).
Completing 100% with 91 violations.
elapsed time = 00:01:10, memory = 1209.40 (MB).
[INFO DRT-0199] Number of violations = 91.
[INFO DRT-0267] cpu time = 00:02:13, elapsed time = 00:01:11, memory = 1209.40 (MB), peak = 1254.95 (MB)
Total wire length = 222292 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96726 um.
Total wire length on LAYER met2 = 96373 um.
Total wire length on LAYER met3 = 21459 um.
Total wire length on LAYER met4 = 7733 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44570.
Up-via summary (total 44570):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21764
met2 976
met3 190
met4 0
------------------------
44570
[INFO DRT-0195] Start 4th optimization iteration.
Completing 10% with 91 violations.
elapsed time = 00:00:00, memory = 1209.40 (MB).
Completing 20% with 91 violations.
elapsed time = 00:00:00, memory = 1209.40 (MB).
Completing 30% with 80 violations.
elapsed time = 00:00:00, memory = 1209.40 (MB).
Completing 40% with 80 violations.
elapsed time = 00:00:00, memory = 1209.40 (MB).
Completing 50% with 80 violations.
elapsed time = 00:00:04, memory = 1209.40 (MB).
Completing 60% with 59 violations.
elapsed time = 00:00:05, memory = 1209.40 (MB).
Completing 70% with 59 violations.
elapsed time = 00:00:05, memory = 1209.40 (MB).
Completing 80% with 41 violations.
elapsed time = 00:00:08, memory = 1209.59 (MB).
Completing 90% with 41 violations.
elapsed time = 00:00:09, memory = 1209.59 (MB).
Completing 100% with 12 violations.
elapsed time = 00:00:15, memory = 1209.59 (MB).
[INFO DRT-0199] Number of violations = 12.
[INFO DRT-0267] cpu time = 00:00:25, elapsed time = 00:00:15, memory = 1209.60 (MB), peak = 1254.95 (MB)
Total wire length = 222257 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96575 um.
Total wire length on LAYER met2 = 96374 um.
Total wire length on LAYER met3 = 21573 um.
Total wire length on LAYER met4 = 7733 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44578.
Up-via summary (total 44578):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21764
met2 984
met3 190
met4 0
------------------------
44578
[INFO DRT-0195] Start 5th optimization iteration.
Completing 10% with 12 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 20% with 12 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 30% with 10 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 40% with 10 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 50% with 10 violations.
elapsed time = 00:00:03, memory = 1209.60 (MB).
Completing 60% with 8 violations.
elapsed time = 00:00:04, memory = 1209.60 (MB).
Completing 70% with 8 violations.
elapsed time = 00:00:04, memory = 1209.60 (MB).
Completing 80% with 8 violations.
elapsed time = 00:00:06, memory = 1209.60 (MB).
Completing 90% with 8 violations.
elapsed time = 00:00:06, memory = 1209.60 (MB).
Completing 100% with 8 violations.
elapsed time = 00:00:06, memory = 1209.60 (MB).
[INFO DRT-0199] Number of violations = 8.
[INFO DRT-0267] cpu time = 00:00:10, elapsed time = 00:00:06, memory = 1209.60 (MB), peak = 1254.95 (MB)
Total wire length = 222257 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96533 um.
Total wire length on LAYER met2 = 96374 um.
Total wire length on LAYER met3 = 21616 um.
Total wire length on LAYER met4 = 7733 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44577.
Up-via summary (total 44577):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21761
met2 986
met3 190
met4 0
------------------------
44577
[INFO DRT-0195] Start 6th optimization iteration.
Completing 10% with 8 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 20% with 8 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 30% with 8 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 40% with 8 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 50% with 8 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 60% with 1 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 70% with 1 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 80% with 1 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 90% with 1 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 100% with 1 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
[INFO DRT-0199] Number of violations = 1.
[INFO DRT-0267] cpu time = 00:00:02, elapsed time = 00:00:02, memory = 1209.60 (MB), peak = 1254.95 (MB)
Total wire length = 222259 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96538 um.
Total wire length on LAYER met2 = 96372 um.
Total wire length on LAYER met3 = 21616 um.
Total wire length on LAYER met4 = 7733 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44576.
Up-via summary (total 44576):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21760
met2 986
met3 190
met4 0
------------------------
44576
[INFO DRT-0195] Start 7th optimization iteration.
Completing 10% with 1 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 20% with 1 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:01, memory = 1209.60 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:01, memory = 1209.60 (MB), peak = 1254.95 (MB)
Total wire length = 222261 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96538 um.
Total wire length on LAYER met2 = 96373 um.
Total wire length on LAYER met3 = 21616 um.
Total wire length on LAYER met4 = 7733 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44576.
Up-via summary (total 44576):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21760
met2 986
met3 190
met4 0
------------------------
44576
[INFO DRT-0195] Start 17th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1209.60 (MB), peak = 1254.95 (MB)
Total wire length = 222261 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96538 um.
Total wire length on LAYER met2 = 96373 um.
Total wire length on LAYER met3 = 21616 um.
Total wire length on LAYER met4 = 7733 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44576.
Up-via summary (total 44576):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21760
met2 986
met3 190
met4 0
------------------------
44576
[INFO DRT-0195] Start 25th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1209.60 (MB), peak = 1254.95 (MB)
Total wire length = 222261 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96538 um.
Total wire length on LAYER met2 = 96373 um.
Total wire length on LAYER met3 = 21616 um.
Total wire length on LAYER met4 = 7733 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44576.
Up-via summary (total 44576):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21760
met2 986
met3 190
met4 0
------------------------
44576
[INFO DRT-0195] Start 33rd optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1209.60 (MB), peak = 1254.95 (MB)
Total wire length = 222261 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96538 um.
Total wire length on LAYER met2 = 96373 um.
Total wire length on LAYER met3 = 21616 um.
Total wire length on LAYER met4 = 7733 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44576.
Up-via summary (total 44576):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21760
met2 986
met3 190
met4 0
------------------------
44576
[INFO DRT-0195] Start 41st optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1209.60 (MB), peak = 1254.95 (MB)
Total wire length = 222261 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96538 um.
Total wire length on LAYER met2 = 96373 um.
Total wire length on LAYER met3 = 21616 um.
Total wire length on LAYER met4 = 7733 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44576.
Up-via summary (total 44576):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21760
met2 986
met3 190
met4 0
------------------------
44576
[INFO DRT-0195] Start 49th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1209.60 (MB), peak = 1254.95 (MB)
Total wire length = 222261 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96538 um.
Total wire length on LAYER met2 = 96373 um.
Total wire length on LAYER met3 = 21616 um.
Total wire length on LAYER met4 = 7733 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44576.
Up-via summary (total 44576):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21760
met2 986
met3 190
met4 0
------------------------
44576
[INFO DRT-0195] Start 57th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1209.60 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1209.60 (MB), peak = 1254.95 (MB)
Total wire length = 222261 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96538 um.
Total wire length on LAYER met2 = 96373 um.
Total wire length on LAYER met3 = 21616 um.
Total wire length on LAYER met4 = 7733 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44576.
Up-via summary (total 44576):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21760
met2 986
met3 190
met4 0
------------------------
44576
[INFO DRT-0198] Complete detail routing.
Total wire length = 222261 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96538 um.
Total wire length on LAYER met2 = 96373 um.
Total wire length on LAYER met3 = 21616 um.
Total wire length on LAYER met4 = 7733 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44576.
Up-via summary (total 44576):.
------------------------
FR_MASTERSLICE 0
li1 21640
met1 21760
met2 986
met3 190
met4 0
------------------------
44576
[INFO DRT-0267] cpu time = 00:07:50, elapsed time = 00:04:11, memory = 1209.60 (MB), peak = 1254.95 (MB)
[INFO DRT-0180] Post processing.
Saving to /home/ali11-2000/FYP/mpw/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/results/routing/Motor_Top.def