Licence added
diff --git a/verilog/rtl/Core.v b/verilog/rtl/Core.v index 81d18fb..fd15114 100644 --- a/verilog/rtl/Core.v +++ b/verilog/rtl/Core.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 EE, UET Lahore +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk> module CSR( // @[:@3.2] input clock, // @[:@4.4] input reset, // @[:@5.4]
diff --git a/verilog/rtl/DMem.v b/verilog/rtl/DMem.v index 7108a81..5e23109 100644 --- a/verilog/rtl/DMem.v +++ b/verilog/rtl/DMem.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 EE, UET Lahore +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk> module DMem( // @[:@12681.2] input clock, // @[:@12682.4] input [7:0] io_addr, // @[:@12684.4]
diff --git a/verilog/rtl/IMem.v b/verilog/rtl/IMem.v index daf98dd..a95100a 100644 --- a/verilog/rtl/IMem.v +++ b/verilog/rtl/IMem.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 EE, UET Lahore +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk> module IMem( // @[:@12666.2] input clock, // @[:@12667.4] input [8:0] io_addr, // @[:@12669.4]
diff --git a/verilog/rtl/Motor_Top.v b/verilog/rtl/Motor_Top.v index af06661..fff906a 100644 --- a/verilog/rtl/Motor_Top.v +++ b/verilog/rtl/Motor_Top.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 EE, UET Lahore +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk> module Interlink_Module( // @[:@4032.2] input clock, // @[:@4033.4] input reset, // @[:@4034.4]
diff --git a/verilog/rtl/Processor_Tile.v b/verilog/rtl/Processor_Tile.v index 6bc19e4..024107b 100644 --- a/verilog/rtl/Processor_Tile.v +++ b/verilog/rtl/Processor_Tile.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 EE, UET Lahore +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk> module Processor_Tile( // @[:@12742.2] input clock, // @[:@12743.4] input reset, // @[:@12744.4]
diff --git a/verilog/rtl/WB_InterConnect.v b/verilog/rtl/WB_InterConnect.v index aa4338a..c4ff6b8 100644 --- a/verilog/rtl/WB_InterConnect.v +++ b/verilog/rtl/WB_InterConnect.v
@@ -1,3 +1,18 @@ +// SPDX-FileCopyrightText: 2022 EE, UET Lahore +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 +// SPDX-FileContributor: Created by Muhammad Tahir <mtahir@uet.edu.pk> module DMem_Interface( // @[:@1882.2] input clock, // @[:@1883.4] input reset, // @[:@1884.4]