| [INFO]: Current run directory is /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect |
| [INFO]: Storing configs into config.tcl ... |
| [INFO]: Preparing LEF Files |
| [INFO]: Extracting the number of available metal layers from /home/ali112000/Desktop/mpw/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd.tlef |
| [INFO]: The available metal layers (6) are li1 met1 met2 met3 met4 met5 |
| [INFO]: Merging LEF Files... |
| [INFO]: Trimming Liberty... |
| [INFO]: Generating Exclude List... |
| [INFO]: Generating Exclude List... |
| [INFO]: Creating ::env(DONT_USE_CELLS)... |
| [INFO]: Preparation complete |
| [INFO]: Incremented step index to 0. |
| [INFO]: Running Synthesis... |
| [INFO]: Changing netlist from 0 to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/synthesis/WB_InterConnect.v |
| [INFO]: Incremented step index to 1. |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: Synthesis was successful |
| [INFO]: Running Floorplanning... |
| [INFO]: Running Initial Floorplanning... |
| [INFO]: Incremented step index to 2. |
| [INFO]: Core area width: 1088.96 |
| [INFO]: Core area height: 1078.2399999999998 |
| [INFO]: Final Vertical PDN Offset: 16.32 |
| [INFO]: Final Horizontal PDN Offset: 16.65 |
| [INFO]: Final Vertical PDN Pitch: 153.6 |
| [INFO]: Final Horizontal PDN Pitch: 153.18 |
| [INFO]: Changing layout from 0 to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/floorplan/3-initial_fp.def |
| [INFO]: Setting Core Dimensions... |
| [INFO]: Incremented step index to 3. |
| [INFO]: Running IO Placement... |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/floorplan/3-initial_fp.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/floorplan/4-io.def |
| [INFO]: Incremented step index to 4. |
| [INFO]: Running Tap/Decap Insertion... |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/floorplan/4-io.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/floorplan/WB_InterConnect.def |
| [INFO]: Power planning the following nets |
| [INFO]: Power: vccd1 |
| [INFO]: Ground: vssd1 |
| [INFO]: Incremented step index to 5. |
| [INFO]: Generating PDN... |
| [INFO]: PDN generation was successful. |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/floorplan/WB_InterConnect.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/floorplan/6-pdn.def |
| [INFO]: Running Placement... |
| [INFO]: Incremented step index to 6. |
| [INFO]: Running Global Placement... |
| [INFO]: Global placement was successful |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/floorplan/6-pdn.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/placement/7-global.def |
| [INFO]: Incremented step index to 7. |
| [INFO]: Running Resizer Design Optimizations... |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/placement/7-global.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/placement/8-resizer.def |
| [INFO]: Incremented step index to 8. |
| [INFO]: Writing Verilog... |
| [INFO]: Changing netlist from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/synthesis/WB_InterConnect.v to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/placement/WB_InterConnect.resized.v |
| [INFO]: Incremented step index to 9. |
| [INFO]: Running Detailed Placement... |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/placement/8-resizer.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/placement/WB_InterConnect.def |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/placement/WB_InterConnect.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/placement/WB_InterConnect.def |
| [INFO]: Incremented step index to 10. |
| [INFO]: Running TritonCTS... |
| [INFO]: Trimming Liberty... |
| [INFO]: Generating Exclude List... |
| [INFO]: Clock Tree Synthesis was successful |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/placement/WB_InterConnect.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/cts/WB_InterConnect.def |
| [INFO]: Incremented step index to 11. |
| [INFO]: Writing Verilog... |
| [INFO]: Changing netlist from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/placement/WB_InterConnect.resized.v to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/cts/WB_InterConnect.v |
| [INFO]: Incremented step index to 12. |
| [INFO]: Running Resizer Timing Optimizations... |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/cts/WB_InterConnect.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/cts/13-resizer_timing.def |
| [INFO]: Incremented step index to 13. |
| [INFO]: Writing Verilog... |
| [INFO]: Changing netlist from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/cts/WB_InterConnect.v to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/cts/WB_InterConnect.resized.v |
| [INFO]: Routing... |
| [INFO]: Skipping Resizer Timing Optimizations. |
| [INFO]: Incremented step index to 14. |
| [INFO]: Running Diode Insertion... |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/cts/13-resizer_timing.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/15-diodes.def |
| [INFO]: Incremented step index to 15. |
| [INFO]: Running Detailed Placement... |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/15-diodes.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/15-diodes.def |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/15-diodes.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/15-diodes.def |
| [INFO]: Incremented step index to 16. |
| [INFO]: Writing Verilog... |
| [INFO]: Changing netlist from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/cts/WB_InterConnect.resized.v to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/synthesis/WB_InterConnect_diodes.v |
| [INFO]: Incremented step index to 17. |
| [INFO]: Running Fill Insertion... |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/15-diodes.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/18-fill.def |
| [INFO]: Incremented step index to 18. |
| [INFO]: Running Global Routing... |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/18-fill.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/19-global.def |
| [INFO]: Changing layout from 0 to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/19-global.guide |
| [INFO]: Current Def is /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/19-global.def |
| [INFO]: Current Guide is /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/19-global.guide |
| [INFO]: Incremented step index to 19. |
| [INFO]: Writing Verilog... |
| [INFO]: Changing netlist from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/synthesis/WB_InterConnect_diodes.v to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/19-global.v |
| [INFO]: Incremented step index to 20. |
| [INFO]: Running Detailed Routing... |
| [INFO]: No DRC violations after detailed routing. |
| [INFO]: Changing layout from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/19-global.def to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/routing/WB_InterConnect.def |
| [INFO]: Incremented step index to 21. |
| [INFO]: Writing Verilog... |
| [INFO]: Changing netlist from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/19-global.v to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/21-detailed.v |
| [INFO]: Incremented step index to 22. |
| [INFO]: Running SPEF Extraction... |
| [INFO]: Incremented step index to 23. |
| [INFO]: Running SPEF Extraction... |
| [INFO]: Incremented step index to 24. |
| [INFO]: Running SPEF Extraction... |
| [INFO]: Incremented step index to 25. |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: Incremented step index to 26. |
| [INFO]: Running Static Timing Analysis... |
| [INFO]: Incremented step index to 27. |
| [INFO]: Running Magic to generate various views... |
| [INFO]: Streaming out GDS II... |
| [INFO]: Generating MAGLEF views... |
| [INFO]: Generting GDS II with Klayout... |
| [INFO]: Incremented step index to 28. |
| [INFO]: Streaming out GDS II... |
| [INFO]: Back-up GDS-II streamed out. |
| [INFO]: Incremented step index to 29. |
| [INFO]: Running XOR on the layouts using Klayout... |
| [INFO]: Klayout XOR Complete |
| [INFO]: Incremented step index to 30. |
| [INFO]: Running Magic Spice Export from LEF... |
| [INFO]: No illegal overlaps detected during extraction. |
| [INFO]: Incremented step index to 31. |
| [INFO]: Writing Powered Verilog... |
| [INFO]: Incremented step index to 32. |
| [INFO]: Writing Verilog... |
| [INFO]: Yosys won't attempt to rewrite verilog, and the OpenROAD output will be used as is. |
| [INFO]: Changing netlist from /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/routing/21-detailed.v to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/finishing/31-powered_netlist.v |
| [INFO]: Incremented step index to 33. |
| [INFO]: Running LEF LVS... |
| [INFO]: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/finishing/WB_InterConnect.spice against /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/finishing/31-powered_netlist.v |
| [INFO]: No LVS mismatches. |
| [INFO]: Incremented step index to 34. |
| [INFO]: Running Magic DRC... |
| [INFO]: Converting Magic DRC Violations to Magic Readable Format... |
| [INFO]: Converting Magic DRC Violations to Klayout XML Database... |
| [INFO]: Converting DRC Violations to RDB Format... |
| [INFO]: Converted DRC Violations to RDB Format |
| [INFO]: No DRC violations after GDS streaming out. |
| [INFO]: Running Antenna Checks... |
| [INFO]: Incremented step index to 35. |
| [INFO]: Running OpenROAD Antenna Rule Checker... |
| [INFO]: Incremented step index to 36. |
| [INFO]: Running CVC... |
| [INFO]: Saving final set of views in '/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/final'... |
| [INFO]: Saving final set of views in '/home/ali112000/mpw5/UETRV-ECORE'... |
| [INFO]: Calculating Runtime From the Start... |
| [INFO]: Saving runtime environment... |
| [INFO]: Generating Final Summary Report... |
| [INFO]: Design Name: WB_InterConnect |
| Run Directory: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect |
| ---------------------------------------- |
| |
| Magic DRC Summary: |
| Source: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/reports/finishing/drc.rpt |
| Total Magic DRC violations is 0 |
| ---------------------------------------- |
| |
| LVS Summary: |
| Source: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/logs/finishing/34-WB_InterConnect.lvs.lef.log |
| LVS reports no net, device, pin, or property mismatches. |
| Total errors = 0 |
| ---------------------------------------- |
| |
| Antenna Summary: |
| Source: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/reports/finishing/antenna.rpt |
| Number of pins violated: 44 |
| Number of nets violated: 42 |
| [INFO]: check full report here: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/reports/final_summary_report.csv |
| [INFO]: There are no max slew violations in the design at the typical corner. |
| [INFO]: There are no hold violations in the design at the typical corner. |
| [INFO]: There are no setup violations in the design at the typical corner. |
| [SUCCESS]: Flow complete. |
