| OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO ODB-0222] Reading LEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/merged_unpadded.lef |
| [INFO ODB-0223] Created 13 technology layers |
| [INFO ODB-0224] Created 25 technology vias |
| [INFO ODB-0225] Created 441 library cells |
| [INFO ODB-0226] Finished LEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/merged_unpadded.lef |
| [INFO ODB-0127] Reading DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/placement/7-global.def |
| [INFO ODB-0128] Design: WB_InterConnect |
| [INFO ODB-0130] Created 430 pins. |
| [INFO ODB-0131] Created 20261 components and 57035 component-terminals. |
| [INFO ODB-0132] Created 2 special nets and 47612 connections. |
| [INFO ODB-0133] Created 2957 nets and 9423 connections. |
| [INFO ODB-0134] Finished DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/placement/7-global.def |
| ############################################################################### |
| # Created by write_sdc |
| # Mon Mar 21 23:55:43 2022 |
| ############################################################################### |
| current_design WB_InterConnect |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name clock -period 20.0000 [get_ports {clock}] |
| set_clock_transition 0.1500 [get_clocks {clock}] |
| set_clock_uncertainty 0.2500 clock |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_ld_type[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_ld_type[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_ld_type[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rd_en}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_st_type[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_st_type[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wr_en}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_ack_i}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_miso}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_uart_rx}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {reset}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_valid}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_cs}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_st_type[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_st_type[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_st_type[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_st_type[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wr_en}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_valid}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_cs}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_st_type[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_st_type[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_st_type[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_st_type[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wr_en}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_addr_sel}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_clk}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_clk_en}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_cs}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_cs_en}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_irq}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_mosi}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_mosi_en}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_uart_irq}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_uart_tx}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_uart_txen}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_sel[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_sel[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_sel[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_sel[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_stb}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_we}] |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {io_dbus_valid}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_cs}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wr_en}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_valid}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_cs}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wr_en}] |
| set_load -pin_load 0.0334 [get_ports {io_motor_addr_sel}] |
| set_load -pin_load 0.0334 [get_ports {io_spi_clk}] |
| set_load -pin_load 0.0334 [get_ports {io_spi_clk_en}] |
| set_load -pin_load 0.0334 [get_ports {io_spi_cs}] |
| set_load -pin_load 0.0334 [get_ports {io_spi_cs_en}] |
| set_load -pin_load 0.0334 [get_ports {io_spi_irq}] |
| set_load -pin_load 0.0334 [get_ports {io_spi_mosi}] |
| set_load -pin_load 0.0334 [get_ports {io_spi_mosi_en}] |
| set_load -pin_load 0.0334 [get_ports {io_uart_irq}] |
| set_load -pin_load 0.0334 [get_ports {io_uart_tx}] |
| set_load -pin_load 0.0334 [get_ports {io_uart_txen}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_stb}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_we}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_st_type[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_st_type[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_st_type[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_st_type[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[31]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[30]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[29]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[28]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[27]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[26]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_inst[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_st_type[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_st_type[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_st_type[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_st_type[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[31]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[30]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[29]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[28]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[27]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[26]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_sel[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_sel[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_sel[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_sel[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clock}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rd_en}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wr_en}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_ack_i}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_spi_miso}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_uart_rx}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reset}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_ld_type[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_ld_type[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_ld_type[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_st_type[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_st_type[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[0]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
| set_max_fanout 5.0000 [current_design] |
| [INFO]: Setting RC values... |
| [INFO RSZ-0027] Inserted 168 input buffers. |
| [INFO RSZ-0028] Inserted 224 output buffers. |
| [INFO RSZ-0058] Using max wire length 2319um. |
| [INFO RSZ-0034] Found 2 slew violations. |
| [INFO RSZ-0037] Found 1 long wires. |
| [INFO RSZ-0038] Inserted 4 buffers in 3 nets. |
| [INFO RSZ-0039] Resized 2921 instances. |
| Placement Analysis |
| --------------------------------- |
| total displacement 10102.9 u |
| average displacement 0.5 u |
| max displacement 21.9 u |
| original HPWL 326921.1 u |
| legalized HPWL 334902.0 u |
| delta HPWL 2 % |
| |
| [INFO DPL-0020] Mirrored 1366 instances |
| [INFO DPL-0021] HPWL before 334902.0 u |
| [INFO DPL-0022] HPWL after 332462.1 u |
| [INFO DPL-0023] HPWL delta -0.7 % |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _4835_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: _4835_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _4835_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| 0.04 0.32 0.32 v _4835_/Q (sky130_fd_sc_hd__dfxtp_1) |
| 2 0.01 spi.pending_data (net) |
| 0.04 0.00 0.32 v _4437_/A (sky130_fd_sc_hd__nand2_1) |
| 0.04 0.05 0.37 ^ _4437_/Y (sky130_fd_sc_hd__nand2_1) |
| 1 0.00 _1889_ (net) |
| 0.04 0.00 0.37 ^ _4438_/A2 (sky130_fd_sc_hd__a21oi_1) |
| 0.04 0.05 0.43 v _4438_/Y (sky130_fd_sc_hd__a21oi_1) |
| 1 0.00 _0156_ (net) |
| 0.04 0.00 0.43 v _4835_/D (sky130_fd_sc_hd__dfxtp_1) |
| 0.43 data arrival time |
| |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _4835_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.03 0.22 library hold time |
| 0.22 data required time |
| ----------------------------------------------------------------------------- |
| 0.22 data required time |
| -0.43 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.20 slack (MET) |
| |
| |
| Startpoint: _4693_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: _4693_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _4693_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| 0.04 0.33 0.33 v _4693_/Q (sky130_fd_sc_hd__dfxtp_1) |
| 3 0.01 uart.rxm.prescaler[0] (net) |
| 0.04 0.00 0.33 v _3403_/A (sky130_fd_sc_hd__nand2_1) |
| 0.05 0.06 0.38 ^ _3403_/Y (sky130_fd_sc_hd__nand2_1) |
| 1 0.00 _0988_ (net) |
| 0.05 0.00 0.38 ^ _3410_/A1 (sky130_fd_sc_hd__a21oi_1) |
| 0.04 0.05 0.43 v _3410_/Y (sky130_fd_sc_hd__a21oi_1) |
| 1 0.00 _0024_ (net) |
| 0.04 0.00 0.43 v _4693_/D (sky130_fd_sc_hd__dfxtp_1) |
| 0.43 data arrival time |
| |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _4693_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.03 0.22 library hold time |
| 0.22 data required time |
| ----------------------------------------------------------------------------- |
| 0.22 data required time |
| -0.43 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.21 slack (MET) |
| |
| |
| Startpoint: _4700_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: _4700_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _4700_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| 0.05 0.33 0.33 v _4700_/Q (sky130_fd_sc_hd__dfxtp_1) |
| 3 0.01 uart.rxm.prescaler[7] (net) |
| 0.05 0.00 0.33 v _3450_/A (sky130_fd_sc_hd__nand2_1) |
| 0.04 0.05 0.38 ^ _3450_/Y (sky130_fd_sc_hd__nand2_1) |
| 1 0.00 _1028_ (net) |
| 0.04 0.00 0.38 ^ _3458_/A1 (sky130_fd_sc_hd__a21oi_1) |
| 0.04 0.05 0.43 v _3458_/Y (sky130_fd_sc_hd__a21oi_1) |
| 1 0.00 _0031_ (net) |
| 0.04 0.00 0.43 v _4700_/D (sky130_fd_sc_hd__dfxtp_1) |
| 0.43 data arrival time |
| |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _4700_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.03 0.22 library hold time |
| 0.22 data required time |
| ----------------------------------------------------------------------------- |
| 0.22 data required time |
| -0.43 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.21 slack (MET) |
| |
| |
| Startpoint: _4694_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: _4694_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _4694_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| 0.04 0.33 0.33 v _4694_/Q (sky130_fd_sc_hd__dfxtp_1) |
| 3 0.01 uart.rxm.prescaler[1] (net) |
| 0.04 0.00 0.33 v _3411_/A (sky130_fd_sc_hd__nand2_1) |
| 0.05 0.06 0.38 ^ _3411_/Y (sky130_fd_sc_hd__nand2_1) |
| 1 0.00 _0995_ (net) |
| 0.05 0.00 0.38 ^ _3417_/A1 (sky130_fd_sc_hd__a21oi_1) |
| 0.04 0.05 0.43 v _3417_/Y (sky130_fd_sc_hd__a21oi_1) |
| 1 0.00 _0025_ (net) |
| 0.04 0.00 0.43 v _4694_/D (sky130_fd_sc_hd__dfxtp_1) |
| 0.43 data arrival time |
| |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _4694_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.03 0.22 library hold time |
| 0.22 data required time |
| ----------------------------------------------------------------------------- |
| 0.22 data required time |
| -0.43 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.21 slack (MET) |
| |
| |
| Startpoint: _4735_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: _4735_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _4735_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| 0.05 0.33 0.33 v _4735_/Q (sky130_fd_sc_hd__dfxtp_1) |
| 3 0.01 uart.txm.prescaler[7] (net) |
| 0.05 0.00 0.33 v _3611_/A (sky130_fd_sc_hd__nand2_1) |
| 0.04 0.06 0.39 ^ _3611_/Y (sky130_fd_sc_hd__nand2_1) |
| 1 0.00 _1154_ (net) |
| 0.04 0.00 0.39 ^ _3614_/A1 (sky130_fd_sc_hd__a21oi_1) |
| 0.04 0.05 0.44 v _3614_/Y (sky130_fd_sc_hd__a21oi_1) |
| 1 0.00 _0066_ (net) |
| 0.04 0.00 0.44 v _4735_/D (sky130_fd_sc_hd__dfxtp_1) |
| 0.44 data arrival time |
| |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _4735_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.03 0.22 library hold time |
| 0.22 data required time |
| ----------------------------------------------------------------------------- |
| 0.22 data required time |
| -0.44 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.21 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: io_ibus_addr[2] (input port clocked by clock) |
| Endpoint: _4801_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 v input external delay |
| 0.01 0.00 4.00 v io_ibus_addr[2] (in) |
| 1 0.00 io_ibus_addr[2] (net) |
| 0.01 0.00 4.00 v input93/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.08 0.16 4.17 v input93/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 4 0.01 net93 (net) |
| 0.08 0.00 4.17 v _2761_/A (sky130_fd_sc_hd__buf_2) |
| 0.08 0.19 4.36 v _2761_/X (sky130_fd_sc_hd__buf_2) |
| 5 0.03 _0355_ (net) |
| 0.08 0.00 4.36 v _2953_/A (sky130_fd_sc_hd__xor2_4) |
| 0.08 0.22 4.58 v _2953_/X (sky130_fd_sc_hd__xor2_4) |
| 3 0.02 _0547_ (net) |
| 0.08 0.00 4.58 v _2954_/C (sky130_fd_sc_hd__and3_1) |
| 0.06 0.22 4.80 v _2954_/X (sky130_fd_sc_hd__and3_1) |
| 3 0.01 _0548_ (net) |
| 0.06 0.00 4.80 v _3837_/A (sky130_fd_sc_hd__or4_1) |
| 0.08 0.53 5.34 v _3837_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1323_ (net) |
| 0.08 0.00 5.34 v _3843_/B (sky130_fd_sc_hd__or4_1) |
| 0.11 0.58 5.91 v _3843_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _1329_ (net) |
| 0.11 0.00 5.91 v _3844_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 6.36 v _3844_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1330_ (net) |
| 0.09 0.00 6.36 v _3845_/D (sky130_fd_sc_hd__or4_1) |
| 0.10 0.45 6.80 v _3845_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1331_ (net) |
| 0.10 0.00 6.80 v _3846_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.42 7.22 v _3846_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1332_ (net) |
| 0.08 0.00 7.22 v _3847_/D (sky130_fd_sc_hd__or4_1) |
| 0.11 0.47 7.69 v _3847_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _1333_ (net) |
| 0.11 0.00 7.69 v _3848_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.43 8.12 v _3848_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1334_ (net) |
| 0.08 0.00 8.12 v _3849_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.43 8.55 v _3849_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1335_ (net) |
| 0.09 0.00 8.55 v _3850_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 8.99 v _3850_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1336_ (net) |
| 0.09 0.00 8.99 v _3851_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.41 9.40 v _3851_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1337_ (net) |
| 0.08 0.00 9.40 v _3852_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 9.84 v _3852_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1338_ (net) |
| 0.09 0.00 9.84 v _3854_/C (sky130_fd_sc_hd__or4_1) |
| 0.08 0.50 10.34 v _3854_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1340_ (net) |
| 0.08 0.00 10.34 v _3855_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 10.78 v _3855_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1341_ (net) |
| 0.09 0.00 10.78 v _3857_/C (sky130_fd_sc_hd__or4_1) |
| 0.08 0.50 11.28 v _3857_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1343_ (net) |
| 0.08 0.00 11.28 v _3858_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 11.72 v _3858_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1344_ (net) |
| 0.09 0.00 11.72 v _3862_/C (sky130_fd_sc_hd__or4_1) |
| 0.08 0.49 12.21 v _3862_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1348_ (net) |
| 0.08 0.00 12.21 v _3863_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.43 12.64 v _3863_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1349_ (net) |
| 0.09 0.00 12.64 v _3868_/A2 (sky130_fd_sc_hd__o211a_1) |
| 0.04 0.23 12.87 v _3868_/X (sky130_fd_sc_hd__o211a_1) |
| 1 0.00 _0123_ (net) |
| 0.04 0.00 12.87 v _4801_/D (sky130_fd_sc_hd__dfxtp_1) |
| 12.87 data arrival time |
| |
| 0.15 20.00 20.00 clock clock (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| 19.75 ^ _4801_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.08 19.67 library setup time |
| 19.67 data required time |
| ----------------------------------------------------------------------------- |
| 19.67 data required time |
| -12.87 data arrival time |
| ----------------------------------------------------------------------------- |
| 6.80 slack (MET) |
| |
| |
| Startpoint: io_ibus_addr[4] (input port clocked by clock) |
| Endpoint: _4688_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 ^ input external delay |
| 0.03 0.02 4.02 ^ io_ibus_addr[4] (in) |
| 1 0.00 io_ibus_addr[4] (net) |
| 0.03 0.00 4.02 ^ input95/A (sky130_fd_sc_hd__clkbuf_1) |
| 0.17 0.17 4.18 ^ input95/X (sky130_fd_sc_hd__clkbuf_1) |
| 5 0.01 net95 (net) |
| 0.17 0.00 4.18 ^ _2331_/A (sky130_fd_sc_hd__clkbuf_2) |
| 0.15 0.23 4.42 ^ _2331_/X (sky130_fd_sc_hd__clkbuf_2) |
| 5 0.03 _2089_ (net) |
| 0.15 0.00 4.42 ^ _2332_/A (sky130_fd_sc_hd__clkbuf_2) |
| 0.14 0.22 4.64 ^ _2332_/X (sky130_fd_sc_hd__clkbuf_2) |
| 5 0.02 _2090_ (net) |
| 0.14 0.00 4.64 ^ _2848_/A (sky130_fd_sc_hd__or2_2) |
| 0.11 0.20 4.84 ^ _2848_/X (sky130_fd_sc_hd__or2_2) |
| 5 0.02 _0442_ (net) |
| 0.11 0.00 4.84 ^ _3040_/A (sky130_fd_sc_hd__or2_1) |
| 0.07 0.14 4.98 ^ _3040_/X (sky130_fd_sc_hd__or2_1) |
| 2 0.01 _0634_ (net) |
| 0.07 0.00 4.98 ^ _3340_/B (sky130_fd_sc_hd__nor2_1) |
| 0.07 0.07 5.05 v _3340_/Y (sky130_fd_sc_hd__nor2_1) |
| 3 0.01 _0930_ (net) |
| 0.07 0.00 5.05 v _3341_/B (sky130_fd_sc_hd__or2_1) |
| 0.09 0.27 5.32 v _3341_/X (sky130_fd_sc_hd__or2_1) |
| 3 0.01 _0931_ (net) |
| 0.09 0.00 5.32 v _3342_/C (sky130_fd_sc_hd__or3_1) |
| 0.10 0.38 5.71 v _3342_/X (sky130_fd_sc_hd__or3_1) |
| 2 0.01 _0932_ (net) |
| 0.10 0.00 5.71 v _3344_/C1 (sky130_fd_sc_hd__a2111o_1) |
| 0.06 0.37 6.08 v _3344_/X (sky130_fd_sc_hd__a2111o_1) |
| 1 0.00 _0934_ (net) |
| 0.06 0.00 6.08 v _3345_/D (sky130_fd_sc_hd__or4_1) |
| 0.12 0.46 6.54 v _3345_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _0935_ (net) |
| 0.12 0.00 6.54 v _3346_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.42 6.96 v _3346_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _0936_ (net) |
| 0.08 0.00 6.96 v _3347_/D (sky130_fd_sc_hd__or4_1) |
| 0.12 0.48 7.44 v _3347_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _0937_ (net) |
| 0.12 0.00 7.44 v _3353_/B (sky130_fd_sc_hd__or3_1) |
| 0.08 0.40 7.84 v _3353_/X (sky130_fd_sc_hd__or3_1) |
| 1 0.01 _0943_ (net) |
| 0.08 0.00 7.84 v _3354_/C (sky130_fd_sc_hd__or3_1) |
| 0.09 0.37 8.20 v _3354_/X (sky130_fd_sc_hd__or3_1) |
| 1 0.01 _0944_ (net) |
| 0.09 0.00 8.20 v _3355_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.43 8.63 v _3355_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _0945_ (net) |
| 0.08 0.00 8.63 v _3356_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.42 9.05 v _3356_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _0946_ (net) |
| 0.08 0.00 9.05 v _3357_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.41 9.47 v _3357_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _0947_ (net) |
| 0.08 0.00 9.47 v _3358_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 9.90 v _3358_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _0948_ (net) |
| 0.09 0.00 9.90 v _3359_/D (sky130_fd_sc_hd__or4_1) |
| 0.07 0.41 10.31 v _3359_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _0949_ (net) |
| 0.07 0.00 10.31 v _3360_/D (sky130_fd_sc_hd__or4_1) |
| 0.10 0.45 10.76 v _3360_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _0950_ (net) |
| 0.10 0.00 10.76 v _3361_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.43 11.18 v _3361_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _0951_ (net) |
| 0.08 0.00 11.18 v _3362_/D (sky130_fd_sc_hd__or4_1) |
| 0.11 0.46 11.64 v _3362_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _0952_ (net) |
| 0.11 0.00 11.64 v _3363_/C1 (sky130_fd_sc_hd__o211a_1) |
| 0.04 0.13 11.78 v _3363_/X (sky130_fd_sc_hd__o211a_1) |
| 1 0.00 _0019_ (net) |
| 0.04 0.00 11.78 v _4688_/D (sky130_fd_sc_hd__dfxtp_1) |
| 11.78 data arrival time |
| |
| 0.15 20.00 20.00 clock clock (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| 19.75 ^ _4688_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.08 19.67 library setup time |
| 19.67 data required time |
| ----------------------------------------------------------------------------- |
| 19.67 data required time |
| -11.78 data arrival time |
| ----------------------------------------------------------------------------- |
| 7.89 slack (MET) |
| |
| |
| Startpoint: io_ibus_addr[9] (input port clocked by clock) |
| Endpoint: _4811_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 v input external delay |
| 0.01 0.00 4.00 v io_ibus_addr[9] (in) |
| 1 0.00 io_ibus_addr[9] (net) |
| 0.01 0.00 4.00 v input100/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.09 0.18 4.19 v input100/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 5 0.02 net100 (net) |
| 0.09 0.00 4.19 v _2354_/A (sky130_fd_sc_hd__clkbuf_2) |
| 0.10 0.20 4.38 v _2354_/X (sky130_fd_sc_hd__clkbuf_2) |
| 5 0.03 _2107_ (net) |
| 0.10 0.00 4.39 v _2787_/B_N (sky130_fd_sc_hd__or2b_1) |
| 0.13 0.25 4.64 ^ _2787_/X (sky130_fd_sc_hd__or2b_1) |
| 4 0.01 _0381_ (net) |
| 0.13 0.00 4.64 ^ _2788_/B (sky130_fd_sc_hd__or2_2) |
| 0.14 0.22 4.86 ^ _2788_/X (sky130_fd_sc_hd__or2_2) |
| 4 0.03 _0382_ (net) |
| 0.14 0.00 4.86 ^ _2789_/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.20 0.24 5.10 ^ _2789_/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 5 0.02 _0383_ (net) |
| 0.20 0.00 5.10 ^ _2790_/A (sky130_fd_sc_hd__clkbuf_2) |
| 0.15 0.24 5.34 ^ _2790_/X (sky130_fd_sc_hd__clkbuf_2) |
| 5 0.03 _0384_ (net) |
| 0.15 0.00 5.34 ^ _2795_/A (sky130_fd_sc_hd__nor2_1) |
| 0.09 0.13 5.47 v _2795_/Y (sky130_fd_sc_hd__nor2_1) |
| 4 0.02 _0389_ (net) |
| 0.09 0.00 5.47 v _3956_/B (sky130_fd_sc_hd__or2_1) |
| 0.07 0.26 5.73 v _3956_/X (sky130_fd_sc_hd__or2_1) |
| 3 0.01 _1440_ (net) |
| 0.07 0.00 5.73 v _4131_/A (sky130_fd_sc_hd__or3_1) |
| 0.08 0.41 6.14 v _4131_/X (sky130_fd_sc_hd__or3_1) |
| 1 0.01 _1607_ (net) |
| 0.08 0.00 6.14 v _4136_/B (sky130_fd_sc_hd__or4b_1) |
| 0.11 0.57 6.70 v _4136_/X (sky130_fd_sc_hd__or4b_1) |
| 1 0.01 _1612_ (net) |
| 0.11 0.00 6.70 v _4137_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 7.15 v _4137_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1613_ (net) |
| 0.09 0.00 7.15 v _4139_/C (sky130_fd_sc_hd__or4_1) |
| 0.12 0.55 7.70 v _4139_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _1615_ (net) |
| 0.12 0.00 7.70 v _4140_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.43 8.13 v _4140_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1616_ (net) |
| 0.08 0.00 8.13 v _4141_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.43 8.56 v _4141_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1617_ (net) |
| 0.09 0.00 8.56 v _4142_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 9.01 v _4142_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1618_ (net) |
| 0.09 0.00 9.01 v _4143_/B2 (sky130_fd_sc_hd__o2bb2a_1) |
| 0.05 0.30 9.30 v _4143_/X (sky130_fd_sc_hd__o2bb2a_1) |
| 1 0.00 _1619_ (net) |
| 0.05 0.00 9.30 v _4144_/D (sky130_fd_sc_hd__or4_1) |
| 0.10 0.44 9.74 v _4144_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1620_ (net) |
| 0.10 0.00 9.74 v _4145_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.42 10.16 v _4145_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1621_ (net) |
| 0.08 0.00 10.16 v _4146_/D (sky130_fd_sc_hd__or4_1) |
| 0.10 0.45 10.61 v _4146_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _1622_ (net) |
| 0.10 0.00 10.61 v _4147_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 11.05 v _4147_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1623_ (net) |
| 0.09 0.00 11.05 v _4148_/C1 (sky130_fd_sc_hd__a311o_1) |
| 0.06 0.31 11.35 v _4148_/X (sky130_fd_sc_hd__a311o_1) |
| 1 0.00 _1624_ (net) |
| 0.06 0.00 11.35 v _4149_/C1 (sky130_fd_sc_hd__o211a_1) |
| 0.04 0.11 11.47 v _4149_/X (sky130_fd_sc_hd__o211a_1) |
| 1 0.00 _0133_ (net) |
| 0.04 0.00 11.47 v _4811_/D (sky130_fd_sc_hd__dfxtp_1) |
| 11.47 data arrival time |
| |
| 0.15 20.00 20.00 clock clock (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| 19.75 ^ _4811_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.08 19.67 library setup time |
| 19.67 data required time |
| ----------------------------------------------------------------------------- |
| 19.67 data required time |
| -11.47 data arrival time |
| ----------------------------------------------------------------------------- |
| 8.20 slack (MET) |
| |
| |
| Startpoint: io_ibus_addr[2] (input port clocked by clock) |
| Endpoint: io_imem_io_addr[0] (output port clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 ^ input external delay |
| 0.02 0.01 4.01 ^ io_ibus_addr[2] (in) |
| 1 0.00 io_ibus_addr[2] (net) |
| 0.02 0.00 4.01 ^ input93/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.15 0.16 4.17 ^ input93/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 4 0.01 net93 (net) |
| 0.15 0.00 4.17 ^ _2307_/A (sky130_fd_sc_hd__clkbuf_2) |
| 0.14 0.22 4.39 ^ _2307_/X (sky130_fd_sc_hd__clkbuf_2) |
| 5 0.02 _2068_ (net) |
| 0.14 0.00 4.39 ^ _2308_/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.21 0.24 4.63 ^ _2308_/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 5 0.02 _2069_ (net) |
| 0.21 0.00 4.63 ^ _2309_/A (sky130_fd_sc_hd__clkbuf_2) |
| 0.16 0.24 4.87 ^ _2309_/X (sky130_fd_sc_hd__clkbuf_2) |
| 5 0.03 _2070_ (net) |
| 0.16 0.00 4.87 ^ _2310_/A (sky130_fd_sc_hd__buf_2) |
| 0.14 0.22 5.10 ^ _2310_/X (sky130_fd_sc_hd__buf_2) |
| 5 0.03 _2071_ (net) |
| 0.14 0.00 5.10 ^ _2311_/A (sky130_fd_sc_hd__clkbuf_2) |
| 0.14 0.22 5.31 ^ _2311_/X (sky130_fd_sc_hd__clkbuf_2) |
| 5 0.03 _2072_ (net) |
| 0.14 0.00 5.31 ^ _2312_/A (sky130_fd_sc_hd__buf_2) |
| 0.18 0.25 5.56 ^ _2312_/X (sky130_fd_sc_hd__buf_2) |
| 5 0.04 _2073_ (net) |
| 0.18 0.00 5.56 ^ _2313_/A (sky130_fd_sc_hd__clkbuf_2) |
| 0.12 0.21 5.77 ^ _2313_/X (sky130_fd_sc_hd__clkbuf_2) |
| 5 0.02 _2074_ (net) |
| 0.12 0.00 5.78 ^ _2314_/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.18 0.22 6.00 ^ _2314_/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 5 0.02 _2075_ (net) |
| 0.18 0.00 6.00 ^ _2315_/A (sky130_fd_sc_hd__buf_2) |
| 0.16 0.25 6.25 ^ _2315_/X (sky130_fd_sc_hd__buf_2) |
| 5 0.03 _2076_ (net) |
| 0.16 0.00 6.25 ^ _2316_/A (sky130_fd_sc_hd__buf_4) |
| 0.15 0.24 6.49 ^ _2316_/X (sky130_fd_sc_hd__buf_4) |
| 5 0.05 _2077_ (net) |
| 0.15 0.00 6.49 ^ _2320_/A0 (sky130_fd_sc_hd__mux2_1) |
| 0.09 0.19 6.68 ^ _2320_/X (sky130_fd_sc_hd__mux2_1) |
| 1 0.01 _2080_ (net) |
| 0.09 0.00 6.68 ^ _2321_/A (sky130_fd_sc_hd__buf_8) |
| 0.17 0.20 6.88 ^ _2321_/X (sky130_fd_sc_hd__buf_8) |
| 1 0.10 net281 (net) |
| 0.17 0.03 6.91 ^ output281/A (sky130_fd_sc_hd__buf_2) |
| 0.18 0.26 7.17 ^ output281/X (sky130_fd_sc_hd__buf_2) |
| 1 0.03 io_imem_io_addr[0] (net) |
| 0.18 0.00 7.17 ^ io_imem_io_addr[0] (out) |
| 7.17 data arrival time |
| |
| 0.15 20.00 20.00 clock clock (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -7.17 data arrival time |
| ----------------------------------------------------------------------------- |
| 8.58 slack (MET) |
| |
| |
| Startpoint: io_ibus_addr[5] (input port clocked by clock) |
| Endpoint: _4820_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 ^ input external delay |
| 0.02 0.01 4.01 ^ io_ibus_addr[5] (in) |
| 1 0.00 io_ibus_addr[5] (net) |
| 0.02 0.00 4.01 ^ input96/A (sky130_fd_sc_hd__clkbuf_1) |
| 0.13 0.14 4.15 ^ input96/X (sky130_fd_sc_hd__clkbuf_1) |
| 4 0.01 net96 (net) |
| 0.13 0.00 4.15 ^ _2337_/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.17 0.22 4.37 ^ _2337_/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 5 0.02 _2094_ (net) |
| 0.17 0.00 4.37 ^ _2338_/A (sky130_fd_sc_hd__clkbuf_2) |
| 0.15 0.23 4.60 ^ _2338_/X (sky130_fd_sc_hd__clkbuf_2) |
| 5 0.03 _2095_ (net) |
| 0.15 0.00 4.60 ^ _2339_/A (sky130_fd_sc_hd__clkbuf_2) |
| 0.14 0.22 4.83 ^ _2339_/X (sky130_fd_sc_hd__clkbuf_2) |
| 5 0.03 _2096_ (net) |
| 0.14 0.00 4.83 ^ _2861_/A (sky130_fd_sc_hd__or2b_2) |
| 0.12 0.20 5.03 ^ _2861_/X (sky130_fd_sc_hd__or2b_2) |
| 4 0.02 _0455_ (net) |
| 0.12 0.00 5.03 ^ _2958_/A (sky130_fd_sc_hd__or2_4) |
| 0.12 0.21 5.24 ^ _2958_/X (sky130_fd_sc_hd__or2_4) |
| 5 0.04 _0552_ (net) |
| 0.12 0.00 5.24 ^ _2959_/B (sky130_fd_sc_hd__nor2_1) |
| 0.07 0.09 5.33 v _2959_/Y (sky130_fd_sc_hd__nor2_1) |
| 4 0.01 _0553_ (net) |
| 0.07 0.00 5.33 v _4311_/A (sky130_fd_sc_hd__or4_1) |
| 0.09 0.56 5.90 v _4311_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1778_ (net) |
| 0.09 0.00 5.90 v _4313_/C (sky130_fd_sc_hd__or4_1) |
| 0.11 0.54 6.43 v _4313_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _1780_ (net) |
| 0.11 0.00 6.44 v _4314_/C (sky130_fd_sc_hd__or3_1) |
| 0.06 0.33 6.77 v _4314_/X (sky130_fd_sc_hd__or3_1) |
| 1 0.00 _1781_ (net) |
| 0.06 0.00 6.77 v _4315_/D (sky130_fd_sc_hd__or4_1) |
| 0.10 0.45 7.21 v _4315_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _1782_ (net) |
| 0.10 0.00 7.21 v _4316_/D (sky130_fd_sc_hd__or4_1) |
| 0.12 0.48 7.69 v _4316_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _1783_ (net) |
| 0.12 0.00 7.69 v _4317_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.43 8.12 v _4317_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1784_ (net) |
| 0.08 0.00 8.12 v _4318_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 8.55 v _4318_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1785_ (net) |
| 0.09 0.00 8.55 v _4319_/D (sky130_fd_sc_hd__or4_1) |
| 0.07 0.41 8.96 v _4319_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1786_ (net) |
| 0.07 0.00 8.96 v _4320_/D (sky130_fd_sc_hd__or4_1) |
| 0.11 0.46 9.43 v _4320_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _1787_ (net) |
| 0.11 0.00 9.43 v _4321_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.42 9.85 v _4321_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1788_ (net) |
| 0.08 0.00 9.85 v _4322_/D (sky130_fd_sc_hd__or4_1) |
| 0.10 0.46 10.31 v _4322_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _1789_ (net) |
| 0.10 0.00 10.31 v _4325_/B (sky130_fd_sc_hd__or3_1) |
| 0.09 0.41 10.72 v _4325_/X (sky130_fd_sc_hd__or3_1) |
| 1 0.01 _1792_ (net) |
| 0.09 0.00 10.72 v _4327_/B1 (sky130_fd_sc_hd__o211a_1) |
| 0.04 0.14 10.86 v _4327_/X (sky130_fd_sc_hd__o211a_1) |
| 1 0.00 _0142_ (net) |
| 0.04 0.00 10.86 v _4820_/D (sky130_fd_sc_hd__dfxtp_1) |
| 10.86 data arrival time |
| |
| 0.15 20.00 20.00 clock clock (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| 19.75 ^ _4820_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.08 19.67 library setup time |
| 19.67 data required time |
| ----------------------------------------------------------------------------- |
| 19.67 data required time |
| -10.86 data arrival time |
| ----------------------------------------------------------------------------- |
| 8.80 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: io_ibus_addr[2] (input port clocked by clock) |
| Endpoint: _4801_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 4.00 4.00 v input external delay |
| 0.01 0.00 4.00 v io_ibus_addr[2] (in) |
| 1 0.00 io_ibus_addr[2] (net) |
| 0.01 0.00 4.00 v input93/A (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 0.08 0.16 4.17 v input93/X (sky130_fd_sc_hd__dlymetal6s2s_1) |
| 4 0.01 net93 (net) |
| 0.08 0.00 4.17 v _2761_/A (sky130_fd_sc_hd__buf_2) |
| 0.08 0.19 4.36 v _2761_/X (sky130_fd_sc_hd__buf_2) |
| 5 0.03 _0355_ (net) |
| 0.08 0.00 4.36 v _2953_/A (sky130_fd_sc_hd__xor2_4) |
| 0.08 0.22 4.58 v _2953_/X (sky130_fd_sc_hd__xor2_4) |
| 3 0.02 _0547_ (net) |
| 0.08 0.00 4.58 v _2954_/C (sky130_fd_sc_hd__and3_1) |
| 0.06 0.22 4.80 v _2954_/X (sky130_fd_sc_hd__and3_1) |
| 3 0.01 _0548_ (net) |
| 0.06 0.00 4.80 v _3837_/A (sky130_fd_sc_hd__or4_1) |
| 0.08 0.53 5.34 v _3837_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1323_ (net) |
| 0.08 0.00 5.34 v _3843_/B (sky130_fd_sc_hd__or4_1) |
| 0.11 0.58 5.91 v _3843_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _1329_ (net) |
| 0.11 0.00 5.91 v _3844_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 6.36 v _3844_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1330_ (net) |
| 0.09 0.00 6.36 v _3845_/D (sky130_fd_sc_hd__or4_1) |
| 0.10 0.45 6.80 v _3845_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1331_ (net) |
| 0.10 0.00 6.80 v _3846_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.42 7.22 v _3846_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1332_ (net) |
| 0.08 0.00 7.22 v _3847_/D (sky130_fd_sc_hd__or4_1) |
| 0.11 0.47 7.69 v _3847_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.01 _1333_ (net) |
| 0.11 0.00 7.69 v _3848_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.43 8.12 v _3848_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1334_ (net) |
| 0.08 0.00 8.12 v _3849_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.43 8.55 v _3849_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1335_ (net) |
| 0.09 0.00 8.55 v _3850_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 8.99 v _3850_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1336_ (net) |
| 0.09 0.00 8.99 v _3851_/D (sky130_fd_sc_hd__or4_1) |
| 0.08 0.41 9.40 v _3851_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1337_ (net) |
| 0.08 0.00 9.40 v _3852_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 9.84 v _3852_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1338_ (net) |
| 0.09 0.00 9.84 v _3854_/C (sky130_fd_sc_hd__or4_1) |
| 0.08 0.50 10.34 v _3854_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1340_ (net) |
| 0.08 0.00 10.34 v _3855_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 10.78 v _3855_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1341_ (net) |
| 0.09 0.00 10.78 v _3857_/C (sky130_fd_sc_hd__or4_1) |
| 0.08 0.50 11.28 v _3857_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1343_ (net) |
| 0.08 0.00 11.28 v _3858_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.44 11.72 v _3858_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1344_ (net) |
| 0.09 0.00 11.72 v _3862_/C (sky130_fd_sc_hd__or4_1) |
| 0.08 0.49 12.21 v _3862_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1348_ (net) |
| 0.08 0.00 12.21 v _3863_/D (sky130_fd_sc_hd__or4_1) |
| 0.09 0.43 12.64 v _3863_/X (sky130_fd_sc_hd__or4_1) |
| 1 0.00 _1349_ (net) |
| 0.09 0.00 12.64 v _3868_/A2 (sky130_fd_sc_hd__o211a_1) |
| 0.04 0.23 12.87 v _3868_/X (sky130_fd_sc_hd__o211a_1) |
| 1 0.00 _0123_ (net) |
| 0.04 0.00 12.87 v _4801_/D (sky130_fd_sc_hd__dfxtp_1) |
| 12.87 data arrival time |
| |
| 0.15 20.00 20.00 clock clock (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| 19.75 ^ _4801_/CLK (sky130_fd_sc_hd__dfxtp_1) |
| -0.08 19.67 library setup time |
| 19.67 data required time |
| ----------------------------------------------------------------------------- |
| 19.67 data required time |
| -12.87 data arrival time |
| ----------------------------------------------------------------------------- |
| 6.80 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| |
| =========================================================================== |
| max slew violation count 0 |
| max fanout violation count 0 |
| max cap violation count 0 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 6.80 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 0.20 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock clock |
| Latency CRPR Skew |
| _4684_/CLK ^ |
| 1.52 |
| _4684_/CLK ^ |
| 1.37 0.00 0.14 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power |
| ---------------------------------------------------------------- |
| Sequential 5.08e-04 3.12e-05 1.99e-09 5.39e-04 42.2% |
| Combinational 2.25e-04 5.12e-04 1.37e-08 7.38e-04 57.8% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 7.33e-04 5.43e-04 1.57e-08 1.28e-03 100.0% |
| 57.4% 42.6% 0.0% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 51793 u^2 4% utilization. |
| area_report_end |
