| CVC: Circuit Validation Check Version 1.1.0 |
| CVC: Log output to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/reports/finishing/WB_InterConnect.rpt |
| CVC: Error output to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/reports/finishing/WB_InterConnect.rpt.error.gz |
| CVC: Debug output to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/reports/finishing/WB_InterConnect.rpt.debug.gz |
| CVC: Start: Tue Mar 22 00:15:29 2022 |
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| Using the following parameters for CVC (Circuit Validation Check) from /openlane/scripts/cvc/sky130A/cvcrc.sky130A |
| CVC_TOP = 'WB_InterConnect' |
| CVC_NETLIST = '/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/finishing/WB_InterConnect.cdl' |
| CVC_MODE = 'WB_InterConnect' |
| CVC_MODEL_FILE = '/openlane/scripts/cvc/sky130A/cvc.sky130A.models' |
| CVC_POWER_FILE = '/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/finishing/WB_InterConnect.power' |
| CVC_FUSE_FILE = '' |
| CVC_REPORT_FILE = '/home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/reports/finishing/WB_InterConnect.rpt' |
| CVC_REPORT_TITLE = 'CVC $CVC_TOP' |
| CVC_CIRCUIT_ERROR_LIMIT = '100' |
| CVC_SEARCH_LIMIT = '100' |
| CVC_LEAK_LIMIT = '0.0002' |
| CVC_SOI = 'false' |
| CVC_SCRC = 'false' |
| CVC_VTH_GATES = 'false' |
| CVC_MIN_VTH_GATES = 'false' |
| CVC_IGNORE_VTH_FLOATING = 'false' |
| CVC_IGNORE_NO_LEAK_FLOATING = 'false' |
| CVC_LEAK_OVERVOLTAGE = 'true' |
| CVC_LOGIC_DIODES = 'false' |
| CVC_ANALOG_GATES = 'true' |
| CVC_BACKUP_RESULTS = 'false' |
| CVC_MOS_DIODE_ERROR_THRESHOLD = '0' |
| CVC_SHORT_ERROR_THRESHOLD = '0' |
| CVC_BIAS_ERROR_THRESHOLD = '0' |
| CVC_FORWARD_ERROR_THRESHOLD = '0' |
| CVC_FLOATING_ERROR_THRESHOLD = '0' |
| CVC_GATE_ERROR_THRESHOLD = '0' |
| CVC_LEAK?_ERROR_THRESHOLD = '0' |
| CVC_EXPECTED_ERROR_THRESHOLD = '0' |
| CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0' |
| CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0' |
| CVC_CELL_ERROR_LIMIT_FILE = '' |
| CVC_CELL_CHECKSUM_FILE = '' |
| CVC_LARGE_CIRCUIT_SIZE = '10000000' |
| CVC_NET_CHECK_FILE = '' |
| CVC_MODEL_CHECK_FILE = '' |
| End of parameters |
| |
| CVC: Reading device model settings... |
| CVC: Reading power settings... |
| CVC: Parsing netlist /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/finishing/WB_InterConnect.cdl |
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| Cdl fixed data size 1934446 |
| Usage CDL: Time: 0 Memory: 66696 I/O: 8 Swap: 0 |
| CVC: Counting and linking... |
| CVC: Assigning IDs ... |
| Usage DB: Time: 0 Memory: 75208 I/O: 8 Swap: 0 |
| CVC: 123498(123498) instances, 13126(13126) nets, 190352(190352) devices. |
| Setting power for mode... |
| Setting models... |
| CVC: Setting models ... |
| Setting model tolerances... |
| CVC: Shorting switches... |
| model short... |
| Shorted 0 short |
| Setting instance power... |
| CVC: Linking devices... |
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| Usage EQUIV: Time: 0 Memory: 86140 I/O: 48 Swap: 0 |
| Power nets 216 |
| CVC: Shorting non conducting resistors... |
| CVC: Calculating resistor voltages... |
| Usage RES: Time: 0 Memory: 86140 I/O: 56 Swap: 0 |
| Power nets 216 |
| CVC: Calculating min/max voltages... |
| Processing trivial nets found 5176 trivial nets |
| CVC: Ignoring invalid calculations... |
| CVC: Removed 0 calculations |
| Copying master nets |
| CVC: Ignoring non-conducting devices... |
| CVC: Ignored 0 devices |
| Usage MIN/MAX1: Time: 0 Memory: 86464 I/O: 56 Swap: 0 |
| Power nets 4169 |
| ! Checking forward bias diode errors: |
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| ! Checking nmos source/drain vs bias errors: |
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| ! Checking nmos gate vs source errors: |
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| ! Checking pmos source/drain vs bias errors: |
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| ! Checking pmos gate vs source errors: |
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| Usage ERROR: Time: 1 Memory: 86464 I/O: 56 Swap: 0 |
| Saving min/max voltages... |
| CVC: Propagating Simulation voltages 1... |
| Usage SIM1: Time: 1 Memory: 87256 I/O: 56 Swap: 0 |
| Power nets 4169 |
| Saving simulation voltages... |
| CVC: Propagating Simulation voltages 3... |
| Usage SIM2: Time: 1 Memory: 87520 I/O: 56 Swap: 0 |
| Power nets 4169 |
| Added 0 latch voltages |
| CVC: Calculating min/max voltages... |
| Processing trivial nets found 5176 trivial nets |
| CVC: Ignoring invalid calculations... |
| CVC: Removed 0 calculations |
| Copying master nets |
| CVC: Ignoring non-conducting devices... |
| CVC: Ignored 0 devices |
| Usage MIN/MAX2: Time: 1 Memory: 87784 I/O: 56 Swap: 0 |
| Power nets 8122 |
| ! Checking overvoltage errors |
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| ! Checking nmos possible leak errors: |
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| ! Checking pmos possible leak errors: |
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| ! Checking mos floating input errors: |
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| ! Checking expected values: |
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| CVC: Error Counts |
| CVC: Fuse Problems: 0 |
| CVC: Min Voltage Conflicts: 0 |
| CVC: Max Voltage Conflicts: 0 |
| CVC: Leaks: 0 |
| CVC: LDD drain->source: 0 |
| CVC: HI-Z Inputs: 0 |
| CVC: Forward Bias Diodes: 0 |
| CVC: NMOS Source vs Bulk: 0 |
| CVC: NMOS Gate vs Source: 0 |
| CVC: NMOS Possible Leaks: 0 |
| CVC: PMOS Source vs Bulk: 0 |
| CVC: PMOS Gate vs Source: 0 |
| CVC: PMOS Possible Leaks: 0 |
| CVC: Overvoltage-VBG: 0 |
| CVC: Overvoltage-VBS: 0 |
| CVC: Overvoltage-VDS: 0 |
| CVC: Overvoltage-VGS: 0 |
| CVC: Model errors: 0 |
| CVC: Unexpected voltage : 0 |
| CVC: Total: 0 |
| Usage Total: Time: 1 Memory: 88312 I/O: 96 Swap: 0 |
| Virtual net update/access 113111/10759649 |
| CVC: Log output to /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/reports/finishing/WB_InterConnect.rpt |
| CVC: End: Tue Mar 22 00:15:30 2022 |
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