abc/Wishbone_InterConnect/runs/Wishbone_InterConnect/logs/cts/11-cts.log

OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/merged_unpadded.lef
[INFO ODB-0223]     Created 13 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0225]     Created 441 library cells
[INFO ODB-0226] Finished LEF file:  /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/tmp/merged_unpadded.lef
[INFO ODB-0127] Reading DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/placement/WB_InterConnect.def
[INFO ODB-0128] Design: WB_InterConnect
[INFO ODB-0130]     Created 430 pins.
[INFO ODB-0131]     Created 20657 components and 59411 component-terminals.
[INFO ODB-0132]     Created 2 special nets and 49196 connections.
[INFO ODB-0133]     Created 3353 nets and 10215 connections.
[INFO ODB-0134] Finished DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Wishbone_InterConnect/runs/Wishbone_InterConnect/results/placement/WB_InterConnect.def
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# Created by write_sdc
# Mon Mar 21 23:56:03 2022
###############################################################################
current_design WB_InterConnect
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# Timing Constraints
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create_clock -name clock -period 20.0000 [get_ports {clock}]
set_clock_transition 0.1500 [get_clocks {clock}]
set_clock_uncertainty 0.2500 clock
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[0]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[10]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[11]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[12]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[13]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[14]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[15]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[16]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[17]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[18]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[19]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[1]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[20]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[21]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[22]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[23]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[24]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[25]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[26]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[27]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[28]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[29]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[2]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[30]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[31]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[3]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[4]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[5]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[6]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[7]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[8]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[9]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_ld_type[0]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_ld_type[1]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_ld_type[2]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rd_en}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_st_type[0]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_st_type[1]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[0]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[10]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[11]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[12]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[13]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[14]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[15]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[16]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[17]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[18]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[19]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[1]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[20]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[21]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[22]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[23]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[24]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[25]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[26]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[27]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[28]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[29]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[2]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[30]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[31]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[3]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[4]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[5]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[6]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[7]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[8]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[9]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wr_en}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[0]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[10]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[11]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[12]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[13]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[14]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[15]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[16]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[17]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[18]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[19]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[1]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[20]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[21]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[22]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[23]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[24]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[25]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[26]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[27]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[28]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[29]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[2]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[30]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[31]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[3]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[4]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[5]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[6]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[7]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[8]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_rdata[9]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[0]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[10]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[11]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[12]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[13]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[14]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[15]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[16]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[17]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[18]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[19]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[1]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[20]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[21]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[22]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[23]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[24]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[25]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[26]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[27]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[28]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[29]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[2]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[30]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[31]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[3]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[4]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[5]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[6]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[7]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[8]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[9]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[0]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[10]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[11]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[12]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[13]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[14]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[15]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[16]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[17]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[18]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[19]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[1]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[20]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[21]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[22]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[23]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[24]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[25]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[26]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[27]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[28]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[29]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[2]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[30]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[31]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[3]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[4]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[5]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[6]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[7]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[8]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_rdata[9]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_ack_i}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[0]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[10]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[11]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[12]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[13]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[14]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[15]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[16]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[17]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[18]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[19]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[1]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[20]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[21]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[22]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[23]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[24]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[25]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[26]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[27]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[28]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[29]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[2]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[30]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[31]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[3]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[4]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[5]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[6]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[7]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[8]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_data_i[9]}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_miso}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_uart_rx}]
set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {reset}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[0]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[10]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[11]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[12]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[13]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[14]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[15]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[16]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[17]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[18]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[19]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[1]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[20]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[21]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[22]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[23]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[24]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[25]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[26]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[27]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[28]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[29]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[2]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[30]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[31]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[3]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[4]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[5]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[6]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[7]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[8]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[9]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_valid}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[0]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[1]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[2]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[3]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[4]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[5]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[6]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_addr[7]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_cs}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_st_type[0]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_st_type[1]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_st_type[2]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_st_type[3]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[0]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[10]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[11]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[12]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[13]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[14]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[15]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[16]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[17]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[18]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[19]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[1]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[20]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[21]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[22]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[23]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[24]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[25]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[26]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[27]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[28]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[29]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[2]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[30]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[31]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[3]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[4]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[5]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[6]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[7]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[8]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wdata[9]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dmem_io_wr_en}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[0]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[10]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[11]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[12]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[13]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[14]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[15]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[16]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[17]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[18]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[19]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[1]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[20]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[21]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[22]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[23]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[24]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[25]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[26]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[27]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[28]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[29]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[2]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[30]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[31]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[3]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[4]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[5]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[6]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[7]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[8]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[9]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_valid}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[0]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[1]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[2]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[3]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[4]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[5]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[6]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[7]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_addr[8]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_cs}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_st_type[0]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_st_type[1]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_st_type[2]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_st_type[3]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[0]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[10]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[11]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[12]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[13]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[14]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[15]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[16]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[17]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[18]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[19]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[1]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[20]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[21]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[22]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[23]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[24]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[25]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[26]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[27]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[28]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[29]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[2]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[30]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[31]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[3]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[4]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[5]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[6]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[7]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[8]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wdata[9]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_imem_io_wr_en}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_motor_addr_sel}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_clk}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_clk_en}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_cs}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_cs_en}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_irq}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_mosi}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_spi_mosi_en}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_uart_irq}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_uart_tx}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_uart_txen}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[0]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[10]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[11]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[12]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[13]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[14]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[15]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[1]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[2]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[3]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[4]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[5]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[6]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[7]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[8]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_addr[9]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[0]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[10]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[11]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[12]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[13]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[14]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[15]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[16]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[17]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[18]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[19]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[1]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[20]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[21]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[22]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[23]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[24]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[25]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[26]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[27]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[28]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[29]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[2]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[30]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[31]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[3]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[4]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[5]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[6]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[7]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[8]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_data[9]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_sel[0]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_sel[1]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_sel[2]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_sel[3]}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_stb}]
set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_wbm_m2s_we}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {io_dbus_valid}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_cs}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wr_en}]
set_load -pin_load 0.0334 [get_ports {io_ibus_valid}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_cs}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wr_en}]
set_load -pin_load 0.0334 [get_ports {io_motor_addr_sel}]
set_load -pin_load 0.0334 [get_ports {io_spi_clk}]
set_load -pin_load 0.0334 [get_ports {io_spi_clk_en}]
set_load -pin_load 0.0334 [get_ports {io_spi_cs}]
set_load -pin_load 0.0334 [get_ports {io_spi_cs_en}]
set_load -pin_load 0.0334 [get_ports {io_spi_irq}]
set_load -pin_load 0.0334 [get_ports {io_spi_mosi}]
set_load -pin_load 0.0334 [get_ports {io_spi_mosi_en}]
set_load -pin_load 0.0334 [get_ports {io_uart_irq}]
set_load -pin_load 0.0334 [get_ports {io_uart_tx}]
set_load -pin_load 0.0334 [get_ports {io_uart_txen}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_stb}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_we}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[31]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[30]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[29]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[28]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[27]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[26]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[25]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[24]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[23]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[22]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[21]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[20]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[19]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[18]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[17]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[16]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[15]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[14]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[13]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[12]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[11]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[10]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[9]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[8]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[7]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[6]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[5]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[4]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[3]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[2]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[1]}]
set_load -pin_load 0.0334 [get_ports {io_dbus_rdata[0]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[7]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[6]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[5]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[4]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[3]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[2]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[1]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_addr[0]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_st_type[3]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_st_type[2]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_st_type[1]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_st_type[0]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[31]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[30]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[29]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[28]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[27]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[26]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[25]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[24]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[23]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[22]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[21]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[20]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[19]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[18]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[17]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[16]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[15]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[14]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[13]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[12]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[11]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[10]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[9]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[8]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[7]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[6]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[5]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[4]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[3]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[2]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[1]}]
set_load -pin_load 0.0334 [get_ports {io_dmem_io_wdata[0]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[31]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[30]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[29]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[28]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[27]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[26]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[25]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[24]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[23]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[22]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[21]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[20]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[19]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[18]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[17]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[16]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[15]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[14]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[13]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[12]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[11]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[10]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[9]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[8]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[7]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[6]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[5]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[4]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[3]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[2]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[1]}]
set_load -pin_load 0.0334 [get_ports {io_ibus_inst[0]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[8]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[7]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[6]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[5]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[4]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[3]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[2]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[1]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_addr[0]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_st_type[3]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_st_type[2]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_st_type[1]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_st_type[0]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[31]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[30]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[29]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[28]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[27]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[26]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[25]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[24]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[23]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[22]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[21]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[20]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[19]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[18]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[17]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[16]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[15]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[14]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[13]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[12]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[11]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[10]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[9]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[8]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[7]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[6]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[5]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[4]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[3]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[2]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[1]}]
set_load -pin_load 0.0334 [get_ports {io_imem_io_wdata[0]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[15]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[14]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[13]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[12]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[11]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[10]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[9]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[8]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[7]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[6]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[5]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[4]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[3]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[2]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[1]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_addr[0]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[31]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[30]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[29]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[28]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[27]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[26]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[25]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[24]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[23]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[22]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[21]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[20]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[19]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[18]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[17]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[16]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[15]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[14]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[13]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[12]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[11]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[10]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[9]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[8]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[7]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[6]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[5]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[4]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[3]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[2]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[1]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_data[0]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_sel[3]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_sel[2]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_sel[1]}]
set_load -pin_load 0.0334 [get_ports {io_wbm_m2s_sel[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clock}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rd_en}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wr_en}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_ack_i}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_spi_miso}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_uart_rx}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reset}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_ld_type[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_ld_type[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_ld_type[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_st_type[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_st_type[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_wdata[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dmem_io_rdata[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_addr[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_imem_io_rdata[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[31]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[30]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[29]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[28]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[27]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[26]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_motor_data_i[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 5.0000 [current_design]
[INFO]: Setting RC values...
[INFO]: Configuring cts characterization...
[INFO]: Performing clock tree synthesis...
[INFO]: Looking for the following net(s): 
[INFO]: Running Clock Tree Synthesis...
[INFO CTS-0038] Number of created patterns = 50000.
[INFO CTS-0038] Number of created patterns = 100000.
[INFO CTS-0039] Number of created patterns = 137808.
[INFO CTS-0084] Compiling LUT.
Min. len    Max. len    Min. cap    Max. cap    Min. slew   Max. slew
2           8           1           36          1           150         
[WARNING CTS-0043] 4752 wires are pure wire and no slew degradation.
TritonCTS forced slew degradation on these wires.
[INFO CTS-0046]     Number of wire segments: 136611.
[INFO CTS-0047]     Number of keys in characterization LUT: 1923.
[INFO CTS-0048]     Actual min input cap: 1.
[INFO CTS-0007] Net "clock" found for clock "clock".
[INFO CTS-0010]  Clock net "clock" has 236 sinks.
[INFO CTS-0008] TritonCTS found 1 clock nets.
[INFO CTS-0097] Characterization used 3 buffer(s) types.
[INFO CTS-0027] Generating H-Tree topology for net clock.
[INFO CTS-0028]  Total number of sinks: 236.
[INFO CTS-0029]  Sinks will be clustered in groups of up to 25 and with maximum cluster diameter of 50.0 um.
[INFO CTS-0030]  Number of static layers: 0.
[INFO CTS-0020]  Wire segment unit: 13000  dbu (13 um).
[INFO CTS-0019]  Total number of sinks after clustering: 21.
[INFO CTS-0024]  Normalized sink region: [(0.573269, 39.2613), (13.8694, 59.1084)].
[INFO CTS-0025]     Width:  13.2961.
[INFO CTS-0026]     Height: 19.8470.
 Level 1
    Direction: Vertical
    Sinks per sub-region: 11
    Sub-region size: 13.2961 X 9.9235
[INFO CTS-0034]     Segment length (rounded): 4.
    Key: 162 outSlew: 7 load: 1 length: 4 isBuffered: true
 Out of 21 sinks, 4 sinks closer to other cluster.
[INFO CTS-0032]  Stop criterion found. Max number of sinks is 15.
[INFO CTS-0035]  Number of sinks covered: 21.
[INFO CTS-0036]  Average source sink dist: 24557.60 dbu.
[INFO CTS-0037]  Number of outlier sinks: 3.
[INFO CTS-0018]     Created 25 clock buffers.
[INFO CTS-0012]     Minimum number of buffers in the clock path: 2.
[INFO CTS-0013]     Maximum number of buffers in the clock path: 4.
[INFO CTS-0015]     Created 25 clock nets.
[INFO CTS-0016]     Fanout distribution for the current clock = 3:1, 6:1, 7:2, 8:2, 9:1, 11:2, 12:1, 13:4, 14:3, 16:1, 19:1, 20:1, 24:1..
[INFO CTS-0017]     Max level of the clock tree: 1.
[INFO CTS-0098] Clock net "clock"
[INFO CTS-0099]  Sinks 236
[INFO CTS-0100]  Leaf buffers 19
[INFO CTS-0101]  Average sink wire length 866.83 um
[INFO CTS-0102]  Path depth 2 - 4
[INFO]: Repairing long wires on clock nets...
[INFO RSZ-0058] Using max wire length 2319um.
[INFO]: Legalizing...
Placement Analysis
---------------------------------
total displacement        418.9 u
average displacement        0.0 u
max displacement           10.1 u
original HPWL          334171.2 u
legalized HPWL         336863.8 u
delta HPWL                    1 %

[INFO DPL-0020] Mirrored 1371 instances
[INFO DPL-0021] HPWL before          336863.8 u
[INFO DPL-0022] HPWL after           334352.2 u
[INFO DPL-0023] HPWL delta               -0.7 %
cts_report
[INFO CTS-0003] Total number of Clock Roots: 1.
[INFO CTS-0004] Total number of Buffers Inserted: 25.
[INFO CTS-0005] Total number of Clock Subnets: 25.
[INFO CTS-0006] Total number of Sinks: 236.
cts_report_end
min_report

===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: _4743_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: _4742_ (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock source latency
                  0.50    0.35    0.35 ^ clock (in)
     1    0.11                           clock (net)
                  0.51    0.00    0.35 ^ clkbuf_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.23    0.58 ^ clkbuf_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     2    0.02                           clknet_0_clock (net)
                  0.05    0.00    0.58 ^ clkbuf_1_1_0_clock/A (sky130_fd_sc_hd__clkbuf_2)
                  0.65    0.50    1.08 ^ clkbuf_1_1_0_clock/X (sky130_fd_sc_hd__clkbuf_2)
     8    0.12                           clknet_1_1_0_clock (net)
                  0.65    0.00    1.08 ^ clkbuf_leaf_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.06    0.26    1.34 ^ clkbuf_leaf_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     7    0.02                           clknet_leaf_0_clock (net)
                  0.06    0.00    1.34 ^ _4743_/CLK (sky130_fd_sc_hd__dfxtp_1)
                  0.06    0.30    1.64 ^ _4743_/Q (sky130_fd_sc_hd__dfxtp_1)
     2    0.01                           uart.txm._T_66[3] (net)
                  0.06    0.00    1.64 ^ _2453_/A0 (sky130_fd_sc_hd__mux2_1)
                  0.04    0.12    1.76 ^ _2453_/X (sky130_fd_sc_hd__mux2_1)
     1    0.00                           _2165_ (net)
                  0.04    0.00    1.76 ^ _2454_/A (sky130_fd_sc_hd__clkbuf_1)
                  0.04    0.07    1.83 ^ _2454_/X (sky130_fd_sc_hd__clkbuf_1)
     1    0.00                           _0009_ (net)
                  0.04    0.00    1.83 ^ _4742_/D (sky130_fd_sc_hd__dfxtp_1)
                                  1.83   data arrival time

                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock source latency
                  0.50    0.39    0.39 ^ clock (in)
     1    0.11                           clock (net)
                  0.51    0.00    0.39 ^ clkbuf_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.25    0.64 ^ clkbuf_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     2    0.02                           clknet_0_clock (net)
                  0.05    0.00    0.64 ^ clkbuf_1_0_0_clock/A (sky130_fd_sc_hd__clkbuf_2)
                  0.91    0.73    1.37 ^ clkbuf_1_0_0_clock/X (sky130_fd_sc_hd__clkbuf_2)
    13    0.17                           clknet_1_0_0_clock (net)
                  0.91    0.00    1.37 ^ clkbuf_leaf_17_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.08    0.33    1.70 ^ clkbuf_leaf_17_clock/X (sky130_fd_sc_hd__clkbuf_16)
    13    0.04                           clknet_leaf_17_clock (net)
                  0.08    0.00    1.70 ^ _4742_/CLK (sky130_fd_sc_hd__dfxtp_1)
                          0.25    1.95   clock uncertainty
                         -0.06    1.89   clock reconvergence pessimism
                         -0.03    1.87   library hold time
                                  1.87   data required time
-----------------------------------------------------------------------------
                                  1.87   data required time
                                 -1.83   data arrival time
-----------------------------------------------------------------------------
                                 -0.04   slack (VIOLATED)


Startpoint: _4827_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: _4828_ (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock source latency
                  0.50    0.35    0.35 ^ clock (in)
     1    0.11                           clock (net)
                  0.51    0.00    0.35 ^ clkbuf_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.23    0.58 ^ clkbuf_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     2    0.02                           clknet_0_clock (net)
                  0.05    0.00    0.58 ^ clkbuf_1_1_0_clock/A (sky130_fd_sc_hd__clkbuf_2)
                  0.65    0.50    1.08 ^ clkbuf_1_1_0_clock/X (sky130_fd_sc_hd__clkbuf_2)
     8    0.12                           clknet_1_1_0_clock (net)
                  0.65    0.00    1.08 ^ _4827_/CLK (sky130_fd_sc_hd__dfxtp_1)
                  0.06    0.44    1.52 v _4827_/Q (sky130_fd_sc_hd__dfxtp_1)
     5    0.01                           spi.clock_cnt[0] (net)
                  0.06    0.00    1.52 v _4384_/A (sky130_fd_sc_hd__nand2_1)
                  0.09    0.09    1.62 ^ _4384_/Y (sky130_fd_sc_hd__nand2_1)
     3    0.01                           _1845_ (net)
                  0.09    0.00    1.62 ^ _4392_/A (sky130_fd_sc_hd__and3_1)
                  0.05    0.14    1.76 ^ _4392_/X (sky130_fd_sc_hd__and3_1)
     1    0.00                           _1852_ (net)
                  0.05    0.00    1.76 ^ _4393_/A (sky130_fd_sc_hd__clkbuf_1)
                  0.04    0.07    1.83 ^ _4393_/X (sky130_fd_sc_hd__clkbuf_1)
     1    0.00                           _0149_ (net)
                  0.04    0.00    1.83 ^ _4828_/D (sky130_fd_sc_hd__dfxtp_1)
                                  1.83   data arrival time

                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock source latency
                  0.50    0.39    0.39 ^ clock (in)
     1    0.11                           clock (net)
                  0.51    0.00    0.39 ^ clkbuf_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.25    0.64 ^ clkbuf_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     2    0.02                           clknet_0_clock (net)
                  0.05    0.00    0.64 ^ clkbuf_1_0_0_clock/A (sky130_fd_sc_hd__clkbuf_2)
                  0.91    0.73    1.37 ^ clkbuf_1_0_0_clock/X (sky130_fd_sc_hd__clkbuf_2)
    13    0.17                           clknet_1_0_0_clock (net)
                  0.91    0.00    1.37 ^ clkbuf_leaf_7_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.08    0.32    1.69 ^ clkbuf_leaf_7_clock/X (sky130_fd_sc_hd__clkbuf_16)
    12    0.04                           clknet_leaf_7_clock (net)
                  0.08    0.00    1.69 ^ _4828_/CLK (sky130_fd_sc_hd__dfxtp_1)
                          0.25    1.94   clock uncertainty
                         -0.06    1.88   clock reconvergence pessimism
                         -0.03    1.86   library hold time
                                  1.86   data required time
-----------------------------------------------------------------------------
                                  1.86   data required time
                                 -1.83   data arrival time
-----------------------------------------------------------------------------
                                 -0.02   slack (VIOLATED)


Startpoint: _4861_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: _4862_ (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock source latency
                  0.50    0.35    0.35 ^ clock (in)
     1    0.11                           clock (net)
                  0.51    0.00    0.35 ^ clkbuf_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.23    0.58 ^ clkbuf_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     2    0.02                           clknet_0_clock (net)
                  0.05    0.00    0.58 ^ clkbuf_1_1_0_clock/A (sky130_fd_sc_hd__clkbuf_2)
                  0.65    0.50    1.08 ^ clkbuf_1_1_0_clock/X (sky130_fd_sc_hd__clkbuf_2)
     8    0.12                           clknet_1_1_0_clock (net)
                  0.65    0.00    1.08 ^ clkbuf_leaf_1_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.24    1.32 ^ clkbuf_leaf_1_clock/X (sky130_fd_sc_hd__clkbuf_16)
     3    0.01                           clknet_leaf_1_clock (net)
                  0.05    0.00    1.32 ^ _4861_/CLK (sky130_fd_sc_hd__dfxtp_1)
                  0.05    0.29    1.62 ^ _4861_/Q (sky130_fd_sc_hd__dfxtp_1)
     2    0.00                           spi._GEN_44[6] (net)
                  0.05    0.00    1.62 ^ _4528_/A (sky130_fd_sc_hd__or3b_1)
                  0.05    0.10    1.72 ^ _4528_/X (sky130_fd_sc_hd__or3b_1)
     1    0.00                           _1954_ (net)
                  0.05    0.00    1.72 ^ _4529_/B1 (sky130_fd_sc_hd__o211a_1)
                  0.05    0.14    1.86 ^ _4529_/X (sky130_fd_sc_hd__o211a_1)
     1    0.00                           _1955_ (net)
                  0.05    0.00    1.86 ^ _4530_/B1 (sky130_fd_sc_hd__o21a_1)
                  0.04    0.10    1.96 ^ _4530_/X (sky130_fd_sc_hd__o21a_1)
     1    0.00                           _0183_ (net)
                  0.04    0.00    1.96 ^ _4862_/D (sky130_fd_sc_hd__dfxtp_1)
                                  1.96   data arrival time

                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock source latency
                  0.50    0.39    0.39 ^ clock (in)
     1    0.11                           clock (net)
                  0.51    0.00    0.39 ^ clkbuf_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.25    0.64 ^ clkbuf_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     2    0.02                           clknet_0_clock (net)
                  0.05    0.00    0.64 ^ clkbuf_1_0_0_clock/A (sky130_fd_sc_hd__clkbuf_2)
                  0.91    0.73    1.37 ^ clkbuf_1_0_0_clock/X (sky130_fd_sc_hd__clkbuf_2)
    13    0.17                           clknet_1_0_0_clock (net)
                  0.91    0.00    1.37 ^ clkbuf_leaf_16_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.10    0.34    1.71 ^ clkbuf_leaf_16_clock/X (sky130_fd_sc_hd__clkbuf_16)
    19    0.06                           clknet_leaf_16_clock (net)
                  0.10    0.00    1.72 ^ _4862_/CLK (sky130_fd_sc_hd__dfxtp_1)
                          0.25    1.97   clock uncertainty
                         -0.06    1.90   clock reconvergence pessimism
                         -0.02    1.88   library hold time
                                  1.88   data required time
-----------------------------------------------------------------------------
                                  1.88   data required time
                                 -1.96   data arrival time
-----------------------------------------------------------------------------
                                  0.08   slack (MET)


Startpoint: _4827_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: _4891_ (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock source latency
                  0.50    0.35    0.35 ^ clock (in)
     1    0.11                           clock (net)
                  0.51    0.00    0.35 ^ clkbuf_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.23    0.58 ^ clkbuf_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     2    0.02                           clknet_0_clock (net)
                  0.05    0.00    0.58 ^ clkbuf_1_1_0_clock/A (sky130_fd_sc_hd__clkbuf_2)
                  0.65    0.50    1.08 ^ clkbuf_1_1_0_clock/X (sky130_fd_sc_hd__clkbuf_2)
     8    0.12                           clknet_1_1_0_clock (net)
                  0.65    0.00    1.08 ^ _4827_/CLK (sky130_fd_sc_hd__dfxtp_1)
                  0.06    0.44    1.52 v _4827_/Q (sky130_fd_sc_hd__dfxtp_1)
     5    0.01                           spi.clock_cnt[0] (net)
                  0.06    0.00    1.52 v _4384_/A (sky130_fd_sc_hd__nand2_1)
                  0.09    0.09    1.62 ^ _4384_/Y (sky130_fd_sc_hd__nand2_1)
     3    0.01                           _1845_ (net)
                  0.09    0.00    1.62 ^ _4412_/D (sky130_fd_sc_hd__nor4_1)
                  0.04    0.06    1.68 v _4412_/Y (sky130_fd_sc_hd__nor4_1)
     2    0.01                           _1868_ (net)
                  0.04    0.00    1.68 v _4413_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.09    0.17    1.85 v _4413_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     5    0.01                           _1869_ (net)
                  0.09    0.00    1.85 v _4620_/A1 (sky130_fd_sc_hd__a21oi_1)
                  0.10    0.13    1.98 ^ _4620_/Y (sky130_fd_sc_hd__a21oi_1)
     1    0.00                           _2017_ (net)
                  0.10    0.00    1.98 ^ _4621_/C (sky130_fd_sc_hd__nor3_1)
                  0.03    0.05    2.03 v _4621_/Y (sky130_fd_sc_hd__nor3_1)
     1    0.00                           _0212_ (net)
                  0.03    0.00    2.03 v _4891_/D (sky130_fd_sc_hd__dfxtp_4)
                                  2.03   data arrival time

                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock source latency
                  0.50    0.39    0.39 ^ clock (in)
     1    0.11                           clock (net)
                  0.51    0.00    0.39 ^ clkbuf_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.25    0.64 ^ clkbuf_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     2    0.02                           clknet_0_clock (net)
                  0.05    0.00    0.64 ^ clkbuf_1_0_0_clock/A (sky130_fd_sc_hd__clkbuf_2)
                  0.91    0.73    1.37 ^ clkbuf_1_0_0_clock/X (sky130_fd_sc_hd__clkbuf_2)
    13    0.17                           clknet_1_0_0_clock (net)
                  0.91    0.00    1.37 ^ clkbuf_leaf_8_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.09    0.34    1.71 ^ clkbuf_leaf_8_clock/X (sky130_fd_sc_hd__clkbuf_16)
    20    0.06                           clknet_leaf_8_clock (net)
                  0.09    0.00    1.71 ^ _4891_/CLK (sky130_fd_sc_hd__dfxtp_4)
                          0.25    1.96   clock uncertainty
                         -0.06    1.90   clock reconvergence pessimism
                         -0.03    1.87   library hold time
                                  1.87   data required time
-----------------------------------------------------------------------------
                                  1.87   data required time
                                 -2.03   data arrival time
-----------------------------------------------------------------------------
                                  0.16   slack (MET)


Startpoint: _4863_ (rising edge-triggered flip-flop clocked by clock)
Endpoint: _4890_ (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: min

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock source latency
                  0.50    0.35    0.35 ^ clock (in)
     1    0.11                           clock (net)
                  0.51    0.00    0.35 ^ clkbuf_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.23    0.58 ^ clkbuf_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     2    0.02                           clknet_0_clock (net)
                  0.05    0.00    0.58 ^ clkbuf_1_1_0_clock/A (sky130_fd_sc_hd__clkbuf_2)
                  0.65    0.50    1.08 ^ clkbuf_1_1_0_clock/X (sky130_fd_sc_hd__clkbuf_2)
     8    0.12                           clknet_1_1_0_clock (net)
                  0.65    0.00    1.08 ^ clkbuf_leaf_1_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.24    1.32 ^ clkbuf_leaf_1_clock/X (sky130_fd_sc_hd__clkbuf_16)
     3    0.01                           clknet_leaf_1_clock (net)
                  0.05    0.00    1.32 ^ _4863_/CLK (sky130_fd_sc_hd__dfxtp_1)
                  0.06    0.30    1.62 ^ _4863_/Q (sky130_fd_sc_hd__dfxtp_1)
     2    0.01                           spi._T_349 (net)
                  0.06    0.00    1.62 ^ _4616_/A1 (sky130_fd_sc_hd__mux2_1)
                  0.04    0.11    1.74 ^ _4616_/X (sky130_fd_sc_hd__mux2_1)
     1    0.00                           _2014_ (net)
                  0.04    0.00    1.74 ^ _4617_/A1 (sky130_fd_sc_hd__mux2_1)
                  0.04    0.11    1.84 ^ _4617_/X (sky130_fd_sc_hd__mux2_1)
     1    0.00                           _2015_ (net)
                  0.04    0.00    1.84 ^ _4618_/B (sky130_fd_sc_hd__and2_1)
                  0.04    0.10    1.95 ^ _4618_/X (sky130_fd_sc_hd__and2_1)
     1    0.00                           _2016_ (net)
                  0.04    0.00    1.95 ^ _4619_/A (sky130_fd_sc_hd__clkbuf_1)
                  0.04    0.07    2.02 ^ _4619_/X (sky130_fd_sc_hd__clkbuf_1)
     1    0.00                           _0211_ (net)
                  0.04    0.00    2.02 ^ _4890_/D (sky130_fd_sc_hd__dfxtp_4)
                                  2.02   data arrival time

                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock source latency
                  0.50    0.39    0.39 ^ clock (in)
     1    0.11                           clock (net)
                  0.51    0.00    0.39 ^ clkbuf_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.25    0.64 ^ clkbuf_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     2    0.02                           clknet_0_clock (net)
                  0.05    0.00    0.64 ^ clkbuf_1_0_0_clock/A (sky130_fd_sc_hd__clkbuf_2)
                  0.91    0.73    1.37 ^ clkbuf_1_0_0_clock/X (sky130_fd_sc_hd__clkbuf_2)
    13    0.17                           clknet_1_0_0_clock (net)
                  0.91    0.00    1.37 ^ clkbuf_leaf_7_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.08    0.32    1.69 ^ clkbuf_leaf_7_clock/X (sky130_fd_sc_hd__clkbuf_16)
    12    0.04                           clknet_leaf_7_clock (net)
                  0.08    0.00    1.69 ^ _4890_/CLK (sky130_fd_sc_hd__dfxtp_4)
                          0.25    1.94   clock uncertainty
                         -0.06    1.88   clock reconvergence pessimism
                         -0.03    1.85   library hold time
                                  1.85   data required time
-----------------------------------------------------------------------------
                                  1.85   data required time
                                 -2.02   data arrival time
-----------------------------------------------------------------------------
                                  0.16   slack (MET)


min_report_end
max_report

===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: io_ibus_addr[2] (input port clocked by clock)
Endpoint: _4801_ (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock network delay (propagated)
                          4.00    4.00 v input external delay
                  0.01    0.00    4.00 v io_ibus_addr[2] (in)
     1    0.00                           io_ibus_addr[2] (net)
                  0.01    0.00    4.00 v input93/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.08    0.16    4.17 v input93/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     4    0.01                           net93 (net)
                  0.08    0.00    4.17 v _2761_/A (sky130_fd_sc_hd__buf_2)
                  0.08    0.19    4.36 v _2761_/X (sky130_fd_sc_hd__buf_2)
     5    0.03                           _0355_ (net)
                  0.08    0.00    4.36 v _2953_/A (sky130_fd_sc_hd__xor2_4)
                  0.08    0.22    4.58 v _2953_/X (sky130_fd_sc_hd__xor2_4)
     3    0.02                           _0547_ (net)
                  0.08    0.00    4.58 v _2954_/C (sky130_fd_sc_hd__and3_1)
                  0.06    0.22    4.80 v _2954_/X (sky130_fd_sc_hd__and3_1)
     3    0.01                           _0548_ (net)
                  0.06    0.00    4.80 v _3837_/A (sky130_fd_sc_hd__or4_1)
                  0.08    0.53    5.34 v _3837_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1323_ (net)
                  0.08    0.00    5.34 v _3843_/B (sky130_fd_sc_hd__or4_1)
                  0.11    0.58    5.91 v _3843_/X (sky130_fd_sc_hd__or4_1)
     1    0.01                           _1329_ (net)
                  0.11    0.00    5.91 v _3844_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.44    6.36 v _3844_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1330_ (net)
                  0.09    0.00    6.36 v _3845_/D (sky130_fd_sc_hd__or4_1)
                  0.10    0.45    6.80 v _3845_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1331_ (net)
                  0.10    0.00    6.80 v _3846_/D (sky130_fd_sc_hd__or4_1)
                  0.08    0.42    7.22 v _3846_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1332_ (net)
                  0.08    0.00    7.22 v _3847_/D (sky130_fd_sc_hd__or4_1)
                  0.11    0.47    7.69 v _3847_/X (sky130_fd_sc_hd__or4_1)
     1    0.01                           _1333_ (net)
                  0.11    0.00    7.69 v _3848_/D (sky130_fd_sc_hd__or4_1)
                  0.08    0.43    8.12 v _3848_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1334_ (net)
                  0.08    0.00    8.12 v _3849_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.43    8.55 v _3849_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1335_ (net)
                  0.09    0.00    8.55 v _3850_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.44    8.99 v _3850_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1336_ (net)
                  0.09    0.00    8.99 v _3851_/D (sky130_fd_sc_hd__or4_1)
                  0.08    0.41    9.40 v _3851_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1337_ (net)
                  0.08    0.00    9.40 v _3852_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.44    9.84 v _3852_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1338_ (net)
                  0.09    0.00    9.84 v _3854_/C (sky130_fd_sc_hd__or4_1)
                  0.08    0.50   10.34 v _3854_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1340_ (net)
                  0.08    0.00   10.34 v _3855_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.44   10.78 v _3855_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1341_ (net)
                  0.09    0.00   10.78 v _3857_/C (sky130_fd_sc_hd__or4_1)
                  0.08    0.50   11.28 v _3857_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1343_ (net)
                  0.08    0.00   11.28 v _3858_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.44   11.72 v _3858_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1344_ (net)
                  0.09    0.00   11.72 v _3862_/C (sky130_fd_sc_hd__or4_1)
                  0.08    0.49   12.21 v _3862_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1348_ (net)
                  0.08    0.00   12.21 v _3863_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.43   12.64 v _3863_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1349_ (net)
                  0.09    0.00   12.64 v _3868_/A2 (sky130_fd_sc_hd__o211a_1)
                  0.04    0.23   12.87 v _3868_/X (sky130_fd_sc_hd__o211a_1)
     1    0.00                           _0123_ (net)
                  0.04    0.00   12.87 v _4801_/D (sky130_fd_sc_hd__dfxtp_1)
                                 12.87   data arrival time

                         20.00   20.00   clock clock (rise edge)
                          0.00   20.00   clock source latency
                  0.50    0.35   20.35 ^ clock (in)
     1    0.11                           clock (net)
                  0.51    0.00   20.35 ^ clkbuf_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.23   20.58 ^ clkbuf_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     2    0.02                           clknet_0_clock (net)
                  0.05    0.00   20.58 ^ clkbuf_1_1_0_clock/A (sky130_fd_sc_hd__clkbuf_2)
                  0.65    0.50   21.08 ^ clkbuf_1_1_0_clock/X (sky130_fd_sc_hd__clkbuf_2)
     8    0.12                           clknet_1_1_0_clock (net)
                  0.65    0.00   21.08 ^ clkbuf_opt_3_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.25   21.33 ^ clkbuf_opt_3_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     1    0.01                           clknet_opt_3_0_clock (net)
                  0.05    0.00   21.33 ^ clkbuf_leaf_3_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.06    0.14   21.47 ^ clkbuf_leaf_3_clock/X (sky130_fd_sc_hd__clkbuf_16)
    14    0.04                           clknet_leaf_3_clock (net)
                  0.06    0.00   21.47 ^ _4801_/CLK (sky130_fd_sc_hd__dfxtp_1)
                         -0.25   21.22   clock uncertainty
                          0.00   21.22   clock reconvergence pessimism
                         -0.10   21.11   library setup time
                                 21.11   data required time
-----------------------------------------------------------------------------
                                 21.11   data required time
                                -12.87   data arrival time
-----------------------------------------------------------------------------
                                  8.24   slack (MET)


Startpoint: io_ibus_addr[2] (input port clocked by clock)
Endpoint: io_imem_io_addr[0] (output port clocked by clock)
Path Group: clock
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock network delay (propagated)
                          4.00    4.00 ^ input external delay
                  0.02    0.01    4.01 ^ io_ibus_addr[2] (in)
     1    0.00                           io_ibus_addr[2] (net)
                  0.02    0.00    4.01 ^ input93/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.15    0.16    4.17 ^ input93/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     4    0.01                           net93 (net)
                  0.15    0.00    4.17 ^ _2307_/A (sky130_fd_sc_hd__clkbuf_2)
                  0.14    0.22    4.39 ^ _2307_/X (sky130_fd_sc_hd__clkbuf_2)
     5    0.02                           _2068_ (net)
                  0.14    0.00    4.39 ^ _2308_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.21    0.24    4.63 ^ _2308_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     5    0.02                           _2069_ (net)
                  0.21    0.00    4.63 ^ _2309_/A (sky130_fd_sc_hd__clkbuf_2)
                  0.16    0.24    4.87 ^ _2309_/X (sky130_fd_sc_hd__clkbuf_2)
     5    0.03                           _2070_ (net)
                  0.16    0.00    4.87 ^ _2310_/A (sky130_fd_sc_hd__buf_2)
                  0.14    0.22    5.10 ^ _2310_/X (sky130_fd_sc_hd__buf_2)
     5    0.03                           _2071_ (net)
                  0.14    0.00    5.10 ^ _2311_/A (sky130_fd_sc_hd__clkbuf_2)
                  0.14    0.22    5.31 ^ _2311_/X (sky130_fd_sc_hd__clkbuf_2)
     5    0.03                           _2072_ (net)
                  0.14    0.00    5.31 ^ _2312_/A (sky130_fd_sc_hd__buf_2)
                  0.18    0.25    5.56 ^ _2312_/X (sky130_fd_sc_hd__buf_2)
     5    0.04                           _2073_ (net)
                  0.18    0.00    5.56 ^ _2313_/A (sky130_fd_sc_hd__clkbuf_2)
                  0.12    0.21    5.77 ^ _2313_/X (sky130_fd_sc_hd__clkbuf_2)
     5    0.02                           _2074_ (net)
                  0.12    0.00    5.78 ^ _2314_/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.18    0.22    6.00 ^ _2314_/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     5    0.02                           _2075_ (net)
                  0.18    0.00    6.00 ^ _2315_/A (sky130_fd_sc_hd__buf_2)
                  0.16    0.25    6.25 ^ _2315_/X (sky130_fd_sc_hd__buf_2)
     5    0.03                           _2076_ (net)
                  0.16    0.00    6.25 ^ _2316_/A (sky130_fd_sc_hd__buf_4)
                  0.15    0.24    6.49 ^ _2316_/X (sky130_fd_sc_hd__buf_4)
     5    0.05                           _2077_ (net)
                  0.15    0.00    6.49 ^ _2320_/A0 (sky130_fd_sc_hd__mux2_1)
                  0.09    0.19    6.68 ^ _2320_/X (sky130_fd_sc_hd__mux2_1)
     1    0.01                           _2080_ (net)
                  0.09    0.00    6.68 ^ _2321_/A (sky130_fd_sc_hd__buf_8)
                  0.17    0.20    6.88 ^ _2321_/X (sky130_fd_sc_hd__buf_8)
     1    0.10                           net281 (net)
                  0.17    0.03    6.91 ^ output281/A (sky130_fd_sc_hd__buf_2)
                  0.18    0.26    7.17 ^ output281/X (sky130_fd_sc_hd__buf_2)
     1    0.03                           io_imem_io_addr[0] (net)
                  0.18    0.00    7.17 ^ io_imem_io_addr[0] (out)
                                  7.17   data arrival time

                         20.00   20.00   clock clock (rise edge)
                          0.00   20.00   clock network delay (propagated)
                         -0.25   19.75   clock uncertainty
                          0.00   19.75   clock reconvergence pessimism
                         -4.00   15.75   output external delay
                                 15.75   data required time
-----------------------------------------------------------------------------
                                 15.75   data required time
                                 -7.17   data arrival time
-----------------------------------------------------------------------------
                                  8.58   slack (MET)


Startpoint: io_ibus_addr[3] (input port clocked by clock)
Endpoint: io_imem_io_addr[1] (output port clocked by clock)
Path Group: clock
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock network delay (propagated)
                          4.00    4.00 ^ input external delay
                  0.02    0.01    4.01 ^ io_ibus_addr[3] (in)
     1    0.00                           io_ibus_addr[3] (net)
                  0.02    0.00    4.01 ^ input94/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.15    0.16    4.17 ^ input94/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     5    0.01                           net94 (net)
                  0.15    0.00    4.17 ^ _2322_/A (sky130_fd_sc_hd__buf_2)
                  0.15    0.23    4.41 ^ _2322_/X (sky130_fd_sc_hd__buf_2)
     5    0.03                           _2081_ (net)
                  0.15    0.00    4.41 ^ _2323_/A (sky130_fd_sc_hd__clkbuf_2)
                  0.14    0.22    4.63 ^ _2323_/X (sky130_fd_sc_hd__clkbuf_2)
     5    0.02                           _2082_ (net)
                  0.14    0.00    4.63 ^ _2324_/A (sky130_fd_sc_hd__clkbuf_4)
                  0.13    0.24    4.87 ^ _2324_/X (sky130_fd_sc_hd__clkbuf_4)
     5    0.04                           _2083_ (net)
                  0.13    0.00    4.87 ^ _2325_/A (sky130_fd_sc_hd__clkbuf_2)
                  0.12    0.20    5.07 ^ _2325_/X (sky130_fd_sc_hd__clkbuf_2)
     5    0.02                           _2084_ (net)
                  0.12    0.00    5.07 ^ _2326_/A (sky130_fd_sc_hd__clkbuf_4)
                  0.12    0.23    5.30 ^ _2326_/X (sky130_fd_sc_hd__clkbuf_4)
     5    0.04                           _2085_ (net)
                  0.12    0.00    5.30 ^ _2327_/A (sky130_fd_sc_hd__buf_2)
                  0.15    0.22    5.52 ^ _2327_/X (sky130_fd_sc_hd__buf_2)
     5    0.03                           _2086_ (net)
                  0.15    0.00    5.52 ^ _2328_/A (sky130_fd_sc_hd__buf_2)
                  0.15    0.23    5.76 ^ _2328_/X (sky130_fd_sc_hd__buf_2)
     5    0.03                           _2087_ (net)
                  0.15    0.00    5.76 ^ _2329_/A0 (sky130_fd_sc_hd__mux2_1)
                  0.10    0.21    5.96 ^ _2329_/X (sky130_fd_sc_hd__mux2_1)
     1    0.01                           _2088_ (net)
                  0.10    0.00    5.96 ^ _2330_/A (sky130_fd_sc_hd__buf_12)
                  0.18    0.22    6.18 ^ _2330_/X (sky130_fd_sc_hd__buf_12)
     1    0.17                           net282 (net)
                  0.25    0.09    6.27 ^ output282/A (sky130_fd_sc_hd__buf_2)
                  0.17    0.27    6.54 ^ output282/X (sky130_fd_sc_hd__buf_2)
     1    0.03                           io_imem_io_addr[1] (net)
                  0.17    0.00    6.54 ^ io_imem_io_addr[1] (out)
                                  6.54   data arrival time

                         20.00   20.00   clock clock (rise edge)
                          0.00   20.00   clock network delay (propagated)
                         -0.25   19.75   clock uncertainty
                          0.00   19.75   clock reconvergence pessimism
                         -4.00   15.75   output external delay
                                 15.75   data required time
-----------------------------------------------------------------------------
                                 15.75   data required time
                                 -6.54   data arrival time
-----------------------------------------------------------------------------
                                  9.21   slack (MET)


Startpoint: io_imem_io_rdata[29] (input port clocked by clock)
Endpoint: io_dbus_rdata[5] (output port clocked by clock)
Path Group: clock
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock network delay (propagated)
                          4.00    4.00 v input external delay
                  0.02    0.02    4.02 v io_imem_io_rdata[29] (in)
     1    0.01                           io_imem_io_rdata[29] (net)
                  0.02    0.00    4.02 v input122/A (sky130_fd_sc_hd__buf_12)
                  0.08    0.17    4.19 v input122/X (sky130_fd_sc_hd__buf_12)
     2    0.24                           net122 (net)
                  0.30    0.15    4.34 v _2584_/B (sky130_fd_sc_hd__and2_1)
                  0.11    0.35    4.69 v _2584_/X (sky130_fd_sc_hd__and2_1)
     3    0.02                           _2284_ (net)
                  0.11    0.00    4.70 v _2585_/B2 (sky130_fd_sc_hd__a22o_1)
                  0.04    0.23    4.93 v _2585_/X (sky130_fd_sc_hd__a22o_1)
     1    0.00                           _2285_ (net)
                  0.04    0.00    4.93 v _2586_/B2 (sky130_fd_sc_hd__a32o_1)
                  0.04    0.22    5.15 v _2586_/X (sky130_fd_sc_hd__a32o_1)
     1    0.00                           _2286_ (net)
                  0.04    0.00    5.15 v _2588_/A0 (sky130_fd_sc_hd__mux2_1)
                  0.06    0.30    5.45 v _2588_/X (sky130_fd_sc_hd__mux2_1)
     1    0.00                           _2288_ (net)
                  0.06    0.00    5.45 v _2589_/A1 (sky130_fd_sc_hd__mux2_1)
                  0.07    0.34    5.79 v _2589_/X (sky130_fd_sc_hd__mux2_1)
     1    0.01                           _2289_ (net)
                  0.07    0.00    5.79 v _2593_/A2 (sky130_fd_sc_hd__a22o_4)
                  0.14    0.38    6.17 v _2593_/X (sky130_fd_sc_hd__a22o_4)
     1    0.09                           net196 (net)
                  0.15    0.03    6.19 v output196/A (sky130_fd_sc_hd__buf_2)
                  0.09    0.24    6.43 v output196/X (sky130_fd_sc_hd__buf_2)
     1    0.03                           io_dbus_rdata[5] (net)
                  0.09    0.00    6.43 v io_dbus_rdata[5] (out)
                                  6.43   data arrival time

                         20.00   20.00   clock clock (rise edge)
                          0.00   20.00   clock network delay (propagated)
                         -0.25   19.75   clock uncertainty
                          0.00   19.75   clock reconvergence pessimism
                         -4.00   15.75   output external delay
                                 15.75   data required time
-----------------------------------------------------------------------------
                                 15.75   data required time
                                 -6.43   data arrival time
-----------------------------------------------------------------------------
                                  9.32   slack (MET)


Startpoint: io_imem_io_rdata[25] (input port clocked by clock)
Endpoint: io_dbus_rdata[1] (output port clocked by clock)
Path Group: clock
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock network delay (propagated)
                          4.00    4.00 v input external delay
                  0.02    0.02    4.02 v io_imem_io_rdata[25] (in)
     1    0.01                           io_imem_io_rdata[25] (net)
                  0.02    0.00    4.02 v input118/A (sky130_fd_sc_hd__buf_12)
                  0.08    0.17    4.19 v input118/X (sky130_fd_sc_hd__buf_12)
     2    0.24                           net118 (net)
                  0.29    0.14    4.33 v _2528_/B (sky130_fd_sc_hd__and2_2)
                  0.07    0.36    4.69 v _2528_/X (sky130_fd_sc_hd__and2_2)
     3    0.02                           _2232_ (net)
                  0.07    0.00    4.69 v _2529_/B2 (sky130_fd_sc_hd__a22o_1)
                  0.05    0.22    4.91 v _2529_/X (sky130_fd_sc_hd__a22o_1)
     1    0.00                           _2233_ (net)
                  0.05    0.00    4.91 v _2530_/B2 (sky130_fd_sc_hd__a32o_1)
                  0.04    0.22    5.14 v _2530_/X (sky130_fd_sc_hd__a32o_1)
     1    0.00                           _2234_ (net)
                  0.04    0.00    5.14 v _2532_/A0 (sky130_fd_sc_hd__mux2_1)
                  0.06    0.29    5.43 v _2532_/X (sky130_fd_sc_hd__mux2_1)
     1    0.00                           _2236_ (net)
                  0.06    0.00    5.43 v _2534_/A1 (sky130_fd_sc_hd__mux2_1)
                  0.07    0.32    5.75 v _2534_/X (sky130_fd_sc_hd__mux2_1)
     1    0.00                           _2238_ (net)
                  0.07    0.00    5.75 v _2544_/A2 (sky130_fd_sc_hd__a22o_4)
                  0.15    0.39    6.14 v _2544_/X (sky130_fd_sc_hd__a22o_4)
     1    0.10                           net180 (net)
                  0.16    0.03    6.18 v output180/A (sky130_fd_sc_hd__buf_2)
                  0.09    0.25    6.42 v output180/X (sky130_fd_sc_hd__buf_2)
     1    0.03                           io_dbus_rdata[1] (net)
                  0.09    0.00    6.42 v io_dbus_rdata[1] (out)
                                  6.42   data arrival time

                         20.00   20.00   clock clock (rise edge)
                          0.00   20.00   clock network delay (propagated)
                         -0.25   19.75   clock uncertainty
                          0.00   19.75   clock reconvergence pessimism
                         -4.00   15.75   output external delay
                                 15.75   data required time
-----------------------------------------------------------------------------
                                 15.75   data required time
                                 -6.42   data arrival time
-----------------------------------------------------------------------------
                                  9.33   slack (MET)


max_report_end
check_report

===========================================================================
report_checks -unconstrained
============================================================================
Startpoint: io_ibus_addr[2] (input port clocked by clock)
Endpoint: _4801_ (rising edge-triggered flip-flop clocked by clock)
Path Group: clock
Path Type: max

Fanout     Cap    Slew   Delay    Time   Description
-----------------------------------------------------------------------------
                          0.00    0.00   clock clock (rise edge)
                          0.00    0.00   clock network delay (propagated)
                          4.00    4.00 v input external delay
                  0.01    0.00    4.00 v io_ibus_addr[2] (in)
     1    0.00                           io_ibus_addr[2] (net)
                  0.01    0.00    4.00 v input93/A (sky130_fd_sc_hd__dlymetal6s2s_1)
                  0.08    0.16    4.17 v input93/X (sky130_fd_sc_hd__dlymetal6s2s_1)
     4    0.01                           net93 (net)
                  0.08    0.00    4.17 v _2761_/A (sky130_fd_sc_hd__buf_2)
                  0.08    0.19    4.36 v _2761_/X (sky130_fd_sc_hd__buf_2)
     5    0.03                           _0355_ (net)
                  0.08    0.00    4.36 v _2953_/A (sky130_fd_sc_hd__xor2_4)
                  0.08    0.22    4.58 v _2953_/X (sky130_fd_sc_hd__xor2_4)
     3    0.02                           _0547_ (net)
                  0.08    0.00    4.58 v _2954_/C (sky130_fd_sc_hd__and3_1)
                  0.06    0.22    4.80 v _2954_/X (sky130_fd_sc_hd__and3_1)
     3    0.01                           _0548_ (net)
                  0.06    0.00    4.80 v _3837_/A (sky130_fd_sc_hd__or4_1)
                  0.08    0.53    5.34 v _3837_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1323_ (net)
                  0.08    0.00    5.34 v _3843_/B (sky130_fd_sc_hd__or4_1)
                  0.11    0.58    5.91 v _3843_/X (sky130_fd_sc_hd__or4_1)
     1    0.01                           _1329_ (net)
                  0.11    0.00    5.91 v _3844_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.44    6.36 v _3844_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1330_ (net)
                  0.09    0.00    6.36 v _3845_/D (sky130_fd_sc_hd__or4_1)
                  0.10    0.45    6.80 v _3845_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1331_ (net)
                  0.10    0.00    6.80 v _3846_/D (sky130_fd_sc_hd__or4_1)
                  0.08    0.42    7.22 v _3846_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1332_ (net)
                  0.08    0.00    7.22 v _3847_/D (sky130_fd_sc_hd__or4_1)
                  0.11    0.47    7.69 v _3847_/X (sky130_fd_sc_hd__or4_1)
     1    0.01                           _1333_ (net)
                  0.11    0.00    7.69 v _3848_/D (sky130_fd_sc_hd__or4_1)
                  0.08    0.43    8.12 v _3848_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1334_ (net)
                  0.08    0.00    8.12 v _3849_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.43    8.55 v _3849_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1335_ (net)
                  0.09    0.00    8.55 v _3850_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.44    8.99 v _3850_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1336_ (net)
                  0.09    0.00    8.99 v _3851_/D (sky130_fd_sc_hd__or4_1)
                  0.08    0.41    9.40 v _3851_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1337_ (net)
                  0.08    0.00    9.40 v _3852_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.44    9.84 v _3852_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1338_ (net)
                  0.09    0.00    9.84 v _3854_/C (sky130_fd_sc_hd__or4_1)
                  0.08    0.50   10.34 v _3854_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1340_ (net)
                  0.08    0.00   10.34 v _3855_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.44   10.78 v _3855_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1341_ (net)
                  0.09    0.00   10.78 v _3857_/C (sky130_fd_sc_hd__or4_1)
                  0.08    0.50   11.28 v _3857_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1343_ (net)
                  0.08    0.00   11.28 v _3858_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.44   11.72 v _3858_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1344_ (net)
                  0.09    0.00   11.72 v _3862_/C (sky130_fd_sc_hd__or4_1)
                  0.08    0.49   12.21 v _3862_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1348_ (net)
                  0.08    0.00   12.21 v _3863_/D (sky130_fd_sc_hd__or4_1)
                  0.09    0.43   12.64 v _3863_/X (sky130_fd_sc_hd__or4_1)
     1    0.00                           _1349_ (net)
                  0.09    0.00   12.64 v _3868_/A2 (sky130_fd_sc_hd__o211a_1)
                  0.04    0.23   12.87 v _3868_/X (sky130_fd_sc_hd__o211a_1)
     1    0.00                           _0123_ (net)
                  0.04    0.00   12.87 v _4801_/D (sky130_fd_sc_hd__dfxtp_1)
                                 12.87   data arrival time

                         20.00   20.00   clock clock (rise edge)
                          0.00   20.00   clock source latency
                  0.50    0.35   20.35 ^ clock (in)
     1    0.11                           clock (net)
                  0.51    0.00   20.35 ^ clkbuf_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.23   20.58 ^ clkbuf_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     2    0.02                           clknet_0_clock (net)
                  0.05    0.00   20.58 ^ clkbuf_1_1_0_clock/A (sky130_fd_sc_hd__clkbuf_2)
                  0.65    0.50   21.08 ^ clkbuf_1_1_0_clock/X (sky130_fd_sc_hd__clkbuf_2)
     8    0.12                           clknet_1_1_0_clock (net)
                  0.65    0.00   21.08 ^ clkbuf_opt_3_0_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.05    0.25   21.33 ^ clkbuf_opt_3_0_clock/X (sky130_fd_sc_hd__clkbuf_16)
     1    0.01                           clknet_opt_3_0_clock (net)
                  0.05    0.00   21.33 ^ clkbuf_leaf_3_clock/A (sky130_fd_sc_hd__clkbuf_16)
                  0.06    0.14   21.47 ^ clkbuf_leaf_3_clock/X (sky130_fd_sc_hd__clkbuf_16)
    14    0.04                           clknet_leaf_3_clock (net)
                  0.06    0.00   21.47 ^ _4801_/CLK (sky130_fd_sc_hd__dfxtp_1)
                         -0.25   21.22   clock uncertainty
                          0.00   21.22   clock reconvergence pessimism
                         -0.10   21.11   library setup time
                                 21.11   data required time
-----------------------------------------------------------------------------
                                 21.11   data required time
                                -12.87   data arrival time
-----------------------------------------------------------------------------
                                  8.24   slack (MET)



===========================================================================
report_checks --slack_max -0.01
============================================================================
No paths found.
check_report_end
check_slew

===========================================================================
 report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================

===========================================================================
max slew violation count 0
max fanout violation count 0
max cap violation count 0
============================================================================
check_slew_end
tns_report

===========================================================================
 report_tns
============================================================================
tns 0.00
tns_report_end
wns_report

===========================================================================
 report_wns
============================================================================
wns 0.00
wns_report_end
worst_slack

===========================================================================
 report_worst_slack -max (Setup)
============================================================================
worst slack 8.24

===========================================================================
 report_worst_slack -min (Hold)
============================================================================
worst slack -0.04
worst_slack_end
clock_skew

===========================================================================
 report_clock_skew
============================================================================
Clock clock
Latency      CRPR       Skew
_4828_/CLK ^
   1.69
_4827_/CLK ^
   1.08     -0.06       0.55

clock_skew_end
power_report

===========================================================================
 report_power
============================================================================
Group                  Internal  Switching    Leakage      Total
                          Power      Power      Power      Power
----------------------------------------------------------------
Sequential             5.07e-04   3.14e-05   1.99e-09   5.38e-04  32.6%
Combinational          4.26e-04   6.88e-04   1.40e-08   1.11e-03  67.4%
Macro                  0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
Pad                    0.00e+00   0.00e+00   0.00e+00   0.00e+00   0.0%
----------------------------------------------------------------
Total                  9.33e-04   7.20e-04   1.60e-08   1.65e-03 100.0%
                          56.5%      43.5%       0.0%
power_report_end
area_report

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 report_design_area
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Design area 52379 u^2 4% utilization.
area_report_end