| |
| /----------------------------------------------------------------------------\ |
| | | |
| | yosys -- Yosys Open SYnthesis Suite | |
| | | |
| | Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> | |
| | | |
| | Permission to use, copy, modify, and/or distribute this software for any | |
| | purpose with or without fee is hereby granted, provided that the above | |
| | copyright notice and this permission notice appear in all copies. | |
| | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| | | |
| \----------------------------------------------------------------------------/ |
| |
| Yosys 0.12+45 (git sha1 UNKNOWN, gcc 8.3.1 -fPIC -Os) |
| |
| [TCL: yosys -import] Command name collision: found pre-existing command `cd' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `eval' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `exec' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `read' -> skip. |
| [TCL: yosys -import] Command name collision: found pre-existing command `trace' -> skip. |
| |
| 1. Executing Verilog-2005 frontend: /home/ali112000/mpw5/UETRV-ECORE/caravel/verilog/rtl/defines.v |
| Parsing SystemVerilog input from `/home/ali112000/mpw5/UETRV-ECORE/caravel/verilog/rtl/defines.v' to AST representation. |
| Successfully finished Verilog frontend. |
| |
| 2. Executing Verilog-2005 frontend: /home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v |
| Parsing SystemVerilog input from `/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v' to AST representation. |
| Generating RTLIL representation for module `\Interlink_Module'. |
| Generating RTLIL representation for module `\PWM'. |
| Generating RTLIL representation for module `\Quad_Encoder'. |
| Generating RTLIL representation for module `\vedic_2x2'. |
| Generating RTLIL representation for module `\vedic_4x4'. |
| Generating RTLIL representation for module `\vedic_8x8'. |
| Generating RTLIL representation for module `\vedic_16x16'. |
| Generating RTLIL representation for module `\PID_Controller'. |
| Generating RTLIL representation for module `\Motor_Top'. |
| Successfully finished Verilog frontend. |
| |
| 3. Generating Graphviz representation of design. |
| Writing dot description to `/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/synthesis/hierarchy.dot'. |
| Dumping module Motor_Top to page 1. |
| |
| 4. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 4.1. Analyzing design hierarchy.. |
| Top module: \Motor_Top |
| Used module: \PID_Controller |
| Used module: \vedic_16x16 |
| Used module: \vedic_4x4 |
| Used module: \vedic_2x2 |
| Used module: \vedic_8x8 |
| Used module: \Quad_Encoder |
| Used module: \PWM |
| Used module: \Interlink_Module |
| |
| 4.2. Analyzing design hierarchy.. |
| Top module: \Motor_Top |
| Used module: \PID_Controller |
| Used module: \vedic_16x16 |
| Used module: \vedic_4x4 |
| Used module: \vedic_2x2 |
| Used module: \vedic_8x8 |
| Used module: \Quad_Encoder |
| Used module: \PWM |
| Used module: \Interlink_Module |
| Removed 0 unused modules. |
| |
| 5. Executing TRIBUF pass. |
| |
| 6. Executing SYNTH pass. |
| |
| 6.1. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 6.1.1. Analyzing design hierarchy.. |
| Top module: \Motor_Top |
| Used module: \PID_Controller |
| Used module: \vedic_16x16 |
| Used module: \vedic_4x4 |
| Used module: \vedic_2x2 |
| Used module: \vedic_8x8 |
| Used module: \Quad_Encoder |
| Used module: \PWM |
| Used module: \Interlink_Module |
| |
| 6.1.2. Analyzing design hierarchy.. |
| Top module: \Motor_Top |
| Used module: \PID_Controller |
| Used module: \vedic_16x16 |
| Used module: \vedic_4x4 |
| Used module: \vedic_2x2 |
| Used module: \vedic_8x8 |
| Used module: \Quad_Encoder |
| Used module: \PWM |
| Used module: \Interlink_Module |
| Removed 0 unused modules. |
| |
| 6.2. Executing PROC pass (convert processes to netlists). |
| |
| 6.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Cleaned up 0 empty switches. |
| |
| 6.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). |
| Marked 12 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226 in module PID_Controller. |
| Marked 18 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154 in module Quad_Encoder. |
| Marked 24 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115 in module PWM. |
| Marked 9 switch rules as full_case in process $proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:220$66 in module Interlink_Module. |
| Removed a total of 0 dead cases. |
| |
| 6.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). |
| Removed 6 redundant assignments. |
| Promoted 3 assignments to connections. |
| |
| 6.2.4. Executing PROC_INIT pass (extract init attributes). |
| |
| 6.2.5. Executing PROC_ARST pass (detect async resets in processes). |
| |
| 6.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). |
| Creating decoders for process `\PID_Controller.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226'. |
| 1/10: $0\reg_pid_out[15:0] |
| 2/10: $0\e_prev2[15:0] |
| 3/10: $0\e_prev1[15:0] |
| 4/10: $0\fb_sel[0:0] |
| 5/10: $0\sigma_old[15:0] |
| 6/10: $0\feedback[15:0] |
| 7/10: $0\ref$[15:0]$227 |
| 8/10: $0\kd[15:0] |
| 9/10: $0\ki[15:0] |
| 10/10: $0\kp[15:0] |
| Creating decoders for process `\Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| 1/11: $0\qei_output[15:0] |
| 2/11: $0\quad_b_delayed[2:0] |
| 3/11: $0\quad_a_delayed[2:0] |
| 4/11: $0\period_sel[0:0] |
| 5/11: $0\qei_period_count[15:0] |
| 6/11: $0\qei_speed_count[15:0] |
| 7/11: $0\count_sel_2x[0:0] |
| 8/11: $0\speed_enable[0:0] |
| 9/11: $0\period_count[15:0] |
| 10/11: $0\count_reg_2[15:0] |
| 11/11: $0\count_reg[31:0] |
| Creating decoders for process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| 1/12: $0\proc_offset[31:0] |
| 2/12: $0\pwm_db[3:0] |
| 3/12: $0\pid_out_sel[0:0] |
| 4/12: $0\irq_ena[0:0] |
| 5/12: $0\updown[0:0] |
| 6/12: $0\irq_out[0:0] |
| 7/12: $0\stop_out[0:0] |
| 8/12: $0\enable[0:0] |
| 9/12: $0\reg_duty[31:0] |
| 10/12: $0\pwm_duty[31:0] |
| 11/12: $0\value_reload[31:0] |
| 12/12: $0\value_cur[31:0] |
| Creating decoders for process `\Interlink_Module.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:220$66'. |
| 1/2: $0\wb_data_o[31:0] |
| 2/2: $0\wb_ack_o[0:0] |
| |
| 6.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). |
| |
| 6.2.8. Executing PROC_DFF pass (convert process syncs to FFs). |
| Creating register for signal `\PID_Controller.\kp' using process `\PID_Controller.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226'. |
| created $dff cell `$procdff$489' with positive edge clock. |
| Creating register for signal `\PID_Controller.\ki' using process `\PID_Controller.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226'. |
| created $dff cell `$procdff$490' with positive edge clock. |
| Creating register for signal `\PID_Controller.\kd' using process `\PID_Controller.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226'. |
| created $dff cell `$procdff$491' with positive edge clock. |
| Creating register for signal `\PID_Controller.\ref$' using process `\PID_Controller.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226'. |
| created $dff cell `$procdff$492' with positive edge clock. |
| Creating register for signal `\PID_Controller.\feedback' using process `\PID_Controller.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226'. |
| created $dff cell `$procdff$493' with positive edge clock. |
| Creating register for signal `\PID_Controller.\sigma_old' using process `\PID_Controller.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226'. |
| created $dff cell `$procdff$494' with positive edge clock. |
| Creating register for signal `\PID_Controller.\fb_sel' using process `\PID_Controller.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226'. |
| created $dff cell `$procdff$495' with positive edge clock. |
| Creating register for signal `\PID_Controller.\e_prev1' using process `\PID_Controller.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226'. |
| created $dff cell `$procdff$496' with positive edge clock. |
| Creating register for signal `\PID_Controller.\e_prev2' using process `\PID_Controller.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226'. |
| created $dff cell `$procdff$497' with positive edge clock. |
| Creating register for signal `\PID_Controller.\reg_pid_out' using process `\PID_Controller.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226'. |
| created $dff cell `$procdff$498' with positive edge clock. |
| Creating register for signal `\Quad_Encoder.\quad_a_delayed' using process `\Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| created $dff cell `$procdff$499' with positive edge clock. |
| Creating register for signal `\Quad_Encoder.\quad_b_delayed' using process `\Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| created $dff cell `$procdff$500' with positive edge clock. |
| Creating register for signal `\Quad_Encoder.\count_reg' using process `\Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| created $dff cell `$procdff$501' with positive edge clock. |
| Creating register for signal `\Quad_Encoder.\count_reg_2' using process `\Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| created $dff cell `$procdff$502' with positive edge clock. |
| Creating register for signal `\Quad_Encoder.\period_count' using process `\Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| created $dff cell `$procdff$503' with positive edge clock. |
| Creating register for signal `\Quad_Encoder.\speed_enable' using process `\Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| created $dff cell `$procdff$504' with positive edge clock. |
| Creating register for signal `\Quad_Encoder.\count_sel_2x' using process `\Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| created $dff cell `$procdff$505' with positive edge clock. |
| Creating register for signal `\Quad_Encoder.\qei_output' using process `\Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| created $dff cell `$procdff$506' with positive edge clock. |
| Creating register for signal `\Quad_Encoder.\qei_speed_count' using process `\Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| created $dff cell `$procdff$507' with positive edge clock. |
| Creating register for signal `\Quad_Encoder.\qei_period_count' using process `\Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| created $dff cell `$procdff$508' with positive edge clock. |
| Creating register for signal `\Quad_Encoder.\period_sel' using process `\Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| created $dff cell `$procdff$509' with positive edge clock. |
| Creating register for signal `\PWM.\value_cur' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$510' with positive edge clock. |
| Creating register for signal `\PWM.\value_reload' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$511' with positive edge clock. |
| Creating register for signal `\PWM.\pwm_duty' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$512' with positive edge clock. |
| Creating register for signal `\PWM.\reg_duty' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$513' with positive edge clock. |
| Creating register for signal `\PWM.\enable' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$514' with positive edge clock. |
| Creating register for signal `\PWM.\stop_out' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$515' with positive edge clock. |
| Creating register for signal `\PWM.\irq_out' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$516' with positive edge clock. |
| Creating register for signal `\PWM.\lastenable' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$517' with positive edge clock. |
| Creating register for signal `\PWM.\updown' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$518' with positive edge clock. |
| Creating register for signal `\PWM.\irq_ena' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$519' with positive edge clock. |
| Creating register for signal `\PWM.\pid_out_sel' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$520' with positive edge clock. |
| Creating register for signal `\PWM.\pwm_db' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$521' with positive edge clock. |
| Creating register for signal `\PWM.\proc_offset' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$522' with positive edge clock. |
| Creating register for signal `\PWM.\pwm_ld' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$523' with positive edge clock. |
| Creating register for signal `\PWM.\pwm_hd' using process `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| created $dff cell `$procdff$524' with positive edge clock. |
| Creating register for signal `\Interlink_Module.\wb_ack_o' using process `\Interlink_Module.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:220$66'. |
| created $dff cell `$procdff$525' with positive edge clock. |
| Creating register for signal `\Interlink_Module.\wb_data_o' using process `\Interlink_Module.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:220$66'. |
| created $dff cell `$procdff$526' with positive edge clock. |
| |
| 6.2.9. Executing PROC_MEMWR pass (convert process memory writes to cells). |
| |
| 6.2.10. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Found and cleaned up 22 empty switches in `\PID_Controller.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226'. |
| Removing empty process `PID_Controller.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1570$226'. |
| Found and cleaned up 31 empty switches in `\Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| Removing empty process `Quad_Encoder.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:887$154'. |
| Found and cleaned up 37 empty switches in `\PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| Removing empty process `PWM.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:538$115'. |
| Found and cleaned up 9 empty switches in `\Interlink_Module.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:220$66'. |
| Removing empty process `Interlink_Module.$proc$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:220$66'. |
| Cleaned up 99 empty switches. |
| |
| 6.2.11. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| Optimizing module PID_Controller. |
| <suppressed ~3 debug messages> |
| Optimizing module vedic_16x16. |
| Optimizing module vedic_8x8. |
| Optimizing module vedic_4x4. |
| Optimizing module vedic_2x2. |
| Optimizing module Quad_Encoder. |
| <suppressed ~3 debug messages> |
| Optimizing module PWM. |
| <suppressed ~13 debug messages> |
| Optimizing module Interlink_Module. |
| <suppressed ~1 debug messages> |
| |
| 6.3. Executing FLATTEN pass (flatten design). |
| Deleting now unused module PID_Controller. |
| Deleting now unused module vedic_16x16. |
| Deleting now unused module vedic_8x8. |
| Deleting now unused module vedic_4x4. |
| Deleting now unused module vedic_2x2. |
| Deleting now unused module Quad_Encoder. |
| Deleting now unused module PWM. |
| Deleting now unused module Interlink_Module. |
| <suppressed ~19 debug messages> |
| |
| 6.4. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| |
| 6.5. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| Removed 240 unused cells and 2174 unused wires. |
| <suppressed ~514 debug messages> |
| |
| 6.6. Executing CHECK pass (checking for obvious problems). |
| Checking module Motor_Top... |
| Found and reported 0 problems. |
| |
| 6.7. Executing OPT pass (performing simple optimizations). |
| |
| 6.7.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| |
| 6.7.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| <suppressed ~3 debug messages> |
| Removed a total of 1 cells. |
| |
| 6.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Motor_Top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Replacing known input bits on port A of cell $flatten\pid.\mul_kd.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1278$181: \pid.mul_kd._T_29 -> { 1'0 \pid.mul_kd._T_29 [14:0] } |
| Replacing known input bits on port A of cell $flatten\pid.\mul_ki.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1278$181: \pid.mul_ki._T_29 -> { 1'0 \pid.mul_ki._T_29 [14:0] } |
| Replacing known input bits on port A of cell $flatten\pid.\mul_kp.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1278$181: \pid.e_prev1 -> { 1'0 \pid.e_prev1 [14:0] } |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~54 debug messages> |
| |
| 6.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Motor_Top. |
| Performed a total of 0 changes. |
| |
| 6.7.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| Removed a total of 0 cells. |
| |
| 6.7.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| |
| 6.7.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| |
| 6.7.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 6.8. Executing FSM pass (extract and optimize FSM). |
| |
| 6.8.1. Executing FSM_DETECT pass (finding FSMs in design). |
| |
| 6.8.2. Executing FSM_EXTRACT pass (extracting FSM from design). |
| |
| 6.8.3. Executing FSM_OPT pass (simple optimizations of FSMs). |
| |
| 6.8.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| |
| 6.8.5. Executing FSM_OPT pass (simple optimizations of FSMs). |
| |
| 6.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). |
| |
| 6.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells). |
| |
| 6.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic). |
| |
| 6.9. Executing OPT pass (performing simple optimizations). |
| |
| 6.9.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| |
| 6.9.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| Removed a total of 0 cells. |
| |
| 6.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Motor_Top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~54 debug messages> |
| |
| 6.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Motor_Top. |
| Performed a total of 0 changes. |
| |
| 6.9.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| Removed a total of 0 cells. |
| |
| 6.9.6. Executing OPT_DFF pass (perform DFF optimizations). |
| Adding SRST signal on $flatten\qei.$procdff$509 ($dff) from module Motor_Top (D = $flatten\qei.$procmux$298_Y, Q = \qei.period_sel, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$527 ($sdff) from module Motor_Top (D = \io_wbs_m2s_data [2], Q = \qei.period_sel). |
| Adding SRST signal on $flatten\qei.$procdff$508 ($dff) from module Motor_Top (D = $flatten\qei.$procmux$308_Y, Q = \qei.qei_period_count, rval = 16'0001111111111111). |
| Adding EN signal on $auto$ff.cc:262:slice$533 ($sdff) from module Motor_Top (D = $flatten\qei.$procmux$306_Y, Q = \qei.qei_period_count). |
| Adding SRST signal on $flatten\qei.$procdff$507 ($dff) from module Motor_Top (D = $flatten\qei.$procmux$315_Y, Q = \qei.qei_speed_count, rval = 16'0000000000000000). |
| Adding EN signal on $auto$ff.cc:262:slice$539 ($sdff) from module Motor_Top (D = \qei.count_reg_2, Q = \qei.qei_speed_count). |
| Adding SRST signal on $flatten\qei.$procdff$506 ($dff) from module Motor_Top (D = $flatten\qei.$procmux$285_Y, Q = \qei.qei_output, rval = 16'0000000000000000). |
| Adding SRST signal on $flatten\qei.$procdff$505 ($dff) from module Motor_Top (D = $flatten\qei.$procmux$322_Y, Q = \qei.count_sel_2x, rval = 1'1). |
| Adding EN signal on $auto$ff.cc:262:slice$544 ($sdff) from module Motor_Top (D = \io_wbs_m2s_data [0], Q = \qei.count_sel_2x). |
| Adding SRST signal on $flatten\qei.$procdff$504 ($dff) from module Motor_Top (D = $flatten\qei.$procmux$329_Y, Q = \qei.speed_enable, rval = 1'1). |
| Adding EN signal on $auto$ff.cc:262:slice$550 ($sdff) from module Motor_Top (D = \io_wbs_m2s_data [1], Q = \qei.speed_enable). |
| Adding SRST signal on $flatten\qei.$procdff$503 ($dff) from module Motor_Top (D = $flatten\qei.$procmux$340_Y, Q = \qei.period_count, rval = 16'0000000000000000). |
| Adding EN signal on $auto$ff.cc:262:slice$556 ($sdff) from module Motor_Top (D = $flatten\qei.$procmux$338_Y, Q = \qei.period_count). |
| Adding SRST signal on $flatten\qei.$procdff$502 ($dff) from module Motor_Top (D = $flatten\qei.$procmux$348_Y, Q = \qei.count_reg_2, rval = 16'0000000000000000). |
| Adding EN signal on $auto$ff.cc:262:slice$558 ($sdff) from module Motor_Top (D = $flatten\qei.$procmux$346_Y, Q = \qei.count_reg_2). |
| Adding SRST signal on $flatten\qei.$procdff$501 ($dff) from module Motor_Top (D = $flatten\qei.$procmux$359_Y, Q = \qei.count_reg, rval = 0). |
| Adding EN signal on $auto$ff.cc:262:slice$560 ($sdff) from module Motor_Top (D = $flatten\qei.$procmux$359_Y, Q = \qei.count_reg). |
| Adding SRST signal on $flatten\qei.$procdff$500 ($dff) from module Motor_Top (D = { \qei.quad_b_delayed [1:0] \io_qei_ch_b }, Q = \qei.quad_b_delayed, rval = 3'000). |
| Adding SRST signal on $flatten\qei.$procdff$499 ($dff) from module Motor_Top (D = { \qei.quad_a_delayed [1:0] \io_qei_ch_a }, Q = \qei.quad_a_delayed, rval = 3'000). |
| Adding SRST signal on $flatten\pwm.$procdff$521 ($dff) from module Motor_Top (D = $flatten\pwm.$procmux$370_Y, Q = \pwm.pwm_db, rval = 4'0010). |
| Adding EN signal on $auto$ff.cc:262:slice$566 ($sdff) from module Motor_Top (D = \pwm._T_114, Q = \pwm.pwm_db). |
| Adding SRST signal on $flatten\pwm.$procdff$520 ($dff) from module Motor_Top (D = $flatten\pwm.$procmux$375_Y, Q = \pwm.pid_out_sel, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$568 ($sdff) from module Motor_Top (D = \io_wbs_m2s_data [3], Q = \pwm.pid_out_sel). |
| Adding SRST signal on $flatten\pwm.$procdff$519 ($dff) from module Motor_Top (D = $flatten\pwm.$procmux$380_Y, Q = \pwm.irq_ena, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$570 ($sdff) from module Motor_Top (D = \io_wbs_m2s_data [2], Q = \pwm.irq_ena). |
| Adding SRST signal on $flatten\pwm.$procdff$518 ($dff) from module Motor_Top (D = $flatten\pwm.$procmux$385_Y, Q = \pwm.updown, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$572 ($sdff) from module Motor_Top (D = \io_wbs_m2s_data [1], Q = \pwm.updown). |
| Adding SRST signal on $flatten\pwm.$procdff$516 ($dff) from module Motor_Top (D = $flatten\pwm.$procmux$395_Y, Q = \pwm.irq_out, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$574 ($sdff) from module Motor_Top (D = $flatten\pwm.$procmux$391_Y, Q = \pwm.irq_out). |
| Adding SRST signal on $flatten\pwm.$procdff$515 ($dff) from module Motor_Top (D = $flatten\pwm.$procmux$411_Y, Q = \pwm.stop_out, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$580 ($sdff) from module Motor_Top (D = $flatten\pwm.$procmux$407_Y, Q = \pwm.stop_out). |
| Adding SRST signal on $flatten\pwm.$procdff$514 ($dff) from module Motor_Top (D = $flatten\pwm.$procmux$416_Y, Q = \pwm.enable, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$586 ($sdff) from module Motor_Top (D = \io_wbs_m2s_data [0], Q = \pwm.enable). |
| Adding SRST signal on $flatten\pwm.$procdff$513 ($dff) from module Motor_Top (D = $flatten\pwm.$procmux$421_Y, Q = \pwm.reg_duty, rval = 0). |
| Adding EN signal on $auto$ff.cc:262:slice$588 ($sdff) from module Motor_Top (D = \io_wbs_m2s_data, Q = \pwm.reg_duty). |
| Adding SRST signal on $flatten\pwm.$procdff$512 ($dff) from module Motor_Top (D = $flatten\pwm.$procmux$429_Y, Q = \pwm.pwm_duty, rval = 0). |
| Adding EN signal on $auto$ff.cc:262:slice$590 ($sdff) from module Motor_Top (D = $flatten\pwm.$procmux$427_Y, Q = \pwm.pwm_duty). |
| Adding SRST signal on $flatten\pwm.$procdff$511 ($dff) from module Motor_Top (D = $flatten\pwm.$procmux$434_Y, Q = \pwm.value_reload, rval = 255). |
| Adding EN signal on $auto$ff.cc:262:slice$592 ($sdff) from module Motor_Top (D = \io_wbs_m2s_data, Q = \pwm.value_reload). |
| Adding SRST signal on $flatten\pwm.$procdff$510 ($dff) from module Motor_Top (D = $flatten\pwm.$procmux$457_Y, Q = \pwm.value_cur, rval = 0). |
| Adding EN signal on $auto$ff.cc:262:slice$594 ($sdff) from module Motor_Top (D = $flatten\pwm.$procmux$457_Y, Q = \pwm.value_cur). |
| Adding SRST signal on $flatten\pid.$procdff$498 ($dff) from module Motor_Top (D = $flatten\pid.$procmux$228_Y, Q = \pid.reg_pid_out, rval = 16'0000000000000000). |
| Adding EN signal on $auto$ff.cc:262:slice$598 ($sdff) from module Motor_Top (D = \pid._T_108, Q = \pid.reg_pid_out). |
| Adding SRST signal on $flatten\pid.$procdff$497 ($dff) from module Motor_Top (D = $flatten\pid.$procmux$233_Y, Q = \pid.e_prev2, rval = 16'0000000000000000). |
| Adding EN signal on $auto$ff.cc:262:slice$600 ($sdff) from module Motor_Top (D = \pid.e_prev1, Q = \pid.e_prev2). |
| Adding SRST signal on $flatten\pid.$procdff$496 ($dff) from module Motor_Top (D = $flatten\pid.$procmux$241_Y, Q = \pid.e_prev1, rval = 16'0000000000000000). |
| Adding EN signal on $auto$ff.cc:262:slice$602 ($sdff) from module Motor_Top (D = $flatten\pid.$procmux$239_Y, Q = \pid.e_prev1). |
| Adding SRST signal on $flatten\pid.$procdff$495 ($dff) from module Motor_Top (D = $flatten\pid.$procmux$246_Y, Q = \pid.fb_sel, rval = 1'0). |
| Adding EN signal on $auto$ff.cc:262:slice$604 ($sdff) from module Motor_Top (D = \io_wbs_m2s_data [0], Q = \pid.fb_sel). |
| Adding SRST signal on $flatten\pid.$procdff$494 ($dff) from module Motor_Top (D = $flatten\pid.$procmux$251_Y, Q = \pid.sigma_old, rval = 16'0000000000000000). |
| Adding EN signal on $auto$ff.cc:262:slice$606 ($sdff) from module Motor_Top (D = \pid.mul_ki._T_29, Q = \pid.sigma_old). |
| Adding SRST signal on $flatten\pid.$procdff$493 ($dff) from module Motor_Top (D = $flatten\pid.$procmux$259_Y, Q = \pid.feedback, rval = 16'0000000000000000). |
| Adding EN signal on $auto$ff.cc:262:slice$608 ($sdff) from module Motor_Top (D = $flatten\pid.$procmux$259_Y, Q = \pid.feedback). |
| Adding SRST signal on $flatten\pid.$procdff$492 ($dff) from module Motor_Top (D = $flatten\pid.$procmux$264_Y, Q = \pid.ref$, rval = 16'0000000000010100). |
| Adding EN signal on $auto$ff.cc:262:slice$612 ($sdff) from module Motor_Top (D = \io_wbs_m2s_data [15:0], Q = \pid.ref$). |
| Adding SRST signal on $flatten\pid.$procdff$491 ($dff) from module Motor_Top (D = $flatten\pid.$procmux$269_Y, Q = \pid.kd, rval = 16'0000000000000000). |
| Adding EN signal on $auto$ff.cc:262:slice$614 ($sdff) from module Motor_Top (D = { \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7:0] }, Q = \pid.kd). |
| Adding SRST signal on $flatten\pid.$procdff$490 ($dff) from module Motor_Top (D = $flatten\pid.$procmux$274_Y, Q = \pid.ki, rval = 16'0000000000000000). |
| Adding EN signal on $auto$ff.cc:262:slice$616 ($sdff) from module Motor_Top (D = { \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7:0] }, Q = \pid.ki). |
| Adding SRST signal on $flatten\pid.$procdff$489 ($dff) from module Motor_Top (D = $flatten\pid.$procmux$279_Y, Q = \pid.kp, rval = 16'0000000000000001). |
| Adding EN signal on $auto$ff.cc:262:slice$618 ($sdff) from module Motor_Top (D = { \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7] \io_wbs_m2s_data [7:0] }, Q = \pid.kp). |
| Adding SRST signal on $flatten\interlink.$procdff$526 ($dff) from module Motor_Top (D = $flatten\interlink.$procmux$481_Y, Q = \interlink.wb_data_o, rval = 0). |
| Adding SRST signal on $flatten\interlink.$procdff$525 ($dff) from module Motor_Top (D = \interlink._T_235, Q = \interlink.wb_ack_o, rval = 1'0). |
| |
| 6.9.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| Removed 66 unused cells and 66 unused wires. |
| <suppressed ~67 debug messages> |
| |
| 6.9.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| <suppressed ~3 debug messages> |
| |
| 6.9.9. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 6.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Motor_Top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~32 debug messages> |
| |
| 6.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Motor_Top. |
| Performed a total of 0 changes. |
| |
| 6.9.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| <suppressed ~18 debug messages> |
| Removed a total of 6 cells. |
| |
| 6.9.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.9.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| Removed 0 unused cells and 6 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 6.9.15. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| |
| 6.9.16. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 6.9.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Motor_Top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~32 debug messages> |
| |
| 6.9.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Motor_Top. |
| Performed a total of 0 changes. |
| |
| 6.9.19. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| Removed a total of 0 cells. |
| |
| 6.9.20. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.9.21. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| |
| 6.9.22. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| |
| 6.9.23. Finished OPT passes. (There is nothing left to do.) |
| |
| 6.10. Executing WREDUCE pass (reducing word size of cells). |
| Removed top 2 bits (of 12) from port B of cell Motor_Top.$flatten\interlink.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:154$37 ($eq). |
| Removed top 2 bits (of 12) from port B of cell Motor_Top.$flatten\interlink.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:152$35 ($eq). |
| Removed top 2 bits (of 12) from port B of cell Motor_Top.$flatten\interlink.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:150$33 ($eq). |
| Removed top 2 bits (of 12) from port B of cell Motor_Top.$flatten\interlink.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:148$31 ($eq). |
| Removed top 2 bits (of 12) from port B of cell Motor_Top.$flatten\interlink.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:146$29 ($eq). |
| Removed top 2 bits (of 12) from port B of cell Motor_Top.$flatten\interlink.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:144$27 ($eq). |
| Removed top 3 bits (of 12) from port B of cell Motor_Top.$flatten\interlink.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:136$21 ($eq). |
| Removed top 3 bits (of 12) from port B of cell Motor_Top.$flatten\interlink.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:134$19 ($eq). |
| Removed top 3 bits (of 12) from port B of cell Motor_Top.$flatten\interlink.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:132$17 ($eq). |
| Removed top 8 bits (of 12) from port B of cell Motor_Top.$flatten\interlink.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:122$8 ($eq). |
| Removed top 8 bits (of 12) from port B of cell Motor_Top.$flatten\interlink.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:120$6 ($eq). |
| Removed top 9 bits (of 12) from port B of cell Motor_Top.$flatten\interlink.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:118$4 ($eq). |
| Removed cell Motor_Top.$flatten\pwm.$procmux$454 ($mux). |
| Removed top 31 bits (of 32) from port B of cell Motor_Top.$flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:421$93 ($sub). |
| Removed top 1 bits (of 33) from port Y of cell Motor_Top.$flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:421$93 ($sub). |
| Removed top 31 bits (of 32) from port B of cell Motor_Top.$flatten\pwm.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:420$92 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pwm.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:412$84 ($add). |
| Removed top 28 bits (of 32) from port B of cell Motor_Top.$flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:398$79 ($sub). |
| Removed top 1 bits (of 33) from port Y of cell Motor_Top.$flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:398$79 ($sub). |
| Removed top 28 bits (of 32) from port B of cell Motor_Top.$flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:394$77 ($sub). |
| Removed top 1 bits (of 33) from port Y of cell Motor_Top.$flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:394$77 ($sub). |
| Removed top 27 bits (of 32) from port B of cell Motor_Top.$flatten\pwm.$lt$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:391$75 ($lt). |
| Removed top 27 bits (of 32) from port B of cell Motor_Top.$flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:386$72 ($sub). |
| Removed top 1 bits (of 33) from port Y of cell Motor_Top.$flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:386$72 ($sub). |
| Removed top 27 bits (of 32) from port B of cell Motor_Top.$flatten\pwm.$ge$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:385$71 ($ge). |
| Removed cell Motor_Top.$flatten\qei.$procmux$356 ($mux). |
| Removed cell Motor_Top.$flatten\qei.$procmux$303 ($mux). |
| Removed top 15 bits (of 16) from port B of cell Motor_Top.$flatten\qei.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:793$139 ($add). |
| Removed top 8 bits (of 16) from port B of cell Motor_Top.$flatten\qei.$eq$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:791$137 ($eq). |
| Removed top 15 bits (of 16) from port B of cell Motor_Top.$flatten\qei.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:786$132 ($add). |
| Removed top 31 bits (of 32) from port B of cell Motor_Top.$flatten\qei.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:779$127 ($sub). |
| Removed top 1 bits (of 33) from port Y of cell Motor_Top.$flatten\qei.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:779$127 ($sub). |
| Removed top 31 bits (of 32) from port B of cell Motor_Top.$flatten\qei.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:778$126 ($add). |
| Removed top 15 bits (of 16) from port B of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1275$180 ($add). |
| Removed top 2 bits (of 18) from port A of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 10 bits (of 18) from port B of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 2 bits (of 18) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 8 bits (of 24) from port A of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 8 bits (of 24) from port B of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 7 bits (of 24) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 8 bits (of 24) from port A of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 7 bits (of 24) from port B of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 6 bits (of 24) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 6 bits (of 32) from port A of cell Motor_Top.$flatten\pid.\mul_kd.$not$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1301$188 ($not). |
| Removed top 30 bits (of 32) from port B of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190 ($add). |
| Removed top 16 bits (of 32) from mux cell Motor_Top.$flatten\pid.\mul_kd.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1307$191 ($mux). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 15 bits (of 16) from port B of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1275$180 ($add). |
| Removed top 2 bits (of 18) from port A of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 10 bits (of 18) from port B of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 2 bits (of 18) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 8 bits (of 24) from port A of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 8 bits (of 24) from port B of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 7 bits (of 24) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 8 bits (of 24) from port A of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 7 bits (of 24) from port B of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 6 bits (of 24) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 6 bits (of 32) from port A of cell Motor_Top.$flatten\pid.\mul_ki.$not$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1301$188 ($not). |
| Removed top 30 bits (of 32) from port B of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190 ($add). |
| Removed top 16 bits (of 32) from mux cell Motor_Top.$flatten\pid.\mul_ki.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1307$191 ($mux). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 15 bits (of 16) from port B of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1275$180 ($add). |
| Removed top 2 bits (of 18) from port A of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 10 bits (of 18) from port B of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 2 bits (of 18) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 8 bits (of 24) from port A of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 8 bits (of 24) from port B of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 7 bits (of 24) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 8 bits (of 24) from port A of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 7 bits (of 24) from port B of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 6 bits (of 24) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 6 bits (of 32) from port A of cell Motor_Top.$flatten\pid.\mul_kp.$not$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1301$188 ($not). |
| Removed top 30 bits (of 32) from port B of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190 ($add). |
| Removed top 16 bits (of 32) from mux cell Motor_Top.$flatten\pid.\mul_kp.$ternary$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1307$191 ($mux). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 12) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 6) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 8 bits (of 16) from FF cell Motor_Top.$auto$ff.cc:262:slice$615 ($sdffe). |
| Removed top 8 bits (of 16) from FF cell Motor_Top.$auto$ff.cc:262:slice$617 ($sdffe). |
| Removed top 8 bits (of 16) from FF cell Motor_Top.$auto$ff.cc:262:slice$619 ($sdffe). |
| Removed cell Motor_Top.$flatten\pid.$procmux$257 ($mux). |
| Removed top 16 bits (of 32) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190 ($add). |
| Removed top 16 bits (of 32) from port A of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190 ($add). |
| Removed top 16 bits (of 32) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190 ($add). |
| Removed top 16 bits (of 32) from port A of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190 ($add). |
| Removed top 16 bits (of 32) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190 ($add). |
| Removed top 16 bits (of 32) from port A of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190 ($add). |
| Removed top 16 bits (of 32) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.$not$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1301$188 ($not). |
| Removed top 10 bits (of 26) from port A of cell Motor_Top.$flatten\pid.\mul_kd.$not$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1301$188 ($not). |
| Removed top 16 bits (of 32) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.$not$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1301$188 ($not). |
| Removed top 10 bits (of 26) from port A of cell Motor_Top.$flatten\pid.\mul_ki.$not$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1301$188 ($not). |
| Removed top 16 bits (of 32) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.$not$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1301$188 ($not). |
| Removed top 10 bits (of 26) from port A of cell Motor_Top.$flatten\pid.\mul_kp.$not$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1301$188 ($not). |
| Removed top 10 bits (of 18) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 8 bits (of 16) from port A of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 9 bits (of 17) from port B of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 10 bits (of 18) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 8 bits (of 16) from port A of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 9 bits (of 17) from port B of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 10 bits (of 18) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 8 bits (of 16) from port A of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 9 bits (of 17) from port B of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| Removed top 8 bits (of 16) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 8 bits (of 16) from port A of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 9 bits (of 17) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 8 bits (of 16) from port A of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 15 bits (of 16) from port B of cell Motor_Top.$flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 8 bits (of 16) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 8 bits (of 16) from port A of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 9 bits (of 17) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 8 bits (of 16) from port A of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 15 bits (of 16) from port B of cell Motor_Top.$flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 8 bits (of 16) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 8 bits (of 16) from port A of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| Removed top 9 bits (of 17) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 8 bits (of 16) from port A of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed top 15 bits (of 16) from port B of cell Motor_Top.$flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z4.\z1.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed top 8 bits (of 12) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 8 bits (of 12) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 8 bits (of 12) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 8 bits (of 12) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z4.\z1.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z4.\z1.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed top 8 bits (of 12) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 8 bits (of 12) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 8 bits (of 12) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 8 bits (of 12) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z4.\z1.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z4.\z1.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed top 8 bits (of 12) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 8 bits (of 12) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 8 bits (of 12) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed top 8 bits (of 12) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z4.\z1.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 8 bits (of 12) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 11 bits (of 12) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 8 bits (of 12) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 11 bits (of 12) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 8 bits (of 12) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 11 bits (of 12) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 8 bits (of 12) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 11 bits (of 12) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 8 bits (of 12) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 11 bits (of 12) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 8 bits (of 12) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 11 bits (of 12) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| Removed top 4 bits (of 8) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed top 4 bits (of 8) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z4.\z1.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z4.\z1.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z4.\z1.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z4.\z1.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z4.\z1.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z4.\z1.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z4.\z1.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z4.\z1.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z4.\z1.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z4.\z1.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z4.\z1.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed top 4 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z4.\z1.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed top 2 bits (of 4) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 5 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 5 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 5 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 5 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 5 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 5 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 5 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 5 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 5 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 5 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 5 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| Removed top 4 bits (of 6) from port Y of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 2 bits (of 4) from port A of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed top 5 bits (of 6) from port B of cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.\z2.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.\z2.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.\z3.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.\z3.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z3.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.\z2.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.\z2.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.\z3.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.\z3.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z2.\z2.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.\z2.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.\z2.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.\z3.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.\z3.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z3.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.\z2.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.\z2.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.\z3.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.\z3.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kd.\z3.\z2.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.\z2.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.\z2.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.\z3.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.\z3.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z3.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.\z2.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.\z2.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.\z3.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.\z3.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z2.\z2.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.\z2.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.\z2.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.\z3.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.\z3.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z3.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.\z2.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.\z2.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.\z3.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.\z3.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_ki.\z3.\z2.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.\z2.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.\z2.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.\z3.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.\z3.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z3.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.\z2.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.\z2.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.\z3.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.\z3.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z2.\z2.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.\z2.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.\z2.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.\z3.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.\z3.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z3.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1020$158 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.\z2.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.\z2.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.\z3.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.\z3.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.\z4.$and$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1029$165 ($and). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1028$164 ($xor). |
| Removed cell Motor_Top.$flatten\pid.\mul_kp.\z3.\z2.\z4.$xor$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1026$162 ($xor). |
| Removed top 29 bits (of 32) from wire Motor_Top.interlink_io_qei_cfg_do. |
| Removed top 24 bits (of 32) from wire Motor_Top.interlink_io_tmr_cfg_do. |
| Removed top 24 bits (of 32) from wire Motor_Top.pwm_io_reg_cfg_do. |
| Removed top 29 bits (of 32) from wire Motor_Top.qei_io_reg_cfg_do. |
| |
| 6.11. Executing PEEPOPT pass (run peephole optimizers). |
| |
| 6.12. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| Removed 384 unused cells and 719 unused wires. |
| <suppressed ~1096 debug messages> |
| |
| 6.13. Executing ALUMACC pass (create $alu and $macc cells). |
| Extracting $alu and $macc cells in module Motor_Top: |
| creating $macc model for $flatten\pid.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1452$202 ($add). |
| creating $macc model for $flatten\pid.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1461$204 ($add). |
| creating $macc model for $flatten\pid.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1482$219 ($add). |
| creating $macc model for $flatten\pid.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1450$200 ($sub). |
| creating $macc model for $flatten\pid.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1475$214 ($sub). |
| creating $macc model for $flatten\pid.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1478$216 ($sub). |
| creating $macc model for $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1275$180 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1275$180 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1275$180 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 ($add). |
| creating $macc model for $flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171 ($add). |
| creating $macc model for $flatten\pwm.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:412$84 ($add). |
| creating $macc model for $flatten\pwm.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:420$92 ($add). |
| creating $macc model for $flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:386$72 ($sub). |
| creating $macc model for $flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:394$77 ($sub). |
| creating $macc model for $flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:398$79 ($sub). |
| creating $macc model for $flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:421$93 ($sub). |
| creating $macc model for $flatten\qei.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:778$126 ($add). |
| creating $macc model for $flatten\qei.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:786$132 ($add). |
| creating $macc model for $flatten\qei.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:793$139 ($add). |
| creating $macc model for $flatten\qei.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:779$127 ($sub). |
| merging $macc model for $flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 into $flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 into $flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kp.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 into $flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 into $flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 into $flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 into $flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kp.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 into $flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 into $flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_kp.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kp.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kp.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kp.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kp.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kp.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 into $flatten\pid.\mul_kp.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 into $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187. |
| merging $macc model for $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 into $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187. |
| merging $macc model for $flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 into $flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 into $flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_ki.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 into $flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 into $flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 into $flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 into $flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_ki.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 into $flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 into $flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_ki.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_ki.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_ki.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_ki.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_ki.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_ki.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 into $flatten\pid.\mul_ki.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 into $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187. |
| merging $macc model for $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 into $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187. |
| merging $macc model for $flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 into $flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 into $flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kd.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 into $flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 into $flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 into $flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167 into $flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kd.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173 into $flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 into $flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_kd.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kd.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kd.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kd.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1098$169 into $flatten\pid.\mul_kd.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171. |
| merging $macc model for $flatten\pid.\mul_kd.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1183$175 into $flatten\pid.\mul_kd.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177. |
| merging $macc model for $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1288$183 into $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187. |
| merging $macc model for $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1294$185 into $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187. |
| creating $alu model for $macc $flatten\pid.\mul_kp.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173. |
| creating $alu model for $macc $flatten\pid.\mul_kp.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190. |
| creating $alu model for $macc $flatten\pid.\mul_kp.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pid.\mul_ki.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pid.\mul_kp.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1275$180. |
| creating $alu model for $macc $flatten\pid.\mul_ki.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pid.\mul_ki.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pid.\mul_ki.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pid.\mul_ki.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pid.\mul_ki.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173. |
| creating $alu model for $macc $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190. |
| creating $alu model for $macc $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1275$180. |
| creating $alu model for $macc $flatten\pid.\mul_kp.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pid.\mul_kp.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pid.\mul_kd.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pid.\mul_kp.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pid.\mul_ki.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pwm.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:412$84. |
| creating $alu model for $macc $flatten\pid.\mul_kd.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:386$72. |
| creating $alu model for $macc $flatten\pwm.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:420$92. |
| creating $alu model for $macc $flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:394$77. |
| creating $alu model for $macc $flatten\pid.\mul_kd.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:398$79. |
| creating $alu model for $macc $flatten\pid.\mul_kd.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:421$93. |
| creating $alu model for $macc $flatten\pid.\mul_kd.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\qei.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:778$126. |
| creating $alu model for $macc $flatten\pid.\mul_kd.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167. |
| creating $alu model for $macc $flatten\qei.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:786$132. |
| creating $alu model for $macc $flatten\pid.\mul_kd.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173. |
| creating $alu model for $macc $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190. |
| creating $alu model for $macc $flatten\qei.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:779$127. |
| creating $alu model for $macc $flatten\qei.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:793$139. |
| creating $alu model for $macc $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1275$180. |
| creating $alu model for $macc $flatten\pid.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1478$216. |
| creating $alu model for $macc $flatten\pid.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1475$214. |
| creating $alu model for $macc $flatten\pid.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1450$200. |
| creating $alu model for $macc $flatten\pid.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1482$219. |
| creating $alu model for $macc $flatten\pid.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1461$204. |
| creating $alu model for $macc $flatten\pid.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1452$202. |
| creating $macc cell for $flatten\pid.\mul_ki.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$626 |
| creating $macc cell for $flatten\pid.\mul_kd.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177: $auto$alumacc.cc:365:replace_macc$627 |
| creating $macc cell for $flatten\pid.\mul_kp.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$628 |
| creating $macc cell for $flatten\pid.\mul_ki.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$629 |
| creating $macc cell for $flatten\pid.\mul_kd.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$630 |
| creating $macc cell for $flatten\pid.\mul_ki.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$631 |
| creating $macc cell for $flatten\pid.\mul_kp.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$632 |
| creating $macc cell for $flatten\pid.\mul_kd.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$633 |
| creating $macc cell for $flatten\pid.\mul_kp.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$634 |
| creating $macc cell for $flatten\pid.\mul_kp.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$635 |
| creating $macc cell for $flatten\pid.\mul_kd.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$636 |
| creating $macc cell for $flatten\pid.\mul_kp.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$637 |
| creating $macc cell for $flatten\pid.\mul_kp.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$638 |
| creating $macc cell for $flatten\pid.\mul_kd.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177: $auto$alumacc.cc:365:replace_macc$639 |
| creating $macc cell for $flatten\pid.\mul_ki.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$640 |
| creating $macc cell for $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187: $auto$alumacc.cc:365:replace_macc$641 |
| creating $macc cell for $flatten\pid.\mul_kd.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$642 |
| creating $macc cell for $flatten\pid.\mul_kp.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$643 |
| creating $macc cell for $flatten\pid.\mul_ki.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$644 |
| creating $macc cell for $flatten\pid.\mul_kd.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$645 |
| creating $macc cell for $flatten\pid.\mul_kd.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$646 |
| creating $macc cell for $flatten\pid.\mul_kp.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177: $auto$alumacc.cc:365:replace_macc$647 |
| creating $macc cell for $flatten\pid.\mul_kd.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$648 |
| creating $macc cell for $flatten\pid.\mul_ki.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$649 |
| creating $macc cell for $flatten\pid.\mul_kp.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177: $auto$alumacc.cc:365:replace_macc$650 |
| creating $macc cell for $flatten\pid.\mul_kd.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$651 |
| creating $macc cell for $flatten\pid.\mul_kp.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$652 |
| creating $macc cell for $flatten\pid.\mul_ki.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177: $auto$alumacc.cc:365:replace_macc$653 |
| creating $macc cell for $flatten\pid.\mul_kd.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177: $auto$alumacc.cc:365:replace_macc$654 |
| creating $macc cell for $flatten\pid.\mul_kd.\z3.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$655 |
| creating $macc cell for $flatten\pid.\mul_ki.\z3.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$656 |
| creating $macc cell for $flatten\pid.\mul_ki.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$657 |
| creating $macc cell for $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187: $auto$alumacc.cc:365:replace_macc$658 |
| creating $macc cell for $flatten\pid.\mul_ki.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177: $auto$alumacc.cc:365:replace_macc$659 |
| creating $macc cell for $flatten\pid.\mul_kp.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177: $auto$alumacc.cc:365:replace_macc$660 |
| creating $macc cell for $flatten\pid.\mul_ki.\z2.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$661 |
| creating $macc cell for $flatten\pid.\mul_kp.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$662 |
| creating $macc cell for $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1298$187: $auto$alumacc.cc:365:replace_macc$663 |
| creating $macc cell for $flatten\pid.\mul_ki.\z2.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$664 |
| creating $macc cell for $flatten\pid.\mul_kd.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$665 |
| creating $macc cell for $flatten\pid.\mul_kp.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1101$171: $auto$alumacc.cc:365:replace_macc$666 |
| creating $macc cell for $flatten\pid.\mul_ki.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1186$177: $auto$alumacc.cc:365:replace_macc$667 |
| creating $alu model for $flatten\pwm.$ge$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:385$71 ($ge): new $alu |
| creating $alu model for $flatten\pwm.$gt$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:397$78 ($gt): new $alu |
| creating $alu model for $flatten\pwm.$le$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:389$73 ($le): new $alu |
| creating $alu model for $flatten\pwm.$lt$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:391$75 ($lt): merged with $flatten\pwm.$ge$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:385$71. |
| creating $alu model for $flatten\pwm.$lt$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:401$80 ($lt): new $alu |
| creating $alu model for $flatten\pwm.$lt$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:675$119 ($lt): new $alu |
| creating $alu cell for $flatten\pwm.$lt$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:675$119: $auto$alumacc.cc:485:replace_alu$673 |
| creating $alu cell for $flatten\pwm.$lt$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:401$80: $auto$alumacc.cc:485:replace_alu$678 |
| creating $alu cell for $flatten\pwm.$le$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:389$73: $auto$alumacc.cc:485:replace_alu$683 |
| creating $alu cell for $flatten\pwm.$gt$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:397$78: $auto$alumacc.cc:485:replace_alu$692 |
| creating $alu cell for $flatten\pwm.$ge$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:385$71, $flatten\pwm.$lt$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:391$75: $auto$alumacc.cc:485:replace_alu$703 |
| creating $alu cell for $flatten\pid.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1452$202: $auto$alumacc.cc:485:replace_alu$716 |
| creating $alu cell for $flatten\pid.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1461$204: $auto$alumacc.cc:485:replace_alu$719 |
| creating $alu cell for $flatten\pid.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1482$219: $auto$alumacc.cc:485:replace_alu$722 |
| creating $alu cell for $flatten\pid.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1450$200: $auto$alumacc.cc:485:replace_alu$725 |
| creating $alu cell for $flatten\pid.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1475$214: $auto$alumacc.cc:485:replace_alu$728 |
| creating $alu cell for $flatten\pid.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1478$216: $auto$alumacc.cc:485:replace_alu$731 |
| creating $alu cell for $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1275$180: $auto$alumacc.cc:485:replace_alu$734 |
| creating $alu cell for $flatten\qei.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:793$139: $auto$alumacc.cc:485:replace_alu$737 |
| creating $alu cell for $flatten\qei.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:779$127: $auto$alumacc.cc:485:replace_alu$740 |
| creating $alu cell for $flatten\pid.\mul_kd.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190: $auto$alumacc.cc:485:replace_alu$743 |
| creating $alu cell for $flatten\pid.\mul_kd.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173: $auto$alumacc.cc:485:replace_alu$746 |
| creating $alu cell for $flatten\qei.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:786$132: $auto$alumacc.cc:485:replace_alu$749 |
| creating $alu cell for $flatten\pid.\mul_kd.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$752 |
| creating $alu cell for $flatten\qei.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:778$126: $auto$alumacc.cc:485:replace_alu$755 |
| creating $alu cell for $flatten\pid.\mul_kd.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$758 |
| creating $alu cell for $flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:421$93: $auto$alumacc.cc:485:replace_alu$761 |
| creating $alu cell for $flatten\pid.\mul_kd.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$764 |
| creating $alu cell for $flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:398$79: $auto$alumacc.cc:485:replace_alu$767 |
| creating $alu cell for $flatten\pid.\mul_kd.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$770 |
| creating $alu cell for $flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:394$77: $auto$alumacc.cc:485:replace_alu$773 |
| creating $alu cell for $flatten\pwm.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:420$92: $auto$alumacc.cc:485:replace_alu$776 |
| creating $alu cell for $flatten\pwm.$sub$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:386$72: $auto$alumacc.cc:485:replace_alu$779 |
| creating $alu cell for $flatten\pid.\mul_kd.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$782 |
| creating $alu cell for $flatten\pwm.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:412$84: $auto$alumacc.cc:485:replace_alu$785 |
| creating $alu cell for $flatten\pid.\mul_ki.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$788 |
| creating $alu cell for $flatten\pid.\mul_kp.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$791 |
| creating $alu cell for $flatten\pid.\mul_kd.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$794 |
| creating $alu cell for $flatten\pid.\mul_kp.\z3.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$797 |
| creating $alu cell for $flatten\pid.\mul_kp.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$800 |
| creating $alu cell for $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1275$180: $auto$alumacc.cc:485:replace_alu$803 |
| creating $alu cell for $flatten\pid.\mul_ki.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190: $auto$alumacc.cc:485:replace_alu$806 |
| creating $alu cell for $flatten\pid.\mul_ki.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173: $auto$alumacc.cc:485:replace_alu$809 |
| creating $alu cell for $flatten\pid.\mul_ki.\z1.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$812 |
| creating $alu cell for $flatten\pid.\mul_ki.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$815 |
| creating $alu cell for $flatten\pid.\mul_ki.\z1.\z3.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$818 |
| creating $alu cell for $flatten\pid.\mul_ki.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$821 |
| creating $alu cell for $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1275$180: $auto$alumacc.cc:485:replace_alu$824 |
| creating $alu cell for $flatten\pid.\mul_kp.\z1.\z2.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$827 |
| creating $alu cell for $flatten\pid.\mul_ki.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$830 |
| creating $alu cell for $flatten\pid.\mul_kp.\z2.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$833 |
| creating $alu cell for $flatten\pid.\mul_kp.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1304$190: $auto$alumacc.cc:485:replace_alu$836 |
| creating $alu cell for $flatten\pid.\mul_kp.\z1.\z4.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1092$167: $auto$alumacc.cc:485:replace_alu$839 |
| creating $alu cell for $flatten\pid.\mul_kp.\z1.$add$/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/../../verilog/rtl/Motor_Top.v:1175$173: $auto$alumacc.cc:485:replace_alu$842 |
| created 48 $alu and 42 $macc cells. |
| |
| 6.14. Executing SHARE pass (SAT-based resource sharing). |
| |
| 6.15. Executing OPT pass (performing simple optimizations). |
| |
| 6.15.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| <suppressed ~23 debug messages> |
| |
| 6.15.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| <suppressed ~459 debug messages> |
| Removed a total of 153 cells. |
| |
| 6.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Motor_Top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~31 debug messages> |
| |
| 6.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Motor_Top. |
| Performed a total of 0 changes. |
| |
| 6.15.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| Removed a total of 0 cells. |
| |
| 6.15.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| Removed 43 unused cells and 53 unused wires. |
| <suppressed ~111 debug messages> |
| |
| 6.15.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| |
| 6.15.9. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 6.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Motor_Top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~31 debug messages> |
| |
| 6.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Motor_Top. |
| Performed a total of 0 changes. |
| |
| 6.15.12. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| Removed a total of 0 cells. |
| |
| 6.15.13. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| |
| 6.15.15. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| |
| 6.15.16. Finished OPT passes. (There is nothing left to do.) |
| |
| 6.16. Executing MEMORY pass. |
| |
| 6.16.1. Executing OPT_MEM pass (optimize memories). |
| Performed a total of 0 transformations. |
| |
| 6.16.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). |
| Performed a total of 0 transformations. |
| |
| 6.16.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). |
| |
| 6.16.4. Executing MEMORY_DFF pass (merging $dff cells to $memrd). |
| |
| 6.16.5. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| |
| 6.16.6. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). |
| |
| 6.16.7. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). |
| Performed a total of 0 transformations. |
| |
| 6.16.8. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| |
| 6.16.9. Executing MEMORY_COLLECT pass (generating $mem cells). |
| |
| 6.17. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| |
| 6.18. Executing OPT pass (performing simple optimizations). |
| |
| 6.18.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| <suppressed ~546 debug messages> |
| |
| 6.18.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| Removed a total of 0 cells. |
| |
| 6.18.3. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.18.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| Removed 1 unused cells and 1 unused wires. |
| <suppressed ~2 debug messages> |
| |
| 6.18.5. Finished fast OPT passes. |
| |
| 6.19. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). |
| |
| 6.20. Executing OPT pass (performing simple optimizations). |
| |
| 6.20.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| |
| 6.20.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| Removed a total of 0 cells. |
| |
| 6.20.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Motor_Top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~18 debug messages> |
| |
| 6.20.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Motor_Top. |
| Performed a total of 0 changes. |
| |
| 6.20.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| Removed a total of 0 cells. |
| |
| 6.20.6. Executing OPT_SHARE pass. |
| Found cells that share an operand and can be merged by moving the $mux $flatten\pwm.$procmux$407 in front of them: |
| $flatten\pwm.$procmux$405 |
| $flatten\pwm.$procmux$401 |
| |
| Found cells that share an operand and can be merged by moving the $mux $flatten\qei.$procmux$354 in front of them: |
| $auto$alumacc.cc:485:replace_alu$755 |
| $auto$alumacc.cc:485:replace_alu$740 |
| |
| 6.20.7. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.20.8. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| Removed 0 unused cells and 7 unused wires. |
| <suppressed ~2 debug messages> |
| |
| 6.20.9. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| <suppressed ~28 debug messages> |
| |
| 6.20.10. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 6.20.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Motor_Top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~19 debug messages> |
| |
| 6.20.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Motor_Top. |
| Consolidated identical input bits for $mux cell $auto$opt_share.cc:241:merge_operators$853: |
| Old ports: A=32'11111111111111111111111111111111, B=1, Y=$auto$rtlil.cc:2443:Mux$854 |
| New ports: A=1'1, B=1'0, Y=$auto$rtlil.cc:2443:Mux$854 [1] |
| New connections: { $auto$rtlil.cc:2443:Mux$854 [31:2] $auto$rtlil.cc:2443:Mux$854 [0] } = { $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] $auto$rtlil.cc:2443:Mux$854 [1] 1'1 } |
| Optimizing cells in module \Motor_Top. |
| Performed a total of 1 changes. |
| |
| 6.20.13. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| Removed a total of 0 cells. |
| |
| 6.20.14. Executing OPT_SHARE pass. |
| |
| 6.20.15. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.20.16. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| Removed 0 unused cells and 3 unused wires. |
| <suppressed ~1 debug messages> |
| |
| 6.20.17. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| <suppressed ~1 debug messages> |
| |
| 6.20.18. Rerunning OPT passes. (Maybe there is more to do..) |
| |
| 6.20.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Motor_Top.. |
| Creating internal representation of mux trees. |
| Evaluating internal representation of mux trees. |
| Analyzing evaluation results. |
| Removed 0 multiplexer ports. |
| <suppressed ~18 debug messages> |
| |
| 6.20.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Motor_Top. |
| Performed a total of 0 changes. |
| |
| 6.20.21. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| Removed a total of 0 cells. |
| |
| 6.20.22. Executing OPT_SHARE pass. |
| |
| 6.20.23. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.20.24. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| |
| 6.20.25. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| |
| 6.20.26. Finished OPT passes. (There is nothing left to do.) |
| |
| 6.21. Executing TECHMAP pass (map to technology primitives). |
| |
| 6.21.1. Executing Verilog-2005 frontend: /build/bin/../share/yosys/techmap.v |
| Parsing Verilog input from `/build/bin/../share/yosys/techmap.v' to AST representation. |
| Generating RTLIL representation for module `\_90_simplemap_bool_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_logic_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_compare_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_various'. |
| Generating RTLIL representation for module `\_90_simplemap_registers'. |
| Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. |
| Generating RTLIL representation for module `\_90_shift_shiftx'. |
| Generating RTLIL representation for module `\_90_fa'. |
| Generating RTLIL representation for module `\_90_lcu'. |
| Generating RTLIL representation for module `\_90_alu'. |
| Generating RTLIL representation for module `\_90_macc'. |
| Generating RTLIL representation for module `\_90_alumacc'. |
| Generating RTLIL representation for module `\$__div_mod_u'. |
| Generating RTLIL representation for module `\$__div_mod_trunc'. |
| Generating RTLIL representation for module `\_90_div'. |
| Generating RTLIL representation for module `\_90_mod'. |
| Generating RTLIL representation for module `\$__div_mod_floor'. |
| Generating RTLIL representation for module `\_90_divfloor'. |
| Generating RTLIL representation for module `\_90_modfloor'. |
| Generating RTLIL representation for module `\_90_pow'. |
| Generating RTLIL representation for module `\_90_pmux'. |
| Generating RTLIL representation for module `\_90_lut'. |
| Successfully finished Verilog frontend. |
| |
| 6.21.2. Continuing TECHMAP pass. |
| Using extmapper simplemap for cells of type $sdff. |
| Using extmapper simplemap for cells of type $mux. |
| Using extmapper simplemap for cells of type $and. |
| Using extmapper simplemap for cells of type $or. |
| Using extmapper simplemap for cells of type $eq. |
| Using extmapper simplemap for cells of type $logic_not. |
| Using extmapper simplemap for cells of type $dff. |
| Using extmapper simplemap for cells of type $sdffe. |
| Using template $paramod$86918417b1d705351097c6e77e8f74c668cf6343\_90_alu for cells of type $alu. |
| Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_90_alu for cells of type $alu. |
| Using template $paramod$f85408ed1aa3d09e465edae8a7bf590332ae9f7b\_90_alu for cells of type $alu. |
| Using template $paramod$3e45f4ea55ff926adfd926ab63b8a874a739f6d2\_90_alu for cells of type $alu. |
| Using extmapper simplemap for cells of type $not. |
| Using template $paramod$b0777dc865134c8525a4aa84de8cfa938974cad1\_90_alu for cells of type $alu. |
| Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_90_alu for cells of type $alu. |
| Using template $paramod$d4c0c20b0ee59f495e14575c4397dc0a6dd9e8e6\_90_alu for cells of type $alu. |
| Using template $paramod$fe36d6d725c0243822683f7451312ebcd99a78d3\_90_alu for cells of type $alu. |
| Using extmapper simplemap for cells of type $xor. |
| Using extmapper simplemap for cells of type $reduce_and. |
| Using extmapper simplemap for cells of type $reduce_or. |
| Using extmapper maccmap for cells of type $macc. |
| add { \pid.mul_ki.z3.z2.z2.result1 \pid.mul_ki.z1.z4.z4.temp1 } (2 bits, unsigned) |
| add { \pid.mul_ki.z3.z2.z1.result1 \pid.mul_ki.z1.z4.z3.temp1 } (2 bits, unsigned) |
| add { \pid.mul_ki.z3.z2.z1.result3 \pid.mul_ki.z3.z2.z1.result2 } (2 bits, unsigned) |
| Using extmapper simplemap for cells of type $ne. |
| Using extmapper simplemap for cells of type $reduce_bool. |
| Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_90_alu for cells of type $alu. |
| add \pid.mul_ki.z1.q4 (8 bits, unsigned) |
| add { \pid.mul_ki.z1.z3.q6 \pid.mul_ki.z1.z3.z1.result1 \pid.mul_ki.z1.z3.z1.result0 } (8 bits, unsigned) |
| add { \pid.mul_ki.z1.z4.q6 \pid.mul_ki.z1.z4.z1.result1 \pid.mul_ki.z1.z4.z1.result0 4'0000 } (12 bits, unsigned) |
| Using template $paramod$b9513f2555ba02118b069422fea717af39120cf7\_90_alu for cells of type $alu. |
| add \pid.mul_kp.z1.z1.q4 (4 bits, unsigned) |
| add { \pid.mul_kp.z1.z1.z3.result3 \pid.mul_kp.z1.z1.z3.result2 \pid.mul_kp.z1.z1.z3.result1 \pid.mul_kp.z1.z1.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_kp.z1.z1.z4.result3 \pid.mul_kp.z1.z1.z4.result2 \pid.mul_kp.z1.z1.z4.result1 \pid.mul_kp.z1.z1.z4.result0 2'00 } (6 bits, unsigned) |
| add { \pid.mul_kd.z3.z1.z2.result1 \pid.mul_kd.z1.z3.z4.temp1 } (2 bits, unsigned) |
| add { \pid.mul_kd.z3.z1.z1.result1 \pid.mul_kd.z1.z3.z3.temp1 } (2 bits, unsigned) |
| add { \pid.mul_kd.z3.z1.z1.result3 \pid.mul_kd.z3.z1.z1.result2 } (2 bits, unsigned) |
| Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_90_alu for cells of type $alu. |
| add \pid.mul_ki.z1.z4.q4 (4 bits, unsigned) |
| add { \pid.mul_ki.z1.z4.z3.result3 \pid.mul_ki.z1.z4.z3.result2 \pid.mul_ki.z1.z4.z3.result1 \pid.mul_ki.z1.z4.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_ki.z1.z4.z4.result3 \pid.mul_ki.z1.z4.z4.result2 \pid.mul_ki.z1.z4.z4.result1 \pid.mul_ki.z1.z4.z4.result0 2'00 } (6 bits, unsigned) |
| add \pid.mul_kp.z2.z1.q4 (4 bits, unsigned) |
| add { \pid.mul_kp.z2.z1.z3.result3 \pid.mul_kp.z2.z1.z3.result2 \pid.mul_kp.z2.z1.z3.result1 \pid.mul_kp.z2.z1.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_kp.z2.z1.z4.result3 \pid.mul_kp.z2.z1.z4.result2 \pid.mul_kp.z2.z1.z4.result1 \pid.mul_kp.z2.z1.z4.result0 2'00 } (6 bits, unsigned) |
| add { \pid.mul_kd.z3.z2.z2.result1 \pid.mul_kd.z1.z4.z4.temp1 } (2 bits, unsigned) |
| add { \pid.mul_kd.z3.z2.z1.result1 \pid.mul_kd.z1.z4.z3.temp1 } (2 bits, unsigned) |
| add { \pid.mul_kd.z3.z2.z1.result3 \pid.mul_kd.z3.z2.z1.result2 } (2 bits, unsigned) |
| add \pid.mul_ki.z1.z1.q4 (4 bits, unsigned) |
| add { \pid.mul_ki.z1.z1.z3.result3 \pid.mul_ki.z1.z1.z3.result2 \pid.mul_ki.z1.z1.z3.result1 \pid.mul_ki.z1.z1.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_ki.z1.z1.z4.result3 \pid.mul_ki.z1.z1.z4.result2 \pid.mul_ki.z1.z1.z4.result1 \pid.mul_ki.z1.z1.z4.result0 2'00 } (6 bits, unsigned) |
| add { \pid.mul_kp.z3.z1.z2.result1 \pid.mul_kp.z1.z3.z4.temp1 } (2 bits, unsigned) |
| add { \pid.mul_kp.z3.z1.z1.result1 \pid.mul_kp.z1.z3.z3.temp1 } (2 bits, unsigned) |
| add { \pid.mul_kp.z3.z1.z1.result3 \pid.mul_kp.z3.z1.z1.result2 } (2 bits, unsigned) |
| Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. |
| add { \pid.mul_kp.z2.z3.z2.result1 \pid.mul_kp.z2.z3.z2.result0 } (2 bits, unsigned) |
| add { \pid.mul_kp.z2.z3.z3.result1 \pid.mul_kp.z2.z3.z3.result0 } (2 bits, unsigned) |
| add { \pid.mul_kp.z2.z3.z1.result3 \pid.mul_kp.z2.z3.z1.result2 } (2 bits, unsigned) |
| add \pid.mul_ki.z1.z2.q4 (4 bits, unsigned) |
| add { \pid.mul_ki.z1.z2.z3.result3 \pid.mul_ki.z1.z2.z3.result2 \pid.mul_ki.z1.z2.z3.result1 \pid.mul_ki.z1.z2.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_ki.z1.z2.z4.result3 \pid.mul_ki.z1.z2.z4.result2 \pid.mul_ki.z1.z2.z4.result1 \pid.mul_ki.z1.z2.z4.result0 2'00 } (6 bits, unsigned) |
| add { \pid.mul_kp.z3.z2.q6 [1:0] \pid.mul_kp.z3.z2.z1.result1 \pid.mul_kp.z1.z4.z3.temp1 } (4 bits, unsigned) |
| add { \pid.mul_kp.z3.z3.q6 [1:0] \pid.mul_kp.z3.z1.z1.result1 \pid.mul_kp.z1.z3.z3.temp1 } (4 bits, unsigned) |
| add \pid.mul_kp.z3.z1.q6 [5:2] (4 bits, unsigned) |
| add { \pid.mul_ki.z3.z1.z2.result1 \pid.mul_ki.z1.z3.z4.temp1 } (2 bits, unsigned) |
| add { \pid.mul_ki.z3.z1.z1.result1 \pid.mul_ki.z1.z3.z3.temp1 } (2 bits, unsigned) |
| add { \pid.mul_ki.z3.z1.z1.result3 \pid.mul_ki.z3.z1.z1.result2 } (2 bits, unsigned) |
| add \pid.mul_kp.z3.z1.q4 (4 bits, unsigned) |
| add { \pid.mul_kp.z3.z1.z1.result3 \pid.mul_kp.z3.z1.z1.result2 \pid.mul_kp.z3.z1.z1.result1 \pid.mul_kp.z1.z3.z3.temp1 } (4 bits, unsigned) |
| add { \pid.mul_kp.z3.z1.z2.result3 \pid.mul_kp.z3.z1.z2.result2 \pid.mul_kp.z3.z1.z2.result1 \pid.mul_kp.z1.z3.z4.temp1 2'00 } (6 bits, unsigned) |
| add \pid.mul_kp.z1.z2.q4 (4 bits, unsigned) |
| add { \pid.mul_kp.z1.z2.z3.result3 \pid.mul_kp.z1.z2.z3.result2 \pid.mul_kp.z1.z2.z3.result1 \pid.mul_kp.z1.z2.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_kp.z1.z2.z4.result3 \pid.mul_kp.z1.z2.z4.result2 \pid.mul_kp.z1.z2.z4.result1 \pid.mul_kp.z1.z2.z4.result0 2'00 } (6 bits, unsigned) |
| add \pid.mul_kd.z1.z4.q4 (4 bits, unsigned) |
| add { \pid.mul_kd.z1.z4.z3.result3 \pid.mul_kd.z1.z4.z3.result2 \pid.mul_kd.z1.z4.z3.result1 \pid.mul_kd.z1.z4.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_kd.z1.z4.z4.result3 \pid.mul_kd.z1.z4.z4.result2 \pid.mul_kd.z1.z4.z4.result1 \pid.mul_kd.z1.z4.z4.result0 2'00 } (6 bits, unsigned) |
| add \pid.mul_kp.z1.q4 (8 bits, unsigned) |
| add { \pid.mul_kp.z1.z3.q6 \pid.mul_kp.z1.z3.z1.result1 \pid.mul_kp.z1.z3.z1.result0 } (8 bits, unsigned) |
| add { \pid.mul_kp.z1.z4.q6 \pid.mul_kp.z1.z4.z1.result1 \pid.mul_kp.z1.z4.z1.result0 4'0000 } (12 bits, unsigned) |
| add \pid.mul_kd.z1.z3.q4 (4 bits, unsigned) |
| add { \pid.mul_kd.z1.z3.z3.result3 \pid.mul_kd.z1.z3.z3.result2 \pid.mul_kd.z1.z3.z3.result1 \pid.mul_kd.z1.z3.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_kd.z1.z3.z4.result3 \pid.mul_kd.z1.z3.z4.result2 \pid.mul_kd.z1.z3.z4.result1 \pid.mul_kd.z1.z3.z4.result0 2'00 } (6 bits, unsigned) |
| add { \pid.mul_ki.z2.q6 [3:0] \pid.mul_ki.z2.z1.q6 [1:0] \pid.mul_ki.z2.z1.z1.result1 \pid.mul_ki.z2.z1.z1.result0 } (8 bits, unsigned) |
| add { \pid.mul_ki.z3.q6 [3:0] \pid.mul_ki.z3.z1.q6 [1:0] \pid.mul_ki.z3.z1.z1.result1 \pid.mul_ki.z1.z3.z3.temp1 } (8 bits, unsigned) |
| add \pid.mul_ki.z1.q6 [11:4] (8 bits, unsigned) |
| add { \pid.mul_kp.z3.z2.z2.result1 \pid.mul_kp.z1.z4.z4.temp1 } (2 bits, unsigned) |
| add { \pid.mul_kp.z3.z2.z1.result1 \pid.mul_kp.z1.z4.z3.temp1 } (2 bits, unsigned) |
| add { \pid.mul_kp.z3.z2.z1.result3 \pid.mul_kp.z3.z2.z1.result2 } (2 bits, unsigned) |
| add { \pid.mul_kp.z2.z2.q6 [1:0] \pid.mul_kp.z2.z2.z1.result1 \pid.mul_kp.z2.z2.z1.result0 } (4 bits, unsigned) |
| add { \pid.mul_kp.z2.z3.q6 [1:0] \pid.mul_kp.z2.z3.z1.result1 \pid.mul_kp.z2.z3.z1.result0 } (4 bits, unsigned) |
| add \pid.mul_kp.z2.z1.q6 [5:2] (4 bits, unsigned) |
| add \pid.mul_kd.z3.z1.q4 (4 bits, unsigned) |
| add { \pid.mul_kd.z3.z1.z1.result3 \pid.mul_kd.z3.z1.z1.result2 \pid.mul_kd.z3.z1.z1.result1 \pid.mul_kd.z1.z3.z3.temp1 } (4 bits, unsigned) |
| add { \pid.mul_kd.z3.z1.z2.result3 \pid.mul_kd.z3.z1.z2.result2 \pid.mul_kd.z3.z1.z2.result1 \pid.mul_kd.z1.z3.z4.temp1 2'00 } (6 bits, unsigned) |
| add \pid.mul_kp.z1.z4.q4 (4 bits, unsigned) |
| add { \pid.mul_kp.z1.z4.z3.result3 \pid.mul_kp.z1.z4.z3.result2 \pid.mul_kp.z1.z4.z3.result1 \pid.mul_kp.z1.z4.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_kp.z1.z4.z4.result3 \pid.mul_kp.z1.z4.z4.result2 \pid.mul_kp.z1.z4.z4.result1 \pid.mul_kp.z1.z4.z4.result0 2'00 } (6 bits, unsigned) |
| add { \pid.mul_kd.z2.q6 [3:0] \pid.mul_kd.z2.z1.q6 [1:0] \pid.mul_kd.z2.z1.z1.result1 \pid.mul_kd.z2.z1.z1.result0 } (8 bits, unsigned) |
| add { \pid.mul_kd.z3.q6 [3:0] \pid.mul_kd.z3.z1.q6 [1:0] \pid.mul_kd.z3.z1.z1.result1 \pid.mul_kd.z1.z3.z3.temp1 } (8 bits, unsigned) |
| add \pid.mul_kd.z1.q6 [11:4] (8 bits, unsigned) |
| add \pid.mul_kd.z1.q4 (8 bits, unsigned) |
| add { \pid.mul_kd.z1.z3.q6 \pid.mul_kd.z1.z3.z1.result1 \pid.mul_kd.z1.z3.z1.result0 } (8 bits, unsigned) |
| add { \pid.mul_kd.z1.z4.q6 \pid.mul_kd.z1.z4.z1.result1 \pid.mul_kd.z1.z4.z1.result0 4'0000 } (12 bits, unsigned) |
| add \pid.mul_ki.z2.z1.q4 (4 bits, unsigned) |
| add { \pid.mul_ki.z2.z1.z3.result3 \pid.mul_ki.z2.z1.z3.result2 \pid.mul_ki.z2.z1.z3.result1 \pid.mul_ki.z2.z1.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_ki.z2.z1.z4.result3 \pid.mul_ki.z2.z1.z4.result2 \pid.mul_ki.z2.z1.z4.result1 \pid.mul_ki.z2.z1.z4.result0 2'00 } (6 bits, unsigned) |
| add { \pid.mul_kd.z3.z2.q6 [1:0] \pid.mul_kd.z3.z2.z1.result1 \pid.mul_kd.z1.z4.z3.temp1 } (4 bits, unsigned) |
| add { \pid.mul_kd.z3.z3.q6 [1:0] \pid.mul_kd.z3.z1.z1.result1 \pid.mul_kd.z1.z3.z3.temp1 } (4 bits, unsigned) |
| add \pid.mul_kd.z3.z1.q6 [5:2] (4 bits, unsigned) |
| add { \pid.mul_kd.z2.z3.z2.result1 \pid.mul_kd.z2.z3.z2.result0 } (2 bits, unsigned) |
| add { \pid.mul_kd.z2.z3.z3.result1 \pid.mul_kd.z2.z3.z3.result0 } (2 bits, unsigned) |
| add { \pid.mul_kd.z2.z3.z1.result3 \pid.mul_kd.z2.z3.z1.result2 } (2 bits, unsigned) |
| add { \pid.mul_ki.z2.z3.z2.result1 \pid.mul_ki.z2.z3.z2.result0 } (2 bits, unsigned) |
| add { \pid.mul_ki.z2.z3.z3.result1 \pid.mul_ki.z2.z3.z3.result0 } (2 bits, unsigned) |
| add { \pid.mul_ki.z2.z3.z1.result3 \pid.mul_ki.z2.z3.z1.result2 } (2 bits, unsigned) |
| add { \pid.mul_kp.z2.q6 [3:0] \pid.mul_kp.z2.z1.q6 [1:0] \pid.mul_kp.z2.z1.z1.result1 \pid.mul_kp.z2.z1.z1.result0 } (8 bits, unsigned) |
| add { \pid.mul_kp.z3.q6 [3:0] \pid.mul_kp.z3.z1.q6 [1:0] \pid.mul_kp.z3.z1.z1.result1 \pid.mul_kp.z1.z3.z3.temp1 } (8 bits, unsigned) |
| add \pid.mul_kp.z1.q6 [11:4] (8 bits, unsigned) |
| add \pid.mul_kd.z2.z1.q4 (4 bits, unsigned) |
| add { \pid.mul_kd.z2.z1.z3.result3 \pid.mul_kd.z2.z1.z3.result2 \pid.mul_kd.z2.z1.z3.result1 \pid.mul_kd.z2.z1.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_kd.z2.z1.z4.result3 \pid.mul_kd.z2.z1.z4.result2 \pid.mul_kd.z2.z1.z4.result1 \pid.mul_kd.z2.z1.z4.result0 2'00 } (6 bits, unsigned) |
| add \pid.mul_ki.z3.z1.q4 (4 bits, unsigned) |
| add { \pid.mul_ki.z3.z1.z1.result3 \pid.mul_ki.z3.z1.z1.result2 \pid.mul_ki.z3.z1.z1.result1 \pid.mul_ki.z1.z3.z3.temp1 } (4 bits, unsigned) |
| add { \pid.mul_ki.z3.z1.z2.result3 \pid.mul_ki.z3.z1.z2.result2 \pid.mul_ki.z3.z1.z2.result1 \pid.mul_ki.z1.z3.z4.temp1 2'00 } (6 bits, unsigned) |
| add \pid.mul_ki.z1.z3.q4 (4 bits, unsigned) |
| add { \pid.mul_ki.z1.z3.z3.result3 \pid.mul_ki.z1.z3.z3.result2 \pid.mul_ki.z1.z3.z3.result1 \pid.mul_ki.z1.z3.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_ki.z1.z3.z4.result3 \pid.mul_ki.z1.z3.z4.result2 \pid.mul_ki.z1.z3.z4.result1 \pid.mul_ki.z1.z3.z4.result0 2'00 } (6 bits, unsigned) |
| add \pid.mul_kd.z1.z1.q4 (4 bits, unsigned) |
| add { \pid.mul_kd.z1.z1.z3.result3 \pid.mul_kd.z1.z1.z3.result2 \pid.mul_kd.z1.z1.z3.result1 \pid.mul_kd.z1.z1.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_kd.z1.z1.z4.result3 \pid.mul_kd.z1.z1.z4.result2 \pid.mul_kd.z1.z1.z4.result1 \pid.mul_kd.z1.z1.z4.result0 2'00 } (6 bits, unsigned) |
| add { \pid.mul_kp.z2.z2.z2.result1 \pid.mul_kp.z2.z2.z2.result0 } (2 bits, unsigned) |
| add { \pid.mul_kp.z2.z2.z3.result1 \pid.mul_kp.z2.z2.z3.result0 } (2 bits, unsigned) |
| add { \pid.mul_kp.z2.z2.z1.result3 \pid.mul_kp.z2.z2.z1.result2 } (2 bits, unsigned) |
| add { \pid.mul_kd.z2.z2.q6 [1:0] \pid.mul_kd.z2.z2.z1.result1 \pid.mul_kd.z2.z2.z1.result0 } (4 bits, unsigned) |
| add { \pid.mul_kd.z2.z3.q6 [1:0] \pid.mul_kd.z2.z3.z1.result1 \pid.mul_kd.z2.z3.z1.result0 } (4 bits, unsigned) |
| add \pid.mul_kd.z2.z1.q6 [5:2] (4 bits, unsigned) |
| add { \pid.mul_ki.z2.z2.q6 [1:0] \pid.mul_ki.z2.z2.z1.result1 \pid.mul_ki.z2.z2.z1.result0 } (4 bits, unsigned) |
| add { \pid.mul_ki.z2.z3.q6 [1:0] \pid.mul_ki.z2.z3.z1.result1 \pid.mul_ki.z2.z3.z1.result0 } (4 bits, unsigned) |
| add \pid.mul_ki.z2.z1.q6 [5:2] (4 bits, unsigned) |
| add { \pid.mul_ki.z2.z2.z2.result1 \pid.mul_ki.z2.z2.z2.result0 } (2 bits, unsigned) |
| add { \pid.mul_ki.z2.z2.z3.result1 \pid.mul_ki.z2.z2.z3.result0 } (2 bits, unsigned) |
| add { \pid.mul_ki.z2.z2.z1.result3 \pid.mul_ki.z2.z2.z1.result2 } (2 bits, unsigned) |
| add \pid.mul_kp.z1.z3.q4 (4 bits, unsigned) |
| add { \pid.mul_kp.z1.z3.z3.result3 \pid.mul_kp.z1.z3.z3.result2 \pid.mul_kp.z1.z3.z3.result1 \pid.mul_kp.z1.z3.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_kp.z1.z3.z4.result3 \pid.mul_kp.z1.z3.z4.result2 \pid.mul_kp.z1.z3.z4.result1 \pid.mul_kp.z1.z3.z4.result0 2'00 } (6 bits, unsigned) |
| add { \pid.mul_kd.z2.z2.z2.result1 \pid.mul_kd.z2.z2.z2.result0 } (2 bits, unsigned) |
| add { \pid.mul_kd.z2.z2.z3.result1 \pid.mul_kd.z2.z2.z3.result0 } (2 bits, unsigned) |
| add { \pid.mul_kd.z2.z2.z1.result3 \pid.mul_kd.z2.z2.z1.result2 } (2 bits, unsigned) |
| add { \pid.mul_ki.z3.z2.q6 [1:0] \pid.mul_ki.z3.z2.z1.result1 \pid.mul_ki.z1.z4.z3.temp1 } (4 bits, unsigned) |
| add { \pid.mul_ki.z3.z3.q6 [1:0] \pid.mul_ki.z3.z1.z1.result1 \pid.mul_ki.z1.z3.z3.temp1 } (4 bits, unsigned) |
| add \pid.mul_ki.z3.z1.q6 [5:2] (4 bits, unsigned) |
| add \pid.mul_kd.z1.z2.q4 (4 bits, unsigned) |
| add { \pid.mul_kd.z1.z2.z3.result3 \pid.mul_kd.z1.z2.z3.result2 \pid.mul_kd.z1.z2.z3.result1 \pid.mul_kd.z1.z2.z3.result0 } (4 bits, unsigned) |
| add { \pid.mul_kd.z1.z2.z4.result3 \pid.mul_kd.z1.z2.z4.result2 \pid.mul_kd.z1.z2.z4.result1 \pid.mul_kd.z1.z2.z4.result0 2'00 } (6 bits, unsigned) |
| Using extmapper simplemap for cells of type $pos. |
| Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000010000 for cells of type $lcu. |
| Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000110 for cells of type $fa. |
| Using template $paramod$00298f3f8094950cb9a5ff2fda48d0d8bde8806c\_90_alu for cells of type $alu. |
| Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. |
| Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa. |
| Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu. |
| Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa. |
| Using template $paramod$740b056ede97228d3eae64ea2fdc81f0a33e0fe7\_90_alu for cells of type $alu. |
| Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001000 for cells of type $lcu. |
| Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000001100 for cells of type $fa. |
| Using template $paramod$ee3d784672cdb1cb32d9a801a3af776716f16b74\_90_alu for cells of type $alu. |
| Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000001000 for cells of type $fa. |
| Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\_90_alu for cells of type $alu. |
| Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000100000 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000011111 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000110 for cells of type $lcu. |
| Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000001100 for cells of type $lcu. |
| No more expansions possible. |
| <suppressed ~6757 debug messages> |
| |
| 6.22. Executing OPT pass (performing simple optimizations). |
| |
| 6.22.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| <suppressed ~3720 debug messages> |
| |
| 6.22.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| <suppressed ~987 debug messages> |
| Removed a total of 329 cells. |
| |
| 6.22.3. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.22.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| Removed 1164 unused cells and 4051 unused wires. |
| <suppressed ~1165 debug messages> |
| |
| 6.22.5. Finished fast OPT passes. |
| |
| 6.23. Executing ABC pass (technology mapping using ABC). |
| |
| 6.23.1. Extracting gate netlist of module `\Motor_Top' to `<abc-temp-dir>/input.blif'.. |
| Extracted 6223 gates and 6685 wires to a netlist network with 461 inputs and 299 outputs. |
| |
| 6.23.1.1. Executing ABC. |
| Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1 |
| ABC: ABC command line: "source <abc-temp-dir>/abc.script". |
| ABC: |
| ABC: + read_blif <abc-temp-dir>/input.blif |
| ABC: + read_library <abc-temp-dir>/stdcells.genlib |
| ABC: Entered genlib library with 13 gates from file "<abc-temp-dir>/stdcells.genlib". |
| ABC: + strash |
| ABC: + dretime |
| ABC: + map |
| ABC: + write_blif <abc-temp-dir>/output.blif |
| |
| 6.23.1.2. Re-integrating ABC results. |
| ABC RESULTS: AND cells: 146 |
| ABC RESULTS: ANDNOT cells: 2058 |
| ABC RESULTS: MUX cells: 552 |
| ABC RESULTS: NAND cells: 238 |
| ABC RESULTS: NOR cells: 396 |
| ABC RESULTS: NOT cells: 373 |
| ABC RESULTS: OR cells: 510 |
| ABC RESULTS: ORNOT cells: 195 |
| ABC RESULTS: XNOR cells: 426 |
| ABC RESULTS: XOR cells: 1097 |
| ABC RESULTS: internal signals: 5925 |
| ABC RESULTS: input signals: 461 |
| ABC RESULTS: output signals: 299 |
| Removing temp directory. |
| |
| 6.24. Executing OPT pass (performing simple optimizations). |
| |
| 6.24.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| <suppressed ~124 debug messages> |
| |
| 6.24.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| <suppressed ~147 debug messages> |
| Removed a total of 49 cells. |
| |
| 6.24.3. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 6.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| Removed 3 unused cells and 4099 unused wires. |
| <suppressed ~1664 debug messages> |
| |
| 6.24.5. Finished fast OPT passes. |
| |
| 6.25. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 6.25.1. Analyzing design hierarchy.. |
| Top module: \Motor_Top |
| |
| 6.25.2. Analyzing design hierarchy.. |
| Top module: \Motor_Top |
| Removed 0 unused modules. |
| |
| 6.26. Printing statistics. |
| |
| === Motor_Top === |
| |
| Number of wires: 8032 |
| Number of wire bits: 17054 |
| Number of public wires: 2141 |
| Number of public wire bits: 11163 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 6387 |
| $_ANDNOT_ 2057 |
| $_AND_ 146 |
| $_DFF_P_ 35 |
| $_MUX_ 552 |
| $_NAND_ 238 |
| $_NOR_ 348 |
| $_NOT_ 370 |
| $_ORNOT_ 195 |
| $_OR_ 510 |
| $_SDFFE_PP0P_ 331 |
| $_SDFFE_PP1P_ 27 |
| $_SDFF_PP0_ 55 |
| $_XNOR_ 426 |
| $_XOR_ 1097 |
| |
| 6.27. Executing CHECK pass (checking for obvious problems). |
| Checking module Motor_Top... |
| Found and reported 0 problems. |
| |
| 7. Generating Graphviz representation of design. |
| Writing dot description to `/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/synthesis/post_techmap.dot'. |
| Dumping module Motor_Top to page 1. |
| |
| 8. Executing SHARE pass (SAT-based resource sharing). |
| |
| 9. Executing OPT pass (performing simple optimizations). |
| |
| 9.1. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| |
| 9.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| Removed a total of 0 cells. |
| |
| 9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \Motor_Top.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \Motor_Top. |
| Performed a total of 0 changes. |
| |
| 9.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\Motor_Top'. |
| Removed a total of 0 cells. |
| |
| 9.6. Executing OPT_DFF pass (perform DFF optimizations). |
| |
| 9.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| |
| 9.8. Executing OPT_EXPR pass (perform const folding). |
| Optimizing module Motor_Top. |
| |
| 9.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 10. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| Removed 0 unused cells and 2046 unused wires. |
| <suppressed ~2046 debug messages> |
| |
| 11. Printing statistics. |
| |
| === Motor_Top === |
| |
| Number of wires: 5986 |
| Number of wire bits: 6481 |
| Number of public wires: 95 |
| Number of public wire bits: 590 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 6387 |
| $_ANDNOT_ 2057 |
| $_AND_ 146 |
| $_DFF_P_ 35 |
| $_MUX_ 552 |
| $_NAND_ 238 |
| $_NOR_ 348 |
| $_NOT_ 370 |
| $_ORNOT_ 195 |
| $_OR_ 510 |
| $_SDFFE_PP0P_ 331 |
| $_SDFFE_PP1P_ 27 |
| $_SDFF_PP0_ 55 |
| $_XNOR_ 426 |
| $_XOR_ 1097 |
| |
| mapping tbuf |
| |
| 12. Executing TECHMAP pass (map to technology primitives). |
| |
| 12.1. Executing Verilog-2005 frontend: /home/ali112000/Desktop/mpw/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v |
| Parsing Verilog input from `/home/ali112000/Desktop/mpw/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v' to AST representation. |
| Generating RTLIL representation for module `\$_TBUF_'. |
| Successfully finished Verilog frontend. |
| |
| 12.2. Continuing TECHMAP pass. |
| No more expansions possible. |
| <suppressed ~3 debug messages> |
| |
| 13. Executing SIMPLEMAP pass (map simple cells to gate primitives). |
| |
| 14. Executing TECHMAP pass (map to technology primitives). |
| |
| 14.1. Executing Verilog-2005 frontend: /home/ali112000/Desktop/mpw/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v |
| Parsing Verilog input from `/home/ali112000/Desktop/mpw/pdk/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v' to AST representation. |
| Generating RTLIL representation for module `\$_DLATCH_P_'. |
| Generating RTLIL representation for module `\$_DLATCH_N_'. |
| Successfully finished Verilog frontend. |
| |
| 14.2. Continuing TECHMAP pass. |
| No more expansions possible. |
| <suppressed ~4 debug messages> |
| |
| 15. Executing SIMPLEMAP pass (map simple cells to gate primitives). |
| |
| 16. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). |
| cell sky130_fd_sc_hd__dfxtp_2 (noninv, pins=3, area=21.27) is a direct match for cell type $_DFF_P_. |
| cell sky130_fd_sc_hd__dfrtp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN0_. |
| cell sky130_fd_sc_hd__dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_. |
| cell sky130_fd_sc_hd__dfbbn_2 (noninv, pins=6, area=35.03) is a direct match for cell type $_DFFSR_NNN_. |
| final dff cell mappings: |
| unmapped dff cell: $_DFF_N_ |
| \sky130_fd_sc_hd__dfxtp_2 _DFF_P_ (.CLK( C), .D( D), .Q( Q)); |
| unmapped dff cell: $_DFF_NN0_ |
| unmapped dff cell: $_DFF_NN1_ |
| unmapped dff cell: $_DFF_NP0_ |
| unmapped dff cell: $_DFF_NP1_ |
| \sky130_fd_sc_hd__dfrtp_2 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESET_B( R)); |
| \sky130_fd_sc_hd__dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SET_B( R)); |
| unmapped dff cell: $_DFF_PP0_ |
| unmapped dff cell: $_DFF_PP1_ |
| \sky130_fd_sc_hd__dfbbn_2 _DFFSR_NNN_ (.CLK_N( C), .D( D), .Q( Q), .Q_N(~Q), .RESET_B( R), .SET_B( S)); |
| unmapped dff cell: $_DFFSR_NNP_ |
| unmapped dff cell: $_DFFSR_NPN_ |
| unmapped dff cell: $_DFFSR_NPP_ |
| unmapped dff cell: $_DFFSR_PNN_ |
| unmapped dff cell: $_DFFSR_PNP_ |
| unmapped dff cell: $_DFFSR_PPN_ |
| unmapped dff cell: $_DFFSR_PPP_ |
| |
| 16.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). |
| Mapping DFF cells in module `\Motor_Top': |
| mapped 448 $_DFF_P_ cells to \sky130_fd_sc_hd__dfxtp_2 cells. |
| |
| 17. Printing statistics. |
| |
| === Motor_Top === |
| |
| Number of wires: 6757 |
| Number of wire bits: 7252 |
| Number of public wires: 95 |
| Number of public wire bits: 590 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 7158 |
| $_ANDNOT_ 2057 |
| $_AND_ 146 |
| $_MUX_ 1323 |
| $_NAND_ 238 |
| $_NOR_ 348 |
| $_NOT_ 370 |
| $_ORNOT_ 195 |
| $_OR_ 510 |
| $_XNOR_ 426 |
| $_XOR_ 1097 |
| sky130_fd_sc_hd__dfxtp_2 448 |
| |
| [INFO]: ABC: WireLoad : S_4 |
| |
| 18. Executing ABC pass (technology mapping using ABC). |
| |
| 18.1. Extracting gate netlist of module `\Motor_Top' to `/tmp/yosys-abc-CI9urH/input.blif'.. |
| Extracted 6710 gates and 7178 wires to a netlist network with 466 inputs and 449 outputs. |
| |
| 18.1.1. Executing ABC. |
| Running ABC command: /build/bin/yosys-abc -s -f /tmp/yosys-abc-CI9urH/abc.script 2>&1 |
| ABC: ABC command line: "source /tmp/yosys-abc-CI9urH/abc.script". |
| ABC: |
| ABC: + read_blif /tmp/yosys-abc-CI9urH/input.blif |
| ABC: + read_lib -w /home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/synthesis/trimmed.lib |
| ABC: Parsing finished successfully. Parsing time = 0.07 sec |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfbbn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfrtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfsbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfstp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxbp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dfxtp_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_1". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_2". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtn_4". |
| ABC: Scl_LibertyReadGenlib() skipped sequential cell "sky130_fd_sc_hd__dlxtp_1". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_2". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_4". |
| ABC: Scl_LibertyReadGenlib() skipped three-state cell "sky130_fd_sc_hd__ebufn_8". |
| ABC: Library "sky130A_merged" from "/home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/synthesis/trimmed.lib" has 175 cells (17 skipped: 14 seq; 3 tri-state; 0 no func; 0 dont_use). Time = 0.10 sec |
| ABC: Memory = 7.77 MB. Time = 0.10 sec |
| ABC: Warning: Detected 2 multi-output gates (for example, "sky130_fd_sc_hd__fa_1"). |
| ABC: + read_constr -v /home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/synthesis/synthesis.sdc |
| ABC: Setting driving cell to be "sky130_fd_sc_hd__inv_2". |
| ABC: Setting output load to be 33.442001. |
| ABC: + read_constr /home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/synthesis/synthesis.sdc |
| ABC: + fx |
| ABC: + mfs |
| ABC: + strash |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + retime -D -D 20000 -M 5 |
| ABC: + scleanup |
| ABC: Error: The network is combinational. |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + refactor |
| ABC: + balance |
| ABC: + rewrite |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + refactor -z |
| ABC: + rewrite -z |
| ABC: + balance |
| ABC: + fraig_store |
| ABC: + fraig_restore |
| ABC: + amap -m -Q 0.1 -F 20 -A 20 -C 5000 |
| ABC: + retime -D -D 20000 |
| ABC: + &get -n |
| ABC: + &st |
| ABC: + &dch |
| ABC: + &nf |
| ABC: + &put |
| ABC: + buffer -N 5 -S 750.0 |
| ABC: + upsize -D 20000 |
| ABC: Current delay (10896.84 ps) does not exceed the target delay (20000.00 ps). Upsizing is not performed. |
| ABC: + dnsize -D 20000 |
| ABC: + stime -p |
| ABC: WireLoad = "none" Gates = 5310 ( 20.1 %) Cap = 9.7 ff ( 4.7 %) Area = 43999.70 ( 79.8 %) Delay = 10946.75 ps ( 4.6 %) |
| ABC: Path 0 -- 82 : 0 4 pi A = 0.00 Df = 67.5 -36.8 ps S = 100.4 ps Cin = 0.0 ff Cout = 20.7 ff Cmax = 0.0 ff G = 0 |
| ABC: Path 1 -- 1946 : 2 3 sky130_fd_sc_hd__xnor2_2 A = 16.27 Df = 253.1 -4.5 ps S = 222.1 ps Cin = 8.5 ff Cout = 13.3 ff Cmax = 121.8 ff G = 150 |
| ABC: Path 2 -- 1947 : 3 2 sky130_fd_sc_hd__or3b_2 A = 8.76 Df = 713.6 -190.0 ps S = 75.2 ps Cin = 1.5 ff Cout = 3.0 ff Cmax = 269.2 ff G = 184 |
| ABC: Path 3 -- 1950 : 3 1 sky130_fd_sc_hd__or3_2 A = 7.51 Df =1118.0 -503.3 ps S = 72.8 ps Cin = 1.5 ff Cout = 2.4 ff Cmax = 310.4 ff G = 149 |
| ABC: Path 4 -- 1951 : 5 2 sky130_fd_sc_hd__a311o_2 A = 11.26 Df =1490.9 -716.4 ps S = 65.7 ps Cin = 2.3 ff Cout = 7.2 ff Cmax = 298.5 ff G = 300 |
| ABC: Path 5 -- 1955 : 4 3 sky130_fd_sc_hd__a31o_2 A = 8.76 Df =1770.9 -800.1 ps S = 95.7 ps Cin = 2.4 ff Cout = 13.8 ff Cmax = 271.9 ff G = 560 |
| ABC: Path 6 -- 1970 : 5 3 sky130_fd_sc_hd__o311ai_2 A = 16.27 Df =2198.1-1058.7 ps S = 417.5 ps Cin = 4.4 ff Cout = 16.1 ff Cmax = 82.4 ff G = 347 |
| ABC: Path 7 -- 1971 : 5 2 sky130_fd_sc_hd__a221o_2 A = 11.26 Df =2434.5 -890.3 ps S = 64.9 ps Cin = 2.3 ff Cout = 7.1 ff Cmax = 299.4 ff G = 291 |
| ABC: Path 8 -- 1973 : 4 2 sky130_fd_sc_hd__a31o_2 A = 8.76 Df =2648.1 -814.2 ps S = 119.7 ps Cin = 2.4 ff Cout = 18.4 ff Cmax = 271.9 ff G = 749 |
| ABC: Path 9 -- 1988 : 2 4 sky130_fd_sc_hd__xor2_2 A = 16.27 Df =2869.2 -844.8 ps S = 169.7 ps Cin = 8.6 ff Cout = 9.8 ff Cmax = 130.0 ff G = 108 |
| ABC: Path 10 -- 1990 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df =3097.0 -918.9 ps S = 216.7 ps Cin = 2.1 ff Cout = 17.7 ff Cmax = 130.0 ff G = 796 |
| ABC: Path 11 -- 2005 : 2 2 sky130_fd_sc_hd__nor2_2 A = 6.26 Df =3151.3 -866.2 ps S = 88.1 ps Cin = 4.4 ff Cout = 5.1 ff Cmax = 141.9 ff G = 108 |
| ABC: Path 12 -- 2206 : 5 2 sky130_fd_sc_hd__o2111a_2 A = 12.51 Df =3465.4 -60.1 ps S = 65.2 ps Cin = 2.4 ff Cout = 7.1 ff Cmax = 299.4 ff G = 280 |
| ABC: Path 13 -- 2207 : 4 4 sky130_fd_sc_hd__a31o_2 A = 8.76 Df =3657.1 -38.1 ps S = 112.2 ps Cin = 2.4 ff Cout = 17.0 ff Cmax = 271.9 ff G = 702 |
| ABC: Path 14 -- 2209 : 3 2 sky130_fd_sc_hd__and3_2 A = 7.51 Df =3912.4 -45.3 ps S = 62.1 ps Cin = 1.5 ff Cout = 6.4 ff Cmax = 309.5 ff G = 407 |
| ABC: Path 15 -- 2211 : 3 3 sky130_fd_sc_hd__or3_2 A = 7.51 Df =4341.3 -299.6 ps S = 97.7 ps Cin = 1.5 ff Cout = 9.1 ff Cmax = 310.4 ff G = 574 |
| ABC: Path 16 -- 2218 : 3 2 sky130_fd_sc_hd__and3_2 A = 7.51 Df =4577.7 -349.4 ps S = 59.1 ps Cin = 1.5 ff Cout = 6.1 ff Cmax = 309.5 ff G = 393 |
| ABC: Path 17 -- 2241 : 3 3 sky130_fd_sc_hd__or3b_2 A = 8.76 Df =5066.2 -403.2 ps S = 97.2 ps Cin = 1.5 ff Cout = 8.5 ff Cmax = 269.2 ff G = 546 |
| ABC: Path 18 -- 2254 : 3 2 sky130_fd_sc_hd__a21o_2 A = 8.76 Df =5281.6 -350.7 ps S = 50.6 ps Cin = 2.4 ff Cout = 7.0 ff Cmax = 309.5 ff G = 288 |
| ABC: Path 19 -- 2258 : 3 3 sky130_fd_sc_hd__a21o_2 A = 8.76 Df =5505.6 -212.9 ps S = 61.7 ps Cin = 2.4 ff Cout = 9.6 ff Cmax = 309.5 ff G = 390 |
| ABC: Path 20 -- 2321 : 3 3 sky130_fd_sc_hd__a21o_2 A = 8.76 Df =5737.0 -226.5 ps S = 69.6 ps Cin = 2.4 ff Cout = 11.4 ff Cmax = 309.5 ff G = 461 |
| ABC: Path 21 -- 2323 : 3 2 sky130_fd_sc_hd__and3_2 A = 7.51 Df =5953.8 -173.4 ps S = 60.3 ps Cin = 1.5 ff Cout = 6.3 ff Cmax = 309.5 ff G = 401 |
| ABC: Path 22 -- 2327 : 3 2 sky130_fd_sc_hd__or3_2 A = 7.51 Df =6442.2 -408.6 ps S = 91.3 ps Cin = 1.5 ff Cout = 7.1 ff Cmax = 310.4 ff G = 449 |
| ABC: Path 23 -- 2329 : 3 3 sky130_fd_sc_hd__a21o_2 A = 8.76 Df =6690.0 -492.2 ps S = 68.8 ps Cin = 2.4 ff Cout = 11.2 ff Cmax = 309.5 ff G = 458 |
| ABC: Path 24 -- 2331 : 3 3 sky130_fd_sc_hd__a21oi_2 A = 8.76 Df =6861.9 -532.4 ps S = 144.6 ps Cin = 4.6 ff Cout = 8.8 ff Cmax = 128.2 ff G = 180 |
| ABC: Path 25 -- 2338 : 3 3 sky130_fd_sc_hd__o21a_2 A = 8.76 Df =7046.3 -449.7 ps S = 98.3 ps Cin = 2.4 ff Cout = 16.4 ff Cmax = 294.8 ff G = 660 |
| ABC: Path 26 -- 2343 : 3 2 sky130_fd_sc_hd__a21o_2 A = 8.76 Df =7201.8 -53.3 ps S = 68.3 ps Cin = 2.4 ff Cout = 10.9 ff Cmax = 309.5 ff G = 445 |
| ABC: Path 27 -- 2345 : 3 2 sky130_fd_sc_hd__a21o_2 A = 8.76 Df =7380.2 -28.7 ps S = 68.6 ps Cin = 2.4 ff Cout = 10.9 ff Cmax = 309.5 ff G = 445 |
| ABC: Path 28 -- 2347 : 3 2 sky130_fd_sc_hd__a21o_2 A = 8.76 Df =7620.4 -109.5 ps S = 80.3 ps Cin = 2.4 ff Cout = 13.5 ff Cmax = 309.5 ff G = 556 |
| ABC: Path 29 -- 2348 : 3 2 sky130_fd_sc_hd__a21oi_2 A = 8.76 Df =7805.5 -219.1 ps S = 159.3 ps Cin = 4.6 ff Cout = 10.2 ff Cmax = 128.2 ff G = 218 |
| ABC: Path 30 -- 2360 : 2 2 sky130_fd_sc_hd__or2b_2 A = 8.76 Df =7976.3 -55.2 ps S = 81.4 ps Cin = 1.6 ff Cout = 13.7 ff Cmax = 312.2 ff G = 836 |
| ABC: Path 31 -- 2371 : 2 2 sky130_fd_sc_hd__xnor2_2 A = 16.27 Df =8139.2 -4.1 ps S = 190.4 ps Cin = 8.5 ff Cout = 10.6 ff Cmax = 121.8 ff G = 120 |
| ABC: Path 32 -- 2513 : 2 2 sky130_fd_sc_hd__xnor2_2 A = 16.27 Df =8352.5 -4.6 ps S = 195.0 ps Cin = 8.5 ff Cout = 11.0 ff Cmax = 121.8 ff G = 125 |
| ABC: Path 33 -- 2514 : 2 2 sky130_fd_sc_hd__xnor2_2 A = 16.27 Df =8565.7 -2.2 ps S = 229.4 ps Cin = 8.5 ff Cout = 14.0 ff Cmax = 121.8 ff G = 157 |
| ABC: Path 34 -- 2524 : 2 2 sky130_fd_sc_hd__xor2_2 A = 16.27 Df =8858.8 -86.3 ps S = 217.5 ps Cin = 8.6 ff Cout = 14.0 ff Cmax = 130.0 ff G = 156 |
| ABC: Path 35 -- 2576 : 2 2 sky130_fd_sc_hd__xor2_2 A = 16.27 Df =9153.4 -6.4 ps S = 222.0 ps Cin = 8.6 ff Cout = 14.4 ff Cmax = 130.0 ff G = 161 |
| ABC: Path 36 -- 2607 : 2 2 sky130_fd_sc_hd__xor2_2 A = 16.27 Df =9443.0 -93.3 ps S = 213.2 ps Cin = 8.6 ff Cout = 13.6 ff Cmax = 130.0 ff G = 152 |
| ABC: Path 37 -- 3267 : 2 2 sky130_fd_sc_hd__xnor2_2 A = 16.27 Df =9673.7 -80.7 ps S = 230.8 ps Cin = 8.5 ff Cout = 14.1 ff Cmax = 121.8 ff G = 159 |
| ABC: Path 38 -- 3372 : 3 3 sky130_fd_sc_hd__o21ai_2 A = 8.76 Df =9911.5 -170.6 ps S = 220.2 ps Cin = 4.5 ff Cout = 16.0 ff Cmax = 139.2 ff G = 337 |
| ABC: Path 39 -- 3472 : 5 3 sky130_fd_sc_hd__a311o_2 A = 11.26 Df =10345.7 -215.3 ps S = 64.2 ps Cin = 2.3 ff Cout = 6.6 ff Cmax = 298.5 ff G = 275 |
| ABC: Path 40 -- 3473 : 1 5 sky130_fd_sc_hd__buf_1 A = 3.75 Df =10520.7 -144.1 ps S = 277.8 ps Cin = 2.1 ff Cout = 23.1 ff Cmax = 130.0 ff G = 1046 |
| ABC: Path 41 -- 3476 : 2 1 sky130_fd_sc_hd__nor2_2 A = 6.26 Df =10641.3 -199.5 ps S = 61.1 ps Cin = 4.4 ff Cout = 2.4 ff Cmax = 141.9 ff G = 52 |
| ABC: Path 42 -- 3480 : 5 1 sky130_fd_sc_hd__o221a_2 A = 11.26 Df =10946.8 -165.8 ps S = 196.2 ps Cin = 2.3 ff Cout = 33.4 ff Cmax = 281.1 ff G = 1424 |
| ABC: Start-point = pi81 (\pid.sigma_old [6]). End-point = po78 ($auto$rtlil.cc:2515:MuxGate$20195). |
| ABC: + print_stats -m |
| ABC: netlist : i/o = 466/ 449 lat = 0 nd = 5310 edge = 12815 area =44005.66 delay =46.00 lev = 46 |
| ABC: + write_blif /tmp/yosys-abc-CI9urH/output.blif |
| |
| 18.1.2. Re-integrating ABC results. |
| ABC RESULTS: sky130_fd_sc_hd__a2111o_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a2111oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a211o_2 cells: 24 |
| ABC RESULTS: sky130_fd_sc_hd__a211oi_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__a21bo_2 cells: 48 |
| ABC RESULTS: sky130_fd_sc_hd__a21boi_2 cells: 8 |
| ABC RESULTS: sky130_fd_sc_hd__a21o_2 cells: 104 |
| ABC RESULTS: sky130_fd_sc_hd__a21oi_2 cells: 168 |
| ABC RESULTS: sky130_fd_sc_hd__a221o_2 cells: 81 |
| ABC RESULTS: sky130_fd_sc_hd__a221oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a22o_2 cells: 148 |
| ABC RESULTS: sky130_fd_sc_hd__a22oi_2 cells: 27 |
| ABC RESULTS: sky130_fd_sc_hd__a2bb2o_2 cells: 45 |
| ABC RESULTS: sky130_fd_sc_hd__a2bb2oi_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__a311o_2 cells: 13 |
| ABC RESULTS: sky130_fd_sc_hd__a311oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a31o_2 cells: 66 |
| ABC RESULTS: sky130_fd_sc_hd__a31oi_2 cells: 6 |
| ABC RESULTS: sky130_fd_sc_hd__a32o_2 cells: 37 |
| ABC RESULTS: sky130_fd_sc_hd__a32oi_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__a41o_2 cells: 7 |
| ABC RESULTS: sky130_fd_sc_hd__and2_2 cells: 270 |
| ABC RESULTS: sky130_fd_sc_hd__and2b_2 cells: 110 |
| ABC RESULTS: sky130_fd_sc_hd__and3_2 cells: 166 |
| ABC RESULTS: sky130_fd_sc_hd__and3b_2 cells: 20 |
| ABC RESULTS: sky130_fd_sc_hd__and4_2 cells: 26 |
| ABC RESULTS: sky130_fd_sc_hd__and4b_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__and4bb_2 cells: 4 |
| ABC RESULTS: sky130_fd_sc_hd__buf_1 cells: 900 |
| ABC RESULTS: sky130_fd_sc_hd__inv_2 cells: 168 |
| ABC RESULTS: sky130_fd_sc_hd__mux2_2 cells: 85 |
| ABC RESULTS: sky130_fd_sc_hd__nand2_2 cells: 478 |
| ABC RESULTS: sky130_fd_sc_hd__nand3_2 cells: 31 |
| ABC RESULTS: sky130_fd_sc_hd__nand3b_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__nand4_2 cells: 10 |
| ABC RESULTS: sky130_fd_sc_hd__nand4b_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__nor2_2 cells: 386 |
| ABC RESULTS: sky130_fd_sc_hd__nor2b_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__nor3_2 cells: 13 |
| ABC RESULTS: sky130_fd_sc_hd__nor3b_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__nor4_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__o2111a_2 cells: 5 |
| ABC RESULTS: sky130_fd_sc_hd__o2111ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o211a_2 cells: 147 |
| ABC RESULTS: sky130_fd_sc_hd__o211ai_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o21a_2 cells: 142 |
| ABC RESULTS: sky130_fd_sc_hd__o21ai_2 cells: 135 |
| ABC RESULTS: sky130_fd_sc_hd__o21ba_2 cells: 23 |
| ABC RESULTS: sky130_fd_sc_hd__o21bai_2 cells: 10 |
| ABC RESULTS: sky130_fd_sc_hd__o221a_2 cells: 129 |
| ABC RESULTS: sky130_fd_sc_hd__o221ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o22a_2 cells: 21 |
| ABC RESULTS: sky130_fd_sc_hd__o22ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o2bb2a_2 cells: 25 |
| ABC RESULTS: sky130_fd_sc_hd__o2bb2ai_2 cells: 2 |
| ABC RESULTS: sky130_fd_sc_hd__o311a_2 cells: 16 |
| ABC RESULTS: sky130_fd_sc_hd__o311ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o31a_2 cells: 21 |
| ABC RESULTS: sky130_fd_sc_hd__o31ai_2 cells: 3 |
| ABC RESULTS: sky130_fd_sc_hd__o32a_2 cells: 9 |
| ABC RESULTS: sky130_fd_sc_hd__o32ai_2 cells: 1 |
| ABC RESULTS: sky130_fd_sc_hd__o41a_2 cells: 8 |
| ABC RESULTS: sky130_fd_sc_hd__or2_2 cells: 347 |
| ABC RESULTS: sky130_fd_sc_hd__or2b_2 cells: 73 |
| ABC RESULTS: sky130_fd_sc_hd__or3_2 cells: 80 |
| ABC RESULTS: sky130_fd_sc_hd__or3b_2 cells: 19 |
| ABC RESULTS: sky130_fd_sc_hd__or4_2 cells: 28 |
| ABC RESULTS: sky130_fd_sc_hd__or4b_2 cells: 9 |
| ABC RESULTS: sky130_fd_sc_hd__xnor2_2 cells: 379 |
| ABC RESULTS: sky130_fd_sc_hd__xor2_2 cells: 192 |
| ABC RESULTS: internal signals: 6263 |
| ABC RESULTS: input signals: 466 |
| ABC RESULTS: output signals: 449 |
| Removing temp directory. |
| |
| 19. Executing SETUNDEF pass (replace undef values with defined constants). |
| |
| 20. Executing HILOMAP pass (mapping to constant drivers). |
| |
| 21. Executing SPLITNETS pass (splitting up multi-bit signals). |
| |
| 22. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \Motor_Top.. |
| Removed 24 unused cells and 7234 unused wires. |
| <suppressed ~105 debug messages> |
| |
| 23. Executing INSBUF pass (insert buffer cells for connected wires). |
| Added Motor_Top.$auto$insbuf.cc:79:execute$26925: \io_pwm_high_en -> \io_pwm_low_en |
| |
| 24. Executing CHECK pass (checking for obvious problems). |
| Checking module Motor_Top... |
| Warning: Wire Motor_Top.\io_wbs_data_o [31] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [30] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [29] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [28] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [27] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [26] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [25] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [24] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [23] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [22] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [21] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [20] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [19] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [18] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [17] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [16] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [15] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [14] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [13] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [12] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [11] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [10] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [9] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [8] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [7] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [6] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [5] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [4] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [3] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [2] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [1] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_data_o [0] is used but has no driver. |
| Warning: Wire Motor_Top.\io_wbs_ack_o is used but has no driver. |
| Warning: Wire Motor_Top.\io_pwm_low_en is used but has no driver. |
| Warning: Wire Motor_Top.\io_pwm_low is used but has no driver. |
| Warning: Wire Motor_Top.\io_pwm_high_en is used but has no driver. |
| Warning: Wire Motor_Top.\io_pwm_high is used but has no driver. |
| Warning: Wire Motor_Top.\io_motor_irq is used but has no driver. |
| Found and reported 38 problems. |
| |
| 25. Printing statistics. |
| |
| === Motor_Top === |
| |
| Number of wires: 5738 |
| Number of wire bits: 5818 |
| Number of public wires: 430 |
| Number of public wire bits: 510 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 5759 |
| sky130_fd_sc_hd__a2111o_2 1 |
| sky130_fd_sc_hd__a2111oi_2 1 |
| sky130_fd_sc_hd__a211o_2 24 |
| sky130_fd_sc_hd__a211oi_2 5 |
| sky130_fd_sc_hd__a21bo_2 48 |
| sky130_fd_sc_hd__a21boi_2 8 |
| sky130_fd_sc_hd__a21o_2 104 |
| sky130_fd_sc_hd__a21oi_2 168 |
| sky130_fd_sc_hd__a221o_2 81 |
| sky130_fd_sc_hd__a221oi_2 1 |
| sky130_fd_sc_hd__a22o_2 148 |
| sky130_fd_sc_hd__a22oi_2 27 |
| sky130_fd_sc_hd__a2bb2o_2 45 |
| sky130_fd_sc_hd__a2bb2oi_2 2 |
| sky130_fd_sc_hd__a311o_2 13 |
| sky130_fd_sc_hd__a311oi_2 1 |
| sky130_fd_sc_hd__a31o_2 66 |
| sky130_fd_sc_hd__a31oi_2 6 |
| sky130_fd_sc_hd__a32o_2 37 |
| sky130_fd_sc_hd__a32oi_2 1 |
| sky130_fd_sc_hd__a41o_2 7 |
| sky130_fd_sc_hd__and2_2 270 |
| sky130_fd_sc_hd__and2b_2 110 |
| sky130_fd_sc_hd__and3_2 166 |
| sky130_fd_sc_hd__and3b_2 20 |
| sky130_fd_sc_hd__and4_2 26 |
| sky130_fd_sc_hd__and4b_2 5 |
| sky130_fd_sc_hd__and4bb_2 4 |
| sky130_fd_sc_hd__buf_1 900 |
| sky130_fd_sc_hd__buf_2 1 |
| sky130_fd_sc_hd__dfxtp_2 448 |
| sky130_fd_sc_hd__inv_2 168 |
| sky130_fd_sc_hd__mux2_2 85 |
| sky130_fd_sc_hd__nand2_2 478 |
| sky130_fd_sc_hd__nand3_2 31 |
| sky130_fd_sc_hd__nand3b_2 5 |
| sky130_fd_sc_hd__nand4_2 10 |
| sky130_fd_sc_hd__nand4b_2 1 |
| sky130_fd_sc_hd__nor2_2 386 |
| sky130_fd_sc_hd__nor2b_2 3 |
| sky130_fd_sc_hd__nor3_2 13 |
| sky130_fd_sc_hd__nor3b_2 2 |
| sky130_fd_sc_hd__nor4_2 2 |
| sky130_fd_sc_hd__o2111a_2 5 |
| sky130_fd_sc_hd__o2111ai_2 1 |
| sky130_fd_sc_hd__o211a_2 147 |
| sky130_fd_sc_hd__o211ai_2 3 |
| sky130_fd_sc_hd__o21a_2 142 |
| sky130_fd_sc_hd__o21ai_2 135 |
| sky130_fd_sc_hd__o21ba_2 23 |
| sky130_fd_sc_hd__o21bai_2 10 |
| sky130_fd_sc_hd__o221a_2 129 |
| sky130_fd_sc_hd__o221ai_2 1 |
| sky130_fd_sc_hd__o22a_2 21 |
| sky130_fd_sc_hd__o22ai_2 1 |
| sky130_fd_sc_hd__o2bb2a_2 25 |
| sky130_fd_sc_hd__o2bb2ai_2 2 |
| sky130_fd_sc_hd__o311a_2 16 |
| sky130_fd_sc_hd__o311ai_2 1 |
| sky130_fd_sc_hd__o31a_2 21 |
| sky130_fd_sc_hd__o31ai_2 3 |
| sky130_fd_sc_hd__o32a_2 9 |
| sky130_fd_sc_hd__o32ai_2 1 |
| sky130_fd_sc_hd__o41a_2 8 |
| sky130_fd_sc_hd__or2_2 347 |
| sky130_fd_sc_hd__or2b_2 73 |
| sky130_fd_sc_hd__or3_2 80 |
| sky130_fd_sc_hd__or3b_2 19 |
| sky130_fd_sc_hd__or4_2 28 |
| sky130_fd_sc_hd__or4b_2 9 |
| sky130_fd_sc_hd__xnor2_2 379 |
| sky130_fd_sc_hd__xor2_2 192 |
| |
| Chip area for module '\Motor_Top': 53533.843200 |
| |
| 26. Executing Verilog backend. |
| Dumping module `\Motor_Top'. |
| |
| Warnings: 38 unique messages, 38 total |
| End of script. Logfile hash: 5d518ed631, CPU: user 11.76s system 0.05s, MEM: 114.40 MB peak |
| Yosys 0.12+45 (git sha1 UNKNOWN, gcc 8.3.1 -fPIC -Os) |
| Time spent: 56% 2x abc (15 sec), 8% 38x opt_expr (2 sec), ... |
