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foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-036 / 81c60a03e1c3865f11dc9f33eece4c7088354f2a / . / abc / Motor_Top / runs / Motor_Top / logs / routing / 21-detailed.log
blob: 6d64fa962a515e93f33f6706ac9f92caae158aeb [file] [log] [blame]
OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/merged_unpadded.lef
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/merged_unpadded.lef
[INFO ODB-0127] Reading DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/routing/19-global.def
[INFO ODB-0128] Design: Motor_Top
[INFO ODB-0130] Created 99 pins.
[INFO ODB-0131] Created 32703 components and 146175 component-terminals.
[INFO ODB-0132] Created 2 special nets and 124264 connections.
[INFO ODB-0133] Created 6002 nets and 21911 connections.
[INFO ODB-0134] Finished DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/tmp/routing/19-global.def
[INFO ORD-0030] Using 2 thread(s).
[INFO DRT-0149] Reading tech and libs.
Units: 1000
Number of layers: 13
Number of macros: 441
Number of vias: 25
Number of viarulegen: 25
[INFO DRT-0150] Reading design.
Design: Motor_Top
Die area: ( 0 0 ) ( 500000 500000 )
Number of track patterns: 12
Number of DEF vias: 3
Number of components: 32703
Number of terminals: 99
Number of snets: 2
Number of nets: 6002
[INFO DRT-0167] List of default vias:
Layer mcon
default via: L1M1_PR
Layer via
default via: M1M2_PR
Layer via2
default via: M2M3_PR
Layer via3
default via: M3M4_PR
Layer via4
default via: M4M5_PR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
Complete 10000 instances.
Complete 20000 instances.
Complete 30000 instances.
[INFO DRT-0164] Number of unique instances = 431.
[INFO DRT-0168] Init region query.
[INFO DRT-0018] Complete 10000 insts.
[INFO DRT-0018] Complete 20000 insts.
[INFO DRT-0018] Complete 30000 insts.
[INFO DRT-0024] Complete FR_MASTERSLICE.
[INFO DRT-0024] Complete FR_VIA.
[INFO DRT-0024] Complete li1.
[INFO DRT-0024] Complete mcon.
[INFO DRT-0024] Complete met1.
[INFO DRT-0024] Complete via.
[INFO DRT-0024] Complete met2.
[INFO DRT-0024] Complete via2.
[INFO DRT-0024] Complete met3.
[INFO DRT-0024] Complete via3.
[INFO DRT-0024] Complete met4.
[INFO DRT-0024] Complete via4.
[INFO DRT-0024] Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] FR_VIA shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 277833.
[INFO DRT-0033] mcon shape region query size = 374916.
[INFO DRT-0033] met1 shape region query size = 73985.
[INFO DRT-0033] via shape region query size = 3080.
[INFO DRT-0033] met2 shape region query size = 1254.
[INFO DRT-0033] via2 shape region query size = 2464.
[INFO DRT-0033] met3 shape region query size = 1307.
[INFO DRT-0033] via3 shape region query size = 2464.
[INFO DRT-0033] met4 shape region query size = 630.
[INFO DRT-0033] via4 shape region query size = 0.
[INFO DRT-0033] met5 shape region query size = 0.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076] Complete 100 pins.
[INFO DRT-0076] Complete 200 pins.
[INFO DRT-0076] Complete 300 pins.
[INFO DRT-0076] Complete 400 pins.
[INFO DRT-0076] Complete 500 pins.
[INFO DRT-0076] Complete 600 pins.
[INFO DRT-0076] Complete 700 pins.
[INFO DRT-0076] Complete 800 pins.
[INFO DRT-0076] Complete 900 pins.
[INFO DRT-0077] Complete 1000 pins.
[INFO DRT-0078] Complete 1651 pins.
[INFO DRT-0079] Complete 100 unique inst patterns.
[INFO DRT-0079] Complete 200 unique inst patterns.
[INFO DRT-0079] Complete 300 unique inst patterns.
[INFO DRT-0079] Complete 400 unique inst patterns.
[INFO DRT-0081] Complete 425 unique inst patterns.
[INFO DRT-0082] Complete 1000 groups.
[INFO DRT-0082] Complete 2000 groups.
[INFO DRT-0082] Complete 3000 groups.
[INFO DRT-0082] Complete 4000 groups.
[INFO DRT-0082] Complete 5000 groups.
[INFO DRT-0082] Complete 6000 groups.
[INFO DRT-0082] Complete 7000 groups.
[INFO DRT-0082] Complete 8000 groups.
[INFO DRT-0084] Complete 8015 groups.
#scanned instances = 32703
#unique instances = 431
#stdCellGenAp = 12250
#stdCellValidPlanarAp = 36
#stdCellValidViaAp = 9509
#stdCellPinNoAp = 0
#stdCellPinCnt = 21911
#instTermValidViaApCnt = 0
#macroGenAp = 0
#macroValidPlanarAp = 0
#macroValidViaAp = 0
#macroNoAp = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:16, elapsed time = 00:00:08, memory = 216.18 (MB), peak = 226.27 (MB)
[INFO DRT-0151] Reading guide.
Number of guides: 43674
[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 72 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 72 STEP 6900 ;
[INFO DRT-0026] Complete 10000 origin guides.
[INFO DRT-0026] Complete 20000 origin guides.
[INFO DRT-0026] Complete 30000 origin guides.
[INFO DRT-0026] Complete 40000 origin guides.
[INFO DRT-0028] Complete FR_MASTERSLICE.
[INFO DRT-0028] Complete FR_VIA.
[INFO DRT-0028] Complete li1.
[INFO DRT-0028] Complete mcon.
[INFO DRT-0028] Complete met1.
[INFO DRT-0028] Complete via.
[INFO DRT-0028] Complete met2.
[INFO DRT-0028] Complete via2.
[INFO DRT-0028] Complete met3.
[INFO DRT-0028] Complete via3.
[INFO DRT-0028] Complete met4.
[INFO DRT-0028] Complete via4.
[INFO DRT-0028] Complete met5.
[INFO DRT-0178] Init guide query.
[INFO DRT-0035] Complete FR_MASTERSLICE (guide).
[INFO DRT-0035] Complete FR_VIA (guide).
[INFO DRT-0035] Complete li1 (guide).
[INFO DRT-0035] Complete mcon (guide).
[INFO DRT-0035] Complete met1 (guide).
[INFO DRT-0035] Complete via (guide).
[INFO DRT-0035] Complete met2 (guide).
[INFO DRT-0035] Complete via2 (guide).
[INFO DRT-0035] Complete met3 (guide).
[INFO DRT-0035] Complete via3 (guide).
[INFO DRT-0035] Complete met4 (guide).
[INFO DRT-0035] Complete via4 (guide).
[INFO DRT-0035] Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] FR_VIA guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 16786.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 12895.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 6686.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 423.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 121.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 0.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 23593 vertical wires in 2 frboxes and 13318 horizontal wires in 2 frboxes.
[INFO DRT-0186] Done with 2884 vertical wires in 2 frboxes and 3834 horizontal wires in 2 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:00:03, elapsed time = 00:00:02, memory = 345.99 (MB), peak = 345.99 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 346.13 (MB), peak = 346.13 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:04, memory = 637.44 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:07, memory = 1006.81 (MB).
Completing 30% with 421 violations.
elapsed time = 00:00:08, memory = 897.01 (MB).
Completing 40% with 421 violations.
elapsed time = 00:00:17, memory = 897.27 (MB).
Completing 50% with 421 violations.
elapsed time = 00:00:19, memory = 1099.47 (MB).
Completing 60% with 1030 violations.
elapsed time = 00:00:23, memory = 1129.20 (MB).
Completing 70% with 1030 violations.
elapsed time = 00:00:28, memory = 1146.76 (MB).
Completing 80% with 1499 violations.
elapsed time = 00:00:30, memory = 983.25 (MB).
Completing 90% with 1499 violations.
elapsed time = 00:00:42, memory = 1065.79 (MB).
Completing 100% with 2188 violations.
elapsed time = 00:00:44, memory = 1237.64 (MB).
[INFO DRT-0199] Number of violations = 3037.
[INFO DRT-0267] cpu time = 00:01:28, elapsed time = 00:00:45, memory = 1237.64 (MB), peak = 1293.86 (MB)
Total wire length = 214402 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 99665 um.
Total wire length on LAYER met2 = 95119 um.
Total wire length on LAYER met3 = 11003 um.
Total wire length on LAYER met4 = 8613 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 45025.
Up-via summary (total 45025):.
------------------------
FR_MASTERSLICE 0
li1 21856
met1 22323
met2 615
met3 231
met4 0
------------------------
45025
[INFO DRT-0195] Start 1st optimization iteration.
Completing 10% with 3037 violations.
elapsed time = 00:00:03, memory = 1047.13 (MB).
Completing 20% with 3037 violations.
elapsed time = 00:00:08, memory = 1159.59 (MB).
Completing 30% with 2483 violations.
elapsed time = 00:00:09, memory = 1047.25 (MB).
Completing 40% with 2483 violations.
elapsed time = 00:00:16, memory = 1076.12 (MB).
Completing 50% with 2483 violations.
elapsed time = 00:00:19, memory = 1287.19 (MB).
Completing 60% with 1954 violations.
elapsed time = 00:00:23, memory = 1047.25 (MB).
Completing 70% with 1954 violations.
elapsed time = 00:00:27, memory = 1047.25 (MB).
Completing 80% with 1346 violations.
elapsed time = 00:00:29, memory = 1047.25 (MB).
Completing 90% with 1346 violations.
elapsed time = 00:00:39, memory = 1076.63 (MB).
Completing 100% with 851 violations.
elapsed time = 00:00:42, memory = 1239.09 (MB).
[INFO DRT-0199] Number of violations = 851.
[INFO DRT-0267] cpu time = 00:01:22, elapsed time = 00:00:42, memory = 1239.09 (MB), peak = 1315.04 (MB)
Total wire length = 212568 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 98841 um.
Total wire length on LAYER met2 = 94117 um.
Total wire length on LAYER met3 = 11022 um.
Total wire length on LAYER met4 = 8586 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44608.
Up-via summary (total 44608):.
------------------------
FR_MASTERSLICE 0
li1 21831
met1 21939
met2 605
met3 233
met4 0
------------------------
44608
[INFO DRT-0195] Start 2nd optimization iteration.
Completing 10% with 851 violations.
elapsed time = 00:00:03, memory = 1047.25 (MB).
Completing 20% with 851 violations.
elapsed time = 00:00:08, memory = 1047.25 (MB).
Completing 30% with 855 violations.
elapsed time = 00:00:10, memory = 1047.25 (MB).
Completing 40% with 855 violations.
elapsed time = 00:00:15, memory = 1047.25 (MB).
Completing 50% with 855 violations.
elapsed time = 00:00:17, memory = 1053.69 (MB).
Completing 60% with 771 violations.
elapsed time = 00:00:21, memory = 1047.11 (MB).
Completing 70% with 771 violations.
elapsed time = 00:00:26, memory = 1047.11 (MB).
Completing 80% with 743 violations.
elapsed time = 00:00:27, memory = 1047.19 (MB).
Completing 90% with 743 violations.
elapsed time = 00:00:35, memory = 1047.19 (MB).
Completing 100% with 696 violations.
elapsed time = 00:00:37, memory = 1047.16 (MB).
[INFO DRT-0199] Number of violations = 696.
[INFO DRT-0267] cpu time = 00:01:12, elapsed time = 00:00:38, memory = 1047.16 (MB), peak = 1315.04 (MB)
Total wire length = 212036 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 98711 um.
Total wire length on LAYER met2 = 93646 um.
Total wire length on LAYER met3 = 11102 um.
Total wire length on LAYER met4 = 8576 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44361.
Up-via summary (total 44361):.
------------------------
FR_MASTERSLICE 0
li1 21831
met1 21681
met2 620
met3 229
met4 0
------------------------
44361
[INFO DRT-0195] Start 3rd optimization iteration.
Completing 10% with 696 violations.
elapsed time = 00:00:06, memory = 1047.16 (MB).
Completing 20% with 696 violations.
elapsed time = 00:00:14, memory = 1065.72 (MB).
Completing 30% with 626 violations.
elapsed time = 00:00:15, memory = 1047.24 (MB).
Completing 40% with 626 violations.
elapsed time = 00:00:23, memory = 1047.24 (MB).
Completing 50% with 626 violations.
elapsed time = 00:00:25, memory = 1075.34 (MB).
Completing 60% with 479 violations.
elapsed time = 00:00:30, memory = 1047.25 (MB).
Completing 70% with 479 violations.
elapsed time = 00:00:36, memory = 1153.72 (MB).
Completing 80% with 341 violations.
elapsed time = 00:00:41, memory = 1047.05 (MB).
Completing 90% with 341 violations.
elapsed time = 00:00:51, memory = 1047.05 (MB).
Completing 100% with 148 violations.
elapsed time = 00:00:53, memory = 1047.05 (MB).
[INFO DRT-0199] Number of violations = 148.
[INFO DRT-0267] cpu time = 00:01:40, elapsed time = 00:00:53, memory = 1047.05 (MB), peak = 1315.04 (MB)
Total wire length = 212033 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 97042 um.
Total wire length on LAYER met2 = 93947 um.
Total wire length on LAYER met3 = 12545 um.
Total wire length on LAYER met4 = 8497 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44830.
Up-via summary (total 44830):.
------------------------
FR_MASTERSLICE 0
li1 21831
met1 21954
met2 822
met3 223
met4 0
------------------------
44830
[INFO DRT-0195] Start 4th optimization iteration.
Completing 10% with 148 violations.
elapsed time = 00:00:00, memory = 1047.05 (MB).
Completing 20% with 148 violations.
elapsed time = 00:00:02, memory = 1047.25 (MB).
Completing 30% with 106 violations.
elapsed time = 00:00:03, memory = 1047.25 (MB).
Completing 40% with 106 violations.
elapsed time = 00:00:06, memory = 1047.25 (MB).
Completing 50% with 106 violations.
elapsed time = 00:00:06, memory = 1047.25 (MB).
Completing 60% with 80 violations.
elapsed time = 00:00:07, memory = 1047.25 (MB).
Completing 70% with 80 violations.
elapsed time = 00:00:08, memory = 1047.25 (MB).
Completing 80% with 42 violations.
elapsed time = 00:00:09, memory = 1047.25 (MB).
Completing 90% with 42 violations.
elapsed time = 00:00:11, memory = 1047.25 (MB).
Completing 100% with 19 violations.
elapsed time = 00:00:12, memory = 1047.25 (MB).
[INFO DRT-0199] Number of violations = 19.
[INFO DRT-0267] cpu time = 00:00:21, elapsed time = 00:00:12, memory = 1047.25 (MB), peak = 1315.04 (MB)
Total wire length = 211988 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96930 um.
Total wire length on LAYER met2 = 93903 um.
Total wire length on LAYER met3 = 12656 um.
Total wire length on LAYER met4 = 8497 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44839.
Up-via summary (total 44839):.
------------------------
FR_MASTERSLICE 0
li1 21831
met1 21946
met2 839
met3 223
met4 0
------------------------
44839
[INFO DRT-0195] Start 5th optimization iteration.
Completing 10% with 19 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 20% with 19 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 30% with 13 violations.
elapsed time = 00:00:01, memory = 1047.25 (MB).
Completing 40% with 13 violations.
elapsed time = 00:00:01, memory = 1047.25 (MB).
Completing 50% with 13 violations.
elapsed time = 00:00:01, memory = 1047.25 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:02, memory = 1047.25 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:02, memory = 1047.25 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:02, memory = 1047.25 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:02, memory = 1047.25 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:02, memory = 1047.25 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:03, elapsed time = 00:00:02, memory = 1047.25 (MB), peak = 1315.04 (MB)
Total wire length = 211994 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96938 um.
Total wire length on LAYER met2 = 93900 um.
Total wire length on LAYER met3 = 12656 um.
Total wire length on LAYER met4 = 8497 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44839.
Up-via summary (total 44839):.
------------------------
FR_MASTERSLICE 0
li1 21831
met1 21946
met2 839
met3 223
met4 0
------------------------
44839
[INFO DRT-0195] Start 17th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1047.25 (MB), peak = 1315.04 (MB)
Total wire length = 211994 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96938 um.
Total wire length on LAYER met2 = 93900 um.
Total wire length on LAYER met3 = 12656 um.
Total wire length on LAYER met4 = 8497 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44839.
Up-via summary (total 44839):.
------------------------
FR_MASTERSLICE 0
li1 21831
met1 21946
met2 839
met3 223
met4 0
------------------------
44839
[INFO DRT-0195] Start 25th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1047.25 (MB), peak = 1315.04 (MB)
Total wire length = 211994 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96938 um.
Total wire length on LAYER met2 = 93900 um.
Total wire length on LAYER met3 = 12656 um.
Total wire length on LAYER met4 = 8497 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44839.
Up-via summary (total 44839):.
------------------------
FR_MASTERSLICE 0
li1 21831
met1 21946
met2 839
met3 223
met4 0
------------------------
44839
[INFO DRT-0195] Start 33rd optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1047.25 (MB), peak = 1315.04 (MB)
Total wire length = 211994 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96938 um.
Total wire length on LAYER met2 = 93900 um.
Total wire length on LAYER met3 = 12656 um.
Total wire length on LAYER met4 = 8497 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44839.
Up-via summary (total 44839):.
------------------------
FR_MASTERSLICE 0
li1 21831
met1 21946
met2 839
met3 223
met4 0
------------------------
44839
[INFO DRT-0195] Start 41st optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1047.25 (MB), peak = 1315.04 (MB)
Total wire length = 211994 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96938 um.
Total wire length on LAYER met2 = 93900 um.
Total wire length on LAYER met3 = 12656 um.
Total wire length on LAYER met4 = 8497 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44839.
Up-via summary (total 44839):.
------------------------
FR_MASTERSLICE 0
li1 21831
met1 21946
met2 839
met3 223
met4 0
------------------------
44839
[INFO DRT-0195] Start 49th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1047.25 (MB), peak = 1315.04 (MB)
Total wire length = 211994 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96938 um.
Total wire length on LAYER met2 = 93900 um.
Total wire length on LAYER met3 = 12656 um.
Total wire length on LAYER met4 = 8497 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44839.
Up-via summary (total 44839):.
------------------------
FR_MASTERSLICE 0
li1 21831
met1 21946
met2 839
met3 223
met4 0
------------------------
44839
[INFO DRT-0195] Start 57th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1047.25 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1047.25 (MB), peak = 1315.04 (MB)
Total wire length = 211994 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96938 um.
Total wire length on LAYER met2 = 93900 um.
Total wire length on LAYER met3 = 12656 um.
Total wire length on LAYER met4 = 8497 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44839.
Up-via summary (total 44839):.
------------------------
FR_MASTERSLICE 0
li1 21831
met1 21946
met2 839
met3 223
met4 0
------------------------
44839
[INFO DRT-0198] Complete detail routing.
Total wire length = 211994 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 96938 um.
Total wire length on LAYER met2 = 93900 um.
Total wire length on LAYER met3 = 12656 um.
Total wire length on LAYER met4 = 8497 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 44839.
Up-via summary (total 44839):.
------------------------
FR_MASTERSLICE 0
li1 21831
met1 21946
met2 839
met3 223
met4 0
------------------------
44839
[INFO DRT-0267] cpu time = 00:06:09, elapsed time = 00:03:14, memory = 1047.25 (MB), peak = 1315.04 (MB)
[INFO DRT-0180] Post processing.
Saving to /home/ali112000/mpw5/UETRV-ECORE/openlane/Motor_Top/runs/Motor_Top/results/routing/Motor_Top.def