Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-005 / slot-036 / 81c60a03e1c3865f11dc9f33eece4c7088354f2a / . / abc / Core / runs / Core / logs / routing / 21-detailed.log
blob: 3777ad3f771f105ec47d815c303210c1d17ea772 [file] [log] [blame]
OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/merged_unpadded.lef
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/merged_unpadded.lef
[INFO ODB-0127] Reading DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/routing/19-global.def
[INFO ODB-0128] Design: Core
[INFO ODB-0130] Created 176 pins.
[INFO ODB-0131] Created 43384 components and 210284 component-terminals.
[INFO ODB-0132] Created 2 special nets and 166988 connections.
[INFO ODB-0133] Created 11278 nets and 43296 connections.
[INFO ODB-0134] Finished DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/routing/19-global.def
[INFO ORD-0030] Using 2 thread(s).
[INFO DRT-0149] Reading tech and libs.
Units: 1000
Number of layers: 13
Number of macros: 441
Number of vias: 25
Number of viarulegen: 25
[INFO DRT-0150] Reading design.
Design: Core
Die area: ( 0 0 ) ( 500000 500000 )
Number of track patterns: 12
Number of DEF vias: 3
Number of components: 43384
Number of terminals: 176
Number of snets: 2
Number of nets: 11278
[INFO DRT-0167] List of default vias:
Layer mcon
default via: L1M1_PR
Layer via
default via: M1M2_PR
Layer via2
default via: M2M3_PR
Layer via3
default via: M3M4_PR
Layer via4
default via: M4M5_PR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
Complete 10000 instances.
Complete 20000 instances.
Complete 30000 instances.
Complete 40000 instances.
[INFO DRT-0164] Number of unique instances = 490.
[INFO DRT-0168] Init region query.
[INFO DRT-0018] Complete 10000 insts.
[INFO DRT-0018] Complete 20000 insts.
[INFO DRT-0018] Complete 30000 insts.
[INFO DRT-0018] Complete 40000 insts.
[INFO DRT-0024] Complete FR_MASTERSLICE.
[INFO DRT-0024] Complete FR_VIA.
[INFO DRT-0024] Complete li1.
[INFO DRT-0024] Complete mcon.
[INFO DRT-0024] Complete met1.
[INFO DRT-0024] Complete via.
[INFO DRT-0024] Complete met2.
[INFO DRT-0024] Complete via2.
[INFO DRT-0024] Complete met3.
[INFO DRT-0024] Complete via3.
[INFO DRT-0024] Complete met4.
[INFO DRT-0024] Complete via4.
[INFO DRT-0024] Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] FR_VIA shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 470061.
[INFO DRT-0033] mcon shape region query size = 385229.
[INFO DRT-0033] met1 shape region query size = 120619.
[INFO DRT-0033] via shape region query size = 3080.
[INFO DRT-0033] met2 shape region query size = 1235.
[INFO DRT-0033] via2 shape region query size = 2464.
[INFO DRT-0033] met3 shape region query size = 1403.
[INFO DRT-0033] via3 shape region query size = 2464.
[INFO DRT-0033] met4 shape region query size = 630.
[INFO DRT-0033] via4 shape region query size = 0.
[INFO DRT-0033] met5 shape region query size = 0.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076] Complete 100 pins.
[INFO DRT-0076] Complete 200 pins.
[INFO DRT-0076] Complete 300 pins.
[INFO DRT-0076] Complete 400 pins.
[INFO DRT-0076] Complete 500 pins.
[INFO DRT-0076] Complete 600 pins.
[INFO DRT-0076] Complete 700 pins.
[INFO DRT-0076] Complete 800 pins.
[INFO DRT-0076] Complete 900 pins.
[INFO DRT-0077] Complete 1000 pins.
[INFO DRT-0078] Complete 1981 pins.
[INFO DRT-0079] Complete 100 unique inst patterns.
[INFO DRT-0079] Complete 200 unique inst patterns.
[INFO DRT-0079] Complete 300 unique inst patterns.
[INFO DRT-0079] Complete 400 unique inst patterns.
[INFO DRT-0081] Complete 484 unique inst patterns.
[INFO DRT-0082] Complete 1000 groups.
[INFO DRT-0082] Complete 2000 groups.
[INFO DRT-0082] Complete 3000 groups.
[INFO DRT-0082] Complete 4000 groups.
[INFO DRT-0082] Complete 5000 groups.
[INFO DRT-0082] Complete 6000 groups.
[INFO DRT-0082] Complete 7000 groups.
[INFO DRT-0082] Complete 8000 groups.
[INFO DRT-0082] Complete 9000 groups.
[INFO DRT-0083] Complete 10000 groups.
[INFO DRT-0084] Complete 17205 groups.
#scanned instances = 43384
#unique instances = 490
#stdCellGenAp = 14551
#stdCellValidPlanarAp = 109
#stdCellValidViaAp = 11306
#stdCellPinNoAp = 0
#stdCellPinCnt = 43296
#instTermValidViaApCnt = 0
#macroGenAp = 0
#macroValidPlanarAp = 0
#macroValidViaAp = 0
#macroNoAp = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:20, elapsed time = 00:00:10, memory = 262.61 (MB), peak = 270.26 (MB)
[INFO DRT-0151] Reading guide.
Number of guides: 97421
[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 72 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 72 STEP 6900 ;
[INFO DRT-0026] Complete 10000 origin guides.
[INFO DRT-0026] Complete 20000 origin guides.
[INFO DRT-0026] Complete 30000 origin guides.
[INFO DRT-0026] Complete 40000 origin guides.
[INFO DRT-0026] Complete 50000 origin guides.
[INFO DRT-0026] Complete 60000 origin guides.
[INFO DRT-0026] Complete 70000 origin guides.
[INFO DRT-0026] Complete 80000 origin guides.
[INFO DRT-0026] Complete 90000 origin guides.
[INFO DRT-0028] Complete FR_MASTERSLICE.
[INFO DRT-0028] Complete FR_VIA.
[INFO DRT-0028] Complete li1.
[INFO DRT-0028] Complete mcon.
[INFO DRT-0028] Complete met1.
[INFO DRT-0028] Complete via.
[INFO DRT-0028] Complete met2.
[INFO DRT-0028] Complete via2.
[INFO DRT-0028] Complete met3.
[INFO DRT-0028] Complete via3.
[INFO DRT-0028] Complete met4.
[INFO DRT-0028] Complete via4.
[INFO DRT-0028] Complete met5.
complete 10000 nets.
[INFO DRT-0178] Init guide query.
[INFO DRT-0029] Complete 10000 nets (guide).
[INFO DRT-0035] Complete FR_MASTERSLICE (guide).
[INFO DRT-0035] Complete FR_VIA (guide).
[INFO DRT-0035] Complete li1 (guide).
[INFO DRT-0035] Complete mcon (guide).
[INFO DRT-0035] Complete met1 (guide).
[INFO DRT-0035] Complete via (guide).
[INFO DRT-0035] Complete met2 (guide).
[INFO DRT-0035] Complete via2 (guide).
[INFO DRT-0035] Complete met3 (guide).
[INFO DRT-0035] Complete via3 (guide).
[INFO DRT-0035] Complete met4 (guide).
[INFO DRT-0035] Complete via4 (guide).
[INFO DRT-0035] Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] FR_VIA guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 34833.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 28082.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 16191.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 2485.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 727.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 0.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 51751 vertical wires in 2 frboxes and 30567 horizontal wires in 2 frboxes.
[INFO DRT-0186] Done with 7737 vertical wires in 2 frboxes and 10043 horizontal wires in 2 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:04, memory = 419.64 (MB), peak = 453.91 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 419.64 (MB), peak = 453.91 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:07, memory = 809.95 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:18, memory = 1290.83 (MB).
Completing 30% with 1492 violations.
elapsed time = 00:00:29, memory = 1509.46 (MB).
Completing 40% with 1492 violations.
elapsed time = 00:00:40, memory = 1509.86 (MB).
Completing 50% with 1492 violations.
elapsed time = 00:00:54, memory = 1510.41 (MB).
Completing 60% with 3067 violations.
elapsed time = 00:01:02, memory = 1529.00 (MB).
Completing 70% with 3067 violations.
elapsed time = 00:01:13, memory = 1529.18 (MB).
Completing 80% with 4500 violations.
elapsed time = 00:01:33, memory = 1581.14 (MB).
Completing 90% with 4500 violations.
elapsed time = 00:01:47, memory = 1581.30 (MB).
Completing 100% with 5935 violations.
elapsed time = 00:02:08, memory = 1597.45 (MB).
[INFO DRT-0199] Number of violations = 9296.
[INFO DRT-0267] cpu time = 00:04:10, elapsed time = 00:02:09, memory = 1597.45 (MB), peak = 1619.19 (MB)
Total wire length = 536277 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 199022 um.
Total wire length on LAYER met2 = 221220 um.
Total wire length on LAYER met3 = 75389 um.
Total wire length on LAYER met4 = 40645 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 98300.
Up-via summary (total 98300):.
------------------------
FR_MASTERSLICE 0
li1 43278
met1 49700
met2 3953
met3 1369
met4 0
------------------------
98300
[INFO DRT-0195] Start 1st optimization iteration.
Completing 10% with 9296 violations.
elapsed time = 00:00:05, memory = 1602.35 (MB).
Completing 20% with 9296 violations.
elapsed time = 00:00:16, memory = 1621.39 (MB).
Completing 30% with 7461 violations.
elapsed time = 00:00:28, memory = 1604.49 (MB).
Completing 40% with 7461 violations.
elapsed time = 00:00:37, memory = 1604.49 (MB).
Completing 50% with 7461 violations.
elapsed time = 00:00:53, memory = 1626.08 (MB).
Completing 60% with 5448 violations.
elapsed time = 00:01:02, memory = 1615.63 (MB).
Completing 70% with 5448 violations.
elapsed time = 00:01:13, memory = 1617.43 (MB).
Completing 80% with 4099 violations.
elapsed time = 00:01:30, memory = 1633.16 (MB).
Completing 90% with 4099 violations.
elapsed time = 00:01:40, memory = 1633.36 (MB).
Completing 100% with 2680 violations.
elapsed time = 00:01:56, memory = 1633.20 (MB).
[INFO DRT-0199] Number of violations = 2680.
[INFO DRT-0267] cpu time = 00:03:46, elapsed time = 00:01:57, memory = 1633.20 (MB), peak = 1648.82 (MB)
Total wire length = 531736 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 197827 um.
Total wire length on LAYER met2 = 218892 um.
Total wire length on LAYER met3 = 74677 um.
Total wire length on LAYER met4 = 40339 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 97498.
Up-via summary (total 97498):.
------------------------
FR_MASTERSLICE 0
li1 43242
met1 49011
met2 3914
met3 1331
met4 0
------------------------
97498
[INFO DRT-0195] Start 2nd optimization iteration.
Completing 10% with 2680 violations.
elapsed time = 00:00:05, memory = 1633.20 (MB).
Completing 20% with 2680 violations.
elapsed time = 00:00:15, memory = 1633.36 (MB).
Completing 30% with 2513 violations.
elapsed time = 00:00:31, memory = 1633.36 (MB).
Completing 40% with 2513 violations.
elapsed time = 00:00:39, memory = 1633.36 (MB).
Completing 50% with 2513 violations.
elapsed time = 00:00:52, memory = 1633.36 (MB).
Completing 60% with 2543 violations.
elapsed time = 00:01:04, memory = 1633.23 (MB).
Completing 70% with 2543 violations.
elapsed time = 00:01:14, memory = 1633.36 (MB).
Completing 80% with 2660 violations.
elapsed time = 00:01:27, memory = 1633.36 (MB).
Completing 90% with 2660 violations.
elapsed time = 00:01:37, memory = 1633.36 (MB).
Completing 100% with 2566 violations.
elapsed time = 00:01:52, memory = 1601.91 (MB).
[INFO DRT-0199] Number of violations = 2566.
[INFO DRT-0267] cpu time = 00:03:40, elapsed time = 00:01:52, memory = 1637.74 (MB), peak = 1689.55 (MB)
Total wire length = 530021 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 197299 um.
Total wire length on LAYER met2 = 218041 um.
Total wire length on LAYER met3 = 74388 um.
Total wire length on LAYER met4 = 40292 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 97165.
Up-via summary (total 97165):.
------------------------
FR_MASTERSLICE 0
li1 43242
met1 48758
met2 3835
met3 1330
met4 0
------------------------
97165
[INFO DRT-0195] Start 3rd optimization iteration.
Completing 10% with 2566 violations.
elapsed time = 00:00:04, memory = 1638.68 (MB).
Completing 20% with 2566 violations.
elapsed time = 00:00:12, memory = 1638.68 (MB).
Completing 30% with 2114 violations.
elapsed time = 00:00:26, memory = 1606.48 (MB).
Completing 40% with 2114 violations.
elapsed time = 00:00:37, memory = 1623.82 (MB).
Completing 50% with 2114 violations.
elapsed time = 00:00:49, memory = 1627.17 (MB).
Completing 60% with 1660 violations.
elapsed time = 00:00:58, memory = 1649.02 (MB).
Completing 70% with 1660 violations.
elapsed time = 00:01:13, memory = 1666.27 (MB).
Completing 80% with 1213 violations.
elapsed time = 00:01:36, memory = 1728.40 (MB).
Completing 90% with 1213 violations.
elapsed time = 00:01:45, memory = 1728.46 (MB).
Completing 100% with 626 violations.
elapsed time = 00:02:01, memory = 1728.46 (MB).
[INFO DRT-0199] Number of violations = 626.
[INFO DRT-0267] cpu time = 00:03:54, elapsed time = 00:02:02, memory = 1728.46 (MB), peak = 1728.46 (MB)
Total wire length = 529772 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 190007 um.
Total wire length on LAYER met2 = 217852 um.
Total wire length on LAYER met3 = 81080 um.
Total wire length on LAYER met4 = 40831 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 98597.
Up-via summary (total 98597):.
------------------------
FR_MASTERSLICE 0
li1 43242
met1 49180
met2 4799
met3 1376
met4 0
------------------------
98597
[INFO DRT-0195] Start 4th optimization iteration.
Completing 10% with 626 violations.
elapsed time = 00:00:02, memory = 1728.46 (MB).
Completing 20% with 626 violations.
elapsed time = 00:00:04, memory = 1728.46 (MB).
Completing 30% with 465 violations.
elapsed time = 00:00:11, memory = 1728.46 (MB).
Completing 40% with 465 violations.
elapsed time = 00:00:11, memory = 1728.46 (MB).
Completing 50% with 465 violations.
elapsed time = 00:00:15, memory = 1728.46 (MB).
Completing 60% with 334 violations.
elapsed time = 00:00:17, memory = 1728.46 (MB).
Completing 70% with 334 violations.
elapsed time = 00:00:18, memory = 1728.46 (MB).
Completing 80% with 132 violations.
elapsed time = 00:00:25, memory = 1728.46 (MB).
Completing 90% with 132 violations.
elapsed time = 00:00:26, memory = 1728.46 (MB).
Completing 100% with 59 violations.
elapsed time = 00:00:33, memory = 1728.46 (MB).
[INFO DRT-0199] Number of violations = 59.
[INFO DRT-0267] cpu time = 00:01:01, elapsed time = 00:00:34, memory = 1728.46 (MB), peak = 1728.46 (MB)
Total wire length = 529713 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 189026 um.
Total wire length on LAYER met2 = 217644 um.
Total wire length on LAYER met3 = 82001 um.
Total wire length on LAYER met4 = 41040 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 98723.
Up-via summary (total 98723):.
------------------------
FR_MASTERSLICE 0
li1 43242
met1 49179
met2 4912
met3 1390
met4 0
------------------------
98723
[INFO DRT-0195] Start 5th optimization iteration.
Completing 10% with 59 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 20% with 59 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 30% with 30 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 40% with 30 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 50% with 30 violations.
elapsed time = 00:00:01, memory = 1728.46 (MB).
Completing 60% with 7 violations.
elapsed time = 00:00:02, memory = 1728.46 (MB).
Completing 70% with 7 violations.
elapsed time = 00:00:02, memory = 1728.46 (MB).
Completing 80% with 2 violations.
elapsed time = 00:00:04, memory = 1728.46 (MB).
Completing 90% with 2 violations.
elapsed time = 00:00:04, memory = 1728.46 (MB).
Completing 100% with 1 violations.
elapsed time = 00:00:06, memory = 1728.46 (MB).
[INFO DRT-0199] Number of violations = 1.
[INFO DRT-0267] cpu time = 00:00:08, elapsed time = 00:00:06, memory = 1728.46 (MB), peak = 1728.46 (MB)
Total wire length = 529700 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 189029 um.
Total wire length on LAYER met2 = 217615 um.
Total wire length on LAYER met3 = 81997 um.
Total wire length on LAYER met4 = 41057 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 98719.
Up-via summary (total 98719):.
------------------------
FR_MASTERSLICE 0
li1 43242
met1 49171
met2 4916
met3 1390
met4 0
------------------------
98719
[INFO DRT-0195] Start 6th optimization iteration.
Completing 10% with 1 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 20% with 1 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 30% with 1 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 40% with 1 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 50% with 1 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1728.46 (MB), peak = 1728.46 (MB)
Total wire length = 529696 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 189030 um.
Total wire length on LAYER met2 = 217612 um.
Total wire length on LAYER met3 = 81995 um.
Total wire length on LAYER met4 = 41057 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 98719.
Up-via summary (total 98719):.
------------------------
FR_MASTERSLICE 0
li1 43242
met1 49171
met2 4916
met3 1390
met4 0
------------------------
98719
[INFO DRT-0195] Start 17th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1728.46 (MB), peak = 1728.46 (MB)
Total wire length = 529696 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 189030 um.
Total wire length on LAYER met2 = 217612 um.
Total wire length on LAYER met3 = 81995 um.
Total wire length on LAYER met4 = 41057 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 98719.
Up-via summary (total 98719):.
------------------------
FR_MASTERSLICE 0
li1 43242
met1 49171
met2 4916
met3 1390
met4 0
------------------------
98719
[INFO DRT-0195] Start 25th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1728.46 (MB), peak = 1728.46 (MB)
Total wire length = 529696 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 189030 um.
Total wire length on LAYER met2 = 217612 um.
Total wire length on LAYER met3 = 81995 um.
Total wire length on LAYER met4 = 41057 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 98719.
Up-via summary (total 98719):.
------------------------
FR_MASTERSLICE 0
li1 43242
met1 49171
met2 4916
met3 1390
met4 0
------------------------
98719
[INFO DRT-0195] Start 33rd optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1728.46 (MB), peak = 1728.46 (MB)
Total wire length = 529696 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 189030 um.
Total wire length on LAYER met2 = 217612 um.
Total wire length on LAYER met3 = 81995 um.
Total wire length on LAYER met4 = 41057 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 98719.
Up-via summary (total 98719):.
------------------------
FR_MASTERSLICE 0
li1 43242
met1 49171
met2 4916
met3 1390
met4 0
------------------------
98719
[INFO DRT-0195] Start 41st optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1728.46 (MB), peak = 1728.46 (MB)
Total wire length = 529696 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 189030 um.
Total wire length on LAYER met2 = 217612 um.
Total wire length on LAYER met3 = 81995 um.
Total wire length on LAYER met4 = 41057 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 98719.
Up-via summary (total 98719):.
------------------------
FR_MASTERSLICE 0
li1 43242
met1 49171
met2 4916
met3 1390
met4 0
------------------------
98719
[INFO DRT-0195] Start 49th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1728.46 (MB), peak = 1728.46 (MB)
Total wire length = 529696 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 189030 um.
Total wire length on LAYER met2 = 217612 um.
Total wire length on LAYER met3 = 81995 um.
Total wire length on LAYER met4 = 41057 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 98719.
Up-via summary (total 98719):.
------------------------
FR_MASTERSLICE 0
li1 43242
met1 49171
met2 4916
met3 1390
met4 0
------------------------
98719
[INFO DRT-0195] Start 57th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 20% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 30% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 40% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 50% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 60% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 70% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 80% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 90% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
Completing 100% with 0 violations.
elapsed time = 00:00:00, memory = 1728.46 (MB).
[INFO DRT-0199] Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 1728.46 (MB), peak = 1728.46 (MB)
Total wire length = 529696 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 189030 um.
Total wire length on LAYER met2 = 217612 um.
Total wire length on LAYER met3 = 81995 um.
Total wire length on LAYER met4 = 41057 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 98719.
Up-via summary (total 98719):.
------------------------
FR_MASTERSLICE 0
li1 43242
met1 49171
met2 4916
met3 1390
met4 0
------------------------
98719
[INFO DRT-0198] Complete detail routing.
Total wire length = 529696 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 189030 um.
Total wire length on LAYER met2 = 217612 um.
Total wire length on LAYER met3 = 81995 um.
Total wire length on LAYER met4 = 41057 um.
Total wire length on LAYER met5 = 0 um.
Total number of vias = 98719.
Up-via summary (total 98719):.
------------------------
FR_MASTERSLICE 0
li1 43242
met1 49171
met2 4916
met3 1390
met4 0
------------------------
98719
[INFO DRT-0267] cpu time = 00:16:42, elapsed time = 00:08:43, memory = 1728.46 (MB), peak = 1728.46 (MB)
[INFO DRT-0180] Post processing.
Saving to /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/results/routing/Core.def