| OpenROAD 8d53e9b018dec98fa63e907ddeb6c5406f035361 |
| This program is licensed under the BSD-3 license. See the LICENSE file for details. |
| Components of this program may be licensed under more restrictive licenses which must be honored. |
| [INFO ODB-0222] Reading LEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/merged_unpadded.lef |
| [INFO ODB-0223] Created 13 technology layers |
| [INFO ODB-0224] Created 25 technology vias |
| [INFO ODB-0225] Created 441 library cells |
| [INFO ODB-0226] Finished LEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/merged_unpadded.lef |
| [INFO ODB-0127] Reading DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/floorplan/6-pdn.def |
| [INFO ODB-0128] Design: Core |
| [INFO ODB-0130] Created 176 pins. |
| [INFO ODB-0131] Created 14413 components and 87566 component-terminals. |
| [INFO ODB-0132] Created 2 special nets and 51104 connections. |
| [INFO ODB-0133] Created 10860 nets and 36462 connections. |
| [INFO ODB-0134] Finished DEF file: /home/ali112000/mpw5/UETRV-ECORE/openlane/Core/runs/Core/tmp/floorplan/6-pdn.def |
| [INFO GPL-0002] DBU: 1000 |
| [INFO GPL-0003] SiteSize: 460 2720 |
| [INFO GPL-0004] CoreAreaLxLy: 5520 10880 |
| [INFO GPL-0005] CoreAreaUxUy: 494040 486880 |
| [INFO GPL-0006] NumInstances: 14413 |
| [INFO GPL-0007] NumPlaceInstances: 10789 |
| [INFO GPL-0008] NumFixedInstances: 3624 |
| [INFO GPL-0009] NumDummyInstances: 0 |
| [INFO GPL-0010] NumNets: 10860 |
| [INFO GPL-0011] NumPins: 36636 |
| [INFO GPL-0012] DieAreaLxLy: 0 0 |
| [INFO GPL-0013] DieAreaUxUy: 500000 500000 |
| [INFO GPL-0014] CoreAreaLxLy: 5520 10880 |
| [INFO GPL-0015] CoreAreaUxUy: 494040 486880 |
| [INFO GPL-0016] CoreArea: 232535520000 |
| [INFO GPL-0017] NonPlaceInstsArea: 5410188800 |
| [INFO GPL-0018] PlaceInstsArea: 108311379200 |
| [INFO GPL-0019] Util(%): 47.69 |
| [INFO GPL-0020] StdInstsArea: 108311379200 |
| [INFO GPL-0021] MacroInstsArea: 0 |
| [InitialPlace] Iter: 1 CG Error: 0.00001059 HPWL: 217346130 |
| [InitialPlace] Iter: 2 CG Error: 0.00001314 HPWL: 131927481 |
| [InitialPlace] Iter: 3 CG Error: 0.00000011 HPWL: 120438202 |
| [InitialPlace] Iter: 4 CG Error: 0.00000036 HPWL: 120733908 |
| [InitialPlace] Iter: 5 CG Error: 0.00000037 HPWL: 120544861 |
| [INFO GPL-0031] FillerInit: NumGCells: 11330 |
| [INFO GPL-0032] FillerInit: NumGNets: 10860 |
| [INFO GPL-0033] FillerInit: NumGPins: 36636 |
| [INFO GPL-0023] TargetDensity: 0.50 |
| [INFO GPL-0024] AveragePlaceInstArea: 10039056 |
| [INFO GPL-0025] IdealBinArea: 20078112 |
| [INFO GPL-0026] IdealBinCnt: 11581 |
| [INFO GPL-0027] TotalBinArea: 232535520000 |
| [INFO GPL-0028] BinCnt: 64 64 |
| [INFO GPL-0029] BinSize: 7634 7438 |
| [INFO GPL-0030] NumBins: 4096 |
| [NesterovSolve] Iter: 1 overflow: 0.992949 HPWL: 52184667 |
| [NesterovSolve] Iter: 10 overflow: 0.984021 HPWL: 73403225 |
| [NesterovSolve] Iter: 20 overflow: 0.982822 HPWL: 77130263 |
| [NesterovSolve] Iter: 30 overflow: 0.982771 HPWL: 76648103 |
| [NesterovSolve] Iter: 40 overflow: 0.982539 HPWL: 76849898 |
| [NesterovSolve] Iter: 50 overflow: 0.98253 HPWL: 77039152 |
| [NesterovSolve] Iter: 60 overflow: 0.982311 HPWL: 77103677 |
| [NesterovSolve] Iter: 70 overflow: 0.982288 HPWL: 77251328 |
| [NesterovSolve] Iter: 80 overflow: 0.982278 HPWL: 77297915 |
| [NesterovSolve] Iter: 90 overflow: 0.982309 HPWL: 77260918 |
| [NesterovSolve] Iter: 100 overflow: 0.982343 HPWL: 77259666 |
| [NesterovSolve] Iter: 110 overflow: 0.982284 HPWL: 77376555 |
| [NesterovSolve] Iter: 120 overflow: 0.982067 HPWL: 77646414 |
| [NesterovSolve] Iter: 130 overflow: 0.981975 HPWL: 78082637 |
| [NesterovSolve] Iter: 140 overflow: 0.9816 HPWL: 78822179 |
| [NesterovSolve] Iter: 150 overflow: 0.9802 HPWL: 80128877 |
| [NesterovSolve] Iter: 160 overflow: 0.979119 HPWL: 82410058 |
| [NesterovSolve] Iter: 170 overflow: 0.975415 HPWL: 86052897 |
| [NesterovSolve] Iter: 180 overflow: 0.970939 HPWL: 91412636 |
| [NesterovSolve] Iter: 190 overflow: 0.964758 HPWL: 98731670 |
| [NesterovSolve] Iter: 200 overflow: 0.956325 HPWL: 108279152 |
| [NesterovSolve] Iter: 210 overflow: 0.945821 HPWL: 120712598 |
| [NesterovSolve] Iter: 220 overflow: 0.931215 HPWL: 136077367 |
| [NesterovSolve] Iter: 230 overflow: 0.914425 HPWL: 154003483 |
| [NesterovSolve] Iter: 240 overflow: 0.893091 HPWL: 173904364 |
| [NesterovSolve] Iter: 250 overflow: 0.869488 HPWL: 195923842 |
| [NesterovSolve] Iter: 260 overflow: 0.841498 HPWL: 218783481 |
| [NesterovSolve] Iter: 270 overflow: 0.811308 HPWL: 240626422 |
| [NesterovSolve] Iter: 280 overflow: 0.779909 HPWL: 260424702 |
| [NesterovSolve] Iter: 290 overflow: 0.745382 HPWL: 278130630 |
| [NesterovSolve] Iter: 300 overflow: 0.708791 HPWL: 294827629 |
| [NesterovSolve] Iter: 310 overflow: 0.669997 HPWL: 310725623 |
| [NesterovSolve] Iter: 320 overflow: 0.627848 HPWL: 326515966 |
| [NesterovSolve] Iter: 330 overflow: 0.582501 HPWL: 338581205 |
| [NesterovSolve] Iter: 340 overflow: 0.535383 HPWL: 349165388 |
| [NesterovSolve] Iter: 350 overflow: 0.485819 HPWL: 357180571 |
| [NesterovSolve] Iter: 360 overflow: 0.431939 HPWL: 364361630 |
| [NesterovSolve] Iter: 370 overflow: 0.380007 HPWL: 371279148 |
| [NesterovSolve] Iter: 380 overflow: 0.331935 HPWL: 377855704 |
| [NesterovSolve] Iter: 390 overflow: 0.293534 HPWL: 381100676 |
| [NesterovSolve] Iter: 400 overflow: 0.260559 HPWL: 384781288 |
| [NesterovSolve] Iter: 410 overflow: 0.228763 HPWL: 387106090 |
| [NesterovSolve] Iter: 420 overflow: 0.199661 HPWL: 389519925 |
| [NesterovSolve] Iter: 430 overflow: 0.171521 HPWL: 391018467 |
| [NesterovSolve] Iter: 440 overflow: 0.145672 HPWL: 392197180 |
| [NesterovSolve] Iter: 450 overflow: 0.125292 HPWL: 393241546 |
| [NesterovSolve] Iter: 460 overflow: 0.105715 HPWL: 394208265 |
| [NesterovSolve] Finished with Overflow: 0.099787 |
| [WARNING STA-0053] /home/ali112000/Desktop/mpw/pdk/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib line 1, library sky130_fd_sc_hd__tt_025C_1v80 already exists. |
| ############################################################################### |
| # Created by write_sdc |
| # Mon Mar 21 23:22:24 2022 |
| ############################################################################### |
| current_design Core |
| ############################################################################### |
| # Timing Constraints |
| ############################################################################### |
| create_clock -name clock -period 20.0000 [get_ports {clock}] |
| set_clock_transition 0.1500 [get_clocks {clock}] |
| set_clock_uncertainty 0.2500 clock |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rdata[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_valid}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[0]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[10]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[11]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[12]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[13]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[14]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[15]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[16]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[17]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[18]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[19]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[1]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[20]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[21]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[22]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[23]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[24]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[25]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[26]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[27]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[28]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[29]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[2]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[30]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[31]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[3]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[4]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[5]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[6]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[7]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[8]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_inst[9]}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_valid}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_irq_motor_irq}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_irq_spi_irq}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_irq_uart_irq}] |
| set_input_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {reset}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_addr[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_ld_type[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_ld_type[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_ld_type[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_rd_en}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_st_type[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_st_type[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wdata[9]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_dbus_wr_en}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[0]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[10]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[11]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[12]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[13]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[14]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[15]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[16]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[17]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[18]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[19]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[1]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[20]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[21]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[22]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[23]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[24]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[25]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[26]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[27]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[28]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[29]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[2]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[30]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[31]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[3]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[4]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[5]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[6]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[7]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[8]}] |
| set_output_delay 4.0000 -clock [get_clocks {clock}] -add_delay [get_ports {io_ibus_addr[9]}] |
| ############################################################################### |
| # Environment |
| ############################################################################### |
| set_load -pin_load 0.0334 [get_ports {io_dbus_rd_en}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wr_en}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[31]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[30]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[29]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[28]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[27]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[26]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_addr[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_ld_type[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_ld_type[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_ld_type[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_st_type[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_st_type[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[31]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[30]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[29]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[28]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[27]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[26]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_dbus_wdata[0]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[31]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[30]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[29]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[28]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[27]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[26]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[25]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[24]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[23]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[22]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[21]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[20]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[19]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[18]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[17]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[16]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[15]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[14]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[13]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[12]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[11]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[10]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[9]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[8]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[7]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[6]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[5]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[4]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[3]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[2]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[1]}] |
| set_load -pin_load 0.0334 [get_ports {io_ibus_addr[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {clock}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_valid}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_irq_motor_irq}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_irq_spi_irq}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_irq_uart_irq}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {reset}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_dbus_rdata[0]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[31]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[30]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[29]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[28]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[27]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[26]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[25]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[24]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[23]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[22]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[21]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[20]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[19]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[18]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[17]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[16]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[15]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[14]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[13]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[12]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[11]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[10]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[9]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[8]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[7]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[6]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[5]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[4]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[3]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[2]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[1]}] |
| set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {io_ibus_inst[0]}] |
| set_timing_derate -early 0.9500 |
| set_timing_derate -late 1.0500 |
| ############################################################################### |
| # Design Rules |
| ############################################################################### |
| set_max_fanout 5.0000 [current_design] |
| [INFO]: Setting RC values... |
| min_report |
| |
| =========================================================================== |
| report_checks -path_delay min (Hold) |
| ============================================================================ |
| Startpoint: _19137_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: _19136_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _19137_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| 0.02 0.32 0.32 v _19137_/Q (sky130_fd_sc_hd__dfxtp_2) |
| 1 0.00 dpath.csr.br_taken (net) |
| 0.02 0.00 0.32 v _19136_/D (sky130_fd_sc_hd__dfxtp_2) |
| 0.32 data arrival time |
| |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _19136_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| -0.01 0.24 library hold time |
| 0.24 data required time |
| ----------------------------------------------------------------------------- |
| 0.24 data required time |
| -0.32 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.08 slack (MET) |
| |
| |
| Startpoint: _19437_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: _19437_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _19437_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| 0.05 0.34 0.34 ^ _19437_/Q (sky130_fd_sc_hd__dfxtp_2) |
| 3 0.01 dpath.csr.timeh[13] (net) |
| 0.05 0.00 0.34 ^ _16367_/A1 (sky130_fd_sc_hd__o21a_2) |
| 0.03 0.11 0.45 ^ _16367_/X (sky130_fd_sc_hd__o21a_2) |
| 1 0.00 _01202_ (net) |
| 0.03 0.00 0.45 ^ _19437_/D (sky130_fd_sc_hd__dfxtp_2) |
| 0.45 data arrival time |
| |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _19437_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| -0.01 0.24 library hold time |
| 0.24 data required time |
| ----------------------------------------------------------------------------- |
| 0.24 data required time |
| -0.45 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.21 slack (MET) |
| |
| |
| Startpoint: _19431_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: _19431_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _19431_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| 0.05 0.34 0.34 ^ _19431_/Q (sky130_fd_sc_hd__dfxtp_2) |
| 3 0.01 dpath.csr.timeh[7] (net) |
| 0.05 0.00 0.34 ^ _16345_/A1 (sky130_fd_sc_hd__o21a_2) |
| 0.03 0.11 0.45 ^ _16345_/X (sky130_fd_sc_hd__o21a_2) |
| 1 0.00 _01196_ (net) |
| 0.03 0.00 0.45 ^ _19431_/D (sky130_fd_sc_hd__dfxtp_2) |
| 0.45 data arrival time |
| |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _19431_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| -0.01 0.24 library hold time |
| 0.24 data required time |
| ----------------------------------------------------------------------------- |
| 0.24 data required time |
| -0.45 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.22 slack (MET) |
| |
| |
| Startpoint: _19612_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: _19612_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _19612_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| 0.05 0.34 0.34 ^ _19612_/Q (sky130_fd_sc_hd__dfxtp_2) |
| 3 0.01 dpath.csr.cycle[24] (net) |
| 0.05 0.00 0.34 ^ _16901_/A1 (sky130_fd_sc_hd__o21a_2) |
| 0.03 0.11 0.45 ^ _16901_/X (sky130_fd_sc_hd__o21a_2) |
| 1 0.00 _01373_ (net) |
| 0.03 0.00 0.45 ^ _19612_/D (sky130_fd_sc_hd__dfxtp_2) |
| 0.45 data arrival time |
| |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _19612_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| -0.01 0.24 library hold time |
| 0.24 data required time |
| ----------------------------------------------------------------------------- |
| 0.24 data required time |
| -0.45 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.22 slack (MET) |
| |
| |
| Startpoint: _19513_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: _19513_ (rising edge-triggered flip-flop clocked by clock) |
| Path Group: clock |
| Path Type: min |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _19513_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| 0.05 0.34 0.34 ^ _19513_/Q (sky130_fd_sc_hd__dfxtp_2) |
| 3 0.01 dpath.csr.cycleh[25] (net) |
| 0.05 0.00 0.34 ^ _16600_/A1 (sky130_fd_sc_hd__o21a_2) |
| 0.03 0.11 0.45 ^ _16600_/X (sky130_fd_sc_hd__o21a_2) |
| 1 0.00 _01278_ (net) |
| 0.03 0.00 0.45 ^ _19513_/D (sky130_fd_sc_hd__dfxtp_2) |
| 0.45 data arrival time |
| |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.25 0.25 clock uncertainty |
| 0.00 0.25 clock reconvergence pessimism |
| 0.25 ^ _19513_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| -0.01 0.24 library hold time |
| 0.24 data required time |
| ----------------------------------------------------------------------------- |
| 0.24 data required time |
| -0.45 data arrival time |
| ----------------------------------------------------------------------------- |
| 0.22 slack (MET) |
| |
| |
| min_report_end |
| max_report |
| |
| =========================================================================== |
| report_checks -path_delay max (Setup) |
| ============================================================================ |
| Startpoint: _18779_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: io_ibus_addr[28] (output port clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _18779_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| 0.11 0.43 0.43 ^ _18779_/Q (sky130_fd_sc_hd__dfxtp_2) |
| 4 0.02 _00005_ (net) |
| 0.11 0.00 0.43 ^ _09382_/A (sky130_fd_sc_hd__buf_1) |
| 0.31 0.30 0.73 ^ _09382_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _03824_ (net) |
| 0.31 0.00 0.73 ^ _09383_/A (sky130_fd_sc_hd__buf_1) |
| 0.79 0.68 1.41 ^ _09383_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.07 _03825_ (net) |
| 0.79 0.00 1.41 ^ _09384_/A (sky130_fd_sc_hd__buf_1) |
| 0.38 0.41 1.82 ^ _09384_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _03826_ (net) |
| 0.38 0.00 1.82 ^ _09385_/A (sky130_fd_sc_hd__buf_1) |
| 0.48 0.46 2.27 ^ _09385_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03827_ (net) |
| 0.48 0.00 2.28 ^ _09386_/A (sky130_fd_sc_hd__buf_1) |
| 0.42 0.42 2.69 ^ _09386_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03828_ (net) |
| 0.42 0.00 2.69 ^ _09387_/A (sky130_fd_sc_hd__buf_1) |
| 0.60 0.55 3.24 ^ _09387_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _03829_ (net) |
| 0.60 0.00 3.24 ^ _09388_/A (sky130_fd_sc_hd__buf_1) |
| 0.53 0.51 3.75 ^ _09388_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _03830_ (net) |
| 0.53 0.00 3.75 ^ _09458_/A (sky130_fd_sc_hd__buf_1) |
| 0.51 0.49 4.25 ^ _09458_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03900_ (net) |
| 0.51 0.00 4.25 ^ _09679_/A (sky130_fd_sc_hd__buf_1) |
| 0.40 0.41 4.66 ^ _09679_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _04121_ (net) |
| 0.40 0.00 4.66 ^ _09698_/A (sky130_fd_sc_hd__buf_1) |
| 0.50 0.47 5.13 ^ _09698_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _04140_ (net) |
| 0.50 0.00 5.13 ^ _09699_/A (sky130_fd_sc_hd__buf_1) |
| 0.58 0.54 5.67 ^ _09699_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _04141_ (net) |
| 0.58 0.00 5.67 ^ _09700_/A (sky130_fd_sc_hd__buf_1) |
| 0.45 0.45 6.12 ^ _09700_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _04142_ (net) |
| 0.45 0.00 6.12 ^ _09868_/A (sky130_fd_sc_hd__buf_1) |
| 0.53 0.50 6.62 ^ _09868_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _04310_ (net) |
| 0.53 0.00 6.62 ^ _09869_/A (sky130_fd_sc_hd__buf_1) |
| 0.64 0.59 7.21 ^ _09869_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.06 _04311_ (net) |
| 0.64 0.00 7.21 ^ _09872_/S0 (sky130_fd_sc_hd__mux4_2) |
| 0.10 0.64 7.85 v _09872_/X (sky130_fd_sc_hd__mux4_2) |
| 1 0.01 _04314_ (net) |
| 0.10 0.00 7.85 v _09875_/A2 (sky130_fd_sc_hd__o211a_2) |
| 0.04 0.26 8.12 v _09875_/X (sky130_fd_sc_hd__o211a_2) |
| 1 0.00 _04317_ (net) |
| 0.04 0.00 8.12 v _09876_/B1 (sky130_fd_sc_hd__a311o_2) |
| 0.07 0.39 8.51 v _09876_/X (sky130_fd_sc_hd__a311o_2) |
| 1 0.01 _04318_ (net) |
| 0.07 0.00 8.51 v _09877_/A3 (sky130_fd_sc_hd__a32o_2) |
| 0.12 0.38 8.88 v _09877_/X (sky130_fd_sc_hd__a32o_2) |
| 4 0.04 _04319_ (net) |
| 0.12 0.00 8.89 v _09926_/A (sky130_fd_sc_hd__nand2_2) |
| 0.07 0.09 8.97 ^ _09926_/Y (sky130_fd_sc_hd__nand2_2) |
| 2 0.00 _04368_ (net) |
| 0.07 0.00 8.97 ^ _10086_/B_N (sky130_fd_sc_hd__or2b_2) |
| 0.06 0.32 9.29 v _10086_/X (sky130_fd_sc_hd__or2b_2) |
| 2 0.00 _04528_ (net) |
| 0.06 0.00 9.29 v _10089_/A (sky130_fd_sc_hd__or2b_2) |
| 0.06 0.32 9.61 v _10089_/X (sky130_fd_sc_hd__or2b_2) |
| 2 0.01 _04531_ (net) |
| 0.06 0.00 9.61 v _11360_/A (sky130_fd_sc_hd__or4bb_2) |
| 0.11 0.70 10.31 v _11360_/X (sky130_fd_sc_hd__or4bb_2) |
| 2 0.01 _05802_ (net) |
| 0.11 0.00 10.31 v _11419_/A3 (sky130_fd_sc_hd__a311o_2) |
| 0.05 0.43 10.73 v _11419_/X (sky130_fd_sc_hd__a311o_2) |
| 1 0.00 _05861_ (net) |
| 0.05 0.00 10.73 v _11421_/A1 (sky130_fd_sc_hd__a21o_2) |
| 0.11 0.29 11.02 v _11421_/X (sky130_fd_sc_hd__a21o_2) |
| 5 0.04 _05863_ (net) |
| 0.11 0.00 11.02 v _11481_/B2 (sky130_fd_sc_hd__a221o_2) |
| 0.11 0.48 11.50 v _11481_/X (sky130_fd_sc_hd__a221o_2) |
| 2 0.03 _05923_ (net) |
| 0.11 0.00 11.50 v _11494_/A2 (sky130_fd_sc_hd__o211a_2) |
| 0.04 0.27 11.77 v _11494_/X (sky130_fd_sc_hd__o211a_2) |
| 1 0.00 _05936_ (net) |
| 0.04 0.00 11.77 v _11495_/C (sky130_fd_sc_hd__and3_2) |
| 0.10 0.29 12.06 v _11495_/X (sky130_fd_sc_hd__and3_2) |
| 5 0.03 _05937_ (net) |
| 0.10 0.00 12.06 v _11548_/A (sky130_fd_sc_hd__nand2_2) |
| 0.06 0.09 12.15 ^ _11548_/Y (sky130_fd_sc_hd__nand2_2) |
| 3 0.01 _05985_ (net) |
| 0.06 0.00 12.15 ^ _11641_/A (sky130_fd_sc_hd__buf_1) |
| 0.21 0.21 12.37 ^ _11641_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _06074_ (net) |
| 0.21 0.00 12.37 ^ _11645_/A (sky130_fd_sc_hd__buf_1) |
| 0.23 0.25 12.62 ^ _11645_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _06078_ (net) |
| 0.23 0.00 12.62 ^ _12064_/A (sky130_fd_sc_hd__buf_1) |
| 0.31 0.32 12.94 ^ _12064_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _06469_ (net) |
| 0.31 0.00 12.94 ^ _12369_/A (sky130_fd_sc_hd__nand2_2) |
| 0.13 0.09 13.03 v _12369_/Y (sky130_fd_sc_hd__nand2_2) |
| 1 0.01 _06750_ (net) |
| 0.13 0.00 13.03 v _12374_/A2 (sky130_fd_sc_hd__a31o_2) |
| 0.05 0.30 13.33 v _12374_/X (sky130_fd_sc_hd__a31o_2) |
| 1 0.01 _06755_ (net) |
| 0.05 0.00 13.33 v _12375_/C1 (sky130_fd_sc_hd__o311a_2) |
| 0.08 0.14 13.47 v _12375_/X (sky130_fd_sc_hd__o311a_2) |
| 2 0.01 _06756_ (net) |
| 0.08 0.00 13.47 v _12376_/B1 (sky130_fd_sc_hd__a21oi_2) |
| 0.82 0.64 14.11 ^ _12376_/Y (sky130_fd_sc_hd__a21oi_2) |
| 1 0.03 io_ibus_addr[28] (net) |
| 0.82 0.01 14.12 ^ io_ibus_addr[28] (out) |
| 14.12 data arrival time |
| |
| 0.15 20.00 20.00 clock clock (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -14.12 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.63 slack (MET) |
| |
| |
| Startpoint: _18779_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: io_ibus_addr[29] (output port clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _18779_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| 0.11 0.43 0.43 ^ _18779_/Q (sky130_fd_sc_hd__dfxtp_2) |
| 4 0.02 _00005_ (net) |
| 0.11 0.00 0.43 ^ _09382_/A (sky130_fd_sc_hd__buf_1) |
| 0.31 0.30 0.73 ^ _09382_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _03824_ (net) |
| 0.31 0.00 0.73 ^ _09383_/A (sky130_fd_sc_hd__buf_1) |
| 0.79 0.68 1.41 ^ _09383_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.07 _03825_ (net) |
| 0.79 0.00 1.41 ^ _09384_/A (sky130_fd_sc_hd__buf_1) |
| 0.38 0.41 1.82 ^ _09384_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _03826_ (net) |
| 0.38 0.00 1.82 ^ _09385_/A (sky130_fd_sc_hd__buf_1) |
| 0.48 0.46 2.27 ^ _09385_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03827_ (net) |
| 0.48 0.00 2.28 ^ _09386_/A (sky130_fd_sc_hd__buf_1) |
| 0.42 0.42 2.69 ^ _09386_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03828_ (net) |
| 0.42 0.00 2.69 ^ _09387_/A (sky130_fd_sc_hd__buf_1) |
| 0.60 0.55 3.24 ^ _09387_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _03829_ (net) |
| 0.60 0.00 3.24 ^ _09388_/A (sky130_fd_sc_hd__buf_1) |
| 0.53 0.51 3.75 ^ _09388_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _03830_ (net) |
| 0.53 0.00 3.75 ^ _09458_/A (sky130_fd_sc_hd__buf_1) |
| 0.51 0.49 4.25 ^ _09458_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03900_ (net) |
| 0.51 0.00 4.25 ^ _09679_/A (sky130_fd_sc_hd__buf_1) |
| 0.40 0.41 4.66 ^ _09679_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _04121_ (net) |
| 0.40 0.00 4.66 ^ _09698_/A (sky130_fd_sc_hd__buf_1) |
| 0.50 0.47 5.13 ^ _09698_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _04140_ (net) |
| 0.50 0.00 5.13 ^ _09699_/A (sky130_fd_sc_hd__buf_1) |
| 0.58 0.54 5.67 ^ _09699_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _04141_ (net) |
| 0.58 0.00 5.67 ^ _09700_/A (sky130_fd_sc_hd__buf_1) |
| 0.45 0.45 6.12 ^ _09700_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _04142_ (net) |
| 0.45 0.00 6.12 ^ _09868_/A (sky130_fd_sc_hd__buf_1) |
| 0.53 0.50 6.62 ^ _09868_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _04310_ (net) |
| 0.53 0.00 6.62 ^ _09869_/A (sky130_fd_sc_hd__buf_1) |
| 0.64 0.59 7.21 ^ _09869_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.06 _04311_ (net) |
| 0.64 0.00 7.21 ^ _09872_/S0 (sky130_fd_sc_hd__mux4_2) |
| 0.10 0.64 7.85 v _09872_/X (sky130_fd_sc_hd__mux4_2) |
| 1 0.01 _04314_ (net) |
| 0.10 0.00 7.85 v _09875_/A2 (sky130_fd_sc_hd__o211a_2) |
| 0.04 0.26 8.12 v _09875_/X (sky130_fd_sc_hd__o211a_2) |
| 1 0.00 _04317_ (net) |
| 0.04 0.00 8.12 v _09876_/B1 (sky130_fd_sc_hd__a311o_2) |
| 0.07 0.39 8.51 v _09876_/X (sky130_fd_sc_hd__a311o_2) |
| 1 0.01 _04318_ (net) |
| 0.07 0.00 8.51 v _09877_/A3 (sky130_fd_sc_hd__a32o_2) |
| 0.12 0.38 8.88 v _09877_/X (sky130_fd_sc_hd__a32o_2) |
| 4 0.04 _04319_ (net) |
| 0.12 0.00 8.89 v _09926_/A (sky130_fd_sc_hd__nand2_2) |
| 0.07 0.09 8.97 ^ _09926_/Y (sky130_fd_sc_hd__nand2_2) |
| 2 0.00 _04368_ (net) |
| 0.07 0.00 8.97 ^ _10086_/B_N (sky130_fd_sc_hd__or2b_2) |
| 0.06 0.32 9.29 v _10086_/X (sky130_fd_sc_hd__or2b_2) |
| 2 0.00 _04528_ (net) |
| 0.06 0.00 9.29 v _10089_/A (sky130_fd_sc_hd__or2b_2) |
| 0.06 0.32 9.61 v _10089_/X (sky130_fd_sc_hd__or2b_2) |
| 2 0.01 _04531_ (net) |
| 0.06 0.00 9.61 v _11360_/A (sky130_fd_sc_hd__or4bb_2) |
| 0.11 0.70 10.31 v _11360_/X (sky130_fd_sc_hd__or4bb_2) |
| 2 0.01 _05802_ (net) |
| 0.11 0.00 10.31 v _11419_/A3 (sky130_fd_sc_hd__a311o_2) |
| 0.05 0.43 10.73 v _11419_/X (sky130_fd_sc_hd__a311o_2) |
| 1 0.00 _05861_ (net) |
| 0.05 0.00 10.73 v _11421_/A1 (sky130_fd_sc_hd__a21o_2) |
| 0.11 0.29 11.02 v _11421_/X (sky130_fd_sc_hd__a21o_2) |
| 5 0.04 _05863_ (net) |
| 0.11 0.00 11.02 v _11481_/B2 (sky130_fd_sc_hd__a221o_2) |
| 0.11 0.48 11.50 v _11481_/X (sky130_fd_sc_hd__a221o_2) |
| 2 0.03 _05923_ (net) |
| 0.11 0.00 11.50 v _11494_/A2 (sky130_fd_sc_hd__o211a_2) |
| 0.04 0.27 11.77 v _11494_/X (sky130_fd_sc_hd__o211a_2) |
| 1 0.00 _05936_ (net) |
| 0.04 0.00 11.77 v _11495_/C (sky130_fd_sc_hd__and3_2) |
| 0.10 0.29 12.06 v _11495_/X (sky130_fd_sc_hd__and3_2) |
| 5 0.03 _05937_ (net) |
| 0.10 0.00 12.06 v _11548_/A (sky130_fd_sc_hd__nand2_2) |
| 0.06 0.09 12.15 ^ _11548_/Y (sky130_fd_sc_hd__nand2_2) |
| 3 0.01 _05985_ (net) |
| 0.06 0.00 12.15 ^ _11641_/A (sky130_fd_sc_hd__buf_1) |
| 0.21 0.21 12.37 ^ _11641_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _06074_ (net) |
| 0.21 0.00 12.37 ^ _11642_/A (sky130_fd_sc_hd__buf_1) |
| 0.31 0.32 12.69 ^ _11642_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _06075_ (net) |
| 0.31 0.00 12.69 ^ _11643_/A (sky130_fd_sc_hd__buf_1) |
| 0.29 0.32 13.00 ^ _11643_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _06076_ (net) |
| 0.29 0.00 13.00 ^ _12392_/S (sky130_fd_sc_hd__mux2_2) |
| 0.06 0.41 13.41 v _12392_/X (sky130_fd_sc_hd__mux2_2) |
| 1 0.01 _06771_ (net) |
| 0.06 0.00 13.41 v _12393_/B2 (sky130_fd_sc_hd__o221a_2) |
| 0.05 0.25 13.67 v _12393_/X (sky130_fd_sc_hd__o221a_2) |
| 2 0.01 _06772_ (net) |
| 0.05 0.00 13.67 v _12397_/B1 (sky130_fd_sc_hd__o22a_2) |
| 0.20 0.38 14.04 v _12397_/X (sky130_fd_sc_hd__o22a_2) |
| 1 0.03 io_ibus_addr[29] (net) |
| 0.20 0.01 14.06 v io_ibus_addr[29] (out) |
| 14.06 data arrival time |
| |
| 0.15 20.00 20.00 clock clock (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -14.06 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.69 slack (MET) |
| |
| |
| Startpoint: _18779_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: io_ibus_addr[22] (output port clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _18779_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| 0.11 0.43 0.43 ^ _18779_/Q (sky130_fd_sc_hd__dfxtp_2) |
| 4 0.02 _00005_ (net) |
| 0.11 0.00 0.43 ^ _09382_/A (sky130_fd_sc_hd__buf_1) |
| 0.31 0.30 0.73 ^ _09382_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _03824_ (net) |
| 0.31 0.00 0.73 ^ _09383_/A (sky130_fd_sc_hd__buf_1) |
| 0.79 0.68 1.41 ^ _09383_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.07 _03825_ (net) |
| 0.79 0.00 1.41 ^ _09384_/A (sky130_fd_sc_hd__buf_1) |
| 0.38 0.41 1.82 ^ _09384_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _03826_ (net) |
| 0.38 0.00 1.82 ^ _09385_/A (sky130_fd_sc_hd__buf_1) |
| 0.48 0.46 2.27 ^ _09385_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03827_ (net) |
| 0.48 0.00 2.28 ^ _09386_/A (sky130_fd_sc_hd__buf_1) |
| 0.42 0.42 2.69 ^ _09386_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03828_ (net) |
| 0.42 0.00 2.69 ^ _09387_/A (sky130_fd_sc_hd__buf_1) |
| 0.60 0.55 3.24 ^ _09387_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _03829_ (net) |
| 0.60 0.00 3.24 ^ _09388_/A (sky130_fd_sc_hd__buf_1) |
| 0.53 0.51 3.75 ^ _09388_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _03830_ (net) |
| 0.53 0.00 3.75 ^ _09458_/A (sky130_fd_sc_hd__buf_1) |
| 0.51 0.49 4.25 ^ _09458_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03900_ (net) |
| 0.51 0.00 4.25 ^ _09679_/A (sky130_fd_sc_hd__buf_1) |
| 0.40 0.41 4.66 ^ _09679_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _04121_ (net) |
| 0.40 0.00 4.66 ^ _09698_/A (sky130_fd_sc_hd__buf_1) |
| 0.50 0.47 5.13 ^ _09698_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _04140_ (net) |
| 0.50 0.00 5.13 ^ _09699_/A (sky130_fd_sc_hd__buf_1) |
| 0.58 0.54 5.67 ^ _09699_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _04141_ (net) |
| 0.58 0.00 5.67 ^ _09700_/A (sky130_fd_sc_hd__buf_1) |
| 0.45 0.45 6.12 ^ _09700_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _04142_ (net) |
| 0.45 0.00 6.12 ^ _09868_/A (sky130_fd_sc_hd__buf_1) |
| 0.53 0.50 6.62 ^ _09868_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _04310_ (net) |
| 0.53 0.00 6.62 ^ _09869_/A (sky130_fd_sc_hd__buf_1) |
| 0.64 0.59 7.21 ^ _09869_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.06 _04311_ (net) |
| 0.64 0.00 7.21 ^ _09872_/S0 (sky130_fd_sc_hd__mux4_2) |
| 0.10 0.64 7.85 v _09872_/X (sky130_fd_sc_hd__mux4_2) |
| 1 0.01 _04314_ (net) |
| 0.10 0.00 7.85 v _09875_/A2 (sky130_fd_sc_hd__o211a_2) |
| 0.04 0.26 8.12 v _09875_/X (sky130_fd_sc_hd__o211a_2) |
| 1 0.00 _04317_ (net) |
| 0.04 0.00 8.12 v _09876_/B1 (sky130_fd_sc_hd__a311o_2) |
| 0.07 0.39 8.51 v _09876_/X (sky130_fd_sc_hd__a311o_2) |
| 1 0.01 _04318_ (net) |
| 0.07 0.00 8.51 v _09877_/A3 (sky130_fd_sc_hd__a32o_2) |
| 0.12 0.38 8.88 v _09877_/X (sky130_fd_sc_hd__a32o_2) |
| 4 0.04 _04319_ (net) |
| 0.12 0.00 8.89 v _09926_/A (sky130_fd_sc_hd__nand2_2) |
| 0.07 0.09 8.97 ^ _09926_/Y (sky130_fd_sc_hd__nand2_2) |
| 2 0.00 _04368_ (net) |
| 0.07 0.00 8.97 ^ _10086_/B_N (sky130_fd_sc_hd__or2b_2) |
| 0.06 0.32 9.29 v _10086_/X (sky130_fd_sc_hd__or2b_2) |
| 2 0.00 _04528_ (net) |
| 0.06 0.00 9.29 v _10089_/A (sky130_fd_sc_hd__or2b_2) |
| 0.06 0.32 9.61 v _10089_/X (sky130_fd_sc_hd__or2b_2) |
| 2 0.01 _04531_ (net) |
| 0.06 0.00 9.61 v _11360_/A (sky130_fd_sc_hd__or4bb_2) |
| 0.11 0.70 10.31 v _11360_/X (sky130_fd_sc_hd__or4bb_2) |
| 2 0.01 _05802_ (net) |
| 0.11 0.00 10.31 v _11419_/A3 (sky130_fd_sc_hd__a311o_2) |
| 0.05 0.43 10.73 v _11419_/X (sky130_fd_sc_hd__a311o_2) |
| 1 0.00 _05861_ (net) |
| 0.05 0.00 10.73 v _11421_/A1 (sky130_fd_sc_hd__a21o_2) |
| 0.11 0.29 11.02 v _11421_/X (sky130_fd_sc_hd__a21o_2) |
| 5 0.04 _05863_ (net) |
| 0.11 0.00 11.02 v _11481_/B2 (sky130_fd_sc_hd__a221o_2) |
| 0.11 0.48 11.50 v _11481_/X (sky130_fd_sc_hd__a221o_2) |
| 2 0.03 _05923_ (net) |
| 0.11 0.00 11.50 v _11482_/C_N (sky130_fd_sc_hd__or3b_2) |
| 0.03 0.22 11.72 ^ _11482_/X (sky130_fd_sc_hd__or3b_2) |
| 1 0.00 _05924_ (net) |
| 0.03 0.00 11.72 ^ _11495_/A (sky130_fd_sc_hd__and3_2) |
| 0.17 0.28 12.00 ^ _11495_/X (sky130_fd_sc_hd__and3_2) |
| 5 0.03 _05937_ (net) |
| 0.17 0.00 12.00 ^ _11548_/A (sky130_fd_sc_hd__nand2_2) |
| 0.06 0.08 12.08 v _11548_/Y (sky130_fd_sc_hd__nand2_2) |
| 3 0.01 _05985_ (net) |
| 0.06 0.00 12.08 v _11641_/A (sky130_fd_sc_hd__buf_1) |
| 0.10 0.16 12.24 v _11641_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _06074_ (net) |
| 0.10 0.00 12.24 v _11642_/A (sky130_fd_sc_hd__buf_1) |
| 0.15 0.22 12.46 v _11642_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _06075_ (net) |
| 0.15 0.00 12.46 v _11643_/A (sky130_fd_sc_hd__buf_1) |
| 0.14 0.23 12.69 v _11643_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _06076_ (net) |
| 0.14 0.00 12.69 v _12229_/A (sky130_fd_sc_hd__or3_2) |
| 0.09 0.54 13.23 v _12229_/X (sky130_fd_sc_hd__or3_2) |
| 1 0.01 _06622_ (net) |
| 0.09 0.00 13.23 v _12232_/A3 (sky130_fd_sc_hd__a31o_2) |
| 0.06 0.30 13.54 v _12232_/X (sky130_fd_sc_hd__a31o_2) |
| 2 0.01 _06625_ (net) |
| 0.06 0.00 13.54 v _12237_/A1_N (sky130_fd_sc_hd__o2bb2a_2) |
| 0.33 0.49 14.03 ^ _12237_/X (sky130_fd_sc_hd__o2bb2a_2) |
| 1 0.03 io_ibus_addr[22] (net) |
| 0.33 0.01 14.04 ^ io_ibus_addr[22] (out) |
| 14.04 data arrival time |
| |
| 0.15 20.00 20.00 clock clock (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -14.04 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.71 slack (MET) |
| |
| |
| Startpoint: _18779_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: io_ibus_addr[31] (output port clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _18779_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| 0.11 0.43 0.43 ^ _18779_/Q (sky130_fd_sc_hd__dfxtp_2) |
| 4 0.02 _00005_ (net) |
| 0.11 0.00 0.43 ^ _09382_/A (sky130_fd_sc_hd__buf_1) |
| 0.31 0.30 0.73 ^ _09382_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _03824_ (net) |
| 0.31 0.00 0.73 ^ _09383_/A (sky130_fd_sc_hd__buf_1) |
| 0.79 0.68 1.41 ^ _09383_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.07 _03825_ (net) |
| 0.79 0.00 1.41 ^ _09384_/A (sky130_fd_sc_hd__buf_1) |
| 0.38 0.41 1.82 ^ _09384_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _03826_ (net) |
| 0.38 0.00 1.82 ^ _09385_/A (sky130_fd_sc_hd__buf_1) |
| 0.48 0.46 2.27 ^ _09385_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03827_ (net) |
| 0.48 0.00 2.28 ^ _09386_/A (sky130_fd_sc_hd__buf_1) |
| 0.42 0.42 2.69 ^ _09386_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03828_ (net) |
| 0.42 0.00 2.69 ^ _09387_/A (sky130_fd_sc_hd__buf_1) |
| 0.60 0.55 3.24 ^ _09387_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _03829_ (net) |
| 0.60 0.00 3.24 ^ _09388_/A (sky130_fd_sc_hd__buf_1) |
| 0.53 0.51 3.75 ^ _09388_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _03830_ (net) |
| 0.53 0.00 3.75 ^ _09458_/A (sky130_fd_sc_hd__buf_1) |
| 0.51 0.49 4.25 ^ _09458_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03900_ (net) |
| 0.51 0.00 4.25 ^ _09679_/A (sky130_fd_sc_hd__buf_1) |
| 0.40 0.41 4.66 ^ _09679_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _04121_ (net) |
| 0.40 0.00 4.66 ^ _09698_/A (sky130_fd_sc_hd__buf_1) |
| 0.50 0.47 5.13 ^ _09698_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _04140_ (net) |
| 0.50 0.00 5.13 ^ _09699_/A (sky130_fd_sc_hd__buf_1) |
| 0.58 0.54 5.67 ^ _09699_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _04141_ (net) |
| 0.58 0.00 5.67 ^ _09700_/A (sky130_fd_sc_hd__buf_1) |
| 0.45 0.45 6.12 ^ _09700_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _04142_ (net) |
| 0.45 0.00 6.12 ^ _09868_/A (sky130_fd_sc_hd__buf_1) |
| 0.53 0.50 6.62 ^ _09868_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _04310_ (net) |
| 0.53 0.00 6.62 ^ _09869_/A (sky130_fd_sc_hd__buf_1) |
| 0.64 0.59 7.21 ^ _09869_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.06 _04311_ (net) |
| 0.64 0.00 7.21 ^ _09872_/S0 (sky130_fd_sc_hd__mux4_2) |
| 0.10 0.64 7.85 v _09872_/X (sky130_fd_sc_hd__mux4_2) |
| 1 0.01 _04314_ (net) |
| 0.10 0.00 7.85 v _09875_/A2 (sky130_fd_sc_hd__o211a_2) |
| 0.04 0.26 8.12 v _09875_/X (sky130_fd_sc_hd__o211a_2) |
| 1 0.00 _04317_ (net) |
| 0.04 0.00 8.12 v _09876_/B1 (sky130_fd_sc_hd__a311o_2) |
| 0.07 0.39 8.51 v _09876_/X (sky130_fd_sc_hd__a311o_2) |
| 1 0.01 _04318_ (net) |
| 0.07 0.00 8.51 v _09877_/A3 (sky130_fd_sc_hd__a32o_2) |
| 0.12 0.38 8.88 v _09877_/X (sky130_fd_sc_hd__a32o_2) |
| 4 0.04 _04319_ (net) |
| 0.12 0.00 8.89 v _09926_/A (sky130_fd_sc_hd__nand2_2) |
| 0.07 0.09 8.97 ^ _09926_/Y (sky130_fd_sc_hd__nand2_2) |
| 2 0.00 _04368_ (net) |
| 0.07 0.00 8.97 ^ _10086_/B_N (sky130_fd_sc_hd__or2b_2) |
| 0.06 0.32 9.29 v _10086_/X (sky130_fd_sc_hd__or2b_2) |
| 2 0.00 _04528_ (net) |
| 0.06 0.00 9.29 v _10089_/A (sky130_fd_sc_hd__or2b_2) |
| 0.06 0.32 9.61 v _10089_/X (sky130_fd_sc_hd__or2b_2) |
| 2 0.01 _04531_ (net) |
| 0.06 0.00 9.61 v _11360_/A (sky130_fd_sc_hd__or4bb_2) |
| 0.11 0.70 10.31 v _11360_/X (sky130_fd_sc_hd__or4bb_2) |
| 2 0.01 _05802_ (net) |
| 0.11 0.00 10.31 v _11419_/A3 (sky130_fd_sc_hd__a311o_2) |
| 0.05 0.43 10.73 v _11419_/X (sky130_fd_sc_hd__a311o_2) |
| 1 0.00 _05861_ (net) |
| 0.05 0.00 10.73 v _11421_/A1 (sky130_fd_sc_hd__a21o_2) |
| 0.11 0.29 11.02 v _11421_/X (sky130_fd_sc_hd__a21o_2) |
| 5 0.04 _05863_ (net) |
| 0.11 0.00 11.02 v _11481_/B2 (sky130_fd_sc_hd__a221o_2) |
| 0.11 0.48 11.50 v _11481_/X (sky130_fd_sc_hd__a221o_2) |
| 2 0.03 _05923_ (net) |
| 0.11 0.00 11.50 v _11494_/A2 (sky130_fd_sc_hd__o211a_2) |
| 0.04 0.27 11.77 v _11494_/X (sky130_fd_sc_hd__o211a_2) |
| 1 0.00 _05936_ (net) |
| 0.04 0.00 11.77 v _11495_/C (sky130_fd_sc_hd__and3_2) |
| 0.10 0.29 12.06 v _11495_/X (sky130_fd_sc_hd__and3_2) |
| 5 0.03 _05937_ (net) |
| 0.10 0.00 12.06 v _11548_/A (sky130_fd_sc_hd__nand2_2) |
| 0.06 0.09 12.15 ^ _11548_/Y (sky130_fd_sc_hd__nand2_2) |
| 3 0.01 _05985_ (net) |
| 0.06 0.00 12.15 ^ _11641_/A (sky130_fd_sc_hd__buf_1) |
| 0.21 0.21 12.37 ^ _11641_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _06074_ (net) |
| 0.21 0.00 12.37 ^ _11645_/A (sky130_fd_sc_hd__buf_1) |
| 0.23 0.25 12.62 ^ _11645_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _06078_ (net) |
| 0.23 0.00 12.62 ^ _12064_/A (sky130_fd_sc_hd__buf_1) |
| 0.31 0.32 12.94 ^ _12064_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _06469_ (net) |
| 0.31 0.00 12.94 ^ _12433_/B1_N (sky130_fd_sc_hd__a21boi_2) |
| 0.25 0.35 13.29 ^ _12433_/Y (sky130_fd_sc_hd__a21boi_2) |
| 1 0.02 _06808_ (net) |
| 0.25 0.00 13.29 ^ _12437_/A2 (sky130_fd_sc_hd__o31a_2) |
| 0.08 0.22 13.51 ^ _12437_/X (sky130_fd_sc_hd__o31a_2) |
| 2 0.01 _06812_ (net) |
| 0.08 0.00 13.51 ^ _12441_/B1 (sky130_fd_sc_hd__o22a_2) |
| 0.37 0.40 13.91 ^ _12441_/X (sky130_fd_sc_hd__o22a_2) |
| 1 0.03 io_ibus_addr[31] (net) |
| 0.37 0.01 13.93 ^ io_ibus_addr[31] (out) |
| 13.93 data arrival time |
| |
| 0.15 20.00 20.00 clock clock (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -13.93 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.82 slack (MET) |
| |
| |
| Startpoint: _18779_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: io_ibus_addr[12] (output port clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _18779_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| 0.11 0.43 0.43 ^ _18779_/Q (sky130_fd_sc_hd__dfxtp_2) |
| 4 0.02 _00005_ (net) |
| 0.11 0.00 0.43 ^ _09382_/A (sky130_fd_sc_hd__buf_1) |
| 0.31 0.30 0.73 ^ _09382_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _03824_ (net) |
| 0.31 0.00 0.73 ^ _09383_/A (sky130_fd_sc_hd__buf_1) |
| 0.79 0.68 1.41 ^ _09383_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.07 _03825_ (net) |
| 0.79 0.00 1.41 ^ _09384_/A (sky130_fd_sc_hd__buf_1) |
| 0.38 0.41 1.82 ^ _09384_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _03826_ (net) |
| 0.38 0.00 1.82 ^ _09385_/A (sky130_fd_sc_hd__buf_1) |
| 0.48 0.46 2.27 ^ _09385_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03827_ (net) |
| 0.48 0.00 2.28 ^ _09386_/A (sky130_fd_sc_hd__buf_1) |
| 0.42 0.42 2.69 ^ _09386_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03828_ (net) |
| 0.42 0.00 2.69 ^ _09387_/A (sky130_fd_sc_hd__buf_1) |
| 0.60 0.55 3.24 ^ _09387_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _03829_ (net) |
| 0.60 0.00 3.24 ^ _09388_/A (sky130_fd_sc_hd__buf_1) |
| 0.53 0.51 3.75 ^ _09388_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _03830_ (net) |
| 0.53 0.00 3.75 ^ _09458_/A (sky130_fd_sc_hd__buf_1) |
| 0.51 0.49 4.25 ^ _09458_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03900_ (net) |
| 0.51 0.00 4.25 ^ _09679_/A (sky130_fd_sc_hd__buf_1) |
| 0.40 0.41 4.66 ^ _09679_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _04121_ (net) |
| 0.40 0.00 4.66 ^ _09698_/A (sky130_fd_sc_hd__buf_1) |
| 0.50 0.47 5.13 ^ _09698_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _04140_ (net) |
| 0.50 0.00 5.13 ^ _09699_/A (sky130_fd_sc_hd__buf_1) |
| 0.58 0.54 5.67 ^ _09699_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _04141_ (net) |
| 0.58 0.00 5.67 ^ _09700_/A (sky130_fd_sc_hd__buf_1) |
| 0.45 0.45 6.12 ^ _09700_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _04142_ (net) |
| 0.45 0.00 6.12 ^ _09868_/A (sky130_fd_sc_hd__buf_1) |
| 0.53 0.50 6.62 ^ _09868_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _04310_ (net) |
| 0.53 0.00 6.62 ^ _09869_/A (sky130_fd_sc_hd__buf_1) |
| 0.64 0.59 7.21 ^ _09869_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.06 _04311_ (net) |
| 0.64 0.00 7.21 ^ _09872_/S0 (sky130_fd_sc_hd__mux4_2) |
| 0.10 0.64 7.85 v _09872_/X (sky130_fd_sc_hd__mux4_2) |
| 1 0.01 _04314_ (net) |
| 0.10 0.00 7.85 v _09875_/A2 (sky130_fd_sc_hd__o211a_2) |
| 0.04 0.26 8.12 v _09875_/X (sky130_fd_sc_hd__o211a_2) |
| 1 0.00 _04317_ (net) |
| 0.04 0.00 8.12 v _09876_/B1 (sky130_fd_sc_hd__a311o_2) |
| 0.07 0.39 8.51 v _09876_/X (sky130_fd_sc_hd__a311o_2) |
| 1 0.01 _04318_ (net) |
| 0.07 0.00 8.51 v _09877_/A3 (sky130_fd_sc_hd__a32o_2) |
| 0.12 0.38 8.88 v _09877_/X (sky130_fd_sc_hd__a32o_2) |
| 4 0.04 _04319_ (net) |
| 0.12 0.00 8.89 v _09926_/A (sky130_fd_sc_hd__nand2_2) |
| 0.07 0.09 8.97 ^ _09926_/Y (sky130_fd_sc_hd__nand2_2) |
| 2 0.00 _04368_ (net) |
| 0.07 0.00 8.97 ^ _10086_/B_N (sky130_fd_sc_hd__or2b_2) |
| 0.06 0.32 9.29 v _10086_/X (sky130_fd_sc_hd__or2b_2) |
| 2 0.00 _04528_ (net) |
| 0.06 0.00 9.29 v _10089_/A (sky130_fd_sc_hd__or2b_2) |
| 0.06 0.32 9.61 v _10089_/X (sky130_fd_sc_hd__or2b_2) |
| 2 0.01 _04531_ (net) |
| 0.06 0.00 9.61 v _11360_/A (sky130_fd_sc_hd__or4bb_2) |
| 0.11 0.70 10.31 v _11360_/X (sky130_fd_sc_hd__or4bb_2) |
| 2 0.01 _05802_ (net) |
| 0.11 0.00 10.31 v _11419_/A3 (sky130_fd_sc_hd__a311o_2) |
| 0.05 0.43 10.73 v _11419_/X (sky130_fd_sc_hd__a311o_2) |
| 1 0.00 _05861_ (net) |
| 0.05 0.00 10.73 v _11421_/A1 (sky130_fd_sc_hd__a21o_2) |
| 0.11 0.29 11.02 v _11421_/X (sky130_fd_sc_hd__a21o_2) |
| 5 0.04 _05863_ (net) |
| 0.11 0.00 11.02 v _11481_/B2 (sky130_fd_sc_hd__a221o_2) |
| 0.11 0.48 11.50 v _11481_/X (sky130_fd_sc_hd__a221o_2) |
| 2 0.03 _05923_ (net) |
| 0.11 0.00 11.50 v _11494_/A2 (sky130_fd_sc_hd__o211a_2) |
| 0.04 0.27 11.77 v _11494_/X (sky130_fd_sc_hd__o211a_2) |
| 1 0.00 _05936_ (net) |
| 0.04 0.00 11.77 v _11495_/C (sky130_fd_sc_hd__and3_2) |
| 0.10 0.29 12.06 v _11495_/X (sky130_fd_sc_hd__and3_2) |
| 5 0.03 _05937_ (net) |
| 0.10 0.00 12.06 v _11548_/A (sky130_fd_sc_hd__nand2_2) |
| 0.06 0.09 12.15 ^ _11548_/Y (sky130_fd_sc_hd__nand2_2) |
| 3 0.01 _05985_ (net) |
| 0.06 0.00 12.15 ^ _11641_/A (sky130_fd_sc_hd__buf_1) |
| 0.21 0.21 12.37 ^ _11641_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _06074_ (net) |
| 0.21 0.00 12.37 ^ _11642_/A (sky130_fd_sc_hd__buf_1) |
| 0.31 0.32 12.69 ^ _11642_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _06075_ (net) |
| 0.31 0.00 12.69 ^ _11643_/A (sky130_fd_sc_hd__buf_1) |
| 0.29 0.32 13.00 ^ _11643_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _06076_ (net) |
| 0.29 0.00 13.00 ^ _11968_/A (sky130_fd_sc_hd__nand2_2) |
| 0.07 0.08 13.08 v _11968_/Y (sky130_fd_sc_hd__nand2_2) |
| 1 0.00 _06381_ (net) |
| 0.07 0.00 13.08 v _11973_/A2 (sky130_fd_sc_hd__a31o_2) |
| 0.05 0.27 13.35 v _11973_/X (sky130_fd_sc_hd__a31o_2) |
| 1 0.01 _06386_ (net) |
| 0.05 0.00 13.35 v _11974_/C_N (sky130_fd_sc_hd__or3b_2) |
| 0.05 0.21 13.56 ^ _11974_/X (sky130_fd_sc_hd__or3b_2) |
| 2 0.01 _06387_ (net) |
| 0.05 0.00 13.56 ^ _11975_/B1 (sky130_fd_sc_hd__o21a_2) |
| 0.28 0.31 13.87 ^ _11975_/X (sky130_fd_sc_hd__o21a_2) |
| 1 0.03 io_ibus_addr[12] (net) |
| 0.28 0.01 13.88 ^ io_ibus_addr[12] (out) |
| 13.88 data arrival time |
| |
| 0.15 20.00 20.00 clock clock (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -13.88 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.87 slack (MET) |
| |
| |
| max_report_end |
| check_report |
| |
| =========================================================================== |
| report_checks -unconstrained |
| ============================================================================ |
| Startpoint: _18779_ (rising edge-triggered flip-flop clocked by clock) |
| Endpoint: io_ibus_addr[28] (output port clocked by clock) |
| Path Group: clock |
| Path Type: max |
| |
| Fanout Cap Slew Delay Time Description |
| ----------------------------------------------------------------------------- |
| 0.15 0.00 0.00 clock clock (rise edge) |
| 0.00 0.00 clock network delay (ideal) |
| 0.15 0.00 0.00 ^ _18779_/CLK (sky130_fd_sc_hd__dfxtp_2) |
| 0.11 0.43 0.43 ^ _18779_/Q (sky130_fd_sc_hd__dfxtp_2) |
| 4 0.02 _00005_ (net) |
| 0.11 0.00 0.43 ^ _09382_/A (sky130_fd_sc_hd__buf_1) |
| 0.31 0.30 0.73 ^ _09382_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _03824_ (net) |
| 0.31 0.00 0.73 ^ _09383_/A (sky130_fd_sc_hd__buf_1) |
| 0.79 0.68 1.41 ^ _09383_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.07 _03825_ (net) |
| 0.79 0.00 1.41 ^ _09384_/A (sky130_fd_sc_hd__buf_1) |
| 0.38 0.41 1.82 ^ _09384_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _03826_ (net) |
| 0.38 0.00 1.82 ^ _09385_/A (sky130_fd_sc_hd__buf_1) |
| 0.48 0.46 2.27 ^ _09385_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03827_ (net) |
| 0.48 0.00 2.28 ^ _09386_/A (sky130_fd_sc_hd__buf_1) |
| 0.42 0.42 2.69 ^ _09386_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03828_ (net) |
| 0.42 0.00 2.69 ^ _09387_/A (sky130_fd_sc_hd__buf_1) |
| 0.60 0.55 3.24 ^ _09387_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _03829_ (net) |
| 0.60 0.00 3.24 ^ _09388_/A (sky130_fd_sc_hd__buf_1) |
| 0.53 0.51 3.75 ^ _09388_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _03830_ (net) |
| 0.53 0.00 3.75 ^ _09458_/A (sky130_fd_sc_hd__buf_1) |
| 0.51 0.49 4.25 ^ _09458_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _03900_ (net) |
| 0.51 0.00 4.25 ^ _09679_/A (sky130_fd_sc_hd__buf_1) |
| 0.40 0.41 4.66 ^ _09679_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _04121_ (net) |
| 0.40 0.00 4.66 ^ _09698_/A (sky130_fd_sc_hd__buf_1) |
| 0.50 0.47 5.13 ^ _09698_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _04140_ (net) |
| 0.50 0.00 5.13 ^ _09699_/A (sky130_fd_sc_hd__buf_1) |
| 0.58 0.54 5.67 ^ _09699_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _04141_ (net) |
| 0.58 0.00 5.67 ^ _09700_/A (sky130_fd_sc_hd__buf_1) |
| 0.45 0.45 6.12 ^ _09700_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.04 _04142_ (net) |
| 0.45 0.00 6.12 ^ _09868_/A (sky130_fd_sc_hd__buf_1) |
| 0.53 0.50 6.62 ^ _09868_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.05 _04310_ (net) |
| 0.53 0.00 6.62 ^ _09869_/A (sky130_fd_sc_hd__buf_1) |
| 0.64 0.59 7.21 ^ _09869_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.06 _04311_ (net) |
| 0.64 0.00 7.21 ^ _09872_/S0 (sky130_fd_sc_hd__mux4_2) |
| 0.10 0.64 7.85 v _09872_/X (sky130_fd_sc_hd__mux4_2) |
| 1 0.01 _04314_ (net) |
| 0.10 0.00 7.85 v _09875_/A2 (sky130_fd_sc_hd__o211a_2) |
| 0.04 0.26 8.12 v _09875_/X (sky130_fd_sc_hd__o211a_2) |
| 1 0.00 _04317_ (net) |
| 0.04 0.00 8.12 v _09876_/B1 (sky130_fd_sc_hd__a311o_2) |
| 0.07 0.39 8.51 v _09876_/X (sky130_fd_sc_hd__a311o_2) |
| 1 0.01 _04318_ (net) |
| 0.07 0.00 8.51 v _09877_/A3 (sky130_fd_sc_hd__a32o_2) |
| 0.12 0.38 8.88 v _09877_/X (sky130_fd_sc_hd__a32o_2) |
| 4 0.04 _04319_ (net) |
| 0.12 0.00 8.89 v _09926_/A (sky130_fd_sc_hd__nand2_2) |
| 0.07 0.09 8.97 ^ _09926_/Y (sky130_fd_sc_hd__nand2_2) |
| 2 0.00 _04368_ (net) |
| 0.07 0.00 8.97 ^ _10086_/B_N (sky130_fd_sc_hd__or2b_2) |
| 0.06 0.32 9.29 v _10086_/X (sky130_fd_sc_hd__or2b_2) |
| 2 0.00 _04528_ (net) |
| 0.06 0.00 9.29 v _10089_/A (sky130_fd_sc_hd__or2b_2) |
| 0.06 0.32 9.61 v _10089_/X (sky130_fd_sc_hd__or2b_2) |
| 2 0.01 _04531_ (net) |
| 0.06 0.00 9.61 v _11360_/A (sky130_fd_sc_hd__or4bb_2) |
| 0.11 0.70 10.31 v _11360_/X (sky130_fd_sc_hd__or4bb_2) |
| 2 0.01 _05802_ (net) |
| 0.11 0.00 10.31 v _11419_/A3 (sky130_fd_sc_hd__a311o_2) |
| 0.05 0.43 10.73 v _11419_/X (sky130_fd_sc_hd__a311o_2) |
| 1 0.00 _05861_ (net) |
| 0.05 0.00 10.73 v _11421_/A1 (sky130_fd_sc_hd__a21o_2) |
| 0.11 0.29 11.02 v _11421_/X (sky130_fd_sc_hd__a21o_2) |
| 5 0.04 _05863_ (net) |
| 0.11 0.00 11.02 v _11481_/B2 (sky130_fd_sc_hd__a221o_2) |
| 0.11 0.48 11.50 v _11481_/X (sky130_fd_sc_hd__a221o_2) |
| 2 0.03 _05923_ (net) |
| 0.11 0.00 11.50 v _11494_/A2 (sky130_fd_sc_hd__o211a_2) |
| 0.04 0.27 11.77 v _11494_/X (sky130_fd_sc_hd__o211a_2) |
| 1 0.00 _05936_ (net) |
| 0.04 0.00 11.77 v _11495_/C (sky130_fd_sc_hd__and3_2) |
| 0.10 0.29 12.06 v _11495_/X (sky130_fd_sc_hd__and3_2) |
| 5 0.03 _05937_ (net) |
| 0.10 0.00 12.06 v _11548_/A (sky130_fd_sc_hd__nand2_2) |
| 0.06 0.09 12.15 ^ _11548_/Y (sky130_fd_sc_hd__nand2_2) |
| 3 0.01 _05985_ (net) |
| 0.06 0.00 12.15 ^ _11641_/A (sky130_fd_sc_hd__buf_1) |
| 0.21 0.21 12.37 ^ _11641_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _06074_ (net) |
| 0.21 0.00 12.37 ^ _11645_/A (sky130_fd_sc_hd__buf_1) |
| 0.23 0.25 12.62 ^ _11645_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.02 _06078_ (net) |
| 0.23 0.00 12.62 ^ _12064_/A (sky130_fd_sc_hd__buf_1) |
| 0.31 0.32 12.94 ^ _12064_/X (sky130_fd_sc_hd__buf_1) |
| 5 0.03 _06469_ (net) |
| 0.31 0.00 12.94 ^ _12369_/A (sky130_fd_sc_hd__nand2_2) |
| 0.13 0.09 13.03 v _12369_/Y (sky130_fd_sc_hd__nand2_2) |
| 1 0.01 _06750_ (net) |
| 0.13 0.00 13.03 v _12374_/A2 (sky130_fd_sc_hd__a31o_2) |
| 0.05 0.30 13.33 v _12374_/X (sky130_fd_sc_hd__a31o_2) |
| 1 0.01 _06755_ (net) |
| 0.05 0.00 13.33 v _12375_/C1 (sky130_fd_sc_hd__o311a_2) |
| 0.08 0.14 13.47 v _12375_/X (sky130_fd_sc_hd__o311a_2) |
| 2 0.01 _06756_ (net) |
| 0.08 0.00 13.47 v _12376_/B1 (sky130_fd_sc_hd__a21oi_2) |
| 0.82 0.64 14.11 ^ _12376_/Y (sky130_fd_sc_hd__a21oi_2) |
| 1 0.03 io_ibus_addr[28] (net) |
| 0.82 0.01 14.12 ^ io_ibus_addr[28] (out) |
| 14.12 data arrival time |
| |
| 0.15 20.00 20.00 clock clock (rise edge) |
| 0.00 20.00 clock network delay (ideal) |
| -0.25 19.75 clock uncertainty |
| 0.00 19.75 clock reconvergence pessimism |
| -4.00 15.75 output external delay |
| 15.75 data required time |
| ----------------------------------------------------------------------------- |
| 15.75 data required time |
| -14.12 data arrival time |
| ----------------------------------------------------------------------------- |
| 1.63 slack (MET) |
| |
| |
| |
| =========================================================================== |
| report_checks --slack_max -0.01 |
| ============================================================================ |
| No paths found. |
| check_report_end |
| check_slew |
| |
| =========================================================================== |
| report_check_types -max_slew -max_cap -max_fanout -violators |
| ============================================================================ |
| |
| =========================================================================== |
| max slew violation count 0 |
| max fanout violation count 0 |
| max cap violation count 0 |
| ============================================================================ |
| check_slew_end |
| tns_report |
| |
| =========================================================================== |
| report_tns |
| ============================================================================ |
| tns 0.00 |
| tns_report_end |
| wns_report |
| |
| =========================================================================== |
| report_wns |
| ============================================================================ |
| wns 0.00 |
| wns_report_end |
| worst_slack |
| |
| =========================================================================== |
| report_worst_slack -max (Setup) |
| ============================================================================ |
| worst slack 1.63 |
| |
| =========================================================================== |
| report_worst_slack -min (Hold) |
| ============================================================================ |
| worst slack 0.08 |
| worst_slack_end |
| clock_skew |
| |
| =========================================================================== |
| report_clock_skew |
| ============================================================================ |
| Clock clock |
| Latency CRPR Skew |
| _18250_/CLK ^ |
| 10.34 |
| _18641_/CLK ^ |
| 9.35 0.00 0.98 |
| |
| clock_skew_end |
| power_report |
| |
| =========================================================================== |
| report_power |
| ============================================================================ |
| Group Internal Switching Leakage Total |
| Power Power Power Power |
| ---------------------------------------------------------------- |
| Sequential 3.57e-03 2.43e-04 1.37e-08 3.81e-03 55.0% |
| Combinational 1.42e-03 1.69e-03 2.63e-08 3.12e-03 45.0% |
| Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% |
| ---------------------------------------------------------------- |
| Total 4.99e-03 1.94e-03 4.00e-08 6.92e-03 100.0% |
| 72.0% 28.0% 0.0% |
| power_report_end |
| area_report |
| |
| =========================================================================== |
| report_design_area |
| ============================================================================ |
| Design area 113722 u^2 49% utilization. |
| area_report_end |
