UART initialization
diff --git a/Makefile b/Makefile index e787f93..4a22cf7 100644 --- a/Makefile +++ b/Makefile
@@ -60,7 +60,7 @@ docker pull efabless/dv_setup:latest .PHONY: setup -setup: install check-env install_mcw pdk openlane +setup: install check-env install_mcw openlane # Openlane blocks=$(shell cd openlane && find * -maxdepth 0 -type d)
diff --git a/openlane/Core/config.tcl b/openlane/Core/config.tcl deleted file mode 100644 index 62e430a..0000000 --- a/openlane/Core/config.tcl +++ /dev/null
@@ -1,57 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -set ::env(PDK) "sky130A" -set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" - -set script_dir [file dirname [file normalize [info script]]] - -set ::env(DESIGN_NAME) Core - -set ::env(VERILOG_FILES) "\ - $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/Processor_Tile.v" - -set ::env(DESIGN_IS_CORE) 0 - -set ::env(CLOCK_PORT) "clock" -set ::env(CLOCK_NET) "" -set ::env(CLOCK_PERIOD) "20" - -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 500 500" - -# set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg - -set ::env(PL_BASIC_PLACEMENT) 0 -set ::env(PL_TARGET_DENSITY) 0.5 -set ::env(CELL_PAD) 2 - -# Maximum layer used for routing is metal 4. -# This is because this macro will be inserted in a top level (user_project_wrapper) -# where the PDN is planned on metal 5. So, to avoid having shorts between routes -# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. -# -# set ::env(GLB_RT_MAXLAYER) 5 - -set ::env(RT_MAX_LAYER) {met4} - -# You can draw more power domains if you need to -set ::env(VDD_NETS) [list {vccd1}] -set ::env(GND_NETS) [list {vssd1}] - -set ::env(DIODE_INSERTION_STRATEGY) 4 -# If you're going to use multiple power domains, then disable cvc run. -set ::env(RUN_CVC) 1
diff --git a/openlane/user_proj_example/config.json b/openlane/user_proj_example/config.json deleted file mode 100644 index c3de8af..0000000 --- a/openlane/user_proj_example/config.json +++ /dev/null
@@ -1,21 +0,0 @@ -{ - "PDK" : "sky130A", - "STD_CELL_LIBRARY" : "sky130_fd_sc_hd", - "CARAVEL_ROOT" : "../../caravel", - "CLOCK_NET" : "counter.clk", - "CLOCK_PERIOD" : "10", - "CLOCK_PORT" : "wb_clk_i", - "DESIGN_IS_CORE" : "0", - "DESIGN_NAME" : "user_proj_example", - "DIE_AREA" : "0 0 900 600", - "DIODE_INSERTION_STRATEGY" : "4", - "FP_PIN_ORDER_CFG" : "pin_order.cfg", - "FP_SIZING" : "absolute", - "GLB_RT_MAXLAYER" : "5", - "GND_NETS" : "vssd1", - "PL_BASIC_PLACEMENT" : "1", - "PL_TARGET_DENSITY" : "0.05", - "RUN_CVC" : "1", - "VDD_NETS" : "vccd1", - "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v", "../../verilog/rtl/user_proj_example.v"] -}
diff --git a/openlane/user_proj_example/config.tcl b/openlane/user_proj_example/config.tcl deleted file mode 100755 index c9266ee..0000000 --- a/openlane/user_proj_example/config.tcl +++ /dev/null
@@ -1,56 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -set ::env(PDK) "sky130A" -set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" - -set script_dir [file dirname [file normalize [info script]]] - -set ::env(DESIGN_NAME) user_proj_example - -set ::env(VERILOG_FILES) "\ - $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_proj_example.v" - -set ::env(DESIGN_IS_CORE) 0 - -set ::env(CLOCK_PORT) "wb_clk_i" -set ::env(CLOCK_NET) "counter.clk" -set ::env(CLOCK_PERIOD) "10" - -set ::env(FP_SIZING) absolute -set ::env(DIE_AREA) "0 0 900 600" - -set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg - -set ::env(PL_BASIC_PLACEMENT) 1 -set ::env(PL_TARGET_DENSITY) 0.05 - -# Maximum layer used for routing is metal 4. -# This is because this macro will be inserted in a top level (user_project_wrapper) -# where the PDN is planned on metal 5. So, to avoid having shorts between routes -# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4. -# -# set ::env(GLB_RT_MAXLAYER) 5 - -set ::env(RT_MAX_LAYER) {met4} - -# You can draw more power domains if you need to -set ::env(VDD_NETS) [list {vccd1}] -set ::env(GND_NETS) [list {vssd1}] - -set ::env(DIODE_INSERTION_STRATEGY) 4 -# If you're going to use multiple power domains, then disable cvc run. -set ::env(RUN_CVC) 1
diff --git a/openlane/user_proj_example/pin_order.cfg b/openlane/user_proj_example/pin_order.cfg deleted file mode 100644 index 2fda806..0000000 --- a/openlane/user_proj_example/pin_order.cfg +++ /dev/null
@@ -1,10 +0,0 @@ -#BUS_SORT - -#S -wb_.* -wbs_.* -la_.* -irq.* - -#N -io_.*
diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json deleted file mode 100644 index d83d5bb..0000000 --- a/openlane/user_project_wrapper/config.json +++ /dev/null
@@ -1,58 +0,0 @@ -{ - "PDK" : "sky130A", - "STD_CELL_LIBRARY" : "sky130_fd_sc_hd", - "CARAVEL_ROOT" : "../../caravel", - "CLOCK_NET" : "mprj.clk", - "CLOCK_PERIOD" : "10", - "CLOCK_PORT" : "user_clock2", - "CLOCK_TREE_SYNTH" : "0", - "DESIGN_NAME" : "user_project_wrapper", - "DIE_AREA" : "0 0 2920 3520", - "DIODE_INSERTION_STRATEGY" : "0", - "EXTRA_GDS_FILES" : "../../gds/user_proj_example.gds", - "EXTRA_LEFS" : "../../lef/user_proj_example.lef", - "FILL_INSERTION" : "0", - "FP_IO_HEXTEND" : "4.8", - "FP_IO_HLENGTH" : "2.4", - "FP_IO_HTHICKNESS_MULT" : "4", - "FP_IO_VEXTEND" : "4.8", - "FP_IO_VLENGTH" : "2.4", - "FP_IO_VTHICKNESS_MULT" : "4", - "FP_PDN_CHECK_NODES" : "0", - "FP_PDN_CORE_RING" : "1", - "FP_PDN_CORE_RING_HOFFSET" : "14", - "FP_PDN_CORE_RING_HSPACING" : "1.7", - "FP_PDN_CORE_RING_HWIDTH" : "3.1", - "FP_PDN_CORE_RING_VOFFSET" : "14", - "FP_PDN_CORE_RING_VSPACING" : "1.7", - "FP_PDN_CORE_RING_VWIDTH" : "3.1", - "FP_PDN_ENABLE_RAILS" : "0", - "FP_PDN_HOFFSET" : "5", - "FP_PDN_HPITCH" : "180", - "FP_PDN_HSPACING" : "15.5", - "FP_PDN_HWIDTH" : "3.1", - "FP_PDN_MACRO_HOOKS" : "mprj vccd1 vssd1", - "FP_PDN_VOFFSET" : "5", - "FP_PDN_VPITCH" : "180", - "FP_PDN_VSPACING" : "15.5", - "FP_PDN_VWIDTH" : "3.1", - "FP_PIN_ORDER_CFG" : "../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg", - "FP_SIZING" : "absolute", - "GLB_RT_MAXLAYER" : "5", - "GND_NETS" : "vssd1 vssd2 vssa1 vssa2", - "MACRO_PLACEMENT_CFG" : "macro.cfg", - "MAGIC_ZEROIZE_ORIGIN" : "0", - "PL_RANDOM_GLB_PLACEMENT" : "1", - "PL_RESIZER_BUFFER_INPUT_PORTS" : "0", - "PL_RESIZER_BUFFER_OUTPUT_PORTS" : "0", - "PL_RESIZER_DESIGN_OPTIMIZATIONS" : "0", - "PL_RESIZER_TIMING_OPTIMIZATIONS" : "0", - "RUN_CVC" : "0", - "SYNTH_TOP_LEVEL" : "1", - "SYNTH_USE_PG_PINS_DEFINES" : "USE_POWER_PINS", - "TAP_DECAP_INSERTION" : "0", - "VDD_NETS" : "vccd1 vccd2 vdda1 vdda2", - "VERILOG_FILES" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_project_wrapper.v"], - "VERILOG_FILES_BLACKBOX" : ["../../caravel/verilog/rtl/defines.v","../../verilog/rtl/user_proj_example.v"] -} -
diff --git a/openlane/user_project_wrapper/config.tcl b/openlane/user_project_wrapper/config.tcl deleted file mode 100755 index f720e39..0000000 --- a/openlane/user_project_wrapper/config.tcl +++ /dev/null
@@ -1,86 +0,0 @@ -# SPDX-FileCopyrightText: 2020 Efabless Corporation -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# SPDX-License-Identifier: Apache-2.0 - -# Base Configurations. Don't Touch -# section begin - -set ::env(PDK) "sky130A" -set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd" - -# YOU ARE NOT ALLOWED TO CHANGE ANY VARIABLES DEFINED IN THE FIXED WRAPPER CFGS -source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/fixed_wrapper_cfgs.tcl - -# YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL -source $::env(CARAVEL_ROOT)/openlane/user_project_wrapper/default_wrapper_cfgs.tcl - -set script_dir [file dirname [file normalize [info script]]] - -set ::env(DESIGN_NAME) user_project_wrapper -#section end - -# User Configurations - -## Source Verilog Files -set ::env(VERILOG_FILES) "\ - $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_project_wrapper.v" - -## Clock configurations -set ::env(CLOCK_PORT) "user_clock2" -set ::env(CLOCK_NET) "mprj.clk" - -set ::env(CLOCK_PERIOD) "10" - -## Internal Macros -### Macro PDN Connections -set ::env(FP_PDN_MACRO_HOOKS) "\ - mprj vccd1 vssd1" - -### Macro Placement -set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro.cfg - -### Black-box verilog and views -set ::env(VERILOG_FILES_BLACKBOX) "\ - $::env(CARAVEL_ROOT)/verilog/rtl/defines.v \ - $script_dir/../../verilog/rtl/user_proj_example.v" - -set ::env(EXTRA_LEFS) "\ - $script_dir/../../lef/user_proj_example.lef" - -set ::env(EXTRA_GDS_FILES) "\ - $script_dir/../../gds/user_proj_example.gds" - -# set ::env(GLB_RT_MAXLAYER) 5 -set ::env(RT_MAX_LAYER) {met4} - -# disable pdn check nodes becuase it hangs with multiple power domains. -# any issue with pdn connections will be flagged with LVS so it is not a critical check. -set ::env(FP_PDN_CHECK_NODES) 0 - -# The following is because there are no std cells in the example wrapper project. -set ::env(SYNTH_TOP_LEVEL) 1 -set ::env(PL_RANDOM_GLB_PLACEMENT) 1 - -set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0 -set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0 -set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0 -set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0 - -set ::env(FP_PDN_ENABLE_RAILS) 0 - -set ::env(DIODE_INSERTION_STRATEGY) 0 -set ::env(FILL_INSERTION) 0 -set ::env(TAP_DECAP_INSERTION) 0 -set ::env(CLOCK_TREE_SYNTH) 0
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg deleted file mode 100644 index a7365ab..0000000 --- a/openlane/user_project_wrapper/macro.cfg +++ /dev/null
@@ -1 +0,0 @@ -mprj 1175 1690 N
diff --git a/openlane/user_project_wrapper/pin_order.cfg b/openlane/user_project_wrapper/pin_order.cfg deleted file mode 120000 index 8797dcd..0000000 --- a/openlane/user_project_wrapper/pin_order.cfg +++ /dev/null
@@ -1 +0,0 @@ -../../../caravel/openlane/user_project_wrapper_empty/pin_order.cfg \ No newline at end of file