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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-005
/
slot-036
/
693ea05a9f85b2bf172a99c9c4537fa012ad3b6d
commit
693ea05a9f85b2bf172a99c9c4537fa012ad3b6d
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tgz
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author
ALI11-2000 <ali1120001@outlook.com>
Tue Mar 22 01:21:40 2022 +0500
committer
ALI11-2000 <ali1120001@outlook.com>
Tue Mar 22 01:21:40 2022 +0500
tree
38f6a4fc38fd653aedd4530b758cb2f0c013fae4
parent
a9d059c4d355b5395e248accafea86f94ba06e95
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Full Soc run
abc/Core/config.tcl
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abc/Core/pin_order.cfg
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abc/Core/runs/Core/OPENLANE_VERSION
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abc/Core/runs/Core/PDK_SOURCES
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abc/Core/runs/Core/cmds.log
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abc/Core/runs/Core/config.tcl
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abc/Core/runs/Core/logs/synthesis/1-synthesis.log
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abc/Core/runs/Core/openlane.log
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abc/Core/runs/Core/reports/synthesis/1-synthesis_dff.stat
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abc/Core/runs/Core/reports/synthesis/1-synthesis_pre.stat
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abc/Core/runs/Core/runtime.yaml
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abc/Core/runs/Core/tmp/merged.lef
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abc/Core/runs/Core/tmp/merged_unpadded.lef
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abc/Core/runs/Core/tmp/routing/config.tracks
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abc/Core/runs/Core/tmp/synthesis/1-sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib
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abc/Core/runs/Core/tmp/synthesis/hierarchy.dot
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abc/Core/runs/Core/tmp/synthesis/merged.lib
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abc/Core/runs/Core/tmp/synthesis/post_techmap.dot
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abc/Core/runs/Core/tmp/synthesis/resizer_opt.exclude.list
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abc/Core/runs/Core/tmp/synthesis/resizer_sky130_fd_sc_hd__tt_025C_1v80.lib
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abc/Core/runs/Core/tmp/synthesis/synthesis.sdc
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abc/Core/runs/Core/tmp/synthesis/trimmed.lib
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abc/Core/runs/Core/tmp/synthesis/trimmed.lib.exclude.list
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abc/Motor_Top/config.tcl
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abc/Motor_Top/pin_order.cfg
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abc/Wishbone_InterConnect/config.tcl
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abc/Wishbone_InterConnect/pin_order.cfg
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abc/user_proj_example/config.json
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abc/user_proj_example/config.tcl
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abc/user_proj_example/pin_order.cfg
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def/user_project_wrapper.def
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gds/user_project_wrapper.gds
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lef/user_project_wrapper.lef
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mag/user_project_wrapper.mag
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maglef/user_project_wrapper.mag
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openlane/user_project_wrapper/config.tcl
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openlane/user_project_wrapper/macro.cfg
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sdc/user_project_wrapper.sdc
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sdf/user_project_wrapper.sdf
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signoff/user_project_wrapper/final_summary_report.csv
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spef/user_project_wrapper.spef
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spi/lvs/user_project_wrapper.spice
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verilog/gl/user_project_wrapper.v
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verilog/rtl/user_project_wrapper.v
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44 files changed
tree: 38f6a4fc38fd653aedd4530b758cb2f0c013fae4
.github/
abc/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
sdc/
sdf/
signoff/
spef/
spi/
verilog/
caravel
.gitignore
LICENSE
Makefile
README.md
README.md
UETRV-ecore
Here is the toplevel block diagram of ECORE.