WB_Interconnect Verilog updated
1 file changed
tree: d28d85a3698cb7433d55cfc99aa5ab2cf55aef78
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
  13. verilog/
  14. .gitignore
  15. LICENSE
  16. Makefile
  17. README.md
README.md

UETRV-ecore

Here is the toplevel block diagram of ECORE

alt text

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License UPRJ_CI Caravel Build

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