commit	36f3ad6bdb786a360683b2454e11ebf2c8c3cad4	[log] [tgz]
author	Ali Imran <ali1120001@outlook.com>	Fri Mar 18 18:50:07 2022 +0500
committer	Ali Imran <ali1120001@outlook.com>	Fri Mar 18 18:50:07 2022 +0500
tree	4bbd3497effd9763373456ff65fec201857ffa85
parent	333db4364fd4e89840832e9d165fb161b6851f56 [diff]

All Modules Verilog added

verilog/rtl/DMem_Interface.v[Added - diff]
verilog/rtl/IMem_Interface.v[Added - diff]
verilog/rtl/Motor_Top.v[Added - diff]
verilog/rtl/Processor_Tile.v[diff]
verilog/rtl/WBM_DBus.v[Added - diff]
verilog/rtl/WB_Interconnect.v[Added - diff]

6 files changed

tree: 4bbd3497effd9763373456ff65fec201857ffa85

README.md

UETRV-ecore

Here is the toplevel block diagram of ECORE

alt text

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quick start of how to use caravel_user_project

Refer to README for this sample project documentation.